# Glossary

> **What this page is.** The terms used across this wiki, the project's
> documents and its logs. Condensed from
> [`../docs/09-reference/glossary-and-faq.md`](../docs/09-reference/glossary-and-faq.md);
> the docs tree wins on disagreement. For questions, see [`FAQ.md`](FAQ.md).

Status: 2026-10-12, tree `master @ 2f066727`.

## GPU, driver and virtualization

| Term | Meaning |
|---|---|
| **BAR0 / BAR1 / BAR3** | PCI BAR windows of the GPU: register interface (16 MB), VRAM aperture (256 MB), instance/PRAMIN window. |
| **CUDASW** | The family of NVIDIA user-space software between applications and the driver: `libcuda`, `libcudart`, the JIT compiler, the fatbinary loader, and friends. |
| **Doorbell** | A register or memory location a driver writes to signal "new work is available" for a channel or queue. |
| **mdev** | Mediated device: the kernel mechanism that turns a physical device into virtual instances (VFIO). |
| **vGPU** | Virtual GPU: the device this project presents to a guest. |
| **SRIOV / VF** | Single-root I/O virtualization / virtual functions (hardware partitioning). |
| **IOMMU / SMMU** | Platform DMA translation and isolation (Intel VT-d / AMD-Vi / ARM SMMU). |

## GSP, firmware and the RM

| Term | Meaning |
|---|---|
| **GSP** | GPU System Processor: the embedded RISC-V (RV64IMAC) that runs firmware containing the Resource Manager. |
| **GSP-RM** | The Resource Manager running on the GSP (the "self-hosted RM"). |
| **RM / RM API** | NVIDIA's Resource Manager and the API used to allocate objects and issue controls. |
| **RMCore** | The RM's object system: classes, handles, parents, methods. |
| **resserv / resource server** | The RM component that owns allocation authority, privileges and lifetimes. |
| **FWSEC** | Firmware security processor stage of the GSP boot sequence. |
| **WPR** | Write-Protected Region: the VRAM area reserved for firmware. |
| **MSGQ** | The GSP message-queue transport: shared-memory element rings with a page table, plus doorbells. |
| **VGX version** | The version the guest announces during RPC negotiation; it selects message layouts. |
| **Reply fidelity** | How completely an emulated reply matches what real hardware returns, as a ladder: status-only → coherent zeroed params → coherent values for consumed fields → exact values. |

## Execution engines and memory

| Term | Meaning |
|---|---|
| **CE** | Copy Engine: a DMA engine; also used for UVM's internal work. |
| **GR** | The graphics/compute engine that executes shaders (graphics pipelines and CUDA kernels). |
| **SEC2** | Secure copy engine used by UVM for protected operations. |
| **GPFIFO** | GPU FIFO: a ring of entries, each pointing to a push buffer for a channel. |
| **Push buffer** | A stream of method calls (engine commands) submitted via a GPFIFO. |
| **PBDMA** | The push-buffer DMA engine in the host scheduler that fetches and executes push buffers. |
| **QMD** | Queue Meta Data: the per-launch descriptor a GR channel reads to execute a kernel grid. |
| **USERD** | Per-channel control block in VRAM: PUT/GET pointers and control state. |
| **Runlist** | The scheduler's list of channels eligible to run. |
| **TSG** | Time-Slice Group: channels sharing a scheduling slot. |
| **Engine record / engine list** | The per-engine descriptors (kind, instance, class, client type) the driver walks after `GPU_GET_ENGINES`; each must be self-consistent or the driver rewrites the following allocation. |
| **GMMU** | GPU Memory Management Unit: page tables, TLB, fault handling. |
| **PDB** | Page Directory Base: root of a GPU page table. |
| **PDE / PTE** | Page-directory entry / page-table entry. |
| **UVM** | NVIDIA's unified memory module: VA spaces, page trees, faults, channel manager ([`UVM-in-the-Guest.md`](UVM-in-the-Guest.md)). |
| **VA / PA / GPA / IOVA** | Virtual address / physical address / guest physical address / I/O virtual address. |
| **vidmem / sysmem / aperture** | GPU local memory / system memory / how an address is qualified. |
| **Semaphore / tracker** | A memory location written by the GPU to signal progress; UVM's tracker waits on it. |
| **AMAPlib** | NVIDIA's shared "address mapping" library: swizzling, bank/channel mapping, aperture rules. |
| **HAL** | Hardware abstraction layer: per-generation functions that program registers and formats. |
| **Class list (classDB)** | The RM classes reported as supported; engine queries are filtered against it, so the class list, engine list and capability controls must agree. |

## Method and tooling

| Term | Meaning |
|---|---|
| **Host oracle / A-B harness** | The same query or deterministic workload run against a bare-metal host driver and inside the guest, then diffed — the reference for what the guest should have seen. |
| **File virtual address (`libcuda+0x...`)** | An address relative to the start of a shared object file, as distinct from a runtime mapping or a disassembler program address. |
| **Session (risc-v-gsp-rm-debugger)** | A recorded run of the firmware workbench — the unit of evidence ([`Riscv-GSP-RM-Debugger.md`](Riscv-GSP-RM-Debugger.md)). |

## Related pages

* [`FAQ.md`](FAQ.md)
* [`System-Overview.md`](System-Overview.md)
* [`GSP-and-GSP-RM.md`](GSP-and-GSP-RM.md)
* [`Introduction-to-GMMU.md`](Introduction-to-GMMU.md)