::: {#mw-page-base .noprint} ::: ::: {#mw-head-base .noprint} ::: ::: {#content .mw-body role="main"} []{#top} ::: {#siteNotice} ::: ::: mw-indicators ::: # GPU Firmware {#firstHeading .firstHeading} > **Imported 2023 material — superseded.** This page is an archived copy of the > previous project wiki (circa 2023) and is kept for historical reference. > Current documentation: > [`../docs/03-architecture/`](../docs/03-architecture/) and > [`../docs/09-reference/`](../docs/09-reference/). ::: {#bodyContent .vector-body} ::: {#siteSub .noprint} From Open-IOV ::: ::: {#contentSub} ::: {.mw-revision .warningbox} ::: {#mw-revision-info} Revision as of 17:13, 9 April 2023 by [Arthur](./index.php%3Ftitle=User:Arthur&action=edit&redlink=1.html "User:Arthur (page does not exist)"){.new .mw-userlink} [([talk](./index.php%3Ftitle=User_talk:Arthur&action=edit&redlink=1.html "User talk:Arthur (page does not exist)"){.new .mw-usertoollinks-talk} \| [contribs](index.php/Special:Contributions/Arthur.html "Special:Contributions/Arthur"){.mw-usertoollinks-contribs})]{.mw-usertoollinks} [([[[→‎Firmware Images](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Firmware_Images)]{.autocomment}]{dir="auto"})]{.comment} ::: ::: {#mw-revision-nav} ([diff](https://open-iov.org/index.php?title=GPU_Firmware&diff=prev&oldid=23779 "GPU Firmware")) [← Older revision](https://open-iov.org/index.php?title=GPU_Firmware&direction=prev&oldid=23779 "GPU Firmware") \| Latest revision (diff) \| Newer revision → (diff) ::: ::: ::: ::: {#contentSub2} ::: ::: {#jump-to-nav} ::: [Jump to navigation](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#mw-head){.mw-jump-link} [Jump to search](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#searchInput){.mw-jump-link} ::: {#mw-content-text .mw-body-content .mw-content-ltr lang="en" dir="ltr"} ::: mw-parser-output GPUs have become highly complex systems containing a number of different embedded controllers. This page will attempt to document embedded GPU firmware and support for IO virtualization through various firmware functions. > An absence of critical technical documentation has historically slowed > growth and adoption of developer ecosystems for GPU virtualization. > > This > [CC-BY-4.0](https://creativecommons.org/licenses/by/4.0/){.external > .text rel="nofollow"} licensed content can either be used with > attribution, or used as inspiration for new documentation, created by > GPU vendors for public commercial distribution as developer > documentation. > > Where possible, this documentation will clearly label dates and > versions of observed-but-not-guaranteed behaviour vs. > vendor-documented stable interfaces/behaviour with guarantees of > forward or backward compatibility. ::: {#toc .toc role="navigation" aria-labelledby="mw-toc-heading"} ::: {.toctitle lang="en" dir="ltr"} ## Contents {#mw-toc-heading} []{.toctogglespan} ::: - [[1]{.tocnumber} [Intel]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Intel) - [[1.1]{.tocnumber} [Firmware Images]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Firmware_Images) - [[1.1.1]{.tocnumber} [Intel Firmware Support Package (FSP)]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Intel_Firmware_Support_Package_(FSP)) - [[1.1.1.1]{.tocnumber} [FSP Configuration]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#FSP_Configuration) - [[1.1.1.1.1]{.tocnumber} [Editing FSP Configuration]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Editing_FSP_Configuration) - [[1.1.1.2]{.tocnumber} [FSP Binary Format]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#FSP_Binary_Format) - [[1.1.2]{.tocnumber} [Known Firmware Package Variations]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Known_Firmware_Package_Variations) - [[1.2]{.tocnumber} [Embedded Controllers]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Embedded_Controllers) - [[1.2.1]{.tocnumber} [GuC]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#GuC) - [[1.2.1.1]{.tocnumber} [Hardware Architecture]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Hardware_Architecture) - [[1.2.1.2]{.tocnumber} [Software Architecture]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Software_Architecture) - [[1.2.1.2.1]{.tocnumber} [GuC Blob Checksum & Code Signing]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#GuC_Blob_Checksum_&_Code_Signing) - [[2]{.tocnumber} [Nvidia]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Nvidia) - [[2.1]{.tocnumber} [Firmware Images]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Firmware_Images_2) - [[2.2]{.tocnumber} [Embedded Controllers]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Embedded_Controllers_2) - [[2.2.1]{.tocnumber} [Falcon / NV-RISCV]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Falcon_/_NV-RISCV) - [[2.2.2]{.tocnumber} [GSP]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#GSP) - [[2.2.2.1]{.tocnumber} [GSP Initialization & Offload]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#GSP_Initialization_&_Offload) - [[2.2.3]{.tocnumber} [CMU]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#CMU) - [[3]{.tocnumber} [AMD]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#AMD) - [[4]{.tocnumber} [References (Talks & Reading Material)]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#References_(Talks_&_Reading_Material)) ::: ## [Intel]{#Intel .mw-headline} ### [Firmware Images]{#Firmware_Images .mw-headline} This section will cover firmware images used in Intel GPUs. ::: {.thumb .tright} ::: {.thumbinner style="width:302px;"} [![Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification.](images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/300px-Screen_Shot_2022-11-18_at_4.14.32_PM.png){.thumbimage decoding="async" width="300" height="261" srcset="images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/450px-Screen_Shot_2022-11-18_at_4.14.32_PM.png 1.5x, images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/600px-Screen_Shot_2022-11-18_at_4.14.32_PM.png 2x"}](index.php/File:Screen_Shot_2022-11-18_at_4.14.32_PM.png.html){.image} ::: thumbcaption ::: magnify [](index.php/File:Screen_Shot_2022-11-18_at_4.14.32_PM.png.html "Enlarge"){.internal} ::: Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. [Source](https://cdrdv2.intel.com/v1/dl/getContent/736809){.external .text rel="nofollow"} ::: ::: ::: #### []{#Intel_Firmware_Support_Package_.28FSP.29}[Intel Firmware Support Package (FSP)]{#Intel_Firmware_Support_Package_(FSP) .mw-headline} Much like CPUs Intel\'s GPUs also contain a Firmware Support Package (FSP). The Coreboot project provides public domain information on the FSP [here](https://doc.coreboot.org/soc/intel/fsp/index.html){.external .text rel="nofollow"}. ##### [FSP Configuration]{#FSP_Configuration .mw-headline} In the context of GPUs the FSP configures several functions of the device. Those functions are as follows: ---------------------------------------------------------------------------------- ------------------------------ FSP Parameter Possible Values GFSP Status 0x00 FIVR SSC Value \*.\*% FIVR RFI Value \*.\*MHz GT Subsystem Vendor ID 0x8086 GT Subsystem Device ID 0x\*\* HDA Subsystem Vendor ID 0x0000 HDA Subsystem Device ID 0x0000 P2SB Enable Yes/No LMEBAR Max GTMMADDR Prefetch Capability Prefetch Enabled [Display Present](index.php/Merged_Drivers.html){.external .text rel="nofollow"} Enabled/Disabled I2C For Third Party Devices Enabled/Disabled I2C Device Address 1 0x0000 I2C Device Address 2 0x0000 I2C Bus Speed Standard mode (0 to 100Kbps) ---------------------------------------------------------------------------------- ------------------------------ : GPU Firmware Support Package ###### [Editing FSP Configuration]{#Editing_FSP_Configuration .mw-headline} The FSP configuration editor can be downloaded [here](https://github.com/tianocore/edk2/tree/master/IntelFsp2Pkg/Tools/ConfigEditor){.external .text rel="nofollow"} and it\'s user manual is available [here](https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Tools/UserManuals/ConfigEditorUserManual.md){.external .text rel="nofollow"}. ##### [FSP Binary Format]{#FSP_Binary_Format .mw-headline} The FSP\'s binary layout is detailed within the [Intel® FSP External Architecture Specification v2.4](https://cdrdv2.intel.com/v1/dl/getContent/736809){.external .text rel="nofollow"} on page 14. #### [Known Firmware Package Variations]{#Known_Firmware_Package_Variations .mw-headline} Some firmware packages may include an \*\*End of Manufacturing Flash Protection Mode\*\* status of Protected or Unprotected. ::: {.thumb .tright} ::: {.thumbinner style="width:302px;"} [![Figure 2: Firmware status information for an Intel DG2 device.](images/thumb/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png/300px-Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png){.thumbimage decoding="async" width="300" height="613" srcset="images/thumb/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png/450px-Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png 1.5x, images/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png 2x"}](index.php/File:Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png.html){.image} ::: thumbcaption ::: magnify [](index.php/File:Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png.html "Enlarge"){.internal} ::: Figure 2: Firmware status information for an Intel DG2 device. ::: ::: ::: Similar [SPI Write Protection](https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/){.external .text rel="nofollow"} functionality is made available through Intel CPUs under [System Management Mode (SMM)](https://en.wikipedia.org/wiki/System_Management_Mode "wikipedia:System Management Mode"){.extiw}. ### [Embedded Controllers]{#Embedded_Controllers .mw-headline} This section will cover firmware images as they apply to various embedded controllers within the Intel GPU. #### [GuC]{#GuC .mw-headline} The Graphics micro (µ) Controller (GuC) is an embedded controller contained within Intel\'s embedded and discrete graphics (DG\*) series GPUs. ##### [Hardware Architecture]{#Hardware_Architecture .mw-headline} *The following section is supported by [igor-blue.github.io](https://igor-blue.github.io/2021/02/10/graphics-part1.html){.external .text rel="nofollow"} (see reference [1](index.php/GPU_Firmware.html#References_(Talks_&_Reading_Material)){.external .text rel="nofollow"}, [2](index.php/GPU_Firmware.html#References_(Talks_&_Reading_Material)){.external .text rel="nofollow"}):* *\"The GuC - an embedded [i486](https://www.wikiwand.com/en/I486){.external .text rel="nofollow"} core that supports graphics scheduling, power management and firmware attestation.\"* ##### [Software Architecture]{#Software_Architecture .mw-headline} *The following section is supported by [igor-blue.github.io](https://igor-blue.github.io/2021/02/10/graphics-part1.html){.external .text rel="nofollow"} (see reference [1](index.php/GPU_Firmware.html#References_(Talks_&_Reading_Material)){.external .text rel="nofollow"}, [2](index.php/GPU_Firmware.html#References_(Talks_&_Reading_Material)){.external .text rel="nofollow"}):* *\"The μOS kernel runs in 32-bit protected mode, with no paging and old-style segments model (CS, DS, etc'). All code run in ring0. The OS handles HW/SW exceptions and crashes, and supplies debugging and logging services.\"* *\"It runs a single process - which initializes the system and then waits for interrupts/events in a loop.\"* ###### []{#GuC_Blob_Checksum_.26_Code_Signing}[GuC Blob Checksum & Code Signing]{#GuC_Blob_Checksum_&_Code_Signing .mw-headline} *\"The bootrom verifies the firmware with a digital signature using a SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it to SRAM and starts executing.\"* ## [Nvidia]{#Nvidia .mw-headline} ### [Firmware Images]{#Firmware_Images_2 .mw-headline} This section will cover firmware images used in Nvidia GPUs. ### [Embedded Controllers]{#Embedded_Controllers_2 .mw-headline} This section will cover firmware images as they apply to various embedded controllers within the Nvidia GPU. #### []{#Falcon_.2F_NV-RISCV}[Falcon / NV-RISCV]{#Falcon_/_NV-RISCV .mw-headline} The Fast Logic CONtroller (Falcon) and Nvidia RISC-V ([NV-RISCV](https://riscv.org/wp-content/uploads/2016/07/Tue1100_Nvidia_RISCV_Story_V2.pdf){.external .text rel="nofollow"}) processors run the NvOS. #### [GSP]{#GSP .mw-headline} The GPU System Processor (GSP) is an embedded controller used for offload of the RM Core. The GSP runs [Library Operating System (LibOS)](https://lwn.net/Articles/637658/){.external .text rel="nofollow"}. ##### []{#GSP_Initialization_.26_Offload}[GSP Initialization & Offload]{#GSP_Initialization_&_Offload .mw-headline} The [GSP is initialized multiple times](index.php/GPU_Driver_Internals.html#Initialization_3){.external .text rel="nofollow"} during the system\'s bring up and runtime. GSP offload may occur during: - Hardware bring up when a cached version of the RM Core is loaded from SPI flash ```{=html} ``` - During host driver bring up when the RM Core is offloaded by the [OpenRM driver](index.php/OpenRM.html){.external .text rel="nofollow"}. - During guest driver bring up when the RM Core is offloaded. -------------------------------------------------------------------------------- ---------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Load Source Payload Notes [SPI Flash](https://wiki.segger.com/SPI_Flash){.external .text rel="nofollow"} Cached RM Core Used as a fallback in case of no rm offload. OpenRM RM Core This is the RM Core which was traditionally contained in the proprietary RM driver. VGX Guest Guest RM Core Future OpenRM guests may accomplish RM offload via GSP stubs (controlled via [gspHeapSize](https://github.com/NVIDIA/open-gpu-kernel-modules/blob/758b4ee8189c5198504cb1c3c5bc29027a9118a3/src/common/sdk/nvidia/inc/ctrl/ctrla081.h#L102){.external .text rel="nofollow"}?). -------------------------------------------------------------------------------- ---------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- : Possible GSP Offloads #### [CMU]{#CMU .mw-headline} ## [AMD]{#AMD .mw-headline} ## []{#References_.28Talks_.26_Reading_Material.29}[References (Talks & Reading Material)]{#References_(Talks_&_Reading_Material) .mw-headline} 1. [Security of the Intel Graphics Stack - Part 1 - Introduction](https://igor-blue.github.io/2021/02/10/graphics-part1.html){.external .text rel="nofollow"} 2. [Security of the Intel Graphics Stack - Part 2 - FW \<-\> GuC](https://igor-blue.github.io/2021/02/24/graphics-part2.html){.external .text rel="nofollow"} 3. [Firmware Security Realizations Part 3: SPI Write Protections](https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/){.external .text rel="nofollow"} 4. [Intel® FSP: Firmware Solutions for the Internet of Things](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/fsp-firmware-solutions-iot-video.html){.external .text rel="nofollow"} ::: ::: printfooter Retrieved from \"[https://open-iov.org/index.php?title=GPU_Firmware&oldid=23779](index.php%3Ftitle=GPU_Firmware&oldid=23779.html){dir="ltr"}\" ::: ::: ::: {#catlinks .catlinks .catlinks-allhidden mw="interface"} ::: ::: ::: ::: {#mw-navigation} ## Navigation menu ::: {#mw-head} ### Personal tools {#p-personal-label .vector-menu-heading} ::: vector-menu-content - [[Log in](https://open-iov.org/index.php?title=Special:UserLogin&returnto=GPU+Firmware&returntoquery=oldid%3D23779 "You are encouraged to log in; however, it is not mandatory [o]"){accesskey="o"}]{#pt-login} ::: ::: {#left-navigation} ### Namespaces {#p-namespaces-label .vector-menu-heading} ::: vector-menu-content - [[Page](index.php/GPU_Firmware.html "View the content page [c]"){accesskey="c"}]{#ca-nstab-main} - [[Discussion](https://open-iov.org/index.php?title=Talk:GPU_Firmware&action=edit&redlink=1 "Discussion about the content page (page does not exist) [t]"){rel="discussion" accesskey="t"}]{#ca-talk} ::: ### Variants [expanded]{.vector-menu-checkbox-expanded} [collapsed]{.vector-menu-checkbox-collapsed} {#p-variants-label .vector-menu-heading} ::: vector-menu-content ::: ::: ::: {#right-navigation} ### Views {#p-views-label .vector-menu-heading} ::: vector-menu-content - [[Read](index.php/GPU_Firmware.html)]{#ca-view} - [[View source](index.php%3Ftitle=GPU_Firmware&action=edit.html "This page is protected. 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