/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _GSP_DISPLAY_ENGINE_H_
#define _GSP_DISPLAY_ENGINE_H_

/*
 * Minimal host-side display (EVO) engine emulation for the emulated vGPU.
 *
 * The guest's nvidia-modeset programs the display channels through a small
 * push buffer per channel and kicks it by writing the channel's PUT register
 * in BAR0 (the UDISP channel control window).  On real hardware the display
 * engine consumes the methods, advances GET, and - when the push carries an
 * UPDATE (NVC37D/NVC57D_UPDATE 0x200) with the completion notifier armed -
 * writes an NV_DISP_NOTIFIER (status FINISHED) to the notifier surface the
 * guest allocated for the channel.  The driver then stops polling.
 *
 * This engine implements exactly that contract from the host side:
 *   - display channel registration from the RM control
 *     NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58),
 *     which carries the push-buffer guest physical address, size, class and
 *     instance;
 *   - the NVC57D method parser (METHOD/JUMP/NONINC/SET_SUBDEVICE_MASK),
 *     including the wrap JUMP the driver writes at the end of the ring;
 *   - GET emulation (write consumed offset into the channel control page);
 *   - SET_CONTEXT_DMA_NOTIFIER / SET_NOTIFIER_CONTROL tracking and the
 *     FINISHED notifier write on UPDATE;
 *   - a free-running raster line counter for NVC57E_GET_LINE so the driver's
 *     vblank/scanline reads make progress;
 *   - a vblank tick that posts the display event (best-effort; the mode set
 *     itself only needs the notifier).
 *
 * Everything here is host-side emulation of hardware behaviour; the guest
 * driver is unmodified.
 */

struct nv_vgpu_device;

#define GSP_DISP_CLASS_CORE	0xc57d
#define GSP_DISP_CLASS_WINDOW	0xc57e
#define GSP_DISP_CLASS_CURSOR	0xc57b
#define GSP_DISP_CLASS_BASE	0xc57a

/* Channel was announced by NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER. */
void gsp_disp_engine_channel_add(struct nv_vgpu_device *vgpu, u32 hclass,
				 u32 instance, u64 pb_pa, u64 limit,
				 u32 address_space, bool valid);

/*
 * A display channel object was allocated (RM handle).  The push buffer's
 * SET_CONTEXT_DMA_NOTIFIER carries a context-DMA handle, and the guest's
 * display instance memory hash table maps that handle to the notifier
 * surface address; the channel's own hObject is needed to post the
 * completion event the driver registered on it.
 */
void gsp_disp_engine_note_object(struct nv_vgpu_device *vgpu, u32 hclass,
				 u32 instance, u32 h_object);

/* Run one pass for a guest (called from the sema service thread). */
void gsp_disp_engine_pump(struct nv_vgpu_device *vgpu);

/* Drop all display channels of one guest (mdev cleanup). */
void gsp_disp_engine_vgpu_cleanup(struct nv_vgpu_device *vgpu);

int gsp_disp_engine_init(void);
void gsp_disp_engine_fini(void);

#endif /* _GSP_DISPLAY_ENGINE_H_ */