#ifndef _NV_VGPU_BAR_EMULATION_H_
#define _NV_VGPU_BAR_EMULATION_H_

#include "nvidia-vgpu-vfio.h"

struct nv_vgpu_bar_emul_ctx {
	struct nv_vgpu_device *vgpu;
	void *bar0_shadow;
	size_t bar0_shadow_size;
	spinlock_t shadow_lock;
	
	struct {
		u32 offset;
		u32 value;
		bool is_write;
		bool trapped;
	} trap_regs[256];
	int trap_count;
};

int nv_vgpu_bar_emul_init(struct nv_vgpu_device *vgpu);
void nv_vgpu_bar_emul_cleanup(struct nv_vgpu_device *vgpu);

int nv_vgpu_bar_trap_register(struct nv_vgpu_device *vgpu, int bar_idx,
			       u32 offset, u32 size);
int nv_vgpu_bar_untrap_register(struct nv_vgpu_device *vgpu, int bar_idx,
				 u32 offset);

int nv_vgpu_bar_emul_read(struct nv_vgpu_device *vgpu, int bar_idx,
			   u64 offset, void *val, size_t size);
int nv_vgpu_bar_emul_write(struct nv_vgpu_device *vgpu, int bar_idx,
			    u64 offset, void *val, size_t size);

int nv_vgpu_bar_emul_handle_fault(struct nv_vgpu_device *vgpu,
				   unsigned long addr, bool write);

static inline u32 nv_vgpu_read_reg(void __iomem *base, u32 offset)
{
	return readl(base + offset);
}

static inline void nv_vgpu_write_reg(void __iomem *base, u32 offset, u32 val)
{
	writel(val, base + offset);
}

static inline u64 nv_vgpu_read_reg64(void __iomem *base, u32 offset)
{
	return readq(base + offset);
}

static inline void nv_vgpu_write_reg64(void __iomem *base, u32 offset, u64 val)
{
	writeq(val, base + offset);
}

#endif