/* * TU104 Hardware Tables for GSP-RM Emulation * * Static device/engine/interrupt tables for the emulated TU104 GPU. * Derived from device/engine interface definitions, observed GSP-RM * behaviour, and hardware reference headers (hwref/turing/tu104). * * These tables replace what the real GSP-RM firmware would read from * PTOP hardware registers during boot. */ #ifndef _GSP_RM_TU104_H_ #define _GSP_RM_TU104_H_ #include /* ============================================================ * Wire structures (from 570.144 reference, ABI-checked) * ============================================================ */ /* NV2080_CTRL_FIFO_DEVICE_ENTRY (ctrl2080fifo.h) - 100 bytes */ struct tu104_fifo_device_entry { u32 engineData[16]; /* ENGINE_INFO_TYPE_* indexed */ u32 pbdmaIds[2]; u32 pbdmaFaultIds[2]; u32 numPbdmas; char engineName[16]; }; /* NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS - 3212 bytes max */ #define TU104_FIFO_TABLE_MAX_ENTRIES 32 #define TU104_FIFO_TABLE_MAX_DEVICES 256 struct tu104_fifo_get_device_info_params { u32 baseIndex; u32 numEntries; u8 bMore; u8 _pad[3]; struct tu104_fifo_device_entry entries[TU104_FIFO_TABLE_MAX_ENTRIES]; }; /* NV2080_CTRL_INTERNAL_DEVICE_INFO (ctrl2080internal.h) - 48 bytes */ struct tu104_internal_device_info { u32 faultId; u32 instanceId; u32 typeEnum; u32 resetId; u32 devicePriBase; u32 isEngine; u32 rlEngId; u32 runlistPriBase; u32 groupId; u32 ginTargetId; u32 deviceBroadcastPriBase; u32 groupLocalInstanceId; }; /* NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS - up to 512 entries */ #define TU104_INTERNAL_TABLE_MAX_ENTRIES 512 struct tu104_internal_get_device_info_params { u32 numEntries; struct tu104_internal_device_info deviceInfoTable[TU104_INTERNAL_TABLE_MAX_ENTRIES]; }; /* NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS */ #define TU104_INTR_TABLE_MAX_SIZE 128 struct tu104_intr_table_entry { u16 engineIdx; u16 _pad0; u32 pmcIntrMask; u32 vectorStall; u32 vectorNonStall; }; /* NV2080_INTR_CATEGORY_SUBTREE_MAP (ctrl2080internal.h) - 2 bytes */ struct tu104_intr_subtree_map { u8 subtreeStart; u8 subtreeEnd; }; /* NV2080_INTR_CATEGORY enum */ #define TU104_INTR_CATEGORY_DEFAULT 0 #define TU104_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE 1 #define TU104_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION 2 #define TU104_INTR_CATEGORY_RUNLIST 3 #define TU104_INTR_CATEGORY_RUNLIST_NOTIFICATION 4 #define TU104_INTR_CATEGORY_UVM_OWNED 5 #define TU104_INTR_CATEGORY_UVM_SHARED 6 #define TU104_INTR_CATEGORY_ENUM_COUNT 7 #define TU104_INTR_INVALID_SUBTREE 0xFF struct tu104_intr_get_kernel_table_params { u32 tableLen; struct tu104_intr_table_entry table[TU104_INTR_TABLE_MAX_SIZE]; struct tu104_intr_subtree_map subtreeMap[TU104_INTR_CATEGORY_ENUM_COUNT]; }; /* NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO (ctrl2080gpu.h) - 20 bytes */ struct tu104_constructed_falcon_info { u32 engDesc; u32 ctxAttr; u32 ctxBufferSize; u32 addrSpaceList; u32 registerBase; }; #define TU104_MAX_CONSTRUCTED_FALCONS 0x40 struct tu104_get_constructed_falcon_info_params { u32 numConstructedFalcons; struct tu104_constructed_falcon_info constructedFalconsTable[TU104_MAX_CONSTRUCTED_FALCONS]; }; /* ============================================================ * ENGINE_INFO_TYPE indices (engine_info.h) - frozen vGPU ABI * ============================================================ */ #define EI_ENG_DESC 0 #define EI_FIFO_TAG 1 #define EI_RM_ENGINE_TYPE 2 #define EI_RUNLIST 3 #define EI_MMU_FAULT_ID 4 #define EI_RC_MASK 5 #define EI_RESET 6 #define EI_INTR 7 #define EI_MC 8 #define EI_DEV_TYPE_ENUM 9 #define EI_INSTANCE_ID 10 #define EI_RUNLIST_PRI_BASE 11 #define EI_IS_HOST_DRIVEN_ENGINE 12 #define EI_RUNLIST_ENGINE_ID 13 #define EI_CHRAM_PRI_BASE 14 #define EI_KERNEL_RM_MAX 15 /* ============================================================ * ENG_DESC values (MKENGDESC = classId << 8 | instance) * ============================================================ */ #define TU104_ENG_GR0 0xd334df00 /* classId(Graphics)=0xd334df, inst 0 */ #define TU104_ENG_CE0 0x793ceb00 /* classId(OBJCE)=0x793ceb, inst 0 */ #define TU104_ENG_CE1 0x793ceb01 #define TU104_ENG_CE2 0x793ceb02 #define TU104_ENG_CE3 0x793ceb03 #define TU104_ENG_CE4 0x793ceb04 #define TU104_ENG_NVDEC0 0x8f99e100 /* classId(OBJBSP)=0x8f99e1, inst 0 */ #define TU104_ENG_NVDEC1 0x8f99e101 #define TU104_ENG_NVENC0 0xe97b6c00 /* classId(OBJMSENC)=0xe97b6c, inst 0 */ #define TU104_ENG_SEC2 0x28c40800 /* classId(OBJSEC2)=0x28c408, inst 0 */ #define TU104_ENG_NVJPG 0x2b3a5400 /* classId(OBJNVJPG)=0x2b3a54, inst 0 */ #define TU104_ENG_SW 0x95a6f500 /* classId(OBJSWENG)=0x95a6f5, inst 0 */ #define TU104_ENG_FBFLCN 0x8a20bf00 /* classId(OBJFBFLCN)=0x8a20bf, inst 0 */ /* ============================================================ * RM_ENGINE_TYPE values (gpu_engine_type.h) * ============================================================ */ #define TU104_RM_ENGINE_GR0 0x01 #define TU104_RM_ENGINE_CE0 0x09 #define TU104_RM_ENGINE_CE1 0x0a #define TU104_RM_ENGINE_CE2 0x0b #define TU104_RM_ENGINE_CE3 0x0c #define TU104_RM_ENGINE_CE4 0x0d #define TU104_RM_ENGINE_NVDEC0 0x1d #define TU104_RM_ENGINE_NVDEC1 0x1e #define TU104_RM_ENGINE_NVENC0 0x25 #define TU104_RM_ENGINE_SW 0x2d #define TU104_RM_ENGINE_SEC2 0x31 #define TU104_RM_ENGINE_HOST 0x32 #define TU104_RM_ENGINE_PMU 0x34 #define TU104_RM_ENGINE_FBFLCN 0x35 #define TU104_RM_ENGINE_NVJPG0 0x36 /* ============================================================ * MC_ENGINE_IDX values (engine_idx.h) * ============================================================ */ #define TU104_MC_ENGINE_GR 84 #define TU104_MC_ENGINE_CE0 15 #define TU104_MC_ENGINE_CE1 16 #define TU104_MC_ENGINE_CE2 17 #define TU104_MC_ENGINE_CE3 18 #define TU104_MC_ENGINE_CE4 19 #define TU104_MC_ENGINE_NVDEC0 65 #define TU104_MC_ENGINE_NVDEC1 66 #define TU104_MC_ENGINE_NVENC0 38 #define TU104_MC_ENGINE_SEC2 47 #define TU104_MC_ENGINE_NVJPG 51 /* ============================================================ * NV_PFAULT_MMU_ENG_ID values (tu104/dev_fault.h) * ============================================================ */ #define TU104_FAULT_ID_GR 64 #define TU104_FAULT_ID_CE0 15 #define TU104_FAULT_ID_CE1 16 #define TU104_FAULT_ID_CE2 17 #define TU104_FAULT_ID_CE3 18 #define TU104_FAULT_ID_CE4 19 #define TU104_FAULT_ID_NVDEC0 10 #define TU104_FAULT_ID_NVDEC1 25 #define TU104_FAULT_ID_NVENC0 11 #define TU104_FAULT_ID_SEC2 14 #define TU104_FAULT_ID_NVJPG0 24 #define TU104_FAULT_ID_GSP 2 #define TU104_FAULT_ID_PMU 6 /* PBDMA fault ID base (NV_PFIFO_CFG0_PBDMA_FAULT_ID_INIT = 32) */ #define TU104_PBDMA_FAULT_ID_BASE 32 #define TU104_NUM_PBDMAS 12 /* ============================================================ * ROBUST_CHANNEL values (rc.h) * ============================================================ */ #define TU104_RC_GRAPHICS 40 #define TU104_RC_CE0 22 #define TU104_RC_CE1 23 #define TU104_RC_CE2 24 #define TU104_RC_CE3 25 #define TU104_RC_CE4 26 #define TU104_RC_NVDEC0 14 #define TU104_RC_NVDEC1 15 #define TU104_RC_NVENC0 11 #define TU104_RC_SEC2 2 #define TU104_RC_NVJPG0 32 /* ============================================================ * NV_PTOP_DEVICE_INFO_TYPE_ENUM (tu104/dev_top.h) * ============================================================ */ #define TU104_PTOP_TYPE_GRAPHICS 0 #define TU104_PTOP_TYPE_LCE 19 #define TU104_PTOP_TYPE_NVDEC 16 #define TU104_PTOP_TYPE_NVENC 14 #define TU104_PTOP_TYPE_NVJPG 21 #define TU104_PTOP_TYPE_SEC 13 #define TU104_PTOP_TYPE_GSP 20 #define TU104_PTOP_TYPE_IOCTRL 18 /* ============================================================ * FIFO_TAG values (hardware engine enum, 4 bits) * ============================================================ */ #define TU104_TAG_GR 0 #define TU104_TAG_CE0 1 #define TU104_TAG_CE1 2 #define TU104_TAG_CE2 3 #define TU104_TAG_CE3 4 #define TU104_TAG_CE4 5 #define TU104_TAG_NVDEC0 10 #define TU104_TAG_NVDEC1 11 #define TU104_TAG_NVENC0 13 #define TU104_TAG_NVJPG 14 #define TU104_TAG_SEC2 15 /* ============================================================ * TU104 FIFO Engine Table (11 hardware engines + 1 SW) * * Runlist assignment: each engine gets its own runlist. * Runlist 0=GR, 1-5=CE0-CE4, 6-7=NVDEC0-1, 8=NVENC0, 9=SEC2, 10=NVJPG * PBDMA assignment: 1:1 with runlists (PBDMA N services runlist N). * SW engine shares NVJPG's runlist/PBDMA (per fifoConstructSwEngine). * ============================================================ */ static const struct tu104_fifo_device_entry tu104_engine_table[] = { /* [0] GR0 - Graphics */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_GR0, [EI_FIFO_TAG] = TU104_TAG_GR, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_GR0, [EI_RUNLIST] = 0, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_GR, [EI_RC_MASK] = TU104_RC_GRAPHICS, [EI_RESET] = 12, /* NV_PMC_ENABLE_PGRAPH bit */ [EI_INTR] = 0, [EI_MC] = TU104_MC_ENGINE_GR, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_GRAPHICS, [EI_INSTANCE_ID] = 0, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {0, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 0, 0}, .numPbdmas = 1, .engineName = "GRAPHICS", }, /* [1] CE0 */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_CE0, [EI_FIFO_TAG] = TU104_TAG_CE0, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CE0, [EI_RUNLIST] = 1, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_CE0, [EI_RC_MASK] = TU104_RC_CE0, [EI_RESET] = 1, [EI_INTR] = 1, [EI_MC] = TU104_MC_ENGINE_CE0, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_LCE, [EI_INSTANCE_ID] = 0, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {1, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 1, 0}, .numPbdmas = 1, .engineName = "CE0", }, /* [2] CE1 */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_CE1, [EI_FIFO_TAG] = TU104_TAG_CE1, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CE1, [EI_RUNLIST] = 2, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_CE1, [EI_RC_MASK] = TU104_RC_CE1, [EI_RESET] = 2, [EI_INTR] = 2, [EI_MC] = TU104_MC_ENGINE_CE1, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_LCE, [EI_INSTANCE_ID] = 1, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {2, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 2, 0}, .numPbdmas = 1, .engineName = "CE1", }, /* [3] CE2 */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_CE2, [EI_FIFO_TAG] = TU104_TAG_CE2, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CE2, [EI_RUNLIST] = 3, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_CE2, [EI_RC_MASK] = TU104_RC_CE2, [EI_RESET] = 3, [EI_INTR] = 3, [EI_MC] = TU104_MC_ENGINE_CE2, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_LCE, [EI_INSTANCE_ID] = 2, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {3, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 3, 0}, .numPbdmas = 1, .engineName = "CE2", }, /* [4] CE3 */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_CE3, [EI_FIFO_TAG] = TU104_TAG_CE3, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CE3, [EI_RUNLIST] = 4, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_CE3, [EI_RC_MASK] = TU104_RC_CE3, [EI_RESET] = 4, [EI_INTR] = 4, [EI_MC] = TU104_MC_ENGINE_CE3, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_LCE, [EI_INSTANCE_ID] = 3, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {4, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 4, 0}, .numPbdmas = 1, .engineName = "CE3", }, /* [5] CE4 */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_CE4, [EI_FIFO_TAG] = TU104_TAG_CE4, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CE4, [EI_RUNLIST] = 5, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_CE4, [EI_RC_MASK] = TU104_RC_CE4, [EI_RESET] = 5, [EI_INTR] = 5, [EI_MC] = TU104_MC_ENGINE_CE4, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_LCE, [EI_INSTANCE_ID] = 4, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {5, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 5, 0}, .numPbdmas = 1, .engineName = "CE4", }, /* [6] NVDEC0 */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_NVDEC0, [EI_FIFO_TAG] = TU104_TAG_NVDEC0, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_NVDEC0, [EI_RUNLIST] = 6, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_NVDEC0, [EI_RC_MASK] = TU104_RC_NVDEC0, [EI_RESET] = 14, [EI_INTR] = 6, [EI_MC] = TU104_MC_ENGINE_NVDEC0, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_NVDEC, [EI_INSTANCE_ID] = 0, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {6, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 6, 0}, .numPbdmas = 1, .engineName = "NVDEC0", }, /* [7] NVDEC1 */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_NVDEC1, [EI_FIFO_TAG] = TU104_TAG_NVDEC1, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_NVDEC1, [EI_RUNLIST] = 7, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_NVDEC1, [EI_RC_MASK] = TU104_RC_NVDEC1, [EI_RESET] = 15, [EI_INTR] = 7, [EI_MC] = TU104_MC_ENGINE_NVDEC1, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_NVDEC, [EI_INSTANCE_ID] = 1, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {7, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 7, 0}, .numPbdmas = 1, .engineName = "NVDEC1", }, /* [8] NVENC0 */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_NVENC0, [EI_FIFO_TAG] = TU104_TAG_NVENC0, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_NVENC0, [EI_RUNLIST] = 8, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_NVENC0, [EI_RC_MASK] = TU104_RC_NVENC0, [EI_RESET] = 17, [EI_INTR] = 8, [EI_MC] = TU104_MC_ENGINE_NVENC0, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_NVENC, [EI_INSTANCE_ID] = 0, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {8, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 8, 0}, .numPbdmas = 1, .engineName = "NVENC0", }, /* [9] SEC2 */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_SEC2, [EI_FIFO_TAG] = TU104_TAG_SEC2, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_SEC2, [EI_RUNLIST] = 9, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_SEC2, [EI_RC_MASK] = TU104_RC_SEC2, [EI_RESET] = 19, [EI_INTR] = 9, [EI_MC] = TU104_MC_ENGINE_SEC2, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_SEC, [EI_INSTANCE_ID] = 0, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {9, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 9, 0}, .numPbdmas = 1, .engineName = "SEC2", }, /* [10] NVJPG */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_NVJPG, [EI_FIFO_TAG] = TU104_TAG_NVJPG, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_NVJPG0, [EI_RUNLIST] = 10, [EI_MMU_FAULT_ID] = TU104_FAULT_ID_NVJPG0, [EI_RC_MASK] = TU104_RC_NVJPG0, [EI_RESET] = 20, [EI_INTR] = 10, [EI_MC] = TU104_MC_ENGINE_NVJPG, [EI_DEV_TYPE_ENUM] = TU104_PTOP_TYPE_NVJPG, [EI_INSTANCE_ID] = 0, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 1, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {10, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 10, 0}, .numPbdmas = 1, .engineName = "NVJPG", }, /* [11] SW (software engine - shares NVJPG's runlist per fifoConstructSwEngine) */ { .engineData = { [EI_ENG_DESC] = TU104_ENG_SW, [EI_FIFO_TAG] = 0xffffffff, [EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_SW, [EI_RUNLIST] = 10, /* NVJPG's runlist */ [EI_MMU_FAULT_ID] = 0xffffffff, [EI_RC_MASK] = 0, [EI_RESET] = 0, [EI_INTR] = 0, [EI_MC] = 0, [EI_DEV_TYPE_ENUM] = 0, [EI_INSTANCE_ID] = 0, [EI_RUNLIST_PRI_BASE] = 0, [EI_IS_HOST_DRIVEN_ENGINE] = 0, [EI_RUNLIST_ENGINE_ID] = 0, [EI_CHRAM_PRI_BASE] = 0, [EI_KERNEL_RM_MAX] = 0, }, .pbdmaIds = {10, 0}, .pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 10, 0}, .numPbdmas = 1, .engineName = "SOFTWARE", }, }; #define TU104_ENGINE_TABLE_SIZE 12 /* ============================================================ * TU104 Interrupt Table (from intr_phys_tu102.c, kernel table) * * These are the CPU-RM (guest) visible interrupts. * NV_PMC_INTR_INVALID_MASK = 0 (no PMC mask for these). * NV_INTR_VECTOR_INVALID = 0xFFFFFFFF. * ============================================================ */ #define TU104_NV_INTR_VECTOR_INVALID 0xFFFFFFFF static const struct tu104_intr_table_entry tu104_intr_kernel_table[] = { /* MC_ENGINE_IDX_REPLAYABLE_FAULT = 59 */ { .engineIdx = 59, .pmcIntrMask = 0, .vectorStall = 64, /* NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_REPLAYABLE */ .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID }, /* MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR = 62 */ { .engineIdx = 62, .pmcIntrMask = 0, .vectorStall = 131, /* NV_PFB_PRI_MMU_INT_VECTOR_FAULT_ERROR_REPLAYABLE */ .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID }, /* MC_ENGINE_IDX_ACCESS_CNTR = 60 */ { .engineIdx = 60, .pmcIntrMask = 0, .vectorStall = 72, /* HUB_ACCESS_CNTR_INTR_VECTOR */ .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID }, /* MC_ENGINE_IDX_CPU_DOORBELL = 73 */ { .engineIdx = 73, .pmcIntrMask = 0, .vectorStall = 129, /* NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT */ .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID }, /* MC_ENGINE_IDX_PRIV_DOORBELL = 74 */ { .engineIdx = 74, .pmcIntrMask = 0, .vectorStall = 130, /* NV_CTRL_VIRTUAL_INTR_VECTORID_VALUE_CONSTANT */ .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID }, /* MC_ENGINE_IDX_GR_FECS_LOG = 156 */ { .engineIdx = 156, .pmcIntrMask = 0, .vectorStall = TU104_NV_INTR_VECTOR_INVALID, .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID }, /* MC_ENGINE_IDX_GSP = 50 */ { .engineIdx = 50, .pmcIntrMask = 0, .vectorStall = 155, /* GSP_INTR_0_VECTOR */ .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID }, /* MC_ENGINE_IDX_DISP = 2 */ { .engineIdx = 2, .pmcIntrMask = 0, .vectorStall = 154, /* PDISP_VECTOR */ .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID }, }; #define TU104_INTR_KERNEL_TABLE_SIZE 8 /* ============================================================ * TU104 Constructed Falcon Table * * Only FBFLCN (framebuffer falcon) is a "constructed falcon" on Turing * (SEC2, GSP, PMU are skipped as they have their own kernel objects). * ============================================================ */ static const struct tu104_constructed_falcon_info tu104_falcon_table[] = { { .engDesc = TU104_ENG_FBFLCN, .ctxAttr = 0, .ctxBufferSize = 0x400, /* 1KB context buffer */ .addrSpaceList = 0, .registerBase = 0x009a4000, /* NV_PFBFALCON base */ }, }; #define TU104_FALCON_TABLE_SIZE 1 /* ============================================================ * TU104 Internal Device Info Table * * Engines + key non-engine devices. The guest driver queries this * by typeEnum to find device register bases and fault IDs. * ============================================================ */ static const struct tu104_internal_device_info tu104_internal_device_table[] = { /* Engines (isEngine=1) */ { .faultId = TU104_FAULT_ID_GR, .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_GRAPHICS, .resetId = 12, .devicePriBase = 0x00400000, .isEngine = 1, .rlEngId = 0, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 }, { .faultId = TU104_FAULT_ID_CE0, .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_LCE, .resetId = 1, .devicePriBase = 0x00040000, .isEngine = 1, .rlEngId = 1, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 }, { .faultId = TU104_FAULT_ID_CE1, .instanceId = 1, .typeEnum = TU104_PTOP_TYPE_LCE, .resetId = 2, .devicePriBase = 0x00041000, .isEngine = 1, .rlEngId = 2, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 1 }, { .faultId = TU104_FAULT_ID_CE2, .instanceId = 2, .typeEnum = TU104_PTOP_TYPE_LCE, .resetId = 3, .devicePriBase = 0x00042000, .isEngine = 1, .rlEngId = 3, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 2 }, { .faultId = TU104_FAULT_ID_CE3, .instanceId = 3, .typeEnum = TU104_PTOP_TYPE_LCE, .resetId = 4, .devicePriBase = 0x00043000, .isEngine = 1, .rlEngId = 4, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 3 }, { .faultId = TU104_FAULT_ID_CE4, .instanceId = 4, .typeEnum = TU104_PTOP_TYPE_LCE, .resetId = 5, .devicePriBase = 0x00044000, .isEngine = 1, .rlEngId = 5, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 4 }, { .faultId = TU104_FAULT_ID_NVDEC0, .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_NVDEC, .resetId = 14, .devicePriBase = 0x00060000, .isEngine = 1, .rlEngId = 6, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 }, { .faultId = TU104_FAULT_ID_NVDEC1, .instanceId = 1, .typeEnum = TU104_PTOP_TYPE_NVDEC, .resetId = 15, .devicePriBase = 0x00061000, .isEngine = 1, .rlEngId = 7, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 1 }, { .faultId = TU104_FAULT_ID_NVENC0, .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_NVENC, .resetId = 17, .devicePriBase = 0x00070000, .isEngine = 1, .rlEngId = 8, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 }, { .faultId = TU104_FAULT_ID_SEC2, .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_SEC, .resetId = 19, .devicePriBase = 0x00840000, .isEngine = 1, .rlEngId = 9, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 }, { .faultId = TU104_FAULT_ID_NVJPG0, .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_NVJPG, .resetId = 20, .devicePriBase = 0x00080000, .isEngine = 1, .rlEngId = 10, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 }, }; #define TU104_INTERNAL_DEVICE_TABLE_SIZE 11 /* ============================================================ * GspStaticConfigInfo field offsets (ABI-verified, 1656 bytes total) * ============================================================ */ #define TU104_GSCI_OFF_grCapsBits 0 /* 23 bytes */ #define TU104_GSCI_OFF_gidInfo 24 /* 268 bytes */ #define TU104_GSCI_OFF_SKUInfo 292 /* 48 bytes */ #define TU104_GSCI_OFF_fbRegionInfoParams 344 /* 776 bytes */ #define TU104_GSCI_OFF_sriovCaps 1120 /* 80 bytes */ #define TU104_GSCI_OFF_sriovMaxGfid 1200 /* 4 bytes */ #define TU104_GSCI_OFF_engineCaps 1204 /* 12 bytes */ #define TU104_GSCI_OFF_poisonFuseEnabled 1216 /* 1 byte */ #define TU104_GSCI_OFF_fb_length 1224 /* 8 bytes */ #define TU104_GSCI_OFF_fbio_mask 1232 /* 8 bytes */ #define TU104_GSCI_OFF_fb_bus_width 1240 /* 4 bytes */ #define TU104_GSCI_OFF_fb_ram_type 1244 /* 4 bytes */ #define TU104_GSCI_OFF_fbp_mask 1248 /* 8 bytes */ #define TU104_GSCI_OFF_l2_cache_size 1256 /* 4 bytes */ #define TU104_GSCI_OFF_gpuNameString 1260 /* 64 bytes */ #define TU104_GSCI_OFF_gpuShortNameString 1324 /* 64 bytes */ #define TU104_GSCI_OFF_gpuNameString_Unicode 1388 /* 128 bytes */ #define TU104_GSCI_OFF_bIsMobile 1524 /* 1 byte */ #define TU104_GSCI_OFF_bar1PdeBase 1536 /* 8 bytes */ #define TU104_GSCI_OFF_bar2PdeBase 1544 /* 8 bytes */ #define TU104_GSCI_OFF_bVbiosValid 1552 /* 1 byte */ #define TU104_GSCI_OFF_vbiosSubVendor 1556 /* 4 bytes */ #define TU104_GSCI_OFF_vbiosSubDevice 1560 /* 4 bytes */ #define TU104_GSCI_OFF_hInternalClient 1600 /* 4 bytes */ #define TU104_GSCI_OFF_hInternalDevice 1604 /* 4 bytes */ #define TU104_GSCI_OFF_hInternalSubdevice 1608 /* 4 bytes */ #define TU104_GSCI_OFF_ecidInfo 1616 /* 24 bytes */ #define TU104_GSCI_OFF_fwWprLayoutOffset 1640 /* 16 bytes */ #define TU104_GSCI_SIZE 1656 /* Internal handle values (g_gpu_nvoc.h, g_resserv_nvoc.h) */ #define TU104_H_INTERNAL_CLIENT 0xC1E00000 #define TU104_H_INTERNAL_DEVICE 0xABCD0080 #define TU104_H_INTERNAL_SUBDEVICE 0xABCD2080 /* GSP_RM_CONTROL sub-commands */ #define TU104_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE 0x20800a40 #define TU104_CTRL_FIFO_GET_DEVICE_INFO_TABLE 0x20801112 #define TU104_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE 0x20800a5c #define TU104_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO 0x208001b0 #define TU104_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS 0x20800a61 #define TU104_CTRL_BUS_GET_PCI_BAR_INFO 0x20801803 #define TU104_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO 0x20800a01 #define TU104_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION 0x20800a4b #define TU104_CTRL_I2C_TRANSACTION 0x402c0105 #define TU104_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE 0x20802a08 #define TU104_CTRL_CE_GET_PHYSICAL_CAPS 0x20802a07 #define TU104_CTRL_CE_GET_ALL_PHYSICAL_CAPS 0x20802a0b #define TU104_CTRL_CE_GET_ALL_CAPS 0x20802a0a #define TU104_CTRL_CE_GET_CE_PCE_MASK 0x20802a02 /* CE capability bits (NV2080_CTRL_CE_CAPS_*, ctrl2080ce.h: byte:bit) */ #define TU104_CE_CAPS0_SYSMEM_READ 0x04 #define TU104_CE_CAPS0_SYSMEM_WRITE 0x08 #define TU104_CE_CAPS0_SYSMEM 0x20 #define TU104_CE_CAPS0_P2P 0x40 #define TU104_CE_CAPS0_BL_GT_64K 0x80 #define TU104_CE_CAPS0 (TU104_CE_CAPS0_SYSMEM_READ | \ TU104_CE_CAPS0_SYSMEM_WRITE | \ TU104_CE_CAPS0_SYSMEM | \ TU104_CE_CAPS0_P2P | \ TU104_CE_CAPS0_BL_GT_64K) #define TU104_CE_CAPS1 0x00 /* ENGINE_TYPE_COPY0 = 0x9, COPY(i) = COPY0 + i (cl2080_notification.h) */ #define TU104_ENGINE_TYPE_COPY0 0x00000009 #define TU104_NUM_CES 5 #define TU104_CTRL_INTERNAL_GMMU_GET_STATIC_INFO 0x20800a59 #define TU104_CTRL_STATIC_KGR_GET_GLOBAL_SM_ORDER 0x20800a22 #define TU104_CTRL_STATIC_KGR_GET_INFO 0x20800a2a #define TU104_CTRL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO 0x20800a32 /* NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO (engine context buffer info) * NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO: engine[ENGINE_ID_COUNT] * NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS: * engineContextBuffersInfo[GR_MAX_ENGINES] * * The driver's kgraphicsInitializeDeferredStaticData() asks the physical RM * (GSP-RM) for this table; kgrctxAllocMainCtxBuffer() then sizes the golden * image ctx buffer from engine[GRAPHICS].size. A zeroed reply produces a * 0-byte (0-page) allocation -> NV_ERR_NO_MEMORY (mem_desc.c:1353). * * The physical RM probes these sizes from the ctxsw ucode at GR init * (grSetupInitialCtxState -> grDiscoverCtxBufferSize) and reports * NV_U32_MAX for engine IDs the chip does not support. The values below are * the emulated TU104 layout (own buffers, no real GR engine behind them): * sizes are page-aligned scratch regions, NV_U32_MAX = "not supported". */ #define TU104_CTX_ENGINE_ID_COUNT 26 /* _ENGINE_ID_COUNT (0x1a) */ #define TU104_CTX_GPU_MAX_ENGINES 8 /* INTERNAL_GR_MAX_ENGINES */ /* NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_* */ #define TU104_CTX_ENG_GRAPHICS 0x00 #define TU104_CTX_ENG_VLD 0x01 #define TU104_CTX_ENG_VIDEO 0x02 #define TU104_CTX_ENG_MPEG 0x03 #define TU104_CTX_ENG_CAPTURE 0x04 #define TU104_CTX_ENG_DISPLAY 0x05 #define TU104_CTX_ENG_ENCRYPTION 0x06 #define TU104_CTX_ENG_POSTPROCESS 0x07 #define TU104_CTX_ENG_GRAPHICS_ZCULL 0x08 #define TU104_CTX_ENG_GRAPHICS_PM 0x09 #define TU104_CTX_ENG_COMPUTE_PREEMPT 0x0a #define TU104_CTX_ENG_GRAPHICS_PREEMPT 0x0b #define TU104_CTX_ENG_GRAPHICS_SPILL 0x0c #define TU104_CTX_ENG_GRAPHICS_PAGEPOOL 0x0d #define TU104_CTX_ENG_GRAPHICS_BETACB 0x0e #define TU104_CTX_ENG_GRAPHICS_RTV 0x0f #define TU104_CTX_ENG_GRAPHICS_PATCH 0x10 #define TU104_CTX_ENG_GRAPHICS_BUNDLE_CB 0x11 #define TU104_CTX_ENG_GRAPHICS_PAGEPOOL_GLOBAL 0x12 #define TU104_CTX_ENG_GRAPHICS_ATTRIBUTE_CB 0x13 #define TU104_CTX_ENG_GRAPHICS_RTV_CB_GLOBAL 0x14 #define TU104_CTX_ENG_GRAPHICS_GFXP_POOL 0x15 #define TU104_CTX_ENG_GRAPHICS_GFXP_CTRL_BLK 0x16 #define TU104_CTX_ENG_GRAPHICS_FECS_EVENT 0x17 #define TU104_CTX_ENG_GRAPHICS_PRIV_ACCESS_MAP 0x18 #define TU104_CTX_ENG_GRAPHICS_SETUP 0x19 /* grabbag: emulated ctx buffer sizes (bytes) */ #define TU104_CTX_SIZE_MAIN 0x200000 #define TU104_CTX_SIZE_ZCULL 0x100000 #define TU104_CTX_SIZE_PM 0x8000 #define TU104_CTX_SIZE_PREEMPT 0x1000 #define TU104_CTX_SIZE_SPILL 0x1000 #define TU104_CTX_SIZE_PAGEPOOL 0x10000 #define TU104_CTX_SIZE_BETACB 0x1000 #define TU104_CTX_SIZE_RTV 0x1000 #define TU104_CTX_SIZE_PATCH 0x2000 #define TU104_CTX_SIZE_BUNDLE_CB 0x1000 #define TU104_CTX_SIZE_ATTRIBUTE_CB 0x1000 #define TU104_CTX_SIZE_RTV_CB_GLOBAL 0x1000 #define TU104_CTX_SIZE_FECS_EVENT 0x1000 #define TU104_CTX_SIZE_PRIV_ACCESS_MAP 0x1000 struct tu104_ctx_buffer_info { u32 size; u32 alignment; }; struct tu104_gr_context_buffers_info { struct tu104_ctx_buffer_info engine[TU104_CTX_ENGINE_ID_COUNT]; }; struct tu104_gr_get_context_buffers_info_params { struct tu104_gr_context_buffers_info engineContextBuffersInfo[TU104_CTX_GPU_MAX_ENGINES]; }; /* FB_GET_INFO_V2 (ctrl2080fb.h): the client sends a list of requested FB info * indices; the physical RM must echo each index back with its data. * _fbGetFbInfos() asserts pFbInfos[i].index == returned index, so a zeroed * reply fires kern_mem_sys_ctrl.c:911 asserts and leaves all FB info zero * (CUDA/UVMLite read total/usable memory, BAR1 size, ECC/LTC info from here). */ #define TU104_CTRL_FB_GET_INFO_V2 0x20801303 #define TU104_FB_INFO_MAX_LIST_SIZE 0x80 struct tu104_fb_info_entry { u32 index; u32 data; }; struct tu104_fb_get_info_v2_params { u32 fbInfoListSize; struct tu104_fb_info_entry fbInfoList[TU104_FB_INFO_MAX_LIST_SIZE]; }; /* NV2080_CTRL_FB_INFO_INDEX_* (subset we populate) */ #define TU104_FB_INFO_IDX_TILE_REGION_COUNT 0x00 #define TU104_FB_INFO_IDX_COMPRESSION_SIZE 0x01 #define TU104_FB_INFO_IDX_PARTITION_COUNT 0x04 #define TU104_FB_INFO_IDX_BAR1_SIZE 0x05 #define TU104_FB_INFO_IDX_RAM_SIZE 0x07 #define TU104_FB_INFO_IDX_TOTAL_RAM_SIZE 0x08 #define TU104_FB_INFO_IDX_HEAP_SIZE 0x09 #define TU104_FB_INFO_IDX_MAPPABLE_HEAP_SIZE 0x0a #define TU104_FB_INFO_IDX_BUS_WIDTH 0x0b #define TU104_FB_INFO_IDX_RAM_TYPE 0x0d #define TU104_FB_INFO_IDX_BANK_COUNT 0x0e #define TU104_FB_INFO_IDX_FB_TAX_SIZE_KB 0x10 #define TU104_FB_INFO_IDX_LARGEST_FREE_REGION_SIZE_KB 0x12 #define TU104_FB_INFO_IDX_PARTITION_MASK 0x14 #define TU104_FB_INFO_IDX_HEAP_FREE 0x16 #define TU104_FB_INFO_IDX_RAM_LOCATION 0x17 #define TU104_FB_INFO_IDX_FBP_COUNT 0x19 #define TU104_FB_INFO_IDX_FBP_MASK 0x1a #define TU104_FB_INFO_IDX_L2CACHE_SIZE 0x1b #define TU104_FB_INFO_IDX_MEMORYINFO_VENDOR_ID 0x1c #define TU104_FB_INFO_IDX_BAR1_AVAIL_SIZE 0x1d #define TU104_FB_INFO_IDX_BAR1_MAX_CONTIG_AVAIL_SIZE 0x1f #define TU104_FB_INFO_IDX_USABLE_RAM_SIZE 0x20 #define TU104_FB_INFO_IDX_LTC_COUNT 0x22 #define TU104_FB_INFO_IDX_LTS_COUNT 0x23 #define TU104_FB_INFO_IDX_PSEUDO_CHANNEL_MODE 0x25 #define TU104_FB_INFO_IDX_ALLOW_PAGE_RETIREMENT 0x2a #define TU104_FB_INFO_IDX_LTC_MASK 0x2b #define TU104_RAM_TYPE_GDDR6 0x11 #define TU104_RAM_LOCATION_GPU_DEDICATED 0x00 #define TU104_PSEUDO_CHANNEL_MODE_DISABLED 0x01 #define TU104_MEMORYINFO_VENDOR_ID_SAMSUNG 0x01 #define TU104_L2CACHE_SIZE 0x400000 /* TU104: 4MB */ #define TU104_LTC_COUNT 8 #define TU104_LTS_COUNT 16 /* BUS_GET_INFO_V2 (ctrl2080bus.h) - same flat index/data list pattern as FB. * UVM's gpuGetSysmemLinkInfo() reads SYSMEM_CONNECTION_TYPE (PCIE) and then * PCIE_GPU_LINK_CAPS for the link bandwidth; a zeroed reply makes * getPCIELinkRateMBps() fail with NV_ERR_INVALID_STATE. */ #define TU104_CTRL_BUS_GET_INFO_V2 0x20801823 #define TU104_BUS_INFO_MAX_LIST_SIZE 0x34 struct tu104_bus_info_entry { u32 index; u32 data; }; struct tu104_bus_get_info_v2_params { u32 busInfoListSize; struct tu104_bus_info_entry busInfoList[TU104_BUS_INFO_MAX_LIST_SIZE]; }; /* NV2080_CTRL_BUS_INFO_INDEX_* (subset we populate) */ #define TU104_BUS_INFO_IDX_TYPE 0x00 #define TU104_BUS_INFO_IDX_INTLINE 0x01 #define TU104_BUS_INFO_IDX_PCIE_GPU_LINK_CAPS 0x03 #define TU104_BUS_INFO_IDX_PCIE_ROOT_LINK_CAPS 0x04 #define TU104_BUS_INFO_IDX_PCIE_UPSTREAM_LINK_CAPS 0x05 #define TU104_BUS_INFO_IDX_PCIE_DOWNSTREAM_LINK_CAPS 0x06 #define TU104_BUS_INFO_IDX_PCIE_GPU_LINK_CTRL_STATUS 0x07 #define TU104_BUS_INFO_IDX_PCIE_ROOT_LINK_CTRL_STATUS 0x08 #define TU104_BUS_INFO_IDX_PCIE_UPSTREAM_LINK_CTRL 0x09 #define TU104_BUS_INFO_IDX_PCIE_DOWNSTREAM_LINK_CTRL 0x0a #define TU104_BUS_INFO_IDX_PCIE_GEN_INFO 0x2d #define TU104_BUS_INFO_IDX_SYSMEM_CONNECTION_TYPE 0x33 #define TU104_BUS_INFO_TYPE_PCI_EXPRESS 0x03 #define TU104_BUS_INFO_SYSMEM_CONN_PCIE 0x00 /* PCIE link caps / GEN info layout: MAX_SPEED 3:0 (8000MBPS=3), MAX_WIDTH * 9:4 (lanes), ASPM 11:10, GEN 15:12, CURR_LEVEL 19:16, GPU_GEN 23:20 * (all GENx = 2 for Gen3), SPEED_CHANGES 24. */ #define TU104_PCIE_LINK_CAP_GEN3_X16 (0x3u | (16u << 4) | \ (2u << 12) | (2u << 16) | \ (2u << 20)) /* LINK_CTRL_STATUS: ASPM 1:0 (0=disabled), LINK_SPEED 19:16, * LINK_WIDTH 25:20 (LINK_WIDTH_X16=0x10). */ #define TU104_PCIE_LINK_CTRL_STATUS_GEN3_X16 ((0x3u << 16) | (0x10u << 20)) /* NV0080_CTRL_GR_INFO entry + infoList indices (ctrl0080gr.h) */ struct tu104_gr_info_entry { u32 index; u32 data; }; #define TU104_GR_INFO_MAX_SIZE 58 /* NV0080_CTRL_GR_INFO_MAX_SIZE (0x3a) */ #define TU104_GR_INFO_MAX_ENGINES 8 struct tu104_gr_static_info { struct tu104_gr_info_entry infoList[TU104_GR_INFO_MAX_SIZE]; }; /* infoList indices we populate (ctrl0080gr.h) */ #define TU104_GR_INFO_IDX_LITTER_NUM_GPCS 0x14 #define TU104_GR_INFO_IDX_LITTER_NUM_TPC_PER_GPC 0x17 #define TU104_GR_INFO_IDX_GPU_CORE_COUNT 0x1d #define TU104_GR_INFO_IDX_LITTER_NUM_SM_PER_TPC 0x20 #define TU104_GR_INFO_IDX_FAMILY_MAX_TPC_PER_GPC 0x2a #define TU104_GR_INFO_IDX_MAX_SUBCONTEXT_COUNT 0x2c #define TU104_GR_INFO_IDX_MAX_LEGACY_SUBCONTEXT_COUNT 0x2d #define TU104_GR_INFO_IDX_MAX_PER_ENGINE_SUBCONTEXT_COUNT 0x2e /* TU104 max subcontexts (NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT_INIT) */ #define TU104_MAX_SUBCONTEXT_COUNT 64 /* NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS (ctrl2080internal.h) * + STATIC_KGR_GET_FLOORSWEEPING_MASKS cmd = 0x20800a26. * Driver computes numGpcs from floorsweepingMasks.gpcMask - zero kills * krcWatchdogInit ("numGpcs > 0" assert -> RmInitAdapter bails). */ #define TU104_CTRL_STATIC_KGR_GET_FLOORSWEEPING_MASKS 0x20800a26 #define TU104_GR_MAX_GPC 12 #define TU104_GR_MAX_TPC_PER_GPC_COUNT 10 struct tu104_gr_floorsweeping_masks { u32 gpcMask; u32 tpcMask[TU104_GR_MAX_GPC]; u32 tpcCount[TU104_GR_MAX_GPC]; u32 physGpcMask; u32 mmuPerGpc[TU104_GR_MAX_GPC]; u32 tpcToPesMap[TU104_GR_MAX_TPC_PER_GPC_COUNT]; u32 numPesPerGpc[TU104_GR_MAX_GPC]; u32 zcullMask[TU104_GR_MAX_GPC]; u32 physGfxGpcMask; u32 numGfxTpc; }; /* TU104 SM topology: 6 GPCs x 4 TPCs x 2 SMs = 48 SMs, 24 TPCs (RTX 2080 SUPER) */ #define TU104_NUM_GPC 6 #define TU104_TPC_PER_GPC 4 #define TU104_SM_PER_TPC 2 #define TU104_NUM_SM (TU104_NUM_GPC * TU104_TPC_PER_GPC * TU104_SM_PER_TPC) #define TU104_NUM_TPC (TU104_NUM_GPC * TU104_TPC_PER_GPC) /* NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER (ctrl2080internal.h) */ #define TU104_GR_MAX_SM 240 #define TU104_GR_MAX_ENGINES 8 struct tu104_gr_sm_id { u16 gpcId; u16 localTpcId; u16 localSmId; u16 globalTpcId; u16 virtualGpcId; u16 migratableTpcId; }; struct tu104_gr_global_sm_order { struct tu104_gr_sm_id globalSmId[TU104_GR_MAX_SM]; u16 numSm; u16 numTpc; }; /* CE fault method buffer size (ceGetFaultMethodBufferSize_GV100 formula, * Turing inherits: 135 * (13*totalCes + 2), page-aligned; TU104 has 5 PCEs) */ #define TU104_CE_FAULT_METHOD_BUFFER_SIZE 12288 /* GMMU static info (kgmmuSetAndGetDefaultFaultBufferSize_TU102 semantics): * the hardware default is reported in NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ * BUFFER_SIZE_VAL units of NVC369_BUF_SIZE (32B). UVM's faultbufConstruct * allocates replayableFaultBufferSize and fails with NV_ERR_NO_MEMORY when * it reads back 0. Turing defaults are 64KB replayable / 4KB legacy; both * must stay within NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES (256). */ #define TU104_GMMU_REPLAYABLE_FAULT_BUFFER_SIZE 0x10000 #define TU104_GMMU_NONREPLAYABLE_FAULT_BUFFER_SIZE 0x1000 /* Turing display IP version (DISP v04.00 per DispIpHal halspec) */ #define TU104_DISPLAY_IP_VERSION 0x04000000 /* Channels per runlist reported to the guest (consumer Turing convention) */ #define TU104_FIFO_NUM_CHANNELS_PER_RUNLIST 64 /* FB region info params: numFBRegions(4) + 16 × 48B entries = 772 → aligned 776 */ struct tu104_fb_region { u64 base; u64 limit; u64 reserved; u32 performance; u8 supportCompressed; u8 supportISO; u8 bProtected; u8 blackList[17]; u8 _pad[6]; }; #endif /* _GSP_RM_TU104_H_ */