{ "schema": "greeneye-sim-profile/1", "name": "tu104-570.144", "description": "Turing TU104 GSP 570.144: device model windows, load layout and boot-shim assumptions. New firmware version = new profile, not a code fork.", "firmware": { "file": "firmware/57X-GSP/570.144/gsp-570.144.fwimage.bin", "sha256": "2d1bb5c60b208cfd115f015b17dd04a6fece05fd2c0dcba3625d9d48cce3ceea", "entry": "0x4009000", "link_base": "0x4000000", "max_vaddr": "0x5bb9000", "size": 28528288 }, "load": { "ram_base": "0x0", "memory_mb": 12288, "note": "firmware executes at its link addresses; PRIV/PMC is at 0x2000000000000000, local memory covers IMEM/DMEM/EMEM (0x0..0x300000000)." }, "devices": { "pmc": { "chip_id": "0x164", "major": 0, "minor": 0, "minor_ext": 0, "evidence": "NV_PMC_BOOT_42 at PMC+0xA00; CHIP_ID bits 28:20 compared against TU10x IDs by the boot code; TU104 = 0x164 (header field).", "windows": [ {"base": "0x2000000000000000", "size": "0x1000"} ] }, "falcon": { "shims": { "debuginfo_host_consume": true }, "debuginfo_stage_mask": "0x700000", "debuginfo_stage_shift": 20, "evidence": "Falcon register header offsets; boot writes MAILBOX0/MAILBOX1/DEBUGINFO/IRQSSET(HALT) and polls DEBUGINFO bits 22:20; DMA field layout and transfer semantics from the register header. DEBUGINFO host-consume is a boot shim, not a device claim.", "windows": [ {"base": "0x2000000000110000", "size": "0x1000"}, {"base": "0x300000000", "size": "0x1000"} ] }, "priscv": { "evidence": "RISC-V-local register header; boot reads TRACECTL/TRACE_RDIDX/TRACE_WTIDX/PRIV_ERR_STAT/IRQMASK through the libos private mapping at 0x300001000.", "windows": [ {"base": "0x2000000000111000", "size": "0x1000"}, {"base": "0x300001000", "size": "0x1000"} ] }, "timer": { "ns_per_insn": 1.0, "evidence": "PTIMER register header (NV_PTIMER_TIME_0 0x9400, TIME_1 0x9410). Values are MODELED from the instruction count; the firmware has not been observed reading this block in the 570.144 boot runs.", "windows": [ {"base": "0x2000000000009000", "size": "0x1000"} ] }, "fwsec": { "wpr2_start": "0x2000000", "wpr2_end": "0x6000000", "evidence": "PFB WPR2 ADDR_LO/HI register header (0x1FA824/0x1FA828, 4KiB alignment, HI points at the last 128KiB block); values are boot-shim supplied (host/booter-written on real hardware).", "windows": [ {"base": "0x20000000001FA000", "size": "0x1000"} ] }, "csb": { "evidence": "CSB/TRANSCOM message-window seam. No register semantics are modelled until a message-window poll is observed (B3); a profile may declare individual registers with width/value/semantics.", "registers": {}, "windows": [] }, "pmu": { "evidence": "PMU stub: no PMU register has been observed; every access stays unhandled and logged.", "windows": [] }, "gmmu": { "evidence": "GMMU/PRI-MMU register surface: NV_PFB_PRI_MMU_* offsets inside the PFB block (block range 0x00100000-0x00100FFF), the WPR/VPR/lock cluster (0x1FA7D8-0x1FA830) and the HSMMU block (0x001FAC00-0x001FAFFF) from the hardware register/field headers. Observe-only: no register semantics are modelled and no read value is invented; the B0-B2 runs did not touch these windows; the B3 wave's WPR2 read pair (0x1FA824/0x1FA828) falls in the wpr-lock window and is recorded observe-only (0 served).", "mode": "observe-only", "windows": [ {"base": "0x2000000000100C80", "size": "0x280", "label": "gmmu-pri-mmu", "registers": {"0x0": {"name": "NV_PFB_PRI_MMU_CTRL", "fields": {"VM_PG_SIZE": [0, 0], "VOL_FAULT": [1, 1], "COMP_FAULT": [2, 2], "MISS_GRAN": [4, 3], "CACHE_MODE": [6, 5], "PDE_CACHE_MODE": [8, 7], "L2_SEND_MODE": [9, 9], "WORK_CREATION_DISABLE": [10, 10], "USE_PDB_BIG_PAGE_SIZE": [11, 11], "USE_FULL_COMP_TAG_LINE": [12, 12], "PRI_FIFO_ERROR_CLEAR": [13, 13], "PRI_FIFO_ERROR": [14, 14], "PRI_FIFO_EMPTY": [15, 15], "PRI_FIFO_SPACE": [23, 16], "ATOMIC_CAPABILITY_MODE": [25, 24], "STRONG_BIT_ATOMIC_CYA": [26, 26], "STRONG_BIT_OVERRIDE_ATOMIC_DISABLE": [26, 26], "ATOMIC_CAPABILITY_SYS_NCOH_MODE": [27, 27], "MMU_APERTURE": [29, 28], "MMU_VOL": [30, 30], "MMU_DISABLE": [31, 31]}}, "0x4": {"name": "NV_PFB_PRI_MMU_PM"}, "0x8": {"name": "NV_PFB_PRI_MMU_PM_ADDR_LOW"}, "0xc": {"name": "NV_PFB_PRI_MMU_PM_ADDR_HIGH"}, "0x10": {"name": "NV_PFB_PRI_MMU_PM_UNIT_MASK"}, "0x14": {"name": "NV_PFB_PRI_MMU_PM_REQ_MASK"}, "0x18": {"name": "NV_PFB_PRI_MMU_CG"}, "0x1c": {"name": "NV_PFB_PRI_MMU_CG1"}, "0x20": {"name": "NV_PFB_PRI_MMU_PG"}, "0x24": {"name": "NV_PFB_PRI_MMU_TLB_CTRL", "fields": {"L2_SIZE": [1, 0], "L2_FA_SIZE": [3, 2], "L2_RB_SIZE": [5, 4], "HUB_SIZE": [7, 6], "HUB_FA_SIZE": [9, 8], "HUB_RB_SIZE": [11, 10], "FILL_SIZE_PTE": [13, 12], "FILL_SIZE_PDE": [15, 14], "FILL_SIZE_RB": [17, 16], "L2_SET_INDEX_BIG_PG": [19, 18], "HUB_SET_INDEX_BIG_PG": [21, 20], "L2_SET_INDEX_SMALL_PG": [23, 22], "HUB_SET_INDEX_SMALL_PG": [25, 24], "HUB_LOCKED_LIMIT": [28, 26], "ATSD_PROP_FLUSH": [26, 26], "INVAL_PROP_FLUSH": [27, 27], "BIND_PROP_FLUSH": [28, 28], "HUB_RSRVD_VM": [31, 29]}}, "0x28": {"name": "NV_PFB_PRI_MMU_RSRVD"}, "0x2c": {"name": "NV_PFB_PRI_MMU_BIND_IMB"}, "0x30": {"name": "NV_PFB_PRI_MMU_BIND"}, "0x34": {"name": "NV_PFB_PRI_MMU_INVALIDATE_VADDR"}, "0x38": {"name": "NV_PFB_PRI_MMU_INVALIDATE_PDB"}, "0x3c": {"name": "NV_PFB_PRI_MMU_INVALIDATE", "fields": {"VADDR_BITS": [31, 4], "UPPER_VADDR_BITS": [19, 0], "PDB_APERTURE": [1, 1], "PDB_ADDR": [31, 4], "UPPER_PDB_ADDR": [19, 0], "PASID_VAL": [19, 0], "SIZE_VAL": [5, 0], "SIZE_GFID": [31, 26], "ALL_VA": [0, 0], "ALL_PDB": [1, 1], "HUBTLB_ONLY": [2, 2], "REPLAY": [5, 3], "SYS_MEMBAR": [6, 6], "ACK": [8, 7], "CANCEL_CLIENT_ID": [14, 9], "CANCEL_GPC_ID": [19, 15], "CANCEL_CLIENT_TYPE": [20, 20], "USE_PASID": [21, 21], "USE_SIZE": [22, 22], "PROP_FLUSH": [23, 23], "CACHE_LEVEL": [26, 24], "TRIGGER": [31, 31], "VADDR_VIRT_BITS": [31, 4], "UPPER_VADDR_VIRT_BITS": [19, 0], "PDB_VIRT_APERTURE": [1, 1], "PDB_VIRT_ADDR": [31, 4], "UPPER_PDB_VIRT_ADDR": [19, 0], "PASID_VIRT_VAL": [19, 0], "SIZE_VIRT_VAL": [5, 0], "SIZE_VIRT_GFID": [31, 26], "VIRT_ALL_VA": [0, 0], "VIRT_ALL_PDB": [1, 1], "VIRT_HUBTLB_ONLY": [2, 2], "VIRT_REPLAY": [5, 3], "VIRT_SYS_MEMBAR": [6, 6], "VIRT_ACK": [8, 7], "VIRT_CANCEL_CLIENT_ID": [14, 9], "VIRT_CANCEL_GPC_ID": [19, 15], "VIRT_CANCEL_CLIENT_TYPE": [20, 20], "VIRT_USE_PASID": [21, 21], "VIRT_USE_SIZE": [22, 22], "VIRT_PROP_FLUSH": [23, 23], "VIRT_CACHE_LEVEL": [26, 24], "VIRT_TRIGGER": [31, 31]}}, "0x40": {"name": "NV_PFB_PRI_MMU_PREFETCH"}, "0x44": {"name": "NV_PFB_PRI_MMU_DEBUG_CTRL"}, "0x48": {"name": "NV_PFB_PRI_MMU_DEBUG_WR"}, "0x4c": {"name": "NV_PFB_PRI_MMU_DEBUG_RD"}, "0x50": {"name": "NV_PFB_PRI_MMU_VPR_INFO"}, "0x54": {"name": "NV_PFB_PRI_MMU_WPR_INFO"}, "0x58": {"name": "NV_PFB_PRI_MMU_VPR_WPR_WRITE"}, "0x5c": {"name": "NV_PFB_PRI_MMU_PRIV_LEVEL_MASK", "fields": {"READ_PROTECTION": [3, 0], "READ_PROTECTION_LEVEL0": [0, 0], "READ_PROTECTION_LEVEL1": [1, 1], "READ_PROTECTION_LEVEL2": [2, 2], "READ_PROTECTION_LEVEL3": [3, 3], "WRITE_PROTECTION": [7, 4], "WRITE_PROTECTION_LEVEL0": [4, 4], "WRITE_PROTECTION_LEVEL1": [5, 5], "WRITE_PROTECTION_LEVEL2": [6, 6], "WRITE_PROTECTION_LEVEL3": [7, 7], "READ_VIOLATION": [8, 8], "WRITE_VIOLATION": [9, 9], "SOURCE_READ_CONTROL": [10, 10], "SOURCE_WRITE_CONTROL": [11, 11], "SOURCE_ENABLE": [31, 12]}}, "0x60": {"name": "NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE"}, "0x64": {"name": "NV_PFB_PRI_MMU_PHYS_SECURE"}, "0x68": {"name": "NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR"}, "0x6c": {"name": "NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB"}, "0x70": {"name": "NV_PFB_PRI_MMU_PM_UPPER_ADDR_LOW"}, "0x74": {"name": "NV_PFB_PRI_MMU_PM_UPPER_ADDR_HIGH"}, "0x78": {"name": "NV_PFB_PRI_MMU_PAGE_FAULT_CTRL", "fields": {"PRF_FILTER": [1, 0], "VIRT_PRF_FILTER": [1, 0]}}, "0x7c": {"name": "NV_PFB_PRI_MMU_PG1"}, "0x180": {"name": "NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL"}, "0x1cc": {"name": "NV_PFB_PRI_MMU_FAULT_ADDR_LO"}, "0x1d0": {"name": "NV_PFB_PRI_MMU_FAULT_ADDR_HI"}, "0x1d4": {"name": "NV_PFB_PRI_MMU_FAULT_INST_LO"}, "0x1d8": {"name": "NV_PFB_PRI_MMU_FAULT_INST_HI"}, "0x1dc": {"name": "NV_PFB_PRI_MMU_FAULT_INFO"}, "0x1e0": {"name": "NV_PFB_PRI_MMU_FAULT_STATUS", "fields": {"DROPPED_BAR1_PHYS": [0, 0], "DROPPED_BAR1_VIRT": [1, 1], "DROPPED_BAR2_PHYS": [2, 2], "DROPPED_BAR2_VIRT": [3, 3], "DROPPED_IFB_PHYS": [4, 4], "DROPPED_IFB_VIRT": [5, 5], "DROPPED_OTHER_PHYS": [6, 6], "DROPPED_OTHER_VIRT": [7, 7], "REPLAYABLE": [8, 8], "NON_REPLAYABLE": [9, 9], "REPLAYABLE_ERROR": [10, 10], "NON_REPLAYABLE_ERROR": [11, 11], "REPLAYABLE_OVERFLOW": [12, 12], "NON_REPLAYABLE_OVERFLOW": [13, 13], "REPLAYABLE_GETPTR_CORRUPTED": [14, 14], "NON_REPLAYABLE_GETPTR_CORRUPTED": [15, 15], "BUSY_TYPE": [29, 28], "BUSY": [30, 30], "VALID": [31, 31], "VIRT_DROPPED_BAR1_PHYS": [0, 0], "VIRT_DROPPED_BAR1_VIRT": [1, 1], "VIRT_DROPPED_BAR2_PHYS": [2, 2], "VIRT_DROPPED_BAR2_VIRT": [3, 3], "VIRT_DROPPED_IFB_PHYS": [4, 4], "VIRT_DROPPED_IFB_VIRT": [5, 5], "VIRT_DROPPED_OTHER_PHYS": [6, 6], "VIRT_DROPPED_OTHER_VIRT": [7, 7], "VIRT_REPLAYABLE": [8, 8], "VIRT_NON_REPLAYABLE": [9, 9], "VIRT_REPLAYABLE_ERROR": [10, 10], "VIRT_NON_REPLAYABLE_ERROR": [11, 11], "VIRT_REPLAYABLE_OVERFLOW": [12, 12], "VIRT_NON_REPLAYABLE_OVERFLOW": [13, 13], "VIRT_REPLAYABLE_GETPTR_CORRUPTED": [14, 14], "VIRT_NON_REPLAYABLE_GETPTR_CORRUPTED": [15, 15], "VIRT_BUSY_TYPE": [29, 28], "VIRT_BUSY": [30, 30], "VIRT_VALID": [31, 31]}}, "0x1e4": {"name": "NV_PFB_PRI_MMU_INVALIDATE_PASID"}, "0x1e8": {"name": "NV_PFB_PRI_MMU_INVALIDATE_SIZE"}, "0x1ec": {"name": "NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL"}, "0x1f0": {"name": "NV_PFB_PRI_MMU_L2TLB_ECC_STATUS"}, "0x1f4": {"name": "NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT"}, "0x1f8": {"name": "NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT"}, "0x1fc": {"name": "NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS"}, "0x200": {"name": "NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL"}, "0x204": {"name": "NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS"}, "0x208": {"name": "NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT"}, "0x20c": {"name": "NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT"}, "0x210": {"name": "NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS"}, "0x214": {"name": "NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL"}, "0x218": {"name": "NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS"}, "0x21c": {"name": "NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT"}, "0x220": {"name": "NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT"}, "0x224": {"name": "NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS"}, "0x228": {"name": "NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR"}, "0x22c": {"name": "NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK"}, "0x234": {"name": "NV_PFB_PRI_MMU_CBC_ADJ"}, "0x238": {"name": "NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK"}, "0x23c": {"name": "NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK"}, "0x240": {"name": "NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS"}, "0x244": {"name": "NV_PFB_PRI_MMU_CBC_BASE"}, "0x248": {"name": "NV_PFB_PRI_MMU_CBC_TOP"}, "0x24c": {"name": "NV_PFB_PRI_MMU_CBC_MAX"}, "0x250": {"name": "NV_PFB_PRI_MMU_HYPERVISOR_CTL"}, "0x254": {"name": "NV_PFB_PRI_MMU_PEER_SUPPORT"}, "0x258": {"name": "NV_PFB_PRI_MMU_BIND_EXT"}, "0x25c": {"name": "NV_PFB_PRI_MMU_INT_VECTOR_ECC_ERROR"}, "0x260": {"name": "NV_PFB_PRI_MMU_INT_VECTOR_INFO_FAULT"}, "0x27c": {"name": "NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK"}}}, {"base": "0x20000000001FA7D8", "size": "0x5C", "label": "gmmu-wpr-lock", "registers": {"0x0": {"name": "NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK"}, "0x4": {"name": "NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK"}, "0x8": {"name": "NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK"}, "0xc": {"name": "NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK"}, "0x10": {"name": "NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK"}, "0x14": {"name": "NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK"}, "0x18": {"name": "NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK"}, "0x1c": {"name": "NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK"}, "0x20": {"name": "NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK"}, "0x28": {"name": "NV_PFB_PRI_MMU_VPR_MODE", "fields": {"VPR_PROTECTED_MODE": [4, 4], "MEMORY_LOCKED": [5, 5], "VPR_NON_COMPRESSIBLE": [6, 6], "SYSWR_WHEN_MEMORY_LOCKED": [7, 7], "MEMORY_LOCK_FUSE": [8, 8], "WPR_COMPRESSIBLE": [9, 9], "SECURE_LOCK": [12, 12], "WPR_WITH_SECURE_LOCK": [13, 13], "FORCE_SPA_EQUAL_GPA": [20, 20], "VPR_FAULT_REPORT": [29, 29], "VPR_LOCK_HWPM": [30, 30], "VPR_LOCK_MISC": [28, 28]}}, "0x2c": {"name": "NV_PFB_PRI_MMU_VPR_ADDR_LO"}, "0x30": {"name": "NV_PFB_PRI_MMU_VPR_ADDR_HI"}, "0x34": {"name": "NV_PFB_PRI_MMU_VPR_CYA_LO"}, "0x38": {"name": "NV_PFB_PRI_MMU_VPR_CYA_HI"}, "0x3c": {"name": "NV_PFB_PRI_MMU_WPR_ALLOW_READ", "fields": {"ALL": [11, 4], "WPR1": [7, 4], "WPR1_SECURE0": [4, 4], "WPR1_SECURE1": [5, 5], "WPR1_SECURE2": [6, 6], "WPR1_SECURE3": [7, 7], "WPR2": [11, 8], "WPR2_SECURE0": [8, 8], "WPR2_SECURE1": [9, 9], "WPR2_SECURE2": [10, 10], "WPR2_SECURE3": [11, 11], "WPR_OK": [27, 27], "MIS_MATCH": [31, 28], "MIS_MATCH0": [28, 28], "MIS_MATCH1": [29, 29], "MIS_MATCH2": [30, 30], "MIS_MATCH3": [31, 31]}}, "0x40": {"name": "NV_PFB_PRI_MMU_WPR_ALLOW_WRITE", "fields": {"ALL": [11, 4], "WPR1": [7, 4], "WPR1_SECURE0": [4, 4], "WPR1_SECURE1": [5, 5], "WPR1_SECURE2": [6, 6], "WPR1_SECURE3": [7, 7], "WPR2": [11, 8], "WPR2_SECURE0": [8, 8], "WPR2_SECURE1": [9, 9], "WPR2_SECURE2": [10, 10], "WPR2_SECURE3": [11, 11], "WPR_ENABLE_FUSE": [27, 27], "MIS_MATCH": [31, 28], "MIS_MATCH0": [28, 28], "MIS_MATCH1": [29, 29], "MIS_MATCH2": [30, 30], "MIS_MATCH3": [31, 31]}}, "0x44": {"name": "NV_PFB_PRI_MMU_WPR1_ADDR_LO"}, "0x48": {"name": "NV_PFB_PRI_MMU_WPR1_ADDR_HI"}, "0x4c": {"name": "NV_PFB_PRI_MMU_WPR2_ADDR_LO"}, "0x50": {"name": "NV_PFB_PRI_MMU_WPR2_ADDR_HI"}, "0x54": {"name": "NV_PFB_PRI_MMU_LOCK_ADDR_LO"}, "0x58": {"name": "NV_PFB_PRI_MMU_LOCK_ADDR_HI"}}}, {"base": "0x20000000001FAC00", "size": "0x400", "label": "gmmu-hsmmu", "registers": {"0x80": {"name": "NV_PFB_HSMMU_PRI_MMU_CTRL", "fields": {"VM_PG_SIZE": [0, 0], "VOL_FAULT": [1, 1], "COMP_FAULT": [2, 2], "MISS_GRAN": [4, 3], "CACHE_MODE": [6, 5], "L2_SEND_MODE": [9, 9], "USE_FULL_COMP_TAG_LINE": [12, 12], "ATOMIC_CAPABILITY_MODE": [25, 24], "STRONG_BIT_ATOMIC_CYA": [26, 26], "STRONG_BIT_OVERRIDE_ATOMIC_DISABLE": [26, 26]}}, "0x84": {"name": "NV_PFB_HSMMU_PRI_MMU_PM"}, "0x88": {"name": "NV_PFB_HSMMU_PRI_MMU_PM_ADDR_LOW"}, "0x8c": {"name": "NV_PFB_HSMMU_PRI_MMU_PM_UPPER_ADDR_LOW"}, "0x90": {"name": "NV_PFB_HSMMU_PRI_MMU_PM_ADDR_HIGH"}, "0x94": {"name": "NV_PFB_HSMMU_PRI_MMU_PM_UPPER_ADDR_HIGH"}, "0x98": {"name": "NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK"}, "0x9c": {"name": "NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK"}, "0xa0": {"name": "NV_PFB_HSMMU_PRI_MMU_TLB_CTRL", "fields": {"UTLB_SIZE": [1, 0], "UTLB_RB_SIZE": [3, 2], "UTLB_FAST_PATH_DISABLE": [4, 4], "L1TLB_SIZE": [17, 16], "L1TLB_FA_SIZE": [19, 18], "L1TLB_RB_SIZE": [21, 20], "L1TLB_SET_INDEX_BIG_PG": [23, 22], "L1TLB_SET_INDEX_SMALL_PG": [25, 24], "L1TLB_FAST_PATH_DISABLE": [26, 26], "SECURE_LOCK": [30, 30], "FAST_BIG_PG_FAULT_DISABLE": [31, 31]}}, "0xa4": {"name": "NV_PFB_HSMMU_PRI_MMU_PREFETCH"}, "0xb0": {"name": "NV_PFB_HSMMU_PRI_MMU_CG"}, "0xb4": {"name": "NV_PFB_HSMMU_PRI_MMU_CG1"}, "0xb8": {"name": "NV_PFB_HSMMU_PRI_MMU_PG"}, "0xc0": {"name": "NV_PFB_HSMMU_PRI_MMU_PG1"}, "0xc4": {"name": "NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL"}, "0xc8": {"name": "NV_PFB_HSMMU_PRI_MMU_DEBUG_WR"}, "0xcc": {"name": "NV_PFB_HSMMU_PRI_MMU_DEBUG_RD"}}} ], "note": "gmmu-pri-mmu spans the NV_PFB_PRI_MMU_* cluster 0x100C80-0x100EFC (interleaved PFB PRI_FB/NISO offsets inside the span stay unclassified); gmmu-wpr-lock overlaps the fwsec WPR2 window at 0x1FA824/0x1FA828 and just declines, so the access follows exactly the same underlying path as a run without the observer (observed by tests, not an assertion that the WPR2 path serves)." }, "fbif": { "evidence": "FBIF/FBPA register surface: NV_PFB_FBPA block (0x009A0000-0x009A3FFF), the 16 per-partition FBPA instances (0x00900000 + i*0x4000) and the 3 MC instances (0x00980000 + i*0x4000) from the hardware register/field headers. Observe-only: FB access-path, compression and ECC semantics are not modelled; no read value is invented.", "mode": "observe-only", "registers": { "0x0": { "name": "NV_PFB_FBPA_PRI_FBPA_CG" }, "0x4": { "name": "NV_PFB_FBPA_PRI_FBPA_CG1" }, "0x8": { "name": "NV_PFB_FBPA_PRI_FBPA_PG" }, "0xc": { "name": "NV_PFB_FBPA_PRI_FBPA_PG1" }, "0x50": { "name": "NV_PFB_FBPA_SPARE" }, "0x54": { "name": "NV_PFB_FBPA_FALCON_MONITOR" }, "0x60": { "name": "NV_PFB_FBPA_CFG_PWRD" }, "0x64": { "name": "NV_PFB_FBPA_FALCON_CTRL_VER" }, "0x80": { "name": "NV_PFB_FBPA_DEBUG_0" }, "0x84": { "name": "NV_PFB_FBPA_DEBUG_1" }, "0x90": { "name": "NV_PFB_FBPA_TESTCMD", "fields": { "CKE": [ 0, 0 ], "CS0": [ 1, 1 ], "CS1": [ 2, 2 ], "RAS": [ 3, 3 ], "CAS": [ 4, 4 ], "WE": [ 5, 5 ], "RES": [ 6, 6 ], "BANK_4": [ 7, 7 ], "BANK": [ 11, 8 ], "ADR": [ 25, 12 ], "ADR_UPPER": [ 28, 26 ], "GO": [ 30, 30 ], "HOLD": [ 31, 31 ], "EXT_ACT": [ 0, 0 ], "EXT_VLD_DRAM0": [ 1, 1 ], "EXT_VLD_DRAM1": [ 2, 2 ], "EXT_ADR_DRAM1": [ 10, 3 ], "EXT_RW_CMD": [ 16, 16 ], "EXT_MRS_CMD": [ 17, 17 ], "EXT_DR_CMD": [ 18, 18 ], "EXT_4CK_CMD": [ 19, 19 ], "EXT_LAM_CMD": [ 20, 20 ], "EXT_1_ADR": [ 23, 0 ], "EXT_1_CSB0": [ 27, 27 ], "EXT_1_CSB1": [ 28, 28 ], "EXT_1_USE_ADR": [ 29, 29 ] } }, "0x94": { "name": "NV_PFB_FBPA_TESTCMD_EXT" }, "0xa0": { "name": "NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0" }, "0xa4": { "name": "NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1" }, "0xa8": { "name": "NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2" }, "0xac": { "name": "NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3" }, "0xb0": { "name": "NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0" }, "0xb4": { "name": "NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1" }, "0xb8": { "name": "NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2" }, "0xbc": { "name": "NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3" }, "0xc0": { "name": "NV_PFB_FBPA_SWIZZLE_DBI" }, "0xc4": { "name": "NV_PFB_FBPA_SWIZZLE_BYTE" }, "0xc8": { "name": "NV_PFB_FBPA_SWIZZLE_ECC" }, "0xcc": { "name": "NV_PFB_FBPA_SPARE2" }, "0xd0": { "name": "NV_PFB_FBPA_REPLAY_RETRY_SUBP0" }, "0xd4": { "name": "NV_PFB_FBPA_REPLAY_RETRY_SUBP1" }, "0xd8": { "name": "NV_PFB_FBPA_REPLAY_CYCLES_SUBP0" }, "0xdc": { "name": "NV_PFB_FBPA_REPLAY_CYCLES_SUBP1" }, "0x100": { "name": "NV_PFB_FBPA_PM" }, "0x148": { "name": "NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK", "fields": { "READ_PROTECTION": [ 3, 0 ], "READ_PROTECTION_LEVEL0": [ 0, 0 ], "READ_PROTECTION_LEVEL1": [ 1, 1 ], "READ_PROTECTION_LEVEL2": [ 2, 2 ], "READ_PROTECTION_LEVEL3": [ 3, 3 ], "WRITE_PROTECTION": [ 7, 4 ], "WRITE_PROTECTION_LEVEL0": [ 4, 4 ], "WRITE_PROTECTION_LEVEL1": [ 5, 5 ], "WRITE_PROTECTION_LEVEL2": [ 6, 6 ], "WRITE_PROTECTION_LEVEL3": [ 7, 7 ], "READ_VIOLATION": [ 8, 8 ], "WRITE_VIOLATION": [ 9, 9 ], "SOURCE_READ_CONTROL": [ 10, 10 ], "SOURCE_WRITE_CONTROL": [ 11, 11 ], "SOURCE_ENABLE": [ 31, 12 ] } }, "0x150": { "name": "NV_PFB_FBPA_ASRCTRL_NONISO" }, "0x154": { "name": "NV_PFB_FBPA_TESTCMD_EXT_1" }, "0x158": { "name": "NV_PFB_FBPA_PTR_RESET" }, "0x15c": { "name": "NV_PFB_FBPA_CONFIG12" }, "0x160": { "name": "NV_PFB_FBPA_MISC_CTRL", "fields": { "INTERVAL_TIMER_PERIOD": [ 2, 0 ], "INTERVAL_TIMER_EN": [ 4, 4 ] } }, "0x164": { "name": "NV_PFB_FBPA_NUM_ACTIVE_FBPS" }, "0x168": { "name": "NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK", "fields": { "READ_PROTECTION": [ 3, 0 ], "READ_PROTECTION_LEVEL0": [ 0, 0 ], "READ_PROTECTION_LEVEL1": [ 1, 1 ], "READ_PROTECTION_LEVEL2": [ 2, 2 ], "READ_PROTECTION_LEVEL3": [ 3, 3 ], "WRITE_PROTECTION": [ 7, 4 ], "WRITE_PROTECTION_LEVEL0": [ 4, 4 ], "WRITE_PROTECTION_LEVEL1": [ 5, 5 ], "WRITE_PROTECTION_LEVEL2": [ 6, 6 ], "WRITE_PROTECTION_LEVEL3": [ 7, 7 ], "READ_VIOLATION": [ 8, 8 ], "WRITE_VIOLATION": [ 9, 9 ], "SOURCE_READ_CONTROL": [ 10, 10 ], "SOURCE_WRITE_CONTROL": [ 11, 11 ], "SOURCE_ENABLE": [ 31, 12 ] } }, "0x16c": { "name": "NV_PFB_FBPA_NUM_ACTIVE_LTCS" }, "0x170": { "name": "NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK", "fields": { "READ_PROTECTION": [ 3, 0 ], "READ_PROTECTION_LEVEL0": [ 0, 0 ], "READ_PROTECTION_LEVEL1": [ 1, 1 ], "READ_PROTECTION_LEVEL2": [ 2, 2 ], "READ_PROTECTION_LEVEL3": [ 3, 3 ], "WRITE_PROTECTION": [ 7, 4 ], "WRITE_PROTECTION_LEVEL0": [ 4, 4 ], "WRITE_PROTECTION_LEVEL1": [ 5, 5 ], "WRITE_PROTECTION_LEVEL2": [ 6, 6 ], "WRITE_PROTECTION_LEVEL3": [ 7, 7 ], "READ_VIOLATION": [ 8, 8 ], "WRITE_VIOLATION": [ 9, 9 ], "SOURCE_READ_CONTROL": [ 10, 10 ], "SOURCE_WRITE_CONTROL": [ 11, 11 ], "SOURCE_ENABLE": [ 31, 12 ] } }, "0x174": { "name": "NV_PFB_FBPA_WPRE0" }, "0x178": { "name": "NV_PFB_FBPA_WPRE1" }, "0x17c": { "name": "NV_PFB_FBPA_WPRE2" }, "0x1d8": { "name": "NV_PFB_FBPA_PM_CAPTURE_CTL" }, "0x200": { "name": "NV_PFB_FBPA_CFG0", "fields": { "BL": [ 1, 0 ], "EXTBANK": [ 2, 2 ], "X8": [ 4, 4 ], "CA_RETURN_TO_ZERO": [ 5, 5 ], "HBM_CMD_PARITY_OVERRIDE": [ 6, 6 ], "EDC_RATE": [ 7, 7 ], "GAPLESS_WTR": [ 8, 8 ], "DRAM_ACPD": [ 11, 11 ], "AUTO_ATR": [ 12, 12 ], "DATA_SCRAMBLE": [ 13, 13 ], "AUTO_SYNC": [ 14, 14 ], "LOW_POWER": [ 15, 15 ], "ABI": [ 16, 16 ], "BURST_LENGTH": [ 17, 17 ], "DM_ON_ADR": [ 18, 18 ], "TIMING_UNIT": [ 19, 19 ], "CMD_PARITY": [ 20, 20 ], "AUTO_ODT": [ 21, 21 ], "CLAMSHELL": [ 22, 22 ], "EDC_EARLY_VALUE": [ 23, 23 ], "BG_8": [ 24, 24 ], "AUTO_PRE": [ 25, 25 ], "SAME_QUSE_TWO_RANKS": [ 26, 26 ], "RDEDC": [ 27, 27 ], "WREDC": [ 28, 28 ], "REPLAY": [ 29, 29 ], "MS01_ECC": [ 30, 30 ], "DRAM_ACK": [ 31, 31 ] } }, "0x204": { "name": "NV_PFB_FBPA_CFG1", "fields": { "SUBP": [ 1, 0 ], "AP": [ 6, 4 ], "COL": [ 15, 12 ], "ROWA": [ 19, 16 ], "ROWB": [ 23, 20 ], "BANK": [ 25, 24 ], "BG_8_OVR": [ 26, 26 ], "NUM_BANKS_PER_BG": [ 28, 27 ], "NUM_BANKS_PER_ROW_BG": [ 30, 29 ] } }, "0x20c": { "name": "NV_PFB_FBPA_CSTATUS" }, "0x210": { "name": "NV_PFB_FBPA_REFCTRL", "fields": { "PUT": [ 6, 0 ], "GET": [ 14, 8 ], "RESET": [ 16, 16 ], "VALID": [ 31, 31 ] } }, "0x214": { "name": "NV_PFB_FBPA_ZQ" }, "0x218": { "name": "NV_PFB_FBPA_PIN" }, "0x21c": { "name": "NV_PFB_FBPA_PAD" }, "0x220": { "name": "NV_PFB_FBPA_TIMING0" }, "0x224": { "name": "NV_PFB_FBPA_TIMING1" }, "0x228": { "name": "NV_PFB_FBPA_TIMING2" }, "0x22c": { "name": "NV_PFB_FBPA_TIMING3" }, "0x230": { "name": "NV_PFB_FBPA_TIMING4" }, "0x234": { "name": "NV_PFB_FBPA_TIMING5" }, "0x238": { "name": "NV_PFB_FBPA_TIMING6" }, "0x23c": { "name": "NV_PFB_FBPA_TIMING7" }, "0x240": { "name": "NV_PFB_FBPA_TIMING8" }, "0x244": { "name": "NV_PFB_FBPA_TIMING9" }, "0x248": { "name": "NV_PFB_FBPA_TIMING10" }, "0x24c": { "name": "NV_PFB_FBPA_TIMING11" }, "0x250": { "name": "NV_PFB_FBPA_TIMING12" }, "0x254": { "name": "NV_PFB_FBPA_TIMING13" }, "0x258": { "name": "NV_PFB_FBPA_TIMING14" }, "0x25c": { "name": "NV_PFB_FBPA_TIMING15" }, "0x260": { "name": "NV_PFB_FBPA_TIMING16" }, "0x264": { "name": "NV_PFB_FBPA_TIMING17" }, "0x268": { "name": "NV_PFB_FBPA_TIMING18" }, "0x26c": { "name": "NV_PFB_FBPA_TIMING19" }, "0x280": { "name": "NV_PFB_FBPA_CG1" }, "0x284": { "name": "NV_PFB_FBPA_CG2" }, "0x288": { "name": "NV_PFB_FBPA_TIMING20_GEN" }, "0x28c": { "name": "NV_PFB_FBPA_TIMING20" }, "0x290": { "name": "NV_PFB_FBPA_CONFIG0" }, "0x294": { "name": "NV_PFB_FBPA_CONFIG1" }, "0x298": { "name": "NV_PFB_FBPA_CONFIG2" }, "0x29c": { "name": "NV_PFB_FBPA_CONFIG3" }, "0x2a0": { "name": "NV_PFB_FBPA_CONFIG4" }, "0x2a4": { "name": "NV_PFB_FBPA_CONFIG5" }, "0x2a8": { "name": "NV_PFB_FBPA_CONFIG6" }, "0x2ac": { "name": "NV_PFB_FBPA_CONFIG7" }, "0x2b0": { "name": "NV_PFB_FBPA_TIMING0_GEN" }, "0x2b4": { "name": "NV_PFB_FBPA_TIMING1_GEN" }, "0x2b8": { "name": "NV_PFB_FBPA_TIMING2_GEN" }, "0x2bc": { "name": "NV_PFB_FBPA_TIMING3_GEN" }, "0x2c0": { "name": "NV_PFB_FBPA_TIMING4_GEN" }, "0x2c4": { "name": "NV_PFB_FBPA_TIMING5_GEN" }, "0x2c8": { "name": "NV_PFB_FBPA_TIMING6_GEN" }, "0x2cc": { "name": "NV_PFB_FBPA_CONFIG8" }, "0x2d0": { "name": "NV_PFB_FBPA_TIMING7_GEN" }, "0x2d4": { "name": "NV_PFB_FBPA_TIMING8_GEN" }, "0x2d8": { "name": "NV_PFB_FBPA_TIMING9_GEN" }, "0x2dc": { "name": "NV_PFB_FBPA_TIMING15_GEN" }, "0x2e0": { "name": "NV_PFB_FBPA_TIMING16_GEN" }, "0x2e4": { "name": "NV_PFB_FBPA_TIMING17_GEN" }, "0x2e8": { "name": "NV_PFB_FBPA_CONFIG9" }, "0x2ec": { "name": "NV_PFB_FBPA_TIMING18_GEN" }, "0x2f0": { "name": "NV_PFB_FBPA_TIMING19_GEN" }, "0x2f4": { "name": "NV_PFB_FBPA_CONFIG10" }, "0x2f8": { "name": "NV_PFB_FBPA_ASR_WAKEUP" }, "0x2fc": { "name": "NV_PFB_FBPA_DRAM_ASR" }, "0x300": { "name": "NV_PFB_FBPA_GENERIC_MRS" } }, "windows": [ {"base": "0x20000000009A0000", "size": "0x4000", "label": "fbpa"}, {"base": "0x2000000000900000", "size": "0x4000", "label": "fbpa-partition", "count": 16, "stride": "0x4000"}, {"base": "0x2000000000980000", "size": "0x4000", "label": "fbpa-mc", "count": 3, "stride": "0x4000"} ] }, "dma": { "evidence": "GSP RISC-V address map: SYSGPA/FBGPA apertures. In this flat model both apertures alias simulator RAM (documented assumption) so booter-style DMA and firmware aperture reads resolve; unmapped transfers are refused and recorded.", "windows": [ {"pa": "0x8180000000000000", "sim": "0x0", "size": "0x8000000"}, {"pa": "0x6180000000000000", "sim": "0x0", "size": "0x8000000"} ] } }, "boot_shim": { "note": "Reset-time state the real SEC2 booter/host provides. Every value here is an assumption recorded in the session; the device model never fakes a register read.", "registers": { "a0": "0x81000", "a1": "0x80000", "a2": "0x4000000", "a3": "0x1b34ea0", "a4": "0x4000000", "a5": "0x0" }, "bootargs_pa": "0x80000", "bootargs_size": 120, "core_dump_pa": "0x40000", "core_dump_size": "0x10000", "wpr_meta_pa": "0x90000", "bootstrap_args": { "pa": "0x81000", "imem_base_pa": "0x0", "imem_size": "0x10000", "imem_bs_size": "0x0", "dmem_base_pa": "0x100000000", "dmem_size": "0x10000", "dmem_bs_size": "0x0", "evidence": "libos bootstrap-args layout (IMEM/DMEM base+size+bs, passed in a0 by the bootloader); the M-mode boot path (mstatus.VM=NVMPU, observed) uses the non-sep-kern TCM configuration (offsets 0, 64 KiB). Values are declared assumptions, not silicon reads." }, "wpr": { "elf_pa": "0x4000000", "elf_size": "0x1b34ea0", "wpr_start": "0x2000000", "wpr_end": "0x6000000", "boot_bin_offset": "0x3000000", "gsp_fw_offset": "0x4000000", "fb_size": "0x200000000" } } }