"""risc-v-gsp-rm-debugger native RV64IMAC simulator (M1).

Pure-Python, deterministic, stdlib-only.  :class:`sim.machine.Machine` executes
RV64IMAC from a 256 MiB RAM region with an NS16550A UART; the debugger-facing
adapter lives in ``greeneye.sim_backend``.  A machine can be given a
``greeneye.device_map.DeviceMap`` and ``unknown_mmio="lenient"`` to serve
unmodelled MMIO accesses from harvested first-touch data instead of faulting.
:mod:`sim.cycles` adds a modeled, table-driven cycle counter alongside the
instruction count (not a timing claim; see ``docs/32-GSP-CYCLE-MODEL.md``).
"""
from .decode import decode16, decode32  # noqa: F401
from .cycles import (  # noqa: F401
    CYCLE_FIDELITY,
    CYCLE_MODEL_NAME,
    DEFAULT_MODEL,
    NOTE,
    CycleModel,
)
from .machine import (  # noqa: F401
    R_BP,
    R_BUDGET,
    R_EBREAK,
    R_ECALL,
    R_FAULT,
    R_STEP,
    R_WATCH,
    UNKNOWN_MMIO_MODES,
    Fault,
    Machine,
    SimMachine,
    Uart16550,
)
from .trace import Trace, make_trace  # noqa: F401

__all__ = [
    "Machine",
    "SimMachine",
    "Uart16550",
    "Fault",
    "decode16",
    "decode32",
    "Trace",
    "make_trace",
    "CycleModel",
    "DEFAULT_MODEL",
    "CYCLE_MODEL_NAME",
    "CYCLE_FIDELITY",
    "NOTE",
    "R_BUDGET",
    "R_BP",
    "R_WATCH",
    "R_EBREAK",
    "R_FAULT",
    "R_STEP",
    "R_ECALL",
    "UNKNOWN_MMIO_MODES",
]