From ab6fed7ee35a114541373af90184acde9bd94b6b Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Wed, 7 Oct 2026 11:05:24 -0400 Subject: gr-regs/vgsp: sample PGRAPH_INTR + PGRAPH_INTR_EN at the dispatch window The m75/m78/m79 launch windows show FECS_CTXSW_STATUS_FE_0.GR_INTR_REQ (bit17) asserted through the SKED CWD ACTIVE state and a following CTXSW_REQ (bit0) that results in the context save/unload. The real driver carries GR_INTR only transiently during its context load and clears it before ACTIVE. The PGRAPH interrupt latch (0x400100) names what the engine is signaling (e.g. ILLEGAL_METHOD bit4, SEMAPHORE bit1, NOTIFY); sampled by the external sampler and dumped in the launch post-mortem. --- tools/gr-regs/reg_sampler.py | 2 ++ 1 file changed, 2 insertions(+) (limited to 'tools') diff --git a/tools/gr-regs/reg_sampler.py b/tools/gr-regs/reg_sampler.py index 495ace8..af00db7 100644 --- a/tools/gr-regs/reg_sampler.py +++ b/tools/gr-regs/reg_sampler.py @@ -31,6 +31,8 @@ import time DEV = "/sys/bus/pci/devices/0000:01:00.0/resource0" REGS = [ (0x000200, "PMC_ENABLE"), + (0x400100, "PGRAPH_INTR"), + (0x40013C, "PGRAPH_INTR_EN"), (0x400700, "PGRAPH_STATUS"), (0x400504, "GRFIFO_STATUS"), (0x400704, "TRAPPED_ADDR"), -- cgit v1.2.3