From 3dd883f43c325f942b25be1accad82c7b431520c Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Wed, 7 Oct 2026 12:55:38 -0400 Subject: gr-regs: capture the faulting SM's WARP_ESR_PC/PC_HI and GPCMMU ESR m90 decoded the TPC0 SM0 warp error as ESR.ERROR=0x20 ADDR_ERROR_TYPE=0xb = MMU_NACK (the ESR.ERROR field is an enum, not a bitmask). Add the 4R companion words (ESR_MASK 0x734, PC 0x738, PC_HI 0x73c) for GPC0/TPC0/SM0 and GPC1/TPC0/SM0 plus the per-GPC GPCMMU ESR at +0x324 so the next cycle captures the faulting PC and the MMU-side latch. --- tools/gr-regs/reg_sampler.py | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'tools') diff --git a/tools/gr-regs/reg_sampler.py b/tools/gr-regs/reg_sampler.py index bce8c0f..acd7e00 100644 --- a/tools/gr-regs/reg_sampler.py +++ b/tools/gr-regs/reg_sampler.py @@ -39,13 +39,21 @@ REGS = [ (0x502C90, "GPC0_EXCEPTION"), (0x502C84, "GPC0_ACTIVITY1"), (0x504730, "G0T0S0_WARP_ESR"), + (0x504734, "G0T0S0_ESR_MASK"), + (0x504738, "G0T0S0_PC"), + (0x50473C, "G0T0S0_PC_HI"), (0x50476C, "G0T0S0_ESR_INFO"), (0x5047B0, "G0T0S1_WARP_ESR"), (0x504830, "G0T0S2_WARP_ESR"), (0x5048B0, "G0T0S3_WARP_ESR"), + (0x500324, "GPC0_GPCMMU_ESR"), (0x50AC90, "GPC1_EXCEPTION"), (0x50C730, "G1T0S0_WARP_ESR"), + (0x50C734, "G1T0S0_ESR_MASK"), + (0x50C738, "G1T0S0_PC"), + (0x50C73C, "G1T0S0_PC_HI"), (0x50C76C, "G1T0S0_ESR_INFO"), + (0x508324, "GPC1_GPCMMU_ESR"), (0x512C90, "GPC2_EXCEPTION"), (0x51AC90, "GPC3_EXCEPTION"), (0x522C90, "GPC4_EXCEPTION"), -- cgit v1.2.3