From 8e64754d9980d2423f1907ae184ec46e63e5ff7e Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Sun, 13 Sep 2026 19:11:39 -0400 Subject: Phase 2: PCI Config Space & BAR Enhancements - Enhanced PCI config space write handlers in main.c: - Added MSI-X Message Control (0x72-0x73) write support - Added MSI-X Table Offset/BIR (0x74-0x77) write support - Added MSI-X PBA Offset/BIR (0x78-0x7B) write support - Enhanced BAR emulation in bar_emulation.c: - Added MSI-X Table emulation (32 entries at BAR0+0x2000) - Added MSI-X PBA emulation (64-bit at BAR0+0x3000) - Added nv_vgpu_msix_set_pending/clear_pending for interrupt injection - Integrated with GSP emulation constants from gsp_emulation.h - Updated bar_emulation.h with MSI-X struct definitions and function declarations - Added GSP emulation constants to gsp_emulation.h (MSIX offsets, polling params) --- kernel/main.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'kernel/main.c') diff --git a/kernel/main.c b/kernel/main.c index efe5082..a277356 100644 --- a/kernel/main.c +++ b/kernel/main.c @@ -823,6 +823,15 @@ static ssize_t nv_vgpu_config_write(struct nv_vgpu_device *vgpu, const char __us case 0x5c: case 0x5d: /* MSI Message Data */ vgpu->pci_config[pos] = val; break; + case 0x72: case 0x73: /* MSI-X Message Control */ + vgpu->pci_config[pos] = val; + break; + case 0x74: case 0x75: case 0x76: case 0x77: /* MSI-X Table Offset/BIR */ + vgpu->pci_config[pos] = val; + break; + case 0x78: case 0x79: case 0x7a: case 0x7b: /* MSI-X PBA Offset/BIR */ + vgpu->pci_config[pos] = val; + break; case 0x88: case 0x89: /* Device Control */ case 0x90: case 0x91: /* Link Control */ case 0x98: case 0x99: /* Slot Control */ -- cgit v1.2.3