From 2302fc09080bad51c73f293294e19fd4db464eb0 Mon Sep 17 00:00:00 2001 From: Open-IOV Date: Wed, 23 Sep 2026 05:44:08 -0400 Subject: Open-IOV: initial public release Open-IOV virtualizes NVIDIA GPUs so that unmodified guest drivers run with real GPU functionality - CUDA first, 3D and video to follow - on unmodified hosts, without a proprietary vGPU license and without patching any driver, firmware or hypervisor. Core principle: emulate the interface, pass through the work. kernel/ open-iov-vfio.ko - host VFIO mdev driver: virtual GPU device (PCI config space, BAR shadows, MSI-X), GSP boot emulation, GSP-RM message-queue/RPC emulation, memory model (GPU-VA to guest-PA discovery) and the semaphore-completion service that advances guest UVM progress. userspace/ libiov.so management API and examples. tools/ guest diagnostics, firmware analysis wrappers, RM probes. scripts/ stack manager, VM harness, build/load/test automation. config/ hardware/version profiles (the portability surface). docs/ documentation tree - start at docs/README.md. wiki/ long-form firmware and protocol deep dives. Status: initialization works end to end for a stock 570.144 Linux guest on Turing (TU104): driver probe, nvidia-smi, the full GSP-RM control battery, object creation and the early CUDA/UVM start-up path. GPU work forwarding - the step that makes CUDA kernels execute on real hardware - is the active work item; see docs/04-implementation/01-known-knowns-and-unknowns.md. License: BSD-3-Clause for the project; GPL-2.0 for kernel modules that link GPL-only kernel interfaces. See LICENSE and docs/09-reference/legal-and-licensing.md. --- kernel/include/gsp_rpc_integration.h | 97 ++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 kernel/include/gsp_rpc_integration.h (limited to 'kernel/include/gsp_rpc_integration.h') diff --git a/kernel/include/gsp_rpc_integration.h b/kernel/include/gsp_rpc_integration.h new file mode 100644 index 0000000..eea3bf3 --- /dev/null +++ b/kernel/include/gsp_rpc_integration.h @@ -0,0 +1,97 @@ +/* + * GSP RPC Integration Layer Header + * Bridges the firmware-decompiled RPC client with existing gsp_comm.c + */ + +#ifndef _NV_VGPU_GSP_RPC_INTEGRATION_H_ +#define _NV_VGPU_GSP_RPC_INTEGRATION_H_ + +#include "nvidia-vgpu-vfio.h" +#include "gsp_comm.h" + +/* Initialize the RPC integration layer */ +int nv_vgpu_gsp_rpc_integration_init(struct nv_vgpu_device *vgpu, + struct nv_vgpu_gsp_comm_ctx *comm_ctx); + +/* Cleanup the RPC integration layer */ +void nv_vgpu_gsp_rpc_integration_cleanup(struct nv_vgpu_device *vgpu); + +/* ============================================================ + * Enhanced RPC Operations (using firmware-decompiled addresses) + * ============================================================ */ + +/* Memory allocation with full firmware parameter support */ +int nv_vgpu_gsp_rpc_alloc_fw(struct nv_vgpu_device *vgpu, + u64 size, u64 alignment, u32 mem_type, + u32 flags, u64 addr_hint, u32 pid, + u64 *gpu_va, u64 *handle, u64 *actual_size); + +/* Memory free */ +int nv_vgpu_gsp_rpc_free_fw(struct nv_vgpu_device *vgpu, u64 handle); + +/* Memory mapping with full firmware parameter support */ +int nv_vgpu_gsp_rpc_map_fw(struct nv_vgpu_device *vgpu, + u64 handle, u64 gpu_va, u64 size, + u32 prot, u32 flags, u64 offset, + u64 *mapped_va); + +/* Memory unmapping */ +int nv_vgpu_gsp_rpc_unmap_fw(struct nv_vgpu_device *vgpu, + u64 handle, u64 gpu_va, u64 size); + +/* Page pinning for DMA */ +int nv_vgpu_gsp_rpc_pin_fw(struct nv_vgpu_device *vgpu, + u64 handle, u64 offset, u64 size, + u32 flags, u64 *dma_addr, u32 *num_pages); + +/* Page unpinning */ +int nv_vgpu_gsp_rpc_unpin_fw(struct nv_vgpu_device *vgpu, + u64 handle, u64 offset, u64 size); + +/* Work scheduling */ +int nv_vgpu_gsp_rpc_schedule_fw(struct nv_vgpu_device *vgpu, + u64 work_handle, u64 callback, u64 arg, + u32 priority, u32 flags); + +/* Yield current work */ +int nv_vgpu_gsp_rpc_yield_fw(struct nv_vgpu_device *vgpu); + +/* BAR trap emulation */ +int nv_vgpu_gsp_rpc_bar_trap_fw(struct nv_vgpu_device *vgpu, + u64 bar_addr, u32 access_type, u32 size, + u64 value, u32 bar_num, u64 *ret_value); + +/* Migration - save state */ +int nv_vgpu_gsp_rpc_migrate_save_fw(struct nv_vgpu_device *vgpu, + u64 src_gpu_id, u64 dst_gpu_id, + u64 memory_bitmap, u64 page_table_ptr, + u64 *checkpoint); + +/* Migration - restore state */ +int nv_vgpu_gsp_rpc_migrate_restore_fw(struct nv_vgpu_device *vgpu, + u64 src_gpu_id, u64 dst_gpu_id, + u64 memory_bitmap, u64 page_table_ptr, + u64 checkpoint); + +/* ============================================================ + * WPR Management (from firmware strings: VPR_WPR_WRITE_MUTEX*) + * ============================================================ */ + +int nv_vgpu_gsp_wpr_write_mutex_acquire(struct nv_vgpu_device *vgpu, u32 wpr_id); +int nv_vgpu_gsp_wpr_write_mutex_release(struct nv_vgpu_device *vgpu, u32 wpr_id); +int nv_vgpu_gsp_wpr_scratch_mutex_acquire(struct nv_vgpu_device *vgpu, u32 wpr_id); +int nv_vgpu_gsp_wpr_scratch_mutex_release(struct nv_vgpu_device *vgpu, u32 wpr_id); + +/* ============================================================ + * Firmware Address Accessors (for debugging/validation) + * ============================================================ */ + +u64 nv_vgpu_gsp_get_primary_dispatcher(void); /* 0x057a1ac0 */ +u64 nv_vgpu_gsp_get_secondary_dispatcher(void); /* 0x04ed39dc */ +u64 nv_vgpu_gsp_get_alloc_main(void); /* 0x057e94ec */ +u64 nv_vgpu_gsp_get_schedule_main(void); /* 0x051efbf4 */ +u64 nv_vgpu_gsp_get_bar_trap_handler_jt(void); /* 0x057675b7 */ +u64 nv_vgpu_gsp_get_bar_trap_handler_primary(void); /* 0x04cb8189 */ +u64 nv_vgpu_gsp_get_entry_point(void); /* 0x04009000 */ + +#endif /* _NV_VGPU_GSP_RPC_INTEGRATION_H_ */ -- cgit v1.2.3