From c648f827545871bd9fe96070d13b89073b857fe2 Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Wed, 7 Oct 2026 10:19:13 -0400 Subject: vgsp: m76 - R2 lane tail (TSG PREEMPT bWait + device-sched off + perf boost) The real client's context-creation tail after the lane-enable trio is #1073 NVA06C_CTRL_CMD_PREEMPT on the TSG with bWait=1, #1075 NV0080 device-sched disable, #1077 PERF_BOOST_SET_2X. The explicit preempt makes the RM perform a clean context save/switch-out at setup time so the first dispatch loads the context normally; without it our lane's context sits loaded from the ladder and task activation ends in a save/unload instead of execution (m72/m73/m75 signature). Gated by gsp_phys_rmcall_gr_lane_tail (default 0). --- kernel/gsp_phys_gpu.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'kernel/gsp_phys_gpu.h') diff --git a/kernel/gsp_phys_gpu.h b/kernel/gsp_phys_gpu.h index ebed0cb..3a590ea 100644 --- a/kernel/gsp_phys_gpu.h +++ b/kernel/gsp_phys_gpu.h @@ -354,6 +354,10 @@ int gsp_phys_rmcall_gr_inst_sys_value(void); * ordering; default 0 = legacy R1-after-F2). */ int gsp_phys_rmcall_gr_r1_first_value(void); +/* m76: send the R2 #1073/#1075/#1077 lane tail after the mode-35 lane + * enable (TSG preempt bWait, device-sched off, perf boost; default 0). */ +int gsp_phys_rmcall_gr_lane_tail_value(void); + /* * Ladder VAS ownership selector (gsp_phys_rmcall_vas_shared; default 0). * 0 = FERMI_VASPACE_A is allocated IS_EXTERNALLY_OWNED (historical ladder -- cgit v1.2.3