From 4925432a14bfab4e678b58fd6aa0236a3e229af5 Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Wed, 21 Oct 2026 20:01:19 -0400 Subject: r434 wedge instrumentation + CWD-slot path: post-retire QMD64 dump (hardware-only w50/w51 INNER get/put = the SKED's CTA dispatch counters, which the submission-time dump cannot show) so the healthy-vs-wedged diff proves whether the grid was dispatched and truncated; post-OK qmdwin reads the launch's own bank; gsp_phys_rmcall_gr_cwd_slot >= 0 emits the CUDA driver's CWD-slot PRI write (SKED_DEBUG_1 ENABLE_CWD_SLOT_COUNT via falcon scratch) + SET_CWD_SLOT_COUNT in the init preamble for the mission's slot-count A/B (-1 = off) --- kernel/gsp_phys_gpu.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'kernel/gsp_phys_gpu.h') diff --git a/kernel/gsp_phys_gpu.h b/kernel/gsp_phys_gpu.h index 8158b46..90783cb 100644 --- a/kernel/gsp_phys_gpu.h +++ b/kernel/gsp_phys_gpu.h @@ -393,6 +393,11 @@ int gsp_phys_gr_icache_inv_value(void); * before writing the release semaphore (default 0 = guest's FE_NONE). */ int gsp_phys_gr_rel_membar_value(void); +/* r434: enable the CWD slot count PRI (SKED_DEBUG_1 bit11) and emit + * SET_CWD_SLOT_COUNT with this value in the GR init preamble + * (-1 = off, default). */ +int gsp_phys_rmcall_gr_cwd_slot_value(void); + /* m179: dedicated re-execution budget for a data-bearing GR launch whose * retirement wait saw zero engine writes, independent of the timeout ladder's * attempt counter (default 3, clamped [0,4]). */ -- cgit v1.2.3