From 191100b51d1e6ed36bf4ff776107d551c4793621 Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Tue, 6 Oct 2026 15:41:01 -0400 Subject: vgsp: m32 rank-2 qmdwin - relocate the inline-QMD destination to a proven ring-chunk page (compile-verified, untested) --- kernel/gsp_phys_gpu.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'kernel/gsp_phys_gpu.c') diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c index 4848f4b..0c7e1e5 100644 --- a/kernel/gsp_phys_gpu.c +++ b/kernel/gsp_phys_gpu.c @@ -618,6 +618,35 @@ int gsp_phys_rmcall_gr_qmdvirt_value(void) } EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_qmdvirt_value); +/* + * Rank-2 qmdwin diagnostic (gsp_phys_rmcall_gr_qmdwin; default 0). When set, + * a forwarded GR launch relocates its inline-QMD destination from the guest + * QMD VA to a dedicated module page mapped at the ladder's own window-0 VA + * 0x107000 (GSP_PHYS_RMCALL_VA_GR_QMDWIN): the same 2 MiB window and small-PT + * page whose PTEs the GPFIFO/PB/REPORT_SEM legs have already proven + * engine-reachable and engine-writable. The PTE is planted by + * gsp_phys_rmcall_pdb_build() at stage 3, before the engine's first fetch of + * that 128 B PTE fetch line (the GMMU caches fetch lines with no invalidate, + * so a runtime PTE write into an already-fetched line would be invisible). + * Slot 0x106 (VA 0x106000) is avoided because the legacy P6a guest-mem + * pre-build owns it whenever a guest GPA is pinned; slot 0x107 is unused. + * With 1, the prewrite and post-mortem use the module page only (no guest + * page); 0 keeps the historical guest-VA destination byte-identical. Read at + * stage 3 (PTE plant) and at each launch (destination choice); enabling it + * after stage 3 falls back to the guest destination with a warning. + */ +static int gsp_phys_rmcall_gr_qmdwin_param; +module_param_named(gsp_phys_rmcall_gr_qmdwin, + gsp_phys_rmcall_gr_qmdwin_param, int, 0644); +MODULE_PARM_DESC(gsp_phys_rmcall_gr_qmdwin, + "Relocate the forwarded GR inline-QMD destination to a dedicated module page in the ladder window-0 PT line (default 0; 1 enables the Rank-2 qmdwin diagnostic)"); + +int gsp_phys_rmcall_gr_qmdwin_value(void) +{ + return gsp_phys_rmcall_gr_qmdwin_param; +} +EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_qmdwin_value); + /* * Ladder VAS ownership selector (gsp_phys_rmcall_vas_shared; default 0). * The H1 GR promote wall is a direct consequence of the ladder's -- cgit v1.2.3