From 0af8085561305d4df339bf641e12f6dff429553b Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Wed, 7 Oct 2026 10:44:20 -0400 Subject: vgsp: m78 - lane-enable skip mask + best-effort lane tail (#1063 no longer aborts it) gsp_phys_rmcall_gr_lane_skip: bit0 skips #1059 CILP mode, bit1 skips #1061 timeslice, bit2 skips #1063 device-sched. Used to bisect which lane-enable control arms the forwarded QMD enqueue and which one leaves the scheduling state that ends in the dispatch-time context save. Also makes the m76 lane tail independent of #1063 (always refused 0x1f by the server). --- kernel/gsp_phys_gpu.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'kernel/gsp_phys_gpu.c') diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c index a394425..a71ab97 100644 --- a/kernel/gsp_phys_gpu.c +++ b/kernel/gsp_phys_gpu.c @@ -795,6 +795,25 @@ unsigned int gsp_phys_rmcall_gr_lmem_tpc_size_value(void) } EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_lmem_tpc_size_value); +/* + * m78 lane-enable skip mask (gsp_phys_rmcall_gr_lane_skip; default 0). Bit 0 + * skips R2 #1059 GR_SET_CTXSW_PREEMPTION_MODE (CILP), bit 1 skips #1061 + * SET_TIMESLICE, bit 2 skips #1063 device-sched. Used to bisect which + * lane-enable control arms the enqueue and which one leaves the scheduling + * state that ends in the dispatch-time context save. + */ +static int gsp_phys_rmcall_gr_lane_skip_param; +module_param_named(gsp_phys_rmcall_gr_lane_skip, + gsp_phys_rmcall_gr_lane_skip_param, int, 0644); +MODULE_PARM_DESC(gsp_phys_rmcall_gr_lane_skip, + "Skip lane-enable controls: 1=#1059 CILP, 2=#1061 timeslice, 4=#1063 device-sched (default 0)"); + +int gsp_phys_rmcall_gr_lane_skip_value(void) +{ + return gsp_phys_rmcall_gr_lane_skip_param; +} +EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_lane_skip_value); + /* * m76 lane tail (gsp_phys_rmcall_gr_lane_tail; default 0). When set, the * mode-35 lane enable also sends the R2 capture's tail after #1063: TSG -- cgit v1.2.3