From 2f5b838c3224e04c5f531c0c85c0e60cb8746b29 Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Fri, 6 Nov 2026 18:52:49 -0500 Subject: vgsp-gl: per-stage synth SPH disable mask (r1562: DS wall reduced to SPH18) --- kernel/gsp_phys_booter.c | 76 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 51 insertions(+), 25 deletions(-) (limited to 'kernel/gsp_phys_booter.c') diff --git a/kernel/gsp_phys_booter.c b/kernel/gsp_phys_booter.c index 9e04c22..1dedf7c 100644 --- a/kernel/gsp_phys_booter.c +++ b/kernel/gsp_phys_booter.c @@ -18598,12 +18598,18 @@ MODULE_PARM_DESC(sema_gl_sph_bind_pair_safe, * 0x2100 <- 0x40 SET_PIPELINE_SHADER(4) ENABLE=FALSE|TYPE=GEOMETRY * and suppress the synthesized j0/j2/j4 binds (a disabled stage has no * program to bind). Default 0 = legacy bytes. + * + * SESSION 155 CONT 10: the all-four bool became a per-stage mask, bit j = + * synth slot j (0=VSA, 1=VSB, 2=TCS, 3=TES, 4=GS, 5=PS). A set bit emits + * that stage's client disable record (for the stages whose record the + * driver's unchanged-program path writes: 0/2/3/4) and skips that slot's + * synthesized bind (j0/j2/j4/j5; j1 is the window's own VTG record). */ -static bool gsp_phys_rmcall_gr_sph_stage_disable; +static u32 gsp_phys_rmcall_gr_sph_stage_disable; module_param_named(sema_gl_sph_stage_disable, - gsp_phys_rmcall_gr_sph_stage_disable, bool, 0644); + gsp_phys_rmcall_gr_sph_stage_disable, uint, 0644); MODULE_PARM_DESC(sema_gl_sph_stage_disable, - "Emit the client's SET_PIPELINE_SHADER disable records for VSA/TCS/TES/GS before the synthesized binds and skip their binds (default 0; legacy bytes)"); + "Per-stage synth-bind disable mask (bit j = synth slot j: 0=VSA,1=VSB,2=TCS,3=TES,4=GS,5=PS): emit the client's SET_PIPELINE_SHADER disable record for that stage and skip its synthesized bind (default 0; legacy bytes)"); static bool gsp_phys_gr_mme_pairs_emitted; /* launch emitted a pair run */ static u32 gsp_phys_gr_mme_pairs_gen; /* gen whose pairs retired OK */ static u32 gsp_phys_gr_mme_launch_gen; /* last built launch's gen */ @@ -29625,13 +29631,20 @@ gr_page_unmapped: READ_ONCE(gsp_phys_rmcall_gr_sph_bind_binding); bool pair_safe = READ_ONCE(gsp_phys_rmcall_gr_sph_bind_pair_safe); - bool stage_disable = - READ_ONCE(gsp_phys_rmcall_gr_sph_stage_disable) && - !sph_bind_all; - bool emit_j2 = !stage_disable && + /* + * SESSION 155 CONT 10: per-stage disable mask + * (bit j = synth slot j). Only meaningful when the + * all-slots knob is off, matching the r1561 bool's + * !sph_bind_all gate. + */ + u32 stage_disable_mask = !sph_bind_all ? + (READ_ONCE(gsp_phys_rmcall_gr_sph_stage_disable) & + 0x3fu) : 0u; + bool stage_disable = stage_disable_mask != 0u; + bool emit_j2 = !(stage_disable_mask & 0x04u) && (sph_bind_all || (sph_bind_mask & 0x04u)); - bool emit_j5 = sph_bind_all || - (sph_bind_mask & 0x20u); + bool emit_j5 = !(stage_disable_mask & 0x20u) && + (sph_bind_all || (sph_bind_mask & 0x20u)); /* * SESSION 155 CONT 8: the DS flags the UNBOUND VTG-class * stages (VSA/VSB/TCS/GS) in SPH bits 1/2/6/9/10/11/18. @@ -29642,9 +29655,9 @@ gr_page_unmapped: * CONT 9: stage_disable suppresses j0/j2/j4 (a disabled * stage has no program to bind). */ - bool emit_j0 = !stage_disable && + bool emit_j0 = !(stage_disable_mask & 0x01u) && (sph_bind_all || (sph_bind_mask & 0x01u)); - bool emit_j4 = !stage_disable && + bool emit_j4 = !(stage_disable_mask & 0x10u) && (sph_bind_all || (sph_bind_mask & 0x10u)); /* @@ -29684,22 +29697,35 @@ gr_page_unmapped: * (SPH18). Emit the client's disable records FIRST (so * no later synth bind re-enables them), with the exact * values the driver's disabled-stage paths write. + * CONT 10: per-bit mask - only the stages whose bit is + * set get a record (bit1 VSB and bit5 PS have no + * unchanged-program record here; bit5 only suppresses + * the synth PS bind). */ if (stage_disable) { - in[nfin++] = 0x20000000u | (1u << 16) | - (0x2000u >> 2); - in[nfin++] = 0x00u; - in[nfin++] = 0x20000000u | (1u << 16) | - (0x2080u >> 2); - in[nfin++] = 0x20u; - in[nfin++] = 0x20000000u | (1u << 16) | - (0x20c0u >> 2); - in[nfin++] = 0x30u; - in[nfin++] = 0x20000000u | (1u << 16) | - (0x2100u >> 2); - in[nfin++] = 0x40u; - pr_info_ratelimited("vgsp-gr: SPH-STAGE-DISABLE VSA/TCS/TES/GS h=0x%x push=0x%llx\n", - req->h_object, req->push_va); + if (stage_disable_mask & 0x01u) { + in[nfin++] = 0x20000000u | (1u << 16) | + (0x2000u >> 2); + in[nfin++] = 0x00u; + } + if (stage_disable_mask & 0x04u) { + in[nfin++] = 0x20000000u | (1u << 16) | + (0x2080u >> 2); + in[nfin++] = 0x20u; + } + if (stage_disable_mask & 0x08u) { + in[nfin++] = 0x20000000u | (1u << 16) | + (0x20c0u >> 2); + in[nfin++] = 0x30u; + } + if (stage_disable_mask & 0x10u) { + in[nfin++] = 0x20000000u | (1u << 16) | + (0x2100u >> 2); + in[nfin++] = 0x40u; + } + pr_info_ratelimited("vgsp-gr: SPH-STAGE-DISABLE mask=0x%x h=0x%x push=0x%llx\n", + stage_disable_mask, req->h_object, + req->push_va); } /* -- cgit v1.2.3