From 7d6c789a469de154ee6d26a7fb9161ef7279a34a Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Wed, 23 Sep 2026 00:04:14 -0400 Subject: kernel: real TU104 config-space layout (PCIe cap at 0x78) + CUDA/UVM tracing Move the emulated PCIe capability to config offset 0x78 and shift MSI to 0x48 / MSI-X to 0x68, matching the real TU104 (host lspci: PM 0x60, MSI 0x68, Express 0x78). This matters because the driver's NV_PCFG mirror (BAR0+0x88000, size 0x1000) is read as PCI config space: osDevReadReg032 -> vgpuDevReadReg032 intercepts [NV_PCFG, +0x30) (or the full 0x1000 for SRIOV) and forwards to osPciReadDword, so NV_XVE_LINK_CAPABILITIES (0x84) must be the PCIe Link Capabilities register, i.e. cap+0x0C with the cap at 0x78. Link Caps = Gen3 x16 (0x103), Link Status = 0x0103. Also set MCFG-visible caps: the guest now reports MSI [48], MSI-X [68], Express [78] exactly like the host GPU. Fixing the capability chain: the first attempt set the PCIe cap's NEXT to 0x0C, which broke enumeration (device 00:06.0 disappeared from the guest) - NEXT must terminate at 0. Unknown still open: QEMU presents type=0x92 (Root Complex Integrated Endpoint) and zeroes 0x84-0x8B in its config cache (never read from us, not refreshed by writes), and poisoning all BAR0 mirror windows with 0x103 does not change the driver's "Unknown PCIe speed" - so the value comes from the VGPU_STATIC_INFO branch (pVSI->pcieGpuLinkCaps, IS_VIRTUAL true via hypervisor detection) rather than any register read. Debug helpers added (temporary): CFGWR config-write log, PCFG change watch, PCIe-cap print at init. --- kernel/bar_emulation.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'kernel/bar_emulation.c') diff --git a/kernel/bar_emulation.c b/kernel/bar_emulation.c index 3448b8c..1229a77 100644 --- a/kernel/bar_emulation.c +++ b/kernel/bar_emulation.c @@ -309,6 +309,22 @@ int nv_vgpu_bar_emul_init(struct nv_vgpu_device *vgpu) *(u32 *)((u8 *)ctx->bar0_shadow + 0xC08084) = 0x00000103; *(u32 *)((u8 *)ctx->bar0_shadow + 0xC08088) = 0x01030000; + /* TEMP EXPERIMENT: poison the candidate mirror windows with the + * Gen3 x16 link-caps value in every dword, to locate where the + * driver's gpuReadBusConfigReg(0x84) actually lands. Ranges are + * chosen to avoid real emulated registers (the CPU intr tree starts + * at 0xB81000). */ + { + u32 off; + + for (off = 0x88000; off < 0x89000; off += 4) + *(u32 *)((u8 *)ctx->bar0_shadow + off) = 0x00000103; + for (off = 0xB80000; off < 0xB80F00; off += 4) + *(u32 *)((u8 *)ctx->bar0_shadow + off) = 0x00000103; + for (off = 0xC08000; off < 0xC08F00; off += 4) + *(u32 *)((u8 *)ctx->bar0_shadow + off) = 0x00000103; + } + /* * Serve a valid VBIOS at the PROM window (BAR0+0x300000). * -- cgit v1.2.3