From 38425e0891760d86d8a34cc84e8b8f8b39479a8d Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Mon, 21 Sep 2026 23:18:53 -0400 Subject: kernel: STATIC_KGR_GET_INFO handler - TU104 litter topology + maxSubcontext=64 Driver caches the GR infoList as pGrInfo and reads MAX_SUBCONTEXT_COUNT (0x2c) - zero made channel-group numMax==0, asserting channel allocation (numMax == numFree && numMax != 0 -> NV_ERR_INVALID_STATE, blocking the per-device open -> NVML 'No devices'). Fill litter topology (6 GPC x 4 TPC x 2 SM = 48 SMs) and subcontext counts = 64 (NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT_INIT). --- kernel/gsp_rm_emulation.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++ kernel/gsp_rm_tu104.h | 26 +++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/kernel/gsp_rm_emulation.c b/kernel/gsp_rm_emulation.c index d1f17cb..842d952 100644 --- a/kernel/gsp_rm_emulation.c +++ b/kernel/gsp_rm_emulation.c @@ -1111,6 +1111,54 @@ static void gsp_rm_handle_kgr_get_global_sm_order(struct gsp_emu_context *ctx, TU104_NUM_SM, TU104_NUM_TPC); } +/* + * STATIC_KGR_GET_INFO (0x20800a2a) + * + * Returns the GR infoList the driver caches as pGrInfo and reads by index - + * critically MAX_SUBCONTEXT_COUNT (0x2c): zero makes the channel group's + * numMax==0 and channel allocation asserts (numMax == numFree && numMax != 0 + * -> NV_ERR_INVALID_STATE -> "No devices"). Fill TU104 litter topology + + * subcontext counts (MAX_VEID_COUNT_INIT = 64). engineInfo[8] x infoList[58] + * of {index,data} = 3712 bytes; engine 0 = GR0. + */ +static void gsp_rm_handle_kgr_get_info(struct gsp_emu_context *ctx, + u32 sequence, + u32 *out_status, + u8 *out_params, + u32 *out_params_size) +{ + struct tu104_gr_static_info *info = + (struct tu104_gr_static_info *)out_params; /* engine 0 */ + u32 i; + + memset(out_params, 0, TU104_GR_INFO_MAX_ENGINES * + sizeof(struct tu104_gr_static_info)); + + /* positional array: index field = position for every entry */ + for (i = 0; i < TU104_GR_INFO_MAX_SIZE; i++) + info->infoList[i].index = i; + + /* TU104 litter topology: 6 GPC x 4 TPC x 2 SM = 48 SMs */ + info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_GPCS].data = TU104_NUM_GPC; + info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_TPC_PER_GPC].data = TU104_TPC_PER_GPC; + info->infoList[TU104_GR_INFO_IDX_GPU_CORE_COUNT].data = TU104_NUM_SM; + info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_SM_PER_TPC].data = TU104_SM_PER_TPC; + info->infoList[TU104_GR_INFO_IDX_FAMILY_MAX_TPC_PER_GPC].data = TU104_TPC_PER_GPC; + + /* subcontext (VEID) counts: 64 per hw */ + info->infoList[TU104_GR_INFO_IDX_MAX_SUBCONTEXT_COUNT].data = TU104_MAX_SUBCONTEXT_COUNT; + info->infoList[TU104_GR_INFO_IDX_MAX_LEGACY_SUBCONTEXT_COUNT].data = TU104_MAX_SUBCONTEXT_COUNT; + info->infoList[TU104_GR_INFO_IDX_MAX_PER_ENGINE_SUBCONTEXT_COUNT].data = TU104_MAX_SUBCONTEXT_COUNT; + + *out_params_size = TU104_GR_INFO_MAX_ENGINES * + sizeof(struct tu104_gr_static_info); + *out_status = 0; + + nv_vgpu_info(ctx->vgpu, "GSPRM: KGR_GET_INFO -> GR0 litter %uGPC/%uTPC/%uSM, maxSubctx=%u", + TU104_NUM_GPC, TU104_TPC_PER_GPC, TU104_NUM_SM, + TU104_MAX_SUBCONTEXT_COUNT); +} + static void gsp_rm_handle_rm_control(struct gsp_emu_context *ctx, const u8 *elem, u32 sequence) { @@ -1205,6 +1253,12 @@ static void gsp_rm_handle_rm_control(struct gsp_emu_context *ctx, reply + GSP_RM_CTRL_HDR_SIZE, &out_params_size); break; + case TU104_CTRL_STATIC_KGR_GET_INFO: + gsp_rm_handle_kgr_get_info(ctx, sequence, + &out_status, + reply + GSP_RM_CTRL_HDR_SIZE, &out_params_size); + break; + default: /* Unknown control command - return success with zeroed params. * Do NOT echo the request: pure queries pass uninitialized diff --git a/kernel/gsp_rm_tu104.h b/kernel/gsp_rm_tu104.h index 5a5fecd..db05f68 100644 --- a/kernel/gsp_rm_tu104.h +++ b/kernel/gsp_rm_tu104.h @@ -701,6 +701,32 @@ static const struct tu104_internal_device_info tu104_internal_device_table[] = { #define TU104_CTRL_I2C_TRANSACTION 0x402c0105 #define TU104_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE 0x20802a08 #define TU104_CTRL_STATIC_KGR_GET_GLOBAL_SM_ORDER 0x20800a22 +#define TU104_CTRL_STATIC_KGR_GET_INFO 0x20800a2a + +/* NV0080_CTRL_GR_INFO entry + infoList indices (ctrl0080gr.h) */ +struct tu104_gr_info_entry { + u32 index; + u32 data; +}; +#define TU104_GR_INFO_MAX_SIZE 58 /* NV0080_CTRL_GR_INFO_MAX_SIZE (0x3a) */ +#define TU104_GR_INFO_MAX_ENGINES 8 + +struct tu104_gr_static_info { + struct tu104_gr_info_entry infoList[TU104_GR_INFO_MAX_SIZE]; +}; + +/* infoList indices we populate (ctrl0080gr.h) */ +#define TU104_GR_INFO_IDX_LITTER_NUM_GPCS 0x14 +#define TU104_GR_INFO_IDX_LITTER_NUM_TPC_PER_GPC 0x17 +#define TU104_GR_INFO_IDX_GPU_CORE_COUNT 0x1d +#define TU104_GR_INFO_IDX_LITTER_NUM_SM_PER_TPC 0x20 +#define TU104_GR_INFO_IDX_FAMILY_MAX_TPC_PER_GPC 0x2a +#define TU104_GR_INFO_IDX_MAX_SUBCONTEXT_COUNT 0x2c +#define TU104_GR_INFO_IDX_MAX_LEGACY_SUBCONTEXT_COUNT 0x2d +#define TU104_GR_INFO_IDX_MAX_PER_ENGINE_SUBCONTEXT_COUNT 0x2e + +/* TU104 max subcontexts (NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT_INIT) */ +#define TU104_MAX_SUBCONTEXT_COUNT 64 /* TU104 SM topology: 6 GPCs x 4 TPCs x 2 SMs = 48 SMs, 24 TPCs (RTX 2080 SUPER) */ #define TU104_NUM_GPC 6 -- cgit v1.2.3