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* vgsp: mode 32 - sibling A promote before V6 constructs (compile-verified, ↵m32reorderArthur Hanson Rasmusson6 days
| | | | untested)
* vgsp: mode 31 sibling A userd memdesc (m28: TSG channel alloc rejected ↵Arthur Hanson Rasmusson6 days
| | | | without it)
* vgsp: mode 31 FBMEM ctx + pre-PDB aux prepare (m27: sysmem MAIN hung the ↵Arthur Hanson Rasmusson6 days
| | | | golden construct)
* vgsp: gate mode 31 on golden replay + physical backend (SA-CHK F1 fix)Arthur Hanson Rasmusson6 days
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* vgsp: mode 31 - D-golden-first TSG-sibling ordering (compile-verified, untested)Arthur Hanson Rasmusson6 days
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* vgsp: m26 GR launch discriminator - rebuilt window (prelude off), QMD-virt ↵Arthur Hanson Rasmusson6 days
| | | | 0x29c, w63 sentinel
* vgsp: TSG-sibling mode 30, UVM-stall Patch C, QMD shadow-window ensure + ↵Arthur Hanson Rasmusson6 days
| | | | launch diagnostics
* vgsp: install the Tier-2 scratch-pool window spine via PDE_UPDATE + IQ2M ↵Arthur Hanson Rasmusson6 days
| | | | | | | | | | | | | | | | | | | sentinel diagnostic - The Tier-2 shadow VAs (0x200000 + page<<21 + line<<16) had no PTE chain in the engine's table view on the shared-management VAS: pdb_build's client PD0 spine for the guest scratch PT pool is discarded by the server's root migration, so every param/program/release/alias leg the launch rewrites to a shadow VA was unreachable by the engine. Install each scratch pool window lazily through DMA_UPDATE_PDE_2 (same control shape as the Tier-1 installer, pool chunk as the leaf PT) the first time a shadow line in it is consumed; shared VAS only, idempotent via rmcall_guest_pt_win_mask. m17 confirmed the install is accepted (pdeIndex=1 VA 0x200000 status 0x0). - IQ2M sentinel: write 0xdeadbeef to the inline-QMD destination word 0 after the prewrite and report iq2m=ran/not-run in the post-mortem so 'engine stalled before the inline window' is distinguishable from 'QMD deposited but not executed' without a server capture.
* vgsp: mode-29 construct-last golden execution lane + fetch-aligned USERD ↵Arthur Hanson Rasmusson6 days
| | | | | | | | | | | | | | | | | control offset - New mode 29 (GOLDEN_EXEC_LAST): identical to mode 28 but skips the TURING_COMPUTE_A alloc on the client-wired golden channel (every GR object construct there blocks RM); stage 3 completes with the golden handle swapped and BIND/GPFIFO_SCHEDULE/token are accepted. Param clamp 0..29. - Shape bits: bit6 TSG parent (alloc accepted, same no-fetch), bit7 host USERD control offset 0 (THE FETCH FIX: the server applies the sysmem userd_mem base directly and ignores the captured USERD_INDEX_VALUE=3, so GP_PUT/GP_GET live at +0x8c/+0x88; m14: GP_GET advanced 1), bit8 pre-promote compute object (invalid order: RM blocked -110 + NOCAT 0x52a8b04). - Failure diagnostics: REAL GR SEM FAILED now dumps both candidate USERD control offsets (ctl and alt).
* vgsp: PRIV VA-only booking bit + verify the exact slot before consuming ↵Arthur Hanson Rasmusson6 days
| | | | | | | | | | | | | unreadable CE entries - fwclient mask bit 15 (0x8000): book the PRIV_ACCESS_MAP VA (the FWCLIENT entry form is init-only; the golden9 form carries the VA at VA_GOLDEN9_PRIV). Accepted on V6 (status 0), completing the maximal promoted context. - gsp_sema_service: svc_entry_want_reached() verifies the exact tracking slot against entry_want before the three unreadable-CE consume shortcuts treat the entry as delivered; when the slot lags, re-seed the expectation and let svc_fake_release author or queue the exact slot (UVM registration stall pair with the pool-VA verified-resolver queue).
* vgsp: golden-exec shape bisection + fwclient per-entry promotion + pool-VA ↵Arthur Hanson Rasmusson6 days
| | | | | | | | | | | | | | | | | | | | | | | | | stall fix - Mode 28 golden execution lane behind gsp_phys_rmcall_gr_promote=28 with a shape bitmask (gsp_phys_rmcall_golden_exec_shape: ring / entries=8 / sysmem USERD / USERD size / hObjectBuffer=VAS / skip replay TURING_A) and a USERD control-offset helper. Finding: the RM-managed golden channel hangs any GR object construct (-110, no assert) as soon as client submission wiring (ring or sysmem USERD) is attached, so only the captured server-owned shape constructs; the machinery is kept for future wiring ideas. - fwclient mask bit 11 (0x800): send each non-MAIN FWCLIENT promote entry as its own one-entry control and continue past refusals. V6 acceptance matrix: PM, PATCH, PRIV_ACCESS_MAP, UNRESTRICTED_PRIV_ACCESS_MAP accepted, FECS_EVENT refused 0x1f. - fwclient mask bit 12 (0x1000): golden9 VA-only global bookings (BUNDLE_CB, PAGEPOOL, ATTRIBUTE_CB, RTV_CB_GLOBAL) accepted on V6; bits 13/14 (0x2000/0x4000): FECS PA-only (refused 0x1f) and FECS VA-only (accepted). - gsp_phys_rmcall_srv_main_ignore: ignore a server-reported MAIN in the srv-ctx commit and force the client INITIALIZE_CTX + VA-only fallback. - gsp_sema_service: pool semaphores never fall back to the learned map; queue the absolute release via svc_pending_add until svc_pool_pa_resolve succeeds, and judge pool slots through the verified resolver in svc_apply_pending and the release decode (UVM registration stall fix).
* vgsp: size the fwclient non-MAIN promote entries from the golden FBMEM aux ↵Arthur Hanson Rasmusson6 days
| | | | buffers
* vgsp: mode 27 - golden9 context promote on the V6 execution channel onlyArthur Hanson Rasmusson6 days
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* vgsp: verbatim replay of the captured GR launch prelude+windowArthur Hanson Rasmusson6 days
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* vgsp: replay the vendor per-channel compute init before the forwarded GR launchArthur Hanson Rasmusson6 days
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* vgsp: prewrite QMD to destination and send explicit PCAS INVALIDATE|SCHEDULE ↵Arthur Hanson Rasmusson6 days
| | | | (IQ2M bisect)
* vgsp: drop SET_OBJECT from the forwarded GR launch replay (guest push has none)Arthur Hanson Rasmusson6 days
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* vgsp: mode 26 - full golden9 context promote on the V6 execution channelArthur Hanson Rasmusson6 days
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* vgsp: raise GR launch release poll to 5 s with progress telemetryArthur Hanson Rasmusson6 days
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* vgsp: point inline-QMD launch at the guest QMD buffer + GR post-mortem loggingArthur Hanson Rasmusson6 days
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* vgsp: alias-map indirect high-VA GR pages and fix up shadow pointersArthur Hanson Rasmusson6 days
| | | | | | | | | The mail kernel's output buffer has no QMD pointer word; the engine reaches it through a pointer inside the parameter bank, so the Tier-1 refusal at its high VA killed the launch. Alias-map such a page's guest HPA at a fresh ladder line and rewrite every matching 8-byte pointer inside the shadowed copy pages (param/program) to the alias, so engine writes land in the guest's own page and the guest's DtoH sees them.
* vgsp: track shadow ranges per record for multi-page GR buffersArthur Hanson Rasmusson6 days
| | | | | | | The inline-record path appends pages after the pointer pages, so the adjacent-entry heuristic missed the second param page. Record each shadowed range (base guest VA, line, mapped PTE count) and extend any page that continues a recorded range, up to 16 pages per 128 B line.
* vgsp: contiguous shadow PTEs for multi-page GR buffers (R4)Arthur Hanson Rasmusson6 days
| | | | | | | | | The mail launch's param buffer spans two pages but the QMD names only the base page. The second page has no pointer word, so the Tier-2 shadow path skipped it and the launch was refused. Map a page with no pointer word that is contiguous with the previous shadow-mapped page into the next PTE of the same 128 B fetch line (each line covers up to 16 consecutive 4 KB pages), keeping the rewritten base-pointer buffer contiguous for the engine.
* vgsp: raise GR forward shadow pool to 24 pagesArthur Hanson Rasmusson6 days
| | | | | | | The mail launch has 8 pointer/QMD pages plus up to two release/sem shadow lines; the 4-page pool exhausted and refused the launch even with the HPA-copy fallback. 24 covers the 16-page launch cap plus the two release shadows.
* vgsp: GR forward shadow fallback for high-VA guest pages (R4)Arthur Hanson Rasmusson6 days
| | | | | | | | | | | | The M1 forward captured the guest's mail launch but was refused at Tier-1: the guest's UVM program/param pages live at 0x7d6e... VAs whose 2 MiB window indices are outside this VAS's PDE range, so DMA_UPDATE_PDE_2 returns 0x1f and the launch fell back (bridge disabled) with the guest polling. When the page HPA was resolved on the identity domain, copy the full guest page into the Tier-2 shadow chunk and rewrite the QMD pointer pair, so pages the engine only reads need no inline coverage. Release/sem pages keep their existing direct-alias shadow lines.
* vgsp: golden9k - size every promoted GR ctx buffer from ↵golden-replayArthur Hanson Rasmusson6 days
| | | | | | | | | | | | | | | | | | GET_ENGINE_CONTEXT_PROPERTIES (REAL GR SEM OK) The golden replay promoted 0x1000 placeholders for FECS_EVENT/PRIV/UNR and 1-page VA-only mappings for the four 3D globals; the server's own geometry reports FECS_EVENT 0x10000, PRIV/UNR 0x80000 each, PAGEPOOL 0x20000, ATTRIBUTE_CB 0x7d7400 and RTV_CB_GLOBAL 0x80000 on this TU104. The girmap sizes are wrong for the engine's ctx-init access-map copies and the ctxsw bundle, producing INJECTED_BUNDLE_ERROR + FECS ctxsw TDR on every VAS shape. fwclient-mask bit 10 (0x400) sizes every promoted buffer from the server's GET_ENGINE_CONTEXT_PROPERTIES (0x801707), re-spaces the VAs to per-buffer caps, extends the ctx small-PT pages to six 2 MB windows and promotes the real sizes. Result (golden9k2): golden promote status 0, FWCLIENT MAIN promote status 0, stage 3 complete, REAL GR SEM OK sem=0xc0ffee01 GPGet=1 GPPut=1, clean teardown, no wedge.
* vgsp: golden9j - FBMEM backing + VAS mappings for the four 3D global ctx buffersArthur Hanson Rasmusson6 days
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* vgsp: golden9i - shared-management ladder VAS binding + walker ctx window ↵Arthur Hanson Rasmusson6 days
| | | | for the golden channel
* vgsp: golden9g - fabricated golden-VAS page-table levels + walker ctx windowArthur Hanson Rasmusson6 days
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* vgsp: golden9f - golden channel on the golden VAS with the client PDBArthur Hanson Rasmusson6 days
| | | | | | | | | | | | The golden9e ctxsw TDR persisted with capture-faithful FBMEM buffers and mapped VAs. Source dig: the ladder VAS is IS_EXTERNALLY_OWNED, and on that path the server's promote defers channel-context binding to UVM (which the ladder never does), so the engine ctxsw never becomes usable. The real golden channel runs on the PTETABLE_HEAP_MANAGED golden VAS (client-owned page tables, not externally owned), which takes the full client-managed commit path. golden9a/b only failed because that VAS had no page directory: install the ladder root PDB on the golden VAS via DMA_SET_PAGE_DIRECTORY before the channel alloc, and bind the golden channel to it.
* vgsp: golden9e - all ctx buffers FBMEM and every promoted VA PDB-mappedArthur Hanson Rasmusson6 days
| | | | | | | | | | | | | | | The golden9c cycle reached the server context init and then the GR ctxsw timed out (FECS_A/B TDR) with host-sysmem MAIN/PATCH/FECS/PRIV/UNR and unmapped promoted VAs; the golden9d FBMEM test ran on a boot left dirty by golden9c and its 0x1f is not attributable. The real golden wire carried FBMEM (physAttr=4) for every ctx buffer, so: - allocate PATCH/FECS/PRIV/UNR as server FBMEM (PATCH sized by the engine geometry query) in gr_ctx_prepare before the PDB build (mode 25 only); - map PATCH/FECS/PRIV/UNR at their promoted VAs with VIDMEM PTEs in the same 2 MB window as MAIN; - move the FECS/PRIV/UNR and VA-only 3D global VAs into that window and give the PA-backed entries PHYS_ATTR_FB. golden9d's FBMEM channel memdescs are kept.
* vgsp: golden9d - FBMEM channel memdescs and FBMEM MAINArthur Hanson Rasmusson6 days
| | | | | | | | | | | The golden9c cycle reached the promote commit and hung the GR engine in the ctxsw wait (FECS_A/B TDR records then a fatal assert). The real golden capture carried client-local FBMEM instance/USERD/RAMFC/mthd memdescs and FBMEM ctx buffers; the host-sysmem substitution is the remaining aperture difference. Allocate one FBMEM block for the four channel memdescs (sliced 0x1000/0x200/ 0x1000/0x1000 like the client memmgr) and back the promoted MAIN with the server FBMEM allocation (VIDMEM physAttr 0x4, VIDMEM PDB leaf PTEs) for mode 25. PATCH/FECS/PRIV/UNR stay host sysmem in this iteration.
* vgsp: golden9c - bind golden channel to the ladder's proven VASArthur Hanson Rasmusson6 days
| | | | | | | | | | | The captured golden VAS cannot be fully constructed by the ladder: its COPY_SERVER_RESERVED_PDES (0x90f10106) consumes client-RM-reserved page-table level PAs that only exist in the real client's memmgr (and are boot-specific). Bind the golden channel to the ladder's own FERMI_VASPACE_A, which already has server page tables installed by the DMA_SET_PAGE_DIRECTORY + PDB build, so the pVAS validation in kchannelConstruct_IMPL is satisfied. hObjectBuffer stays 0 (host sysmem PB is client-local) and the USERD keep the proven V5 memdesc pairing.
* vgsp: add golden-replay mode 25 (captured client construct + atomic 9-entry ↵Arthur Hanson Rasmusson6 days
| | | | | | | | | | | | | | | | | | promote) Ladder mode 25 reproduces the real 570.144 host client's golden-image construct on the golden replay handles: captured channel shape (flags 0x00200320, hObjectBuffer 0, gpFifoOffset 0, gpFifoEntries 0x20, engineType 1, host memdesc substitutions), a single atomic 9-entry GPU_PROMOTE_CTX on the golden channel (MAIN id0 and PATCH id2 combined, ids 3/4/5/6 VA-only globals, ids 9/10/11 FECS/PRIV/UNR combined), then the TURING_A 3D object. The golden VAS/channel/3D object stay alive and the existing V6 FWCLIENT promote follows on the golden-initialized GR-instance state; a failed golden step aborts with no retry and no follow-up promote. The captured VAS COPY_SERVER_RESERVED_PDES control is implemented gated (fwclient mask bit 8, zero-level no-op form) because its level PAs are server-internal. Mode clamp/name/help extended to 25; modes 1-24 unchanged.
* vgsp: fix host crash in FWCLIENT promote order (MAIN first, non-MAIN after)Arthur Hanson Rasmusson7 days
| | | | | | | | | | | | | | | | The 2026-10-05 16:05 crasher sent an accepted non-MAIN PROMOTE_CTX (PM/PATCH/FECS/PRIV/UNR) before a MAIN control that failed 0x40; the writing task then Oopsed in vma_interval_tree_remove with a corrupted VMA rbtree and module list (host kernel memory corruption). Restore the reference order (kgrobjGetPromoteIds_FWCLIENT: MAIN first) and make MAIN-alone the abort point: GPU_INITIALIZE_CTX (mask bit7) then the single-entry MAIN promote; build and send the non-MAIN entries only after MAIN commits (or when MAIN is deselected). The previous accepted-non-MAIN-before-failing-MAIN order is forbidden. Build is unchanged otherwise; mask 0xbf now reproduces the proven-clean mask-0x81 shape when MAIN hits the memdesc gate.
* vgsp: FWCLIENT entry-selection mask and golden-replay hardeningArthur Hanson Rasmusson7 days
| | | | | | | | | | | | - gsp_phys_rmcall_fwclient_mask (default 0x3f): per-entry selection for the mode-24 FWCLIENT promote set; bit6 selects the MAIN UVM VA-only shape. - golden replay: tolerate the client-local system-memory PB step and continue with hObjectBuffer=0; on-ladder TURING_A 3D object retained best-effort. Live bisection on the KMD channel: MAIN alone reaches the per-buffer commit and stops at the engine-context memdesc state; PM-only and PATCH-only are accepted; any multi-entry control containing MAIN is refused 0x1f. All cycles release clean.
* vgsp: GR golden-replay groundwork and FWCLIENT promote mode 24Arthur Hanson Rasmusson7 days
| | | | | | | | | | | | | | | | | | - golden replay (gsp_phys_rmcall_golden, default off): replay the stock client's post-load golden channel allocations (separate VAS, pushbuffer objects, USERD, bare GR channel, TURING_A 3D object) before the ladder channel; best-effort: a failure warns and the ladder continues. - on-ladder TURING_A (0xc597) 3D object allocation before the compute object (best-effort) to initialize server-side GR-instance state. - promote mode 24: the reference FWCLIENT non-3D set (MAIN, PM, PATCH, FECS_EVENT, PRIV_ACCESS_MAP, UNRESTRICTED_PRIV_ACCESS_MAP) as one GPU_PROMOTE_CTX on the KMD channel, with per-entry logging and explicit omission semantics; mode clamps/descriptions extended to 24. Live: mode 23 soft-stops 0x1f on the server-managed shared channel and reaches the per-buffer commit on the KMD channel, where it stops at the missing engine-context memdesc; mode 24 emits all six entries and is refused with 0x1f before BIND. All cycles release clean, GPU green.
* vgsp: GR promote mode 23 (hVirtMemory FBMEM server-managed commit shape)Arthur Hanson Rasmusson7 days
| | | | The hVirtMemory no-entry promote backed by the server-owned FBMEM context object (GSP_RM_ALLOC class 0x40) on the server-managed shared V5 channel. A physical memdesc bypasses the server-booked engine-ctx vaList and hands the memdesc straight to the per-buffer commit 0x5b00d2c, the one remaining promote shape on the stable shared+srvctx path. Runs grv23/grv23v6 soft-stop at PROMOTE_CTX hVirtMemory status=0x1f before BIND with clean releases.
* vgsp: srv_ctxcommit mode 2 (V6 client combined init+VA entry)Arthur Hanson Rasmusson7 days
| | | | | | | | | Make gsp_phys_rmcall_srv_ctxcommit an int mode: 1 (default) = map + INITIALIZE_CTX + UVM-shape VA-only promote; 2 = V6 client variant, no INITIALIZE_CTX and one combined PA+VA MAIN entry with bInitialize=1 and bNonmapped=0 so the first ctxsw initializes from the golden image; 0 = pure server-managed. Lets the next supervised cycle bisect both entry shapes without a rebuild. Build clean; not hardware-tested (GPU wedged).
* vgsp: V6 client-owned ctx-buffer VA commit path (srvctx)Arthur Hanson Rasmusson7 days
| | | | | | | | | | | | Source-confirmed: with the SKIP_CTXBUFFER_ALLOC channel flag the server does not allocate MAIN, does not map/book it, and its internal init/promote helpers return early for KMD virtual contexts. The client therefore owns the buffer. When no server MAIN is reported on a V6 channel, map the prepared client MAIN at the ladder ctx VA (sysmem PTEs), send GPU_INITIALIZE_CTX to install the memdesc, then the UVM-shape VA-only promote; with no server pre-booking the vaListSetManaged gate should pass and the per-buffer commit program the engine context pointer. V5 keeps the historical PA-only fallback. Build clean; not hardware-tested (GPU wedged).
* vgsp: GR forwarding static-review fixes (GR/CE slot bit, release VA->PA, ↵Arthur Hanson Rasmusson7 days
| | | | | | | | | | | | | | | | | | | | | | shadow refusal) Five defects found in a static review of the default-off GR forwarding path (no hardware test possible; GPU wedged): - clear the shared request slot's GR mode bit when a CE request is filled, so a prior GR request can never make a later CE push run the GR work function with stale fields; - resolve the QMD release0 guest VA to a guest PA on the service thread (counter pin/derive, else the trusted resolver) and only convert PA->HPA in the work item; the previous code fed the VA to the PA-based translator and would write release0 into an unrelated guest page; - take the refusal path (goto gr_page_unmapped) on every Tier-2 shadow failure instead of continuing to submit a half-built method stream; - consume the QMD run on replay passes when the GR forward is enabled so replayed QMD words are never reinterpreted as CE method headers; - only queue a captured GR candidate against the channel that captured it. Build clean (make -C kernel, W=1 only pre-existing warnings).
* vgsp: guest GR forwarding backend and capture (gsp_phys_gr_forward, default off)Arthur Hanson Rasmusson7 days
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a default-off guest GR (compute) forwarding path so a guest CUDA launch submitted on its GR channel can be executed by the physical GR engine on the ladder channel, with fail-closed fallback to the host CUDA bridge and the unchanged software release path. - New module parameter gsp_phys_gr_forward (default 0) and accessor. - New GR execution gate: boot_stage.rmcall_gr_exec_ok, latched only after a real GR submission logs REAL GR SEM OK; the backend refuses while it is unset. - Sema capture: a completed 64-word inline QMD on a trusted, non-replay GR decode becomes an svc_gr_cand (push identity, decoded release0, parameter/program/pointer fields, up to 8 captured inline-write records); the CUDA bridge stays authoritative while the parameter is off and is reached in order forward -> bridge -> software release. - Backend: gsp_phys_backend_guest_gr_submit() maps pages at their own guest VAs through fresh Tier-1 small-PT pages/PDE installs or relocates inline-captured pages to ladder shadow pages (Tier 2), builds SET_OBJECT + the inline-QMD method run + REPORT_SEMAPHORE on the compute subchannel, reuses the shared GPFIFO/USERD/doorbell publish tail (extracted from the CE submit path, CE bytes unchanged) and polls the QMD release and/or module semaphore, draining the epoch-gated fault queue on timeout. - Sema wiring: GR requests reuse the INFLIGHT/hold/deferral machinery so the guest channel release applies only on the submit's success/failure edge; hold shims preserve the channel engine type. - Counters and a work_gr state line plus a stats accessor. - Bounds are fixed: 16 pages, 8 inline records, 64 QMD words; every pointer/size checked, pool exhaustion and stale mappings fail closed. - New ABI layouts pinned with static_asserts. Compile-only change: no device test performed. (cherry picked from commit ae507e6f241c7e3498728f9d1ffc2d41ede5cd64)
* vgsp: add gsp_phys_rmcall_channel to force one GR channel variantArthur Hanson Rasmusson7 days
| | | | | | | | | | Lets a bisection pair any promote shape with any channel shape, in particular V6 (SKIP_CTXBUFFER_ALLOC, KMD-managed) with the server-managed VA-only promote: with skip-ctxbuffer the server's kgrctxMapCtxBuffers does not pre-book the engine context vaList, so the VA branch's vaListSetManaged(NV_FALSE) gate should pass and the per-buffer commit can program the engine context VA. Default 0 keeps the mode-selected walk byte-identical. Not hardware-tested (GPU wedged; see Handoff ADDENDUM 51).
* vgsp: GR server-managed context commit experiments (EVICT, VA promote, ↵Arthur Hanson Rasmusson7 days
| | | | | | | | | | | | | | | | | | | | | | | | | external path) Rung-2 bisection after the GET_CTX_BUFFER_INFO ABI fix made the server ctx geometry visible (8 buffers; MAIN 0x133000 FBMEM, PATCH 0x5000): - map the server MAIN/PATCH at the ladder ctx VAs with FBMEM PTEs and send the UVM-shape VA-only promote (bInitialize=0, bNonmapped=0). On the shared VAS the per-entry VA branch calls vaListSetManaged(NV_FALSE) and returns 0x40 because the server pre-booked MAIN as managed; EVICT_CTX (status 0) does not release that booking. - try the same VA promote on the external VAS where the server did not book (kgrctxMapCtxBuffers early-returns): the promote never replies (-110) and leaves the device in the locked fail-safe (WPR2 up, unbound). Do not repeat this shape without a new hypothesis. - FBMEM physAttr selection for the server MAIN fixed (aperture 2 -> 0x4); gsp_phys_rmcall_srv_ctxcommit parameter added (0 = pure server-managed, no client promote). - query prints all 16 entries and records PATCH; query ABI 80-B/5136. Hardware state after the external-VAS run: GPU wedged, reboot required (no automated reboot). All shapes stay default-off behind gr_promote=17 + gsp_phys_srv_ctxbuf.
* vgsp: GR ctx query ABI fix, server-managed ctx map exclusion, raw diag captureArthur Hanson Rasmusson7 days
| | | | | | | | | | | | | | | | - NV2080_CTRL_GR_CTX_BUFFER_INFO is 80 bytes (NvBool is NvU8: flags at 56..59, uuid at 60) and the params are 5136 bytes, not 5648; the previous ABI mismatch is why GR_GET_CTX_BUFFER_INFO returned NV_ERR_INVALID_ARGUMENT (0x1f) on every shared-VAS cycle. - Under gsp_phys_srv_ctxbuf the GSP-RM server allocates/maps/commits the engine context itself: do not install the client GR context-window PDEs and do not map the client ctx VA in the PDB, so a client mapping cannot clobber the server's own context-window page table. - Dump the server-written INSTANCE/RAMFC chunks after BIND/SCHEDULE on the shared GR path so the committed engine-context pointer/VA can be located. - Emit the full NOCAT diag buffer as 16-byte hex rows (the printable copy is capped at 192 dotted bytes and hides binary fault dumps). Untested on hardware at commit time; the next supervised GR cycle validates.
* vgsp: GR shared path ctx-window PDE install and PATCH+MAIN PA-only promote ↵Arthur Hanson Rasmusson7 days
| | | | | | | | | | | fallback - UPDATE_PDE_2 now also installs the GR context window PT pages (PDE 17+). - The shared-path fallback promotes PATCH then MAIN PA-only (mode-13 order, the real client's set); the mapped (bNonmapped=0) entry still hits the known 0x40 structural gate and is not sent. - Shared+srvctx: channel/BIND/schedule/token/GPFIFO fetch all green; the remaining failure is ROBUST_CHANNEL_GR_FAULT_DURING_CTXSW (0x2c).
* vgsp: GR ladder shared-VAS page-table install and server-managed ctx commit pathArthur Hanson Rasmusson7 days
| | | | | | | | | | | | | | | | - DMA_UPDATE_PDE_2 client control installs the ladder leaf PT through the server's own MMU walker on the shared-management VAS (the raw-PDB entries are not preserved by the root migration); FLUSH_PDE_CACHE + post-install refill + PT diagnostics. - srvctx registry profile also disables split VAS management; MAP_MEMORY_DMA is not served by GSP-RM for this client (NV_ERR_INVALID_FUNCTION), so the PDE control replaces it. - shared-path context commit helper: GPU_INITIALIZE_CTX + PA-only GPU_PROMOTE_CTX for the server-reported (or client fallback) MAIN buffer; GR_GET_CTX_BUFFER_INFO sends bufferCount=64. - Result: shared VAS + srvctx no longer wedges; channel/BIND/schedule/token green, PBDMA fetches the GPFIFO (GPGet=1); remaining wall is ROBUST_CHANNEL_GR_FAULT_DURING_CTXSW (0x2c).
* vgsp: host CUDA bridge + sema release recovery; greeneye simulator waveArthur Hanson Rasmusson9 days
| | | | | | | | - kernel: gsp_cuda_bridge (QMD launch capture, debugfs job/out/done, param+output resolution cached from inline writes), sema drain fixes (never hold/starve a channel), GR ring autopin + counter autoreg, per-page push reads, counter-derive gate; module builds clean - tools/cuda-bridge: CUDA driver-API daemon executing mail/vadd kernels on the physical GPU, CUBB2/CBD2 v2 protocol, layout check + self-tests - tools/guest-diag + tools/cuda-ab: scanner/pin fixes, victory push-only mode - debug/risc-v-gsp-rm-vm: Phase S simulator wave (GSP device model, boot ladder, triage/re-demo harnesses, docs 30-41), GPGPU-sim scaffolding - STATE-CURRENT/docs updates
* kernel: capture the guest's PROMOTE_CTX entries; add promote mode 19 ↵Arthur Hanson Rasmusson10 days
| | | | | | | | | | | | | | | (guest-faithful 9-entry set) - gsp_rm_emulation: dump every guest GPU_PROMOTE_CTX (0x2080012b) params and entries so the real client's promote shape is observable (captured on the emulation path: MAIN 2 MB PA+VA, PATCH, BUNDLE_CB/PAGEPOOL/ATTRIBUTE_CB/ RTV_CB_GLOBAL VA-only, FECS, PRIV, UNRESTRICTED) - gsp_phys_booter: promote mode 19 replays that exact 9-entry shape on the V5 channel with host buffers (MAIN 2 MB + PDB map, small buffers, booking-only VAs); clamp 0..19 - docs/eng-ops: mode-19 result recorded - the server never replied (fn76 -110) and the release fail-safe held WPR2/GPU until an approved reboot; mode 19 is known-wedging
* kernel: GR promote mode 18 (client FERMI_CONTEXT_SHARE_A via hContextShare)Arthur Hanson Rasmusson10 days
| | | | | | | | | | | - gsp_phys_booter: mode 18 allocates a FERMI_CONTEXT_SHARE_A (0x9067) on the TSG with the ladder VAS and carries it as hContextShare on the V6 KMD channel, so the share construct can allocate the GraphicsSubcontext the single-MAIN promote needs; clamp 0..18 - docs/eng-ops: GR promote bisection row updated with the session-2 results (modes 12-18: PA-only accepted but no ENG_CTX_VALID; PATCH/PM/FBMEM and server-managed registry all leave the KMD promote at 0x40; wall is the commit/RAMFC path)
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