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SM I-fetch lottery
m91-class recap: the first attempt of a mid-sequence forwarded GR launch
raises SM warp exceptions ("Illegal Instruction Encoding", "Out Of Range
Register") on garbage instruction bytes while a retry of the IDENTICAL QMD
and identical shadow content succeeds (r219: fault at +2.5 s, fast re-arm
recovered 3 ms later; r223 same pattern). The host retry path only replays
the mode-35 lane-enable tail + channel/TSG schedules + doorbell and
re-publishes the same method block on a fresh ring entry: no shadow re-copy,
no QMD re-read, no cache/TLB invalidate exists anywhere in the ladder. Plain
re-submission of byte-identical content flipping the outcome names stale
engine-side fetch state at first dispatch, not a content or programming
error: the window-0 shadow pool alternates two 8-page banks by submit
epoch, so a program VA's bytes change every two launches, and every
captured guest QMD carries the QMD v2.3 cache-control word (word 5) with
INVALIDATE_INSTRUCTION_CACHE (bit 30) clear - the client driver arms that
bit only under its forced-invalidate mode.
Two changes:
1. FAULT-CAP (diagnostic, inert until a fault): when a forwarded launch's
fault epoch advanced across its window, emit one "vgsp-m91: FAULT-CAP"
line per launch (capped at 20 per module-load cycle, then one
suppression notice) with: fault-epoch delta, QMD address + first 64 B,
live program pair (w48/w49) + resolved engine-visible VA/PA, the first
64 B at that code address, retry decision (fast re-arm /
resched/fresh-entry / none) + outcome (ok vs timeout), and the newest
relay-decoded 0x1006 note (exceptType/chid/errString). A fault-free
launch costs one epoch read and one compare (greens unaffected
statically: no prints, no content reads, no engine access).
2. QMD icache invalidate (fix, param-gated default-on
gsp_phys_gr_icache_inv=1): set QMD v2.3 word 5 bit 30 in the forwarded
QMD (forcing an instruction refetch at dispatch) only when the QMD
carries the client driver's standard cache-control signature (word 5
bits 26..29 set) so an unknown QMD revision is never touched; 0 restores
the exact pre-change QMD for a one-flip A/B. The bit cannot alter
instruction bytes or data - it only invalidates cached fetch state (the
same field the client driver sets under forced invalidate) - so green
launches keep their semantics; the only cost is a per-launch refetch.
Expected next-cycle evidence: zero FAULT-CAP lines with the multi-page
client set green confirms the stale-fetch mechanism; any FAULT-CAP content
policies the remaining candidates (shadow-VA reuse distance, cross-cycle
context state left by killed clients). Doc: 03-architecture/13-vexecution-
plane.md m91-class section.
(cherry picked from commit 682a5559b1dbbd482d8fe6bdabbc46220ce0d5de)
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completion with FORENSICS-grv5
Line anchors drifted when a9d29cba landed after the doc was written at
0da66259 (svc_thread, svc_gr_request, svc_pending_add, the H3 guard, the
readiness gate). Also: the grv5 SEMA_DBG=Y campaign showed the notifier and
event wake-up do fire while the counter slot publication is the link that
never writes, so the document's 'completion wake-up' framing was stale in
the stage table, section 3.4, section 6.1, the challenges and the iteration
plan; refresh the status hash, the discovery-cadence wording and the
mode-matrix source note, and extend the change log.
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