1 files changed, 71 insertions, 0 deletions
diff --git a/kernel/gsp_phys_vbios.h b/kernel/gsp_phys_vbios.h
new file mode 100644
index 0000000..5fc6e85
--- /dev/null
+++ b/kernel/gsp_phys_vbios.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef GSP_PHYS_VBIOS_H
+#define GSP_PHYS_VBIOS_H
+
+#include <linux/types.h>
+#include <linux/pci.h>
+
+/*
+ * Real-GSP boot stage 3c support: video-BIOS access and parsing.
+ *
+ * The FWSEC image that verifies and carves WPR2 is not part of the GSP-RM
+ * firmware file - it ships in the GPU's own VBIOS. This module reads the
+ * VBIOS through the PROM window while the physical GPU is claimed, walks the
+ * legacy PCI ROM header / ROM directory, then finds the BIOS Information
+ * Table (BIT) and the FWSEC falcon-ucode entry in the expansion ROM.
+ *
+ * All accesses are read-only. Disabled unless stage 3c is enabled
+ * (gsp_phys_fwsec=1); claim must be enabled too.
+ */
+
+/* Upper bound used by the distribution driver's ROM extraction (1 MB). */
+#define GSP_PHYS_VBIOS_MAX_SIZE		0x00100000
+
+/* PROM data window in BAR0: NV_PROM_DATA(i), 32-bit reads only. */
+#define GSP_PHYS_VBIOS_PROM_WINDOW	0x00300000
+
+/* FWSEC ucode application ids in the BIT falcon-ucode table. */
+#define GSP_PHYS_FWSEC_APPID_FIRMWARE_SEC_LIC	0x05
+#define GSP_PHYS_FWSEC_APPID_DEBUG		0x45
+#define GSP_PHYS_FWSEC_APPID_PROD		0x85
+
+struct gsp_phys_vbios {
+	u8 *data;			/* copied VBIOS image (host memory) */
+	size_t size;			/* usable image size in bytes */
+	u32 pci_offset;			/* image start offset of the base ROM */
+	u32 expansion_rom_offset;	/* expansion ROM base, from image start */
+	u64 version;			/* (binary version << 8) | OEM, 0 if absent */
+};
+
+/*
+ * FWSEC falcon-ucode descriptor as found in the BIT. Only the V2 variant is
+ * accepted: on this GPU generation the security falcon cannot boot the V3
+ * (boot-from-HS) form, so a V3 descriptor is a hard stop.
+ */
+struct gsp_phys_fwsec_desc {
+	u32 app_id;
+	u32 target_id;
+	u32 desc_version;
+	u32 desc_size;
+	u32 desc_offset;		/* offset of the descriptor in the image */
+	u32 imem_phys_base;
+	u32 imem_load_size;
+	u32 imem_virt_base;
+	u32 imem_sec_base;
+	u32 imem_sec_size;
+	u32 dmem_offset;
+	u32 dmem_phys_base;
+	u32 dmem_load_size;
+	u32 interface_offset;
+	u32 virtual_entry;
+};
+
+int gsp_phys_vbios_read(struct gsp_phys_vbios *img, struct pci_dev *pdev,
+			void __iomem *bar0);
+void gsp_phys_vbios_free(struct gsp_phys_vbios *img);
+
+int gsp_phys_vbios_parse_fwsec(const struct gsp_phys_vbios *img,
+			       bool use_debug_app,
+			       struct gsp_phys_fwsec_desc *desc);
+
+#endif /* GSP_PHYS_VBIOS_H */