1 files changed, 27 insertions, 0 deletions
diff --git a/kernel/gsp_phys_gpu.h b/kernel/gsp_phys_gpu.h
index 6bfe3f0..214c62d 100644
--- a/kernel/gsp_phys_gpu.h
+++ b/kernel/gsp_phys_gpu.h
@@ -139,6 +139,33 @@ bool gsp_phys_work_hw_primary_enabled(void);
 bool gsp_phys_relay_enabled(void);
 
 /*
+ * True when the gsp_phys_fault_relay module parameter is set (default 0:
+ * a relayed forwarded CE copy that times out is abandoned to the unchanged
+ * software release fallback, exactly as in P6c C0+C1). When set together
+ * with gsp_phys_relay, gsp_phys_work_forward, gsp_phys_guest_mem and
+ * gsp_phys_work_defer_release, the relay-timeout path drains the GSP-RM
+ * status queue, decodes an engine fault (function 0x1006, corroborated by a
+ * 0x1020 NOCAT record) and delivers it to the guest only when its
+ * runlistId/chid match the ladder channel: the guest channel notifier is
+ * written (info32=exceptType, info16=Nv2080 engine type, status=0xffff) and
+ * the channel event posted (MSI-X). The software releases still run; a fault
+ * is never delivered for a mismatch, a late release or a stale record.
+ * One-line rollback: gsp_phys_fault_relay=0.
+ */
+bool gsp_phys_fault_relay_enabled(void);
+
+/*
+ * True when the gsp_phys_fault_inject module parameter is set (default 0:
+ * forwarded guest CE copies program the real source PTE, byte-identical
+ * behavior). When set, the relayed pair's source PTE is written as an
+ * invalid (zero) entry on the next relay submission, so the engine faults
+ * and the C3 fault path can be exercised end to end. It only ever changes
+ * the source PTE of a relayed pair (a nonzero sem_hpa); every other copy and
+ * every non-relay submission is untouched.
+ */
+bool gsp_phys_fault_inject_enabled(void);
+
+/*
  * Translate a guest GPA to the pinned host PA (gsp_phys_guest_mem ladder
  * support). The mdev is registered with vfio_register_emulated_iommu_dev():
  * its VFIO type-1 container keeps the guest DMA mappings privately, so