diff options
Diffstat (limited to 'kernel/gsp_phys_booter.c')
| -rw-r--r-- | kernel/gsp_phys_booter.c | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/kernel/gsp_phys_booter.c b/kernel/gsp_phys_booter.c index 51d6685..28bf6f9 100644 --- a/kernel/gsp_phys_booter.c +++ b/kernel/gsp_phys_booter.c @@ -9257,9 +9257,23 @@ static void gsp_phys_rmcall_pdb_build(void) u64 va = GSP_PHYS_RMCALL_VA_GR_SHADOW0_BASE + (u64)s * GSP_PHYS_PAGE_SIZE; u32 idx = (u32)((va >> 12) & 0x1ffu); + u64 pte = gsp_phys_rmcall_pte( + (u64)gsp_phys_chunk_page_dma(w0, s)); + u32 kind = + (u32)gsp_phys_rmcall_gr_pte_kind_value(); - put_unaligned_le64(gsp_phys_rmcall_pte( - (u64)gsp_phys_chunk_page_dma(w0, s)), + /* + * m96: on Turing the v2 PTE KIND field (63:56) + * has no PITCH entry (UVM turing sets + * GENERIC_MEMORY 0x06; "PITCH no longer + * exists"); a kind=0 PTE is what the SM + * I-fetch refuses with MMU_NACK while the + * FE tolerates it. gr_pte_kind selects the + * kind for the shadow pool. + */ + if (kind) + pte |= (u64)kind << 56; + put_unaligned_le64(pte, (u8 *)gsp_phys_chunk_page_va(pt, 0) + (size_t)idx * 8); } @@ -13421,6 +13435,12 @@ static int gsp_phys_rmcall_stage3(void __iomem *bar0) memset(&pdb, 0, sizeof(pdb)); pdb.phys_address = cpu_to_le64((u64)gsp_phys_chunk_page_dma( &boot_stage.rmcall_chunks[GSP_PHYS_RMCALL_BUF_VASPDB], 0)); + pr_info("vgsp-boot: rm-call: PDB root dma=0x%llx num_entries=%u flags=0x%x\n", + (u64)gsp_phys_chunk_page_dma( + &boot_stage.rmcall_chunks[GSP_PHYS_RMCALL_BUF_VASPDB], 0), + GSP_PHYS_RMCALL_PDB_NUM_ENTRIES, + GSP_PHYS_RMCALL_PDB_FLAG_APERTURE_SYSMEM_NONCOH | + GSP_PHYS_RMCALL_PDB_FLAG_ALL_CHANNELS); pdb.num_entries = cpu_to_le32(GSP_PHYS_RMCALL_PDB_NUM_ENTRIES); pdb.flags = cpu_to_le32(GSP_PHYS_RMCALL_PDB_FLAG_APERTURE_SYSMEM_NONCOH | GSP_PHYS_RMCALL_PDB_FLAG_ALL_CHANNELS); |