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-rw-r--r--debug/risc-v-gsp-rm-vm/sim/__init__.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/risc-v-gsp-rm-vm/sim/__init__.py b/debug/risc-v-gsp-rm-vm/sim/__init__.py
index 5d7ab1f..ad20893 100644
--- a/debug/risc-v-gsp-rm-vm/sim/__init__.py
+++ b/debug/risc-v-gsp-rm-vm/sim/__init__.py
@@ -1,4 +1,4 @@
-"""green-eye native RV64IMAC simulator (M1).
+"""risc-v-gsp-rm-debugger native RV64IMAC simulator (M1).
Pure-Python, deterministic, stdlib-only. :class:`sim.machine.Machine` executes
RV64IMAC from a 256 MiB RAM region with an NS16550A UART; the debugger-facing