diff options
Diffstat (limited to 'debug/risc-v-gsp-rm-vm/sim/__init__.py')
| -rw-r--r-- | debug/risc-v-gsp-rm-vm/sim/__init__.py | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/debug/risc-v-gsp-rm-vm/sim/__init__.py b/debug/risc-v-gsp-rm-vm/sim/__init__.py new file mode 100644 index 0000000..5d7ab1f --- /dev/null +++ b/debug/risc-v-gsp-rm-vm/sim/__init__.py @@ -0,0 +1,43 @@ +"""green-eye native RV64IMAC simulator (M1). + +Pure-Python, deterministic, stdlib-only. :class:`sim.machine.Machine` executes +RV64IMAC from a 256 MiB RAM region with an NS16550A UART; the debugger-facing +adapter lives in ``greeneye.sim_backend``. A machine can be given a +``greeneye.device_map.DeviceMap`` and ``unknown_mmio="lenient"`` to serve +unmodelled MMIO accesses from harvested first-touch data instead of faulting. +""" +from .decode import decode16, decode32 # noqa: F401 +from .machine import ( # noqa: F401 + R_BP, + R_BUDGET, + R_EBREAK, + R_ECALL, + R_FAULT, + R_STEP, + R_WATCH, + UNKNOWN_MMIO_MODES, + Fault, + Machine, + SimMachine, + Uart16550, +) +from .trace import Trace, make_trace # noqa: F401 + +__all__ = [ + "Machine", + "SimMachine", + "Uart16550", + "Fault", + "decode16", + "decode32", + "Trace", + "make_trace", + "R_BUDGET", + "R_BP", + "R_WATCH", + "R_EBREAK", + "R_FAULT", + "R_STEP", + "R_ECALL", + "UNKNOWN_MMIO_MODES", +] |
