diff options
| -rw-r--r-- | kernel/gsp_phys_booter.c | 33 | ||||
| -rw-r--r-- | kernel/gsp_phys_gpu.c | 20 | ||||
| -rw-r--r-- | kernel/gsp_phys_gpu.h | 4 |
3 files changed, 51 insertions, 6 deletions
diff --git a/kernel/gsp_phys_booter.c b/kernel/gsp_phys_booter.c index 2273164..17fdcee 100644 --- a/kernel/gsp_phys_booter.c +++ b/kernel/gsp_phys_booter.c @@ -13635,14 +13635,34 @@ static int gsp_phys_rmcall_stage3(void __iomem *bar0) ret); return ret; } + /* + * m74 ordering (gsp_phys_rmcall_gr_r1_first; default 0 = + * legacy R1-after-F2): F2's mapped-MAIN promote runs the + * one-shot context-image initializer (0x52a94f8, sets + * pEngCtx+0x135) which consumes the per-VAS vaLists at + * that moment. With R1 after F2 the image's PATCH/PM/ + * priv-map/global pointers are zero and the engine + * context restore fails silently (FECS unloads at QMD + * activation). Sending R1's VA bookings first makes the + * image carry them; the construct still finds the lists + * populated and stays green. + */ + if (gsp_phys_rmcall_gr_r1_first_value()) { + ret = gsp_phys_rmcall_user_lane_va_promote(bar0); + if (ret) + pr_err("vgsp-boot: rm-call: mode 35 VA-only booking promote (R1, first) failed (%d); continuing best-effort (the construct result shows whether the per-VAS ctx-buffer maps were the gate)\n", + ret); + } ret = gsp_phys_rmcall_user_lane_main_promote(bar0); if (ret) pr_err("vgsp-boot: rm-call: mode 35 MAIN mapped promote (F2) failed (%d); continuing best-effort (the construct result shows whether the initialized flag was set)\n", ret); - ret = gsp_phys_rmcall_user_lane_va_promote(bar0); - if (ret) - pr_err("vgsp-boot: rm-call: mode 35 VA-only booking promote (R1) failed (%d); continuing best-effort (the construct result shows whether the per-VAS ctx-buffer maps were the gate)\n", - ret); + if (!gsp_phys_rmcall_gr_r1_first_value()) { + ret = gsp_phys_rmcall_user_lane_va_promote(bar0); + if (ret) + pr_err("vgsp-boot: rm-call: mode 35 VA-only booking promote (R1) failed (%d); continuing best-effort (the construct result shows whether the per-VAS ctx-buffer maps were the gate)\n", + ret); + } gsp_phys_rmcall_ctx_diag_decode("mode35 V7 post-promotes (m62 readback)"); ret = gsp_phys_rmcall_alloc_gr_object_class(bar0, GSP_PHYS_RMCALL_CLASS_COMPUTE, @@ -16625,7 +16645,7 @@ gr_page_unmapped: ioread32(bar0 + 0x0040a508u), ioread32(bar0 + 0x0040a50cu)); if (bar0) - pr_info("vgsp-gr: SKED readback: HWW_ESR=0x%08x HWW_EN=0x%08x INFO1=0x%08x INFO2=0x%08x INFO3=0x%08x CWD_T0=0x%08x CWD_T1=0x%08x CWD_T2=0x%08x ACT=0x%08x FECS_CTX=0x%08x\n", + pr_info("vgsp-gr: SKED readback: HWW_ESR=0x%08x HWW_EN=0x%08x INFO1=0x%08x INFO2=0x%08x INFO3=0x%08x CWD_T0=0x%08x CWD_T1=0x%08x CWD_T2=0x%08x ACT=0x%08x FECS_CTX=0x%08x CWD_FS=0x%08x\n", ioread32(bar0 + 0x00407020u), ioread32(bar0 + 0x00407024u), ioread32(bar0 + 0x00407028u), @@ -16635,7 +16655,8 @@ gr_page_unmapped: ioread32(bar0 + 0x00407064u), ioread32(bar0 + 0x00407068u), ioread32(bar0 + 0x00407054u), - ioread32(bar0 + 0x00409b00u)); + ioread32(bar0 + 0x00409b00u), + ioread32(bar0 + 0x00405b00u)); if (bar0) pr_info("vgsp-gr: SKED watermark[0..15]=0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", ioread32(bar0 + 0x004070a0u), diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c index ceb85ee..2f8a127 100644 --- a/kernel/gsp_phys_gpu.c +++ b/kernel/gsp_phys_gpu.c @@ -796,6 +796,26 @@ unsigned int gsp_phys_rmcall_gr_lmem_tpc_size_value(void) EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_lmem_tpc_size_value); /* + * m74 R1/F2 ordering (gsp_phys_rmcall_gr_r1_first; default 0). 1 = send the + * VA-only booking promote (R1) before F2's mapped-MAIN promote so the + * one-shot context-image initializer (0x52a94f8, pEngCtx+0x135) sees the + * per-VAS vaLists and writes their pointers into the GR context image; + * 0 = legacy order (R1 after F2). The FECS-unload-at-dispatch signature of + * m72/m73 is consistent with the image's aux pointers being zero. + */ +static int gsp_phys_rmcall_gr_r1_first_param; +module_param_named(gsp_phys_rmcall_gr_r1_first, + gsp_phys_rmcall_gr_r1_first_param, int, 0644); +MODULE_PARM_DESC(gsp_phys_rmcall_gr_r1_first, + "Send the R1 VA booking before F2's mapped-MAIN promote (default 0 = legacy order)"); + +int gsp_phys_rmcall_gr_r1_first_value(void) +{ + return gsp_phys_rmcall_gr_r1_first_param; +} +EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_r1_first_value); + +/* * m73 sysmem instance/RAMFC selector (gsp_phys_rmcall_gr_inst_sys; default 0). * The m70 capture-shape FBMEM instance/ramfc makes the FECS context load * never complete (sampler: NEW_CTX=V7 instance with VALID=0, then unloaded; diff --git a/kernel/gsp_phys_gpu.h b/kernel/gsp_phys_gpu.h index 939cf0f..ebed0cb 100644 --- a/kernel/gsp_phys_gpu.h +++ b/kernel/gsp_phys_gpu.h @@ -350,6 +350,10 @@ int gsp_phys_rmcall_gr_skedrec_value(void); /* m73: use host-visible sysmem chunks for V7 instance/RAMFC (m62 shape). */ int gsp_phys_rmcall_gr_inst_sys_value(void); +/* m74: send the R1 VA booking before F2's mapped-MAIN promote (image-init + * ordering; default 0 = legacy R1-after-F2). */ +int gsp_phys_rmcall_gr_r1_first_value(void); + /* * Ladder VAS ownership selector (gsp_phys_rmcall_vas_shared; default 0). * 0 = FERMI_VASPACE_A is allocated IS_EXTERNALLY_OWNED (historical ladder |