Initial commit: Open-IOV vGPU-IO complete stack

- Firmware decompilation: GSP 570.144W (28.5MB ELF, RV64IMAC), 132 decompiled C files
- Kernel modules: nvidia.ko (34MB, OpenRM), open-iov-vfio.ko (2.8MB, VFIO mdev), gsp-vgpu.ko (1.8MB, guest driver)
- Userspace: libiov.so/libvgpu.so (76KB), example_vgpu (28KB), rpc_emulator.c
- PCI config space emulation (256B with PM, MSI, MSI-X, PCIe caps)
- 12 RPC types fully mapped from firmware decompilation
- BAR trap, WPR, scheduling, notification, migration emulation
- Helper scripts: load_vgpu_stack, create_mdev, launch_qemu_vgpu, test_vgpu_stack, setup_guest_driver, unload_vgpu_stack
- Architecture documentation
- Wiki: 10 technical documents
- Git LFS for large binaries (.ko, .bin, .iso, .img, .o, ghidra repos)
- nvidia-open-gpu-kernel-modules as submodule

186 files changed, 64077 insertions, 0 deletions

diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h
new file mode 100644
index 0000000..89e2219
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h
@@ -0,0 +1,68 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000base.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV01_ROOT (client) control commands and parameters */
+
+#define NV0000_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x0000,NV0000_CTRL_##cat,idx)
+
+/* Client command categories (6bits) */
+#define NV0000_CTRL_RESERVED       (0x00)
+#define NV0000_CTRL_SYSTEM         (0x01)
+#define NV0000_CTRL_GPU            (0x02)
+#define NV0000_CTRL_GSYNC          (0x03)
+#define NV0000_CTRL_DIAG           (0x04)
+#define NV0000_CTRL_EVENT          (0x05)
+#define NV0000_CTRL_NVD            (0x06)
+#define NV0000_CTRL_SWINSTR        (0x07)
+#define NV0000_CTRL_PROC           (0x09)
+#define NV0000_CTRL_SYNC_GPU_BOOST (0x0A)
+#define NV0000_CTRL_GPUACCT        (0x0B)
+#define NV0000_CTRL_VGPU           (0x0C)
+#define NV0000_CTRL_CLIENT         (0x0D)
+
+// per-OS categories start at highest category and work backwards
+#define NV0000_CTRL_OS_WINDOWS     (0x3F)
+#define NV0000_CTRL_OS_MACOS       (0x3E)
+#define NV0000_CTRL_OS_UNIX        (0x3D)
+
+
+/*
+ * NV0000_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0000_CTRL_CMD_NULL       (0x0) /* finn: Evaluated from "(FINN_NV01_ROOT_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* _ctrl0000_base_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
new file mode 100644
index 0000000..a05add6
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
@@ -0,0 +1,183 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000client.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+
+#include "ctrl/ctrlxxxx.h"
+#include "class/cl0000.h"
+#include "rs_access.h"
+
+/*
+ * NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE
+ *
+ * This command may be used to query memory address space type associated with an object 
+ *
+ * Parameters:
+ *    hObject[IN]
+ *     handle of the object to look up
+ *    addrSpaceType[OUT]
+ *     addrSpaceType with associated memory descriptor
+ *
+ * Possible status values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_OBJECT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE (0xd01) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS {
+    NvHandle hObject;                /* [in]  - Handle of object to look up */
+    NvU32    mapFlags;                  /* [in]  - Flags that will be used when mapping the object */
+    NvU32    addrSpaceType;             /* [out] - Memory Address Space Type */
+} NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS;
+
+#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID   0x00000000
+#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM    0x00000001
+#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM    0x00000002
+#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM    0x00000003
+#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC    0x00000004
+
+
+
+/*
+ * NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO
+ *
+ * This command may be used to query information on a handle
+ */
+#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO               (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS {
+    NvHandle hObject;         /* [in]  - Handle of object to look up */
+    NvU32    index;           /* [in]  - Type of lookup */
+
+    union {
+        NvHandle hResult; /* [out] - Result of lookup when result is a handle type */
+        NV_DECLARE_ALIGNED(NvU64 iResult, 8); /* [out] - Result of lookup when result is a integer */
+    } data;
+} NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS;
+
+#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID 0x00000000
+#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT  0x00000001
+#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID 0x00000002
+
+/*
+ * NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS
+ *
+ * This command may be used to get this client's access rights for an object
+ * The object to which access rights are checked does not have to be owned by
+ * the client calling the command, it is owned by the hClient parameter
+ */
+#define NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS             (0xd03) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS {
+    NvHandle       hObject;                /* [in]  - Handle of object to look up */
+    NvHandle       hClient;                /* [in]  - Handle of client which owns hObject */
+    RS_ACCESS_MASK maskResult;       /* [out] - Result of lookup */
+} NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY
+ *
+ * DEPRECATED: Calls NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT with hObject=hClient
+ *
+ * This command will modify a client's inherited share policy list
+ * The policy is applied in the same way that NvRmShare applies policies,
+ * except to the client's inherited policy list instead of an object's policy list
+ */
+#define NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY (0xd04) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS {
+    RS_SHARE_POLICY sharePolicy;       /* [in] - Share Policy to apply */
+} NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE
+ *
+ * This command may be used to get a handle of a child of a given type
+ */
+#define NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE (0xd05) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS {
+    NvHandle hParent;                /* [in]  - Handle of parent object */
+    NvU32    classId;                /* [in]  - Class ID of the child object */
+    NvHandle hObject;                /* [out] - Handle of the child object (0 if not found) */
+} NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT
+ *
+ * This command is meant to imitate the NvRmShare API.
+ * Applies a share policy to an object, which should be owned by the caller's client.
+ * The policy is applied in the same way that NvRmShare applies policies.
+ *
+ * This ctrl command is only meant to be used in older branches. For releases after R450,
+ * use NvRmShare directly instead.
+ */
+#define NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT (0xd06) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS {
+    NvHandle        hObject;                /* [in]  - Handle of object to share */
+    RS_SHARE_POLICY sharePolicy;     /* [in]  - Share Policy to apply */
+} NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES
+ *
+ * This command returns true if the objects are duplicates.
+ *
+ * Currently supported only for memory objects.
+ */
+#define NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES (0xd07) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS {
+    NvHandle hObject1;   /* [in]  - Handle of object to be checked */
+    NvHandle hObject2;   /* [in]  - Handle of object to be checked */
+    NvBool   bDuplicates;     /* [out] - Returns true if duplicates     */
+} NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS;
+
+/* _ctrl0000client_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h
new file mode 100644
index 0000000..9b72f20
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h
@@ -0,0 +1,326 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000diag.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+
+#include "ctrl/ctrlxxxx.h"
+/* NV01_ROOT (client) system control commands and parameters */
+
+/*
+ * NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE
+ *
+ * This command returns the current lock meter logging state.
+ *
+ *   state
+ *     This parameter returns the current lock meter logging state.
+ *       NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED
+ *         This value indicates lock metering is disabled.
+ *       NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED
+ *         This value indicates lock metering is enabled.
+ *   count
+ *     This parameter returns the total number of lock metering entries
+ *     (NV0000_CTRL_DIAG_LOCK_METER_ENTRY) available.  This value will
+ *     not exceed NV0000_CTRL_DIAG_LOCK_METER_MAX_ENTRIES.  When lock metering
+ *     is enabled this parameter will return zero.
+ *   missedCount
+ *     This parameter returns the number of lock metering entries that had
+ *     to be discarded due to a  full lock metering table.  This value will
+ *     not exceed NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES.  When lock
+ *     metering is enabled this parameter will return zero.
+ *   bCircularBuffer
+ *     This parameter returns type of buffer.
+ *       TRUE
+ *         Buffer is circular
+ *       FALSE
+ *         Buffer is sequential 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE (0x480) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID (0x80U)
+
+typedef struct NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS {
+    NvU32  state;
+    NvU32  count;
+    NvU32  missedCount;
+    NvBool bCircularBuffer;
+} NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS;
+
+/* valid lock metering state values */
+#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED (0x00000000)
+#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED  (0x00000001)
+
+/* maximum possible number of lock metering entries stored internally */
+#define NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES  (0x20000)
+
+/*
+ * NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE
+ *
+ * This command sets the current lock meter logging state.
+ *
+ *   state
+ *     This parameter specifies the new state of the lock metering mechanism.
+ *     Legal state values are:
+ *       NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE
+ *         This value disables lock metering.
+ *       NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE
+ *         This value enables lock metering.
+ *       NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET
+ *         This value resets, or clears, all lock metering state.  Lock
+ *         metering must be disabled prior to attempting a reset.
+ *   bCircularBuffer
+ *     This parameter specifies type of buffer.
+ *     Possible values are:
+ *       TRUE
+ *         For circular buffer.
+ *       FALSE
+ *         For sequential buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE      (0x481) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID (0x81U)
+
+typedef struct NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS {
+    NvU32  state;
+    NvBool bCircularBuffer;
+} NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS;
+
+/* valid lock metering state values */
+#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE     (0x00000000)
+#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE      (0x00000001)
+#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET       (0x00000002)
+
+/*
+ * NV0000_CTRL_DIAG_LOCK_METER_ENTRY
+ *
+ * This structure represents a single lock meter entry.
+ *
+ *   counter
+ *     This field contains the number of nanonseconds elapsed since the
+ *     the last system boot when the lock meter entry was generated.
+ *   freq
+ *     This field contains the CPU performance counter frequency in units
+ *     of ticks per second.
+ *   line
+ *     This field contains the relevant line number.
+ *   filename
+ *     This field contains the relevant file name.
+ *   tag
+ *     This field contains a tag uniquely identifying the user of the metered
+ *     lock operations.
+ *   cpuNum
+ *     This field contains the CPU number from which the metered operation
+ *     was initiated.
+ *   irql
+ *     This field contains the IRQL at which the metered operation was
+ *     initiated.
+ *   data0
+ *   data1
+ *   data2
+ *     These fields contain tag-specific data.
+ */
+#define NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH (0xc)
+
+typedef struct NV0000_CTRL_DIAG_LOCK_METER_ENTRY {
+    NV_DECLARE_ALIGNED(NvU64 counter, 8);
+
+    NvU32 line;
+    NvU8  filename[NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH];
+
+    NvU16 tag;
+    NvU8  cpuNum;
+    NvU8  irql;
+
+    NV_DECLARE_ALIGNED(NvU64 threadId, 8);
+
+    NvU32 data0;
+    NvU32 data1;
+    NvU32 data2;
+} NV0000_CTRL_DIAG_LOCK_METER_ENTRY;
+
+/* valid lock meter entry tag values */
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA        (0x00000001)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED (0x00000002)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND   (0x00000003)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA        (0x00000004)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API         (0x00000010)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API         (0x00000011)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS        (0x00000020)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS        (0x00000021)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA                (0x00000100)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL              (0x00001000)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET             (0x00002000)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET             (0x00002001)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX           (0x00002002)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX           (0x00002003)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP             (0x00003000)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM              (0x00003001)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM            (0x00003002)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA          (0x00003003)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA        (0x00003004)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC               (0x00004000)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM           (0x00004001)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT          (0x00004010)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT         (0x00005000)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE         (0x00005001)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE      (0x00005002)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG (0x00005003)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP           (0x00005004)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN       (0x00005005)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL        (0x00005006)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG   (0x00005007)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP   (0x00005008)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY         (0x00005009)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM          (0x0000500A)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT         (0x0000500B)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT          (0x0000500C)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS       (0x00006000)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA         (0x00007000)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA        (0x00007001)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR                 (0x0000F000)
+#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC                 (0x0000F00F)
+
+/*
+ * NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES
+ *
+ * This command returns lock metering data in a fixed-sized array of entries.
+ * Each request will return up NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_MAX_ENTRIES
+ * entries.
+ *
+ * It is up to the caller to repeat these requests to retrieve the total number
+ * of entries reported by NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE.
+ *
+ *   entryCount
+ *     This parameter returns the total number of valid entries returned
+ *     in the entries array.  This value will not exceed
+ *     NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX but may be less.
+ *     A value of zero indicates there are no more valid entries.
+ *   entries
+ *     This parameter contains the storage into which lock metering entry
+ *     data is returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES         (0x485) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID" */
+
+/* total number of entries returned */
+#define NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX         (0x40)
+
+#define NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID (0x85U)
+
+typedef struct NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS {
+    NvU32 entryCount;
+    NV_DECLARE_ALIGNED(NV0000_CTRL_DIAG_LOCK_METER_ENTRY entries[NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX], 8);
+} NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_DIAG_PROFILE_RPC
+ *
+ * This command returns the RPC runtime information, and
+ * will only return valid when it is running inside VGX mode.
+ *
+ *   rpcProfileCmd:
+ *      RPC profiler command issued by rpc profiler utility
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0000_CTRL_CMD_DIAG_PROFILE_RPC (0x488) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID" */
+
+typedef struct RPC_METER_ENTRY {
+    NV_DECLARE_ALIGNED(NvU64 startTimeInNs, 8);
+    NV_DECLARE_ALIGNED(NvU64 endTimeInNs, 8);
+    NV_DECLARE_ALIGNED(NvU64 rpcDataTag, 8);
+    NV_DECLARE_ALIGNED(NvU64 rpcExtraData, 8);
+} RPC_METER_ENTRY;
+
+#define NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID (0x88U)
+
+typedef struct NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS {
+    NvU32 rpcProfileCmd;
+} NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS;
+
+#define NV0000_CTRL_PROFILE_RPC_CMD_DISABLE (0x00000000)
+#define NV0000_CTRL_PROFILE_RPC_CMD_ENABLE  (0x00000001)
+#define NV0000_CTRL_PROFILE_RPC_CMD_RESET   (0x00000002)
+
+/*
+ * NV0000_CTRL_CMD_DIAG_DUMP_RPC
+ *
+ * This command returns the RPC runtime information, which
+ * will be logged by NV0000_CTRL_CMD_DIAG_PROFILE_RPC command
+ * when running inside VGX mode.
+ *
+ * When issuing this command, the RPC profiler has to be disabled.
+ *
+ *   firstEntryOffset:
+ *     [IN] offset for first entry.
+ *
+ *   outputEntryCout:
+ *     [OUT] number of entries returned in rpcProfilerBuffer.
+ *
+ *   remainingEntryCount:
+ *     [OUT] number of entries remaining. 
+ *
+ *   elapsedTimeInNs:
+ *     [OUT] runtime for the RPC profiler tool. 
+ *
+ *   rpcProfilerBuffer:
+ *     [OUT] buffer to store the RPC entries
+ */
+
+#define NV0000_CTRL_CMD_DIAG_DUMP_RPC       (0x489) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_DIAG_RPC_MAX_ENTRIES    (100)
+
+#define NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID (0x89U)
+
+typedef struct NV0000_CTRL_DIAG_DUMP_RPC_PARAMS {
+    NvU32 firstEntryOffset;
+    NvU32 outputEntryCount;
+    NvU32 remainingEntryCount;
+    NV_DECLARE_ALIGNED(NvU64 elapsedTimeInNs, 8);
+    NV_DECLARE_ALIGNED(RPC_METER_ENTRY rpcProfilerBuffer[NV0000_CTRL_DIAG_RPC_MAX_ENTRIES], 8);
+} NV0000_CTRL_DIAG_DUMP_RPC_PARAMS;
+
+/* _ctrl0000diag_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h
new file mode 100644
index 0000000..1679f84
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h
@@ -0,0 +1,113 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000event.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+
+#include "ctrl/ctrlxxxx.h"
+#include "class/cl0000.h"
+/*
+ * NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * This command sets event notification for the system events.
+ * 
+ *   event
+ *     This parameter specifies the type of event to which the specified
+ *     action is to be applied. The valid event values can be found in
+ *     cl0000.h. 
+ *
+ *   action
+ *     This parameter specifies the desired event notification action.
+ *     Valid notification actions include:
+ *       NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
+ *         This action disables event notification for the specified
+ *         event.
+ *       NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
+ *         This action enables single-shot event notification for the
+ *         specified event.
+ *       NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
+ *         This action enables repeated event notification for the 
+ *         specified event.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_CLIENT
+ *
+ */
+
+#define NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION (0x501) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
+    NvU32 event;
+    NvU32 action;
+} NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
+#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  (0x00000001)
+#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  (0x00000002)
+
+/*
+ * NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS
+ *
+ * This command returns the status of the specified system event type.
+ * See the description of NV01_EVENT for details on registering events.
+ *
+ *   event
+ *     This parameter specifies the event type. Valid event type values
+ *     can be found in cl0000.h.
+ *   status
+ *     This parameter returns the status for a given event type. Valid
+ *     status values can be found in cl0000.h.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_CLIENT
+ *
+ */
+
+#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS           (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS {
+    NvU32 event;
+    NvU32 status;
+} NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS;
+
+/* _ctrl0000event_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
new file mode 100644
index 0000000..3ce0f06
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
@@ -0,0 +1,873 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000gpu.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+#include "ctrl/ctrl0000/ctrl0000system.h"
+#include "ctrl/ctrlxxxx.h"
+#include "nvlimits.h"
+
+/* NV01_ROOT (client) GPU control commands and parameters */
+
+/*
+ * NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS
+ *
+ * This command returns a table of attached gpuId values.
+ * The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size.
+ *
+ *   gpuIds[]
+ *     This parameter returns the table of attached GPU IDs.
+ *     The GPU ID is an opaque platform-dependent value that can be used
+ *     with the NV0000_CTRL_CMD_GPU_GET_ID_INFO command to retrieve
+ *     additional information about the GPU.  The valid entries in gpuIds[]
+ *     are contiguous, with a value of NV0000_CTRL_GPU_INVALID_ID indicating
+ *     the invalid entries.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS    32U
+#define NV0000_CTRL_GPU_INVALID_ID           (0xffffffffU)
+
+#define NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS {
+    NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS];
+} NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS;
+
+/*
+ * Deprecated. Please use NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 instead.
+ */
+#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_MAX_SZNAME      128U
+
+#define NV0000_CTRL_NO_NUMA_NODE        (-1)
+
+#define NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
+    NvU32 gpuId;
+    NvU32 gpuFlags;
+    NvU32 deviceInstance;
+    NvU32 subDeviceInstance;
+    NV_DECLARE_ALIGNED(NvP64 szName, 8);
+    NvU32 sliStatus;
+    NvU32 boardId;
+    NvU32 gpuInstance;
+    NvS32 numaId;
+} NV0000_CTRL_GPU_GET_ID_INFO_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2
+ * This command returns GPU instance information for the specified GPU.
+ *
+ *   [in] gpuId
+ *     This parameter should specify a valid GPU ID value.  If there
+ *     is no GPU present with the specified ID, a status of
+ *     NV_ERR_INVALID_ARGUMENT is returned.
+ *   [out] gpuFlags
+ *     This parameter returns various flags values for the specified GPU.
+ *     Valid flag values include:
+ *       NV0000_CTRL_GPU_ID_INFO_IN_USE
+ *         When true this flag indicates there are client references
+ *         to the GPU in the form of device class instantiations (see
+ *         NV01_DEVICE or NV03_DEVICE descriptions for details).
+ *       NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE
+ *         When true this flag indicates the GPU is linked into an
+ *         active SLI device.
+ *       NV0000_CTRL_GPU_ID_INFO_MOBILE
+ *         When true this flag indicates the GPU is a mobile GPU.
+ *       NV0000_CTRL_GPU_ID_BOOT_MASTER
+ *         When true this flag indicates the GPU is the boot master GPU.
+ *       NV0000_CTRL_GPU_ID_INFO_SOC
+ *         When true this flag indicates the GPU is part of a
+ *         System-on-Chip (SOC).
+ *       NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED
+ *         When ATS is enabled on the system.
+ *   [out] deviceInstance
+ *     This parameter returns the broadcast device instance number associated
+ *     with the specified GPU.  This value can be used to instantiate
+ *     a broadcast reference to the GPU using the NV01_DEVICE classes.
+ *   [out] subDeviceInstance
+ *     This parameter returns the unicast subdevice instance number
+ *     associated with the specified GPU.  This value can be used to
+ *     instantiate a unicast reference to the GPU using the NV20_SUBDEVICE
+ *     classes.
+ *   [out] sliStatus
+ *     This parameters returns the SLI status for the specified GPU.
+ *     Legal values for this member are described by NV0000_CTRL_SLI_STATUS.
+ *   [out] boardId
+ *     This parameter returns the board ID value with which the
+ *     specified GPU is associated.  Multiple GPUs can share the
+ *     same board ID in multi-GPU configurations.
+ *   [out] gpuInstance
+ *     This parameter returns the GPU instance number for the specified GPU.
+ *     GPU instance numbers are assigned in bus-probe order beginning with
+ *     zero and are limited to one less the number of GPUs in the system.
+ *   [out] numaId
+ *     This parameter returns the ID of NUMA node for the specified GPU.
+ *     In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+
+
+#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS {
+    NvU32 gpuId;
+    NvU32 gpuFlags;
+    NvU32 deviceInstance;
+    NvU32 subDeviceInstance;
+    NvU32 sliStatus;
+    NvU32 boardId;
+    NvU32 gpuInstance;
+    NvS32 numaId;
+} NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS;
+
+
+/* valid flags values */
+#define NV0000_CTRL_GPU_ID_INFO_IN_USE                             0:0
+#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE                 (0x00000000U)
+#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE                  (0x00000001U)
+#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE             1:1
+#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000U)
+#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE  (0x00000001U)
+#define NV0000_CTRL_GPU_ID_INFO_MOBILE                             2:2
+#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE                 (0x00000000U)
+#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE                  (0x00000001U)
+#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER                        3:3
+#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE            (0x00000000U)
+#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE             (0x00000001U)
+
+
+#define NV0000_CTRL_GPU_ID_INFO_SOC                                5:5
+#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE                    (0x00000000U)
+#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE                     (0x00000001U)
+#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED                        6:6
+#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE            (0x00000000U)
+#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE             (0x00000001U)
+
+/*
+ * NV0000_CTRL_CMD_GPU_GET_INIT_STATUS
+ *
+ * This command returns the initialization status for the specified GPU, and
+ * will return NV_ERR_INVALID_STATE if called prior to GPU
+ * initialization.
+ *
+ *   gpuId
+ *     This parameter should specify a valid GPU ID value.  If there
+ *     is no GPU present with the specified ID, a status of
+ *     NV_ERR_INVALID_ARGUMENT is returned.
+ *   status
+ *     This parameter returns the status code identifying the initialization
+ *     state of the GPU. If this parameter has the value NV_OK,
+ *     then no errors were detected during GPU initialization. Otherwise, this
+ *     parameter specifies the top-level error that was detected during GPU
+ *     initialization. Note that a value of NV_OK only means that
+ *     no errors were detected during the actual GPU initialization, and other
+ *     errors may have occurred that prevent the GPU from being attached or
+ *     accessible via the NV01_DEVICE or NV20_SUBDEVICE classes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS                  (0x203U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS {
+    NvU32 gpuId;
+    NvU32 status;
+} NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS
+ *
+ * This command returns a mask of valid device IDs.  These device IDs
+ * can be used to instantiate the NV01_DEVICE_0 class (see NV01_DEVICE_0
+ * for more information).
+ *
+ *   deviceIds
+ *     This parameter returns the mask of valid device IDs.  Each enabled bit
+ *     in the mask corresponds to a valid device instance.  Valid device
+ *     instances can be used to initialize the NV0080_ALLOC_PARAMETERS
+ *     structure when using NvRmAlloc to instantiate device handles.  The
+ *     number of device IDs will not exceed NV_MAX_DEVICES in number.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS {
+    NvU32 deviceIds;
+} NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS;
+
+
+
+/*
+ * NV0000_CTRL_CMD_GPU_GET_PROBED_IDS
+ *
+ * This command returns a table of probed gpuId values.
+ * The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size.
+ *
+ *   gpuIds[]
+ *     This parameter returns the table of probed GPU IDs.
+ *     The GPU ID is an opaque platform-dependent value that can
+ *     be used with the NV0000_CTRL_CMD_GPU_ATTACH_IDS and
+ *     NV0000_CTRL_CMD_GPU_DETACH_ID commands to attach and detach
+ *     the GPU.
+ *     The valid entries in gpuIds[] are contiguous, with a value
+ *     of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries.
+ *   excludedGpuIds[]
+ *     This parameter returns the table of excluded GPU IDs.
+ *     An excluded GPU ID is an opaque platform-dependent value that
+ *     can be used with NV0000_CTRL_CMD_GPU_GET_PCI_INFO and
+ *     NV0000_CTRL_CMD_GPU_GET_UUID_INFO.
+ *     The valid entries in excludedGpuIds[] are contiguous, with a value
+ *     of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_MAX_PROBED_GPUS    NV_MAX_DEVICES
+
+#define NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS {
+    NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
+    NvU32 excludedGpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
+} NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPU_GET_PCI_INFO
+ *
+ * This command takes a gpuId and returns PCI bus information about
+ * the device. If the OS does not support returning PCI bus
+ * information, this call will return NV_ERR_NOT_SUPPORTED
+ *
+ *   gpuId
+ *     This parameter should specify a valid GPU ID value.  If there
+ *     is no GPU present with the specified ID, a status of
+ *     NV_ERR_INVALID_ARGUMENT is returned.
+ *
+ *   domain
+ *     This parameter returns the PCI domain of the GPU.
+ *
+ *   bus
+ *     This parameter returns the PCI bus of the GPU.
+ *
+ *   slot
+ *     This parameter returns the PCI slot of the GPU.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU)
+
+typedef struct NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS {
+    NvU32 gpuId;
+    NvU32 domain;
+    NvU16 bus;
+    NvU16 slot;
+} NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPU_ATTACH_IDS
+ *
+ * This command attaches the GPUs with the gpuIds matching those in
+ * the table provided by the client.
+ * The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size.
+ *
+ *   gpuIds[]
+ *     This parameter holds the table of gpuIds to attach. At least
+ *     one gpuId must be specified; clients may use the special
+ *     gpuId value NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS to indicate
+ *     that all probed GPUs are to be attached.
+ *     The entries in gpuIds[] must be contiguous, with a value of
+ *     NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid
+ *     entry.
+ *     If one or more of the gpuId values do not specify a GPU found
+ *     in the system, the NV_ERR_INVALID_ARGUMENT error
+ *     status is returned.
+ *
+ *   failedId
+ *     If NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is specified and
+ *     a GPU cannot be attached, the NV0000_CTRL_CMD_GPU_ATTACH_IDS
+ *     command returns an error code and saves the failing GPU's
+ *     gpuId in this field.
+ *
+ * If a table of gpuIds is provided, these gpuIds will be validated
+ * against the RM's table of probed gpuIds and attached in turn,
+ * if valid; if NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is used, all
+ * probed gpuIds will be attached, in the order the associated GPUs
+ * were probed in by the RM.
+ *
+ * If a gpuId fails to attach, this gpuId is stored in the failedId
+ * field. Any GPUs attached by the command prior the failure are
+ * detached.
+ *
+ * If multiple clients use NV0000_CTRL_CMD_GPU_ATTACH_IDS to attach
+ * a gpuId, the RM ensures that the gpuId won't be detached until
+ * all clients have issued a call to NV0000_CTRL_CMD_GPU_DETACH_IDS
+ * to detach the gpuId (or have terminated).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OPERATING_SYSTEM
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_IRQ_EDGE_TRIGGERED
+ *   NV_ERR_IRQ_NOT_FIRING
+ */
+#define NV0000_CTRL_CMD_GPU_ATTACH_IDS        (0x215U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffffU)
+
+#define NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV0000_CTRL_GPU_ATTACH_IDS_PARAMS {
+    NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
+    NvU32 failedId;
+} NV0000_CTRL_GPU_ATTACH_IDS_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPU_DETACH_IDS
+ *
+ * This command detaches the GPUs with the gpuIds matching those in
+ * the table provided by the client.
+ * The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size.
+ *
+ *   gpuIds[]
+ *     This parameter holds the table of gpuIds to detach. At least
+ *     one gpuId must be specified; clients may use the special
+ *     gpuId NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS to indicate that
+ *     all attached GPUs are to be detached.
+ *     The entries in gpuIds[] must be contiguous, with a value of
+ *     NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid
+ *     entry.
+ *     If one or more of the gpuId values do not specify a GPU found
+ *     in the system, the NV_ERR_INVALID_ARGUMENT error
+ *     status is returned.
+ *
+ * If a table of gpuIds is provided, these gpuIds will be validated
+ * against the RM's list of attached gpuIds; each valid gpuId is
+ * detached immediately if it's no longer in use (i.e. if there are
+ * no client references to the associated GPU in the form of
+ * device class instantiations (see the NV01_DEVICE or NV03_DEVICE
+ * descriptions for details)) and if no other client still requires
+ * the associated GPU to be attached.
+ *
+ * If a given gpuId can't be detached immediately, it will instead
+ * be detached when the last client reference is freed or when
+ * the last client that issued NV0000_CTRL_CMD_GPU_ATTACH_IDS for
+ * this gpuId either issues NV0000_CTRL_CMD_GPU_DETACH_IDS or exits
+ * without detaching the gpuId explicitly.
+ *
+ * Clients may use the NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS command
+ * to obtain a table of the attached gpuIds.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OPERATING_SYSTEM
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0000_CTRL_CMD_GPU_DETACH_IDS          (0x216U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffffU)
+
+#define NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS {
+    NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS];
+} NV0000_CTRL_GPU_DETACH_IDS_PARAMS;
+
+
+
+/*
+ * NV0000_CTRL_CMD_GPU_GET_SVM_SIZE
+ *
+ * This command is used to get the SVM size.
+ *
+ *   gpuId
+ *     This parameter uniquely identifies the GPU whose associated
+ *     SVM size is to be returned. The value of this field must
+ *     match one of those in the table returned by
+ *     NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS
+ *
+ *   SvmSize
+ *     SVM size is returned in this.
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ *
+ */
+#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID (0x40U)
+
+typedef struct NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS {
+    NvU32 gpuId;
+    NvU32 svmSize;
+} NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS;
+
+
+
+/*
+ * NV0000_CTRL_CMD_GPU_GET_UUID_INFO
+ *
+ * This command returns requested information pertaining to the GPU
+ * specified by the GPU UUID passed in.
+ *
+ * Generally only GPUs that have been attached are visible to this call. Therefore
+ * queries on unattached GPUs will fail with NV_ERR_OBJECT_NOT_FOUND.  However, 
+ * a query for a SHA1 UUID may succeed for an unattached GPU in cases where the GID
+ * is cached, such as an excluded GPU.
+ *
+ *   gpuGuid (INPUT)
+ *     The GPU UUID of the gpu whose parameters are to be returned. Refer to
+ *     NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
+ *
+ *   flags (INPUT)
+ *     The _FORMAT* flags designate ascii string format or a binary format.
+ *
+ *     The _TYPE* flags designate either SHA-1-based (32-hex-character) or
+ *     SHA-256-based (64-hex-character).
+ *
+ *   gpuId (OUTPUT)
+ *     The GPU ID of the GPU identified by gpuGuid. Refer to
+ *     NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
+ *
+ *   deviceInstance (OUTPUT)
+ *     The device instance of the GPU identified by gpuGuid. Refer to
+ *     NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
+ *
+ *   subdeviceInstance (OUTPUT)
+ *     The subdevice instance of the GPU identified by gpuGuid. Refer to
+ *     NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *
+ */
+#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO                                   (0x274U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum possible number of bytes of GID information */
+#define NV0000_GPU_MAX_GID_LENGTH                                           (0x00000100U)
+
+#define NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID (0x74U)
+
+typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS {
+    NvU8  gpuUuid[NV0000_GPU_MAX_GID_LENGTH];
+    NvU32 flags;
+    NvU32 gpuId;
+    NvU32 deviceInstance;
+    NvU32 subdeviceInstance;
+} NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS;
+
+#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT                       1:0
+#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII  (0x00000000U)
+#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002U)
+
+#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE                         2:2
+#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1     (0x00000000U)
+#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256   (0x00000001U)
+
+/*
+ * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID
+ *
+ * This command returns the GPU UUID for the provided GPU ID.
+ * Note that only GPUs that have been attached are visible to this call.
+ * Therefore queries on unattached GPUs will fail
+ * with NV_ERR_OBJECT_NOT_FOUND.
+ *
+ *   gpuId (INPUT)
+ *     The GPU ID whose parameters are to be returned. Refer to
+ *     NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
+ *
+ *   flags (INPUT)
+ *
+ *     NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII
+ *       This value is used to request the GPU UUID in ASCII format.
+ *     NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY
+ *       This value is used to request the GPU UUID in binary format.
+ *
+ *     NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1
+ *       This value is used to request that the GPU UUID value
+ *       be SHA1-based (32-hex-character).
+ *     NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256
+ *       This value is used to request that the GPU UUID value
+ *       be SHA256-based (64-hex-character).
+ *
+ *   gpuUuid[NV0000_GPU_MAX_GID_LENGTH] (OUTPUT)
+ *     The GPU UUID of the GPU identified by GPU ID. Refer to
+ *     NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
+ *
+ *   uuidStrLen (OUTPUT)
+ *     The length of the UUID returned which is related to the format that
+ *     was requested using flags.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID              (0x275U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID (0x75U)
+
+typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS {
+    NvU32 gpuId;
+    NvU32 flags;
+    NvU8  gpuUuid[NV0000_GPU_MAX_GID_LENGTH];
+    NvU32 uuidStrLen;
+} NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS;
+
+/* valid format values */
+#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT                       1:0
+#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII  (0x00000000U)
+#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002U)
+
+/*valid type values*/
+#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE                         2:2
+#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1     (0x00000000U)
+#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256   (0x00000001U)
+
+
+
+/*
+ * NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE
+ *
+ * This command is used to enter or exit the so called "drain" state.
+ * When this state is enabled, the existing clients continue executing
+ * as usual, however no new client connections are allowed.
+ * This is done in order to "drain" the system of the running clients
+ * in preparation to selectively powering down the GPU.
+ * No GPU can enter a bleed state if that GPU is in an SLI group.
+ * In that case, NV_ERR_IN_USE is returned.
+ * Requires administrator privileges.
+ *
+ * It is expected, that the "drain" state will be eventually deprecated
+ * and replaced with another mechanism to quiesce a GPU (Bug 1718113).
+ *
+ *  gpuId (INPUT)
+ *    This parameter should specify a valid GPU ID value.  If there
+ *    is no GPU present with the specified ID, a status of
+ *    NV_ERR_INVALID_ARGUMENT is returned.
+ *  newState (INPUT)
+ *    This input parameter is used to enter or exit the "drain"
+ *    software state of the GPU specified by the gpuId parameter.
+ *    Possible values are:
+ *      NV0000_CTRL_GPU_DRAIN_STATE_ENABLED
+ *      NV0000_CTRL_GPU_DRAIN_STATE_DISABLED
+ *  flags (INPUT)
+ *    NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE
+ *      if set, upon reaching quiescence, a request will be made to
+ *      the OS to "forget" the PCI device associated with the
+ *      GPU specified by the gpuId parameter, in case such a request
+ *      is supported by the OS. Otherwise, NV_ERR_NOT_SUPPORTED
+ *      will be returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_IN_USE
+ */
+
+#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE         (0x278U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
+
+/* Possible values of newState */
+#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED           (0x00000000U)
+#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED            (0x00000001U)
+
+/* Defined bits for the "flags" argument */
+#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001U)
+#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE  (0x00000002U)
+
+#define NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x78U)
+
+typedef struct NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS {
+    NvU32 gpuId;
+    NvU32 newState;
+    NvU32 flags;
+} NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE
+ *
+ *  gpuId (INPUT)
+ *    This parameter should specify a valid GPU ID value.  If there
+ *    is no GPU present with the specified ID, a status of
+ *    NVOS_STATUS_ERROR_INVALID_ARGUMENT is returned.
+ *  drainState (OUTPUT)
+ *    This parameter returns a value indicating if the "drain"
+ *    state is currently enabled or not for the specified GPU. See the
+ *    description of NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE.
+ *    Possible values are:
+ *      NV0000_CTRL_GPU_DRAIN_STATE_ENABLED
+ *      NV0000_CTRL_GPU_DRAIN_STATE_DISABLED
+ *  flags (OUTPUT)
+ *    NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE
+ *      if set, upon reaching quiesence, the GPU device will be
+ *      removed automatically from the kernel space, similar
+ *      to what writing "1" to the sysfs "remove" node does.
+ *    NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE
+ *      after removing the GPU, also disable the parent bridge's
+ *      PCIe link. This flag can only be set in conjunction with
+ *      NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE, and then
+ *      only when the GPU is already idle (not attached).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x79U)
+
+typedef struct NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS {
+    NvU32 gpuId;
+    NvU32 drainState;
+    NvU32 flags;
+} NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPU_DISCOVER
+ *
+ * This request asks the OS to scan the PCI tree or a sub-tree for GPUs,
+ * that are not yet known to the OS, and to make them available for use.
+ * If all of domain:bus:slot.function are zeros, the entire tree is scanned,
+ * otherwise the parameters identify the bridge device, that roots the
+ * subtree to be scanned.
+ * Requires administrator privileges.
+ *
+ *  domain (INPUT)
+ *    PCI domain of the bridge
+ *  bus (INPUT)
+ *    PCI bus of the bridge
+ *  slot (INPUT)
+ *    PCI slot of the bridge
+ *  function (INPUT)
+ *    PCI function of the bridge
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_OPERATING_SYSTEM
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27aU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */
+
+typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS {
+    NvU32 domain;
+    NvU8  bus;
+    NvU8  slot;
+    NvU8  function;
+} NV0000_CTRL_GPU_DISCOVER_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE
+ *
+ * This command is used to get the content of the MemOp (CUDA Memory Operation)
+ * enablement mask, which can be overridden by using the MemOpOverride RegKey.
+ *
+ * The enableMask member must be treated as a bitmask, where each bit controls
+ * the enablement of a feature.
+ *
+ * So far, the only feature which is defined controls to whole MemOp APIs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *
+ */
+#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID (0x7BU)
+
+typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
+    NvU32 enableMask;
+} NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS;
+
+#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE   (0x00000001U)
+
+
+
+/*
+ * NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT
+ *
+ * This privileged command is used to disable initialization for the NVLinks
+ * provided in the mask.
+ *
+ * The mask must be applied before the GPU is attached. DISABLE_NVLINK_INIT
+ * is an NOP for non-NVLink GPUs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_IN_USE
+ *
+ */
+#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID (0x81U)
+
+typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS {
+    NvU32  gpuId;
+    NvU32  mask;
+    NvBool bSkipHwNvlinkDisable;
+} NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS;
+
+
+#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA     0x00000175U
+#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN  6U
+#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5U
+
+/*
+ * NV0000_CTRL_CMD_GPU_LEGACY_CONFIG
+ *
+ * Path to use legacy RM GetConfig/Set API. This API is being phased out.
+ */
+#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG                (0x282U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID (0x82U)
+
+typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
+    NvHandle hContext;    /* [in]  - Handle of object to perform operation on (Device, Subdevice, etc) */
+    NvU32    opType;      /* [in]  - Type of API */
+    NvV32    index;       /* [in]  - command type */
+    NvU32    dataType;    /* [out] - data union type */
+
+    union {
+        struct {
+            NvU32 newValue;
+            NvU32 oldValue;
+        } configSet;
+        struct {
+            NvU8  paramData[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA];
+            NvU32 paramSize;
+        } configEx;
+        struct {
+            NvU32 propertyId;
+            NvU32 propertyIn[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN];
+            NvU32 propertyOut[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT];
+        } reservedProperty;
+    } data;
+} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS;
+
+#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET      (0x00000001U)
+#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX   (0x00000002U)
+#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX   (0x00000003U)
+#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004U)
+
+/*
+ * NV0000_CTRL_CMD_IDLE_CHANNELS
+ */
+#define NV0000_CTRL_CMD_IDLE_CHANNELS                  (0x283U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x83U)
+
+typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS {
+    NvHandle hDevice;
+    NvHandle hChannel;
+    NvV32    numChannels;
+    /* C form: NvP64 phClients NV_ALIGN_BYTES(8); */
+    NV_DECLARE_ALIGNED(NvP64 phClients, 8);
+    /* C form: NvP64 phDevices NV_ALIGN_BYTES(8); */
+    NV_DECLARE_ALIGNED(NvP64 phDevices, 8);
+    /* C form: NvP64 phChannels NV_ALIGN_BYTES(8); */
+    NV_DECLARE_ALIGNED(NvP64 phChannels, 8);
+    NvV32    flags;
+    NvV32    timeout;
+} NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS;
+
+#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP     (0x00000001U)
+#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG (0x00000002U)
+
+/*
+ * NV0000_CTRL_CMD_PUSH_GSP_UCODE
+ *
+ * This command is used to push the GSP ucode into RM.
+ * This function is used only on VMware
+ *
+ * Possible status values returned are:
+ *   NV_OK                   The sent data is stored successfully
+ *   NV_ERR_INVALID_ARGUMENT if the arguments are not proper
+ *   NV_ERR_NO_MEMORY        if memory allocation failed
+ *   NV_ERR_NOT_SUPPORTED    if function is invoked on non-GSP setup or any
+ *                              setup other than VMware host
+ *
+ */
+#define NV0000_CTRL_CMD_PUSH_GSP_UCODE     (0x285) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID (0x85U)
+
+typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS {
+    NvU8 image;
+    NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
+    NV_DECLARE_ALIGNED(NvP64 pData, 8);
+} NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS;
+/* _ctrl0000gpu_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h
new file mode 100644
index 0000000..6f8ff13
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h
@@ -0,0 +1,255 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+
+/*
+ * NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE
+ *
+ * This command is used to enable or disable the per process GPU accounting.
+ * This is part of GPU's software state and will persist if persistent
+ * software state is enabled. Refer to the description of
+ * NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE for more information.
+ *  
+ *   gpuId
+ *     This parameter should specify a valid GPU ID value. Refer to the
+ *     description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more
+ *     information. If there is no GPU present with the specified ID,
+ *     a status of NV_ERR_INVALID_ARGUMENT is returned.
+ *   pid
+ *     This input parameter specifies the process id of the process for which
+ *     the accounting state needs to be set. 
+ *     In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This
+ *     parameter is set only when this RM control is called from VGPU plugin, 
+ *     otherwise it is zero meaning set/reset the accounting state for the
+ *     specified GPU.
+ *  newState
+ *    This input parameter is used to enable or disable the GPU accounting.
+ *    Possible values are:
+ *      NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED
+ *      NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE (0xb01) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID" */
+
+/* Possible values of persistentSwState */
+#define NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED     (0x00000000)
+#define NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED    (0x00000001)
+
+#define NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS {
+    NvU32 gpuId;
+    NvU32 pid;
+    NvU32 newState;
+} NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE
+ *
+ * This command is used to get the current state of GPU accounting.
+ *
+ *   gpuId
+ *     This parameter should specify a valid GPU ID value. Refer to the
+ *     description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more
+ *     information. If there is no GPU present with the specified ID,
+ *     a status of NV_ERR_INVALID_ARGUMENT is returned.
+ *   pid
+ *     This input parameter specifies the process id of the process of which the
+ *     accounting state needs to be queried. 
+ *     In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This
+ *     parameter is set only when this RM control is called from VGPU plugin, 
+ *     otherwise it is zero meaning the accounting state needs to be queried for
+ *     the specified GPU.
+ *   state
+ *     This parameter returns a value indicating if per process GPU accounting
+ *     is currently enabled or not for the specified GPU. See the 
+ *     description of NV0000_CTRL_CMD_GPU_SET_ACCOUNTING_STATE.
+ *     Possible values are:
+ *       NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED
+ *       NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE (0xb02) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS {
+    NvU32 gpuId;
+    NvU32 pid;
+    NvU32 state;
+} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS;
+
+/*
+ * NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS
+ *
+ * This command returns GPU accounting data for the process.
+ *
+ *   gpuId
+ *     This parameter should specify a valid GPU ID value. Refer to the
+ *     description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more
+ *     information. If there is no GPU present with the specified ID,
+ *     a status of NV_ERR_INVALID_ARGUMENT is returned.
+ *   pid
+ *     This parameter specifies the PID of the process for which information is
+ *     to be queried.
+ *     In case of VGX host, this parameter specifies VGPU plugin(VM) pid inside 
+ *     which the subPid is running. This parameter is set to VGPU plugin pid 
+ *     when this RM control is called from VGPU plugin. 
+ *   subPid
+ *     In case of VGX host, this parameter specifies the PID of the process for
+ *     which information is to be queried. In other cases, it is zero.
+ *   gpuUtil
+ *     This parameter returns the average GR utilization during the process's
+ *     lifetime.
+ *   fbUtil
+ *     This parameter returns the average FB bandwidth utilization during the
+ *     process's lifetime.
+ *   maxFbUsage
+ *     This parameter returns the maximum FB allocated (in bytes) by the process.
+ *   startTime
+ *     This parameter returns the time stamp value in micro seconds at the time
+ *     process started utilizing GPU.
+ *   stopTime
+ *     This parameter returns the time stamp value in micro seconds at the time
+ *     process stopped utilizing GPU.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO (0xb03) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS {
+    NvU32 gpuId;
+    NvU32 pid;
+    NvU32 subPid;
+    NvU32 gpuUtil;
+    NvU32 fbUtil;
+    NV_DECLARE_ALIGNED(NvU64 maxFbUsage, 8);
+    NV_DECLARE_ALIGNED(NvU64 startTime, 8);
+    NV_DECLARE_ALIGNED(NvU64 endTime, 8);
+} NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS
+ *
+ * This command is used to get the PIDS of processes with accounting
+ * information in the driver.
+ *
+ *   gpuId
+ *     This parameter should specify a valid GPU ID value. Refer to the
+ *     description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more
+ *     information. If there is no GPU present with the specified ID,
+ *     a status of NV_ERR_INVALID_ARGUMENT is returned.
+ *   pid
+ *     This input parameter specifies the process id of the process of which the 
+ *     information needs to be queried. 
+ *     In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This 
+ *     parameter is set only when this RM control is called from VGPU plugin, 
+ *     otherwise it is zero meaning get the pid list of the all the processes 
+ *     running on the specified GPU.
+ *    pidTbl
+ *      This parameter returns the table of all PIDs for which driver has
+ *      accounting info.
+ *    pidCount
+ *      This parameter returns the number of entries in the PID table.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS (0xb04) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID" */
+
+/* max size of pidTable */
+#define NV0000_GPUACCT_PID_MAX_COUNT                4000
+
+#define NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS {
+    NvU32 gpuId;
+    NvU32 pid;
+    NvU32 pidTbl[NV0000_GPUACCT_PID_MAX_COUNT];
+    NvU32 pidCount;
+} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA
+ *
+ * This command is used to clear previously collected GPU accounting data. This
+ * will have no affect on data for the running processes, accounting data for
+ * these processes will not be cleared and will still be logged for these
+ * processes. In order to clear ALL accounting data, accounting needs to be
+ * disabled using NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE before executing
+ * this command.
+ *  
+ *   gpuId
+ *     This parameter should specify a valid GPU ID value. Refer to the
+ *     description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more
+ *     information. If there is no GPU present with the specified ID,
+ *     a status of NV_ERR_INVALID_ARGUMENT is returned.
+ *   pid
+ *     This input parameter specifies the process id of the process for which 
+ *     the accounting data needs to be cleared.
+ *     In case of VGX host, this parameter specifies VGPU plugin(VM) pid for
+ *     which the accounting data needs to be cleared. This parameter is set only 
+ *     when this RM control is called from VGPU plugin, otherwise it is zero 
+ *     meaning clear the accounting data of processes running on baremetal 
+ *     system.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+
+#define NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA (0xb05) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS {
+    NvU32 gpuId;
+    NvU32 pid;
+} NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS;
+
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h
new file mode 100644
index 0000000..2df6c42
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h
@@ -0,0 +1,101 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000gsync.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+
+#include "ctrl/ctrlxxxx.h"
+#include "class/cl30f1.h"
+/* NV01_ROOT (client) system controller control commands and parameters */
+
+/*
+ * NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS
+ *
+ * This command returns a table of attached gsyncId values.
+ * The table is NV0000_CTRL_GSYNC_MAX_ATTACHED_GSYNCS entries in size.
+ *
+ *   gsyncIds[]
+ *     This parameter returns the table of attached gsync IDs.
+ *     The gsync ID is an opaque platform-dependent value that
+ *     can be used with the NV0000_CTRL_CMD_GSYNC_GET_ID_INFO command to
+ *     retrieve additional information about the gsync device.
+ *     The valid entries in gsyncIds[] are contiguous, with a value
+ *     of NV0000_CTRL_GSYNC_INVALID_ID indicating the invalid entries.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS (0x301) /* finn: Evaluated from "(FINN_NV01_ROOT_GSYNC_INTERFACE_ID << 8) | NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS {
+    NvU32 gsyncIds[NV30F1_MAX_GSYNCS];
+} NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS;
+
+/* this value marks entries in gsyncIds[] as invalid */
+#define NV0000_CTRL_GSYNC_INVALID_ID      (0xffffffff)
+
+/*
+ * NV0000_CTRL_CMD_GSYNC_GET_ID_INFO
+ *
+ * This command returns gsync instance information for the
+ * specified gsync device.
+ *
+ *   gsyncId
+ *     This parameter should specify a valid gsync ID value.
+ *     If there is no gsync present with the specified ID, a
+ *     status of NV_ERR_INVALID_ARGUMENT is returned.
+ *   gsyncFlags
+ *     This parameter returns the current state of the gsync device. 
+ *   gsyncInstance
+ *     This parameter returns the instance number associated with the
+ *     specified gsync.  This value can be used to instantiate
+ *     a reference to the gsync using one of the NV30_GSYNC
+ *     classes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0000_CTRL_CMD_GSYNC_GET_ID_INFO (0x302) /* finn: Evaluated from "(FINN_NV01_ROOT_GSYNC_INTERFACE_ID << 8) | NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS {
+    NvU32 gsyncId;
+    NvU32 gsyncFlags;
+    NvU32 gsyncInstance;
+} NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS;
+
+/* _ctrl0000gsync_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h
new file mode 100644
index 0000000..41a4954
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h
@@ -0,0 +1,636 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000nvd.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+
+#include "ctrl/ctrlxxxx.h"
+/* NV01_ROOT (client) nvd control commands and parameters */
+
+/*
+ * NV0080_CTRL_NVD_DUMP_COMPONENT
+ *
+ * The following dump components are used to describe legal ranges in
+ * commands below:
+ *
+ *   NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_SYS
+ *     This is the system dump component.
+ *   NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_NVLOG
+ *     This is the nvlog dump component.
+ *   NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_RESERVED
+ *     This component is reserved.
+ *
+ * See nvdump.h for more information on dump component values.
+ */
+#define NV0000_CTRL_NVD_DUMP_COMPONENT_SYS      (0x400)
+#define NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG    (0x800)
+#define NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED (0xB00)
+
+/*
+ * NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE
+ *
+ * This command gets the expected dump size of a particular system
+ * dump component.  Note that events that occur between this command
+ * and a later NV0000_CTRL_CMD_NVD_GET_DUMP command could alter the size of
+ * the buffer required.
+ *
+ *   component
+ *     This parameter specifies the system dump component for which the
+ *     dump size is desired.  Legal values for this parameter must
+ *     be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_SYS and
+ *     less than NV0000_CTRL_NVD_GET_DUMP_COMPONENT_NVLOG.
+ *   size
+ *     This parameter returns the expected size in bytes.  The maximum
+ *     value of this call is NV0000_CTRL_NVD_MAX_DUMP_SIZE.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT if components are invalid.
+ */
+
+#define NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE       (0x601) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS {
+    NvU32 component;
+    NvU32 size;
+} NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS;
+
+/* Max size that a GET_DUMP_SIZE_PARAMS call can return */
+#define NV0000_CTRL_NVD_MAX_DUMP_SIZE (1000000)
+
+/*
+ * NV0000_CTRL_CMD_NVD_GET_DUMP
+ *
+ * This command gets a dump of a particular system dump component. If triggers
+ * is non-zero, the command waits for the trigger to occur before it returns.
+ *
+ *   pBuffer
+ *     This parameter points to the buffer for the data.
+ *   component
+ *     This parameter specifies the system dump component for which the
+ *     dump is to be retrieved.  Legal values for this parameter must
+ *     be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_SYS and
+ *     less than NV0000_CTRL_NVD_GET_DUMP_COMPONENT_NVLOG.
+ *   size
+ *     On entry, this parameter specifies the maximum length for
+ *     the returned data. On exit, it specifies the number of bytes
+ *     returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_ERROR_INVALID_ARGUMENT if components are invalid.
+ *   NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid
+ *   NVOS_ERROR_INVALID_???? if the buffer was too small
+ */
+#define NV0000_CTRL_CMD_NVD_GET_DUMP  (0x602) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0000_CTRL_NVD_GET_DUMP_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pBuffer, 8);
+    NvU32 component;
+    NvU32 size;
+} NV0000_CTRL_NVD_GET_DUMP_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_NVD_GET_TIMESTAMP
+ *
+ * This command returns the current value of the timestamp used
+ * by the RM in NvDebug dumps. It is provided to keep the RM and NvDebug
+ * clients on the same time base.
+ *
+ *   cpuClkId
+ *     See also NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO
+ *     This parameter specifies the source of the CPU clock. Legal values for
+ *     this parameter include:
+ *       NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT and NV0000_NVD_CPU_TIME_CLK_ID_OSTIME
+ *         This clock id will provide real time in microseconds since 00:00:00 UTC on January 1, 1970.
+ *         It is calculated as follows:
+ *          (seconds * 1000000) + uSeconds
+ *       NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API
+ *         This clock id will provide time stamp that is constant-rate, high
+ *         precision using platform API that is also available in the user mode.
+ *       NV0000_NVD_CPU_TIME_CLK_ID_TSC
+ *         This clock id will provide time stamp using CPU's time stamp counter.
+ *
+ *   timestamp
+ *     Retrieved timestamp
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT      (0x00000000)
+#define NV0000_NVD_CPU_TIME_CLK_ID_OSTIME       (0x00000001)
+#define NV0000_NVD_CPU_TIME_CLK_ID_TSC          (0x00000002)
+#define NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API (0x00000003)
+
+#define NV0000_CTRL_CMD_NVD_GET_TIMESTAMP       (0x603) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
+    NvU8 cpuClkId;
+} NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO
+ *
+ * This command gets the current state of the NvLog buffer system.
+ *
+ *   component (in)
+ *     This parameter specifies the system dump component for which the
+ *     NvLog info is desired.  Legal values for this parameter must
+ *     be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG and
+ *     less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED.
+ *   version (out)
+ *     This parameter returns the version of the Nvlog subsystem.
+ *   runtimeSizes (out)
+ *     This parameter returns the array of sizes for all supported printf
+ *     specifiers.  This information is necessary to know how many bytes
+ *     to decode when given a certain specifier (such as %d).
+ *     The following describes the contents of each array entry:
+ *       NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED
+ *         This array entry has special meaning and is unused in the
+ *         runtimeSizes array.
+ *       NV0000_CTRL_NVD_RUNTIME_SIZE_INT
+ *         This array entry returns the size of integer types for use in
+ *         interpreting the %d, %u, %x, %X, %i, %o specifiers.
+ *       NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG
+ *         This array entry returns the size of long long integer types for
+ *         using in interpreting the %lld, %llu, %llx, %llX, %lli, %llo
+ *         specifiers.
+ *       NV0000_CTRL_NVD_RUNTIME_SIZE_STRING
+ *         This array entry returns zero as strings are not allowed.
+ *       NV0000_CTRL_NVD_RUNTIME_SIZE_PTR
+ *         This array entry returns the size of the pointer type for use
+ *         in interpreting the %p specifier.
+ *       NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR
+ *         This array entry returns the size of the char type for use in
+ *         intpreting the %c specifier.
+ *       NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT
+ *         This array entry returns the size of the float types for use in
+ *         in interpreting the %f, %g, %e, %F, %G, %E specifiers.
+ *     All remaining entries are reserved and return 0.
+ *   printFlags (out)
+ *     This parameter returns the flags of the NvLog system.
+ *       NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_BUFFER_FLAGS
+ *         See NV0000_CTRL_CMD_NVD_GET_NVLOG_BUF_INFO for more details.
+ *       NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_BUFFER_SIZE
+ *         This field returns the buffer size in KBytes.  A value of zero
+ *         is returned when logging is disabled.
+ *       NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP
+ *         This field returns the format of the timestamp.  Legal values
+ *         for this parameter include:
+ *           NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_NONE
+ *             This value indicates no timestamp.
+ *           NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_32BIT
+ *             This value indicates a 32-bit timestamp.
+ *           NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_64BIT
+ *             This value indicates a 64-bit timestamp.
+ *           NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_32BIT_DIFF
+ *             This value indicates a 32-bit differential timestamp.
+ *       NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_RESERVED
+ *          This field is reserved.
+ *       NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_RUNTIME_LEVEL
+ *          This field returns the lowest debug level for which logging
+ *          is enabled by default.
+ *       NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT
+ *          This field indicates if logging for the specified component has
+ *          been initialized. Legal values for this parameter include:
+ *            NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT_NO
+ *              This value indicates NvLog is uninitialized.
+ *            NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT_YES
+ *              This value indicates NvLog has been initialized.
+ *   signature (out)
+ *     This parameter is the signature of the database
+ *     required to decode these logs, autogenerated at buildtime.
+ *   bufferTags (out)
+ *     This parameter identifies the buffer tag used during allocation
+ *     or a value of '0' if buffer is unallocated for each possible
+ *     buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT if components are invalid.
+ */
+#define NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO (0x604) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum size of the runtimeSizes array */
+#define NV0000_CTRL_NVD_MAX_RUNTIME_SIZES  (16)
+
+/* size of signature parameter */
+#define NV0000_CTRL_NVD_SIGNATURE_SIZE     (4)
+
+/* Maximum number of buffers */
+#define NV0000_CTRL_NVD_MAX_BUFFERS        (256)
+
+#define NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS {
+    NvU32 component;
+    NvU32 version;
+    NvU8  runtimeSizes[NV0000_CTRL_NVD_MAX_RUNTIME_SIZES];
+    NvU32 printFlags;
+    NvU32 signature[NV0000_CTRL_NVD_SIGNATURE_SIZE];
+    NvU32 bufferTags[NV0000_CTRL_NVD_MAX_BUFFERS];
+} NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS;
+
+/* runtimeSize array indices */
+#define NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED                       (0)
+#define NV0000_CTRL_NVD_RUNTIME_SIZE_INT                          (1)
+#define NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG                    (2)
+#define NV0000_CTRL_NVD_RUNTIME_SIZE_STRING                       (3)
+#define NV0000_CTRL_NVD_RUNTIME_SIZE_PTR                          (4)
+#define NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR                         (5)
+#define NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT                        (6)
+
+/* printFlags fields and values */
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_INFO          7:0
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE          23:8
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE (0x00000000)
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT (0x00000004)
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_RUNTIME_LEVEL        28:25
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP            30:29
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE      (0x00000000)
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32        (0x00000001)
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64        (0x00000002)
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF   (0x00000003)
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED               31:31
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO           (0x00000000)
+#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES          (0x00000001)
+
+/*
+ * NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO
+ *
+ * This command gets the current state of a specific buffer in the NvLog
+ * buffer system.
+ *
+ *   component (in)
+ *     This parameter specifies the system dump component for which the
+ *     NvLog info is desired.  Legal values for this parameter must
+ *     be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG and
+ *     less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED.
+ *   buffer (in/out)
+ *     This parameter specifies the buffer number from which to retrieve the
+ *     buffer information. Valid values are 0 to (NV0000_CTRL_NVD_MAX_BUFFERS - 1).
+ *     If the buffer is specified using the 'tag' parameter, the buffer
+ *     number is returned through this one.
+ *   tag (in/out)
+ *     If this parameter is non-zero, it will be used to specify the buffer,
+ *     instead of 'buffer' parameter. It returns the tag of the specified buffer
+ *   size (out)
+ *     This parameter returns the size of the specified buffer.
+ *   flags (in/out)
+ *     On input, this parameter sets the following behavior:
+ *       NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE
+ *         This flag controls if the nvlog system should pause output
+ *         to this buffer.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES
+ *             The buffer should be paused until another command 
+ *             unpauses this buffer.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO
+ *             The buffer should not be paused.
+ *     On output, this parameter returns the flags of a specified buffer:
+ *       NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED
+ *         This flag indicates if logging to the specified buffer is
+ *         disabled or not.
+ *       NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE
+ *         This flag indicates the buffer logging type:
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING
+ *             This type value indicates logging to the buffer wraps.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP
+ *             This type value indicates logging to the buffer does not wrap.
+ *       NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE
+ *         This flag indicates if the buffer size is expandable.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO
+ *             The buffer is not expandable.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES
+ *             The buffer is expandable.
+ *       NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGED
+ *         This flag indicates if the buffer occupies non-paged or pageable
+ *         memory.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGED_NO
+ *             The buffer is in pageable memory.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGES_YES
+ *             The buffer is in non-paged memory.
+ *       NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING
+ *         This flag indicates the locking mode for the specified buffer.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE
+ *             This locking value indicates that no locking is performed.  This
+ *             locking mode is typically used for inherently single-threaded
+ *             buffers.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE
+ *             This locking value indicates that the buffer is locked only
+ *             during state changes and that memory copying is unlocked.  This
+ *             mode should not be used tiny buffers that overflow every write
+ *             or two.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL
+ *             This locking value indicates the buffer is locked for the full
+ *             duration of the write.
+ *       NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA
+ *         This flag indicates if the buffer is stored in OCA dumps.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO
+ *             The buffer is not included in OCA dumps.
+ *           NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES
+ *             The buffer is included in OCA dumps.
+ *   pos (out)
+ *      This parameter is the current position of the tracker/cursor in the
+ *      buffer.
+ *   overflow (out)
+ *     This parameter is the number of times the buffer has overflowed.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT if components are invalid.
+ */
+
+#define NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO                 (0x605) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS {
+    NvU32 component;
+    NvU32 buffer;
+    NvU32 tag;
+    NvU32 size;
+    NvU32 flags;
+    NvU32 pos;
+    NvU32 overflow;
+} NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS;
+
+/* flags fields and values */
+/* input */
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE              0:0
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO       (0x00000000)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES      (0x00000001)
+
+/* output */
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED           0:0
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO    (0x00000000)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES   (0x00000001)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE               1:1
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING      (0x00000000)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP    (0x00000001)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE         2:2
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO  (0x00000000)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES (0x00000001)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED           3:3
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO    (0x00000000)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES   (0x00000001)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING            5:4
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE   (0x00000000)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE  (0x00000001)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL   (0x00000002)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA                6:6
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO         (0x00000000)
+#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES        (0x00000001)
+
+/*
+ * NV0000_CTRL_CMD_NVD_GET_NVLOG
+ *
+ * This command retrieves the specified dump block from the specified
+ * NvLog buffer.  To retrieve the entire buffer, the caller should start
+ * with blockNum set to 0 and continue issuing calls with an incremented
+ * blockNum until the returned size value is less than
+ * NV0000_CTRL_NVD_NVLOG_MAX_BLOCK_SIZE.
+ *
+ *   component (in)
+ *     This parameter specifies the system dump component for which the NvLog
+ *     dump operation is to be directed.  Legal values for this parameter
+ *     must be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG
+ *     and less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED.
+ *   buffer (in)
+ *     This parameter specifies the NvLog buffer to dump.
+ *   blockNum (in)
+ *     This parameter specifies the block number for which data is to be
+ *     dumped.
+ *   size (in/out)
+ *     On entry, this parameter specifies the maximum length in bytes for
+ *     the returned data (should be set to NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE).
+ *     On exit, it specifies the number of bytes returned.
+ *   data (out)
+ *     This parameter returns the data for the specified block.  The size
+ *     patameter values indicates the number of valid bytes returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_ERROR_INVALID_ARGUMENT if components are invalid.
+ */
+#define NV0000_CTRL_CMD_NVD_GET_NVLOG                          (0x606) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE                       (4000)
+
+#define NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV0000_CTRL_NVD_GET_NVLOG_PARAMS {
+    NvU32 component;
+    NvU32 buffer;
+    NvU32 blockNum;
+    NvU32 size;
+    NvU8  data[NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE];
+} NV0000_CTRL_NVD_GET_NVLOG_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_NVD_GET_RCERR_RPT
+ *
+ * This command returns block of registers that were recorded at the time
+ * of an RC error for the current process.
+ *
+ *   reqIdx:
+ *      [IN] the index of the report being requested.
+ *      index rolls over to 0.
+ *      if the requested index is not in the circular buffer, then no data is
+ *      transferred & either NV_ERR_INVALID_INDEX (indicating the specified
+ *      index is not in the table) is returned.
+ *
+ *   rptIdx:
+ *      [OUT] the index of the report being returned.
+ *      if the requested index is not in the circular buffer, then the value is
+ *      undefined, no data istransferred & NV_ERR_INVALID_INDEX is returned.
+ *      if the the specified index is present, but does not meet the requested
+ *      criteria (refer to the owner & processId fields). the rptIdx will be
+ *      set to a value that does not match the reqIdx, and no data will be
+ *      transferred. NV_ERR_INSUFFICIENT_PERMISSIONS is still returned.
+ *
+ *   gpuTag:
+ *      [OUT] id of the GPU whose data was collected.
+ *
+ *   rptTimeInNs:
+ *      [OUT] the timestamp for when the report was created.
+ *
+ *   startIdx:
+ *      [OUT] the index of the oldest start record for the first report that
+ *      matches the specified criteria (refer to the owner & processId
+ *      fields). If no records match the specified criteria, this value is
+ *      undefined, the failure code NV_ERR_MISSING_TABLE_ENTRY will
+ *      be returned, and no data will be transferred.
+ *
+ *   endIdx:
+ *      [OUT] the index of the newest end record for the most recent report that
+ *      matches the specified criteria (refer to the owner & processId
+ *      fields). If no records match the specified criteria, this value is
+ *      undefined, the failure code NV_ERR_MISSING_TABLE_ENTRY will
+ *      be returned, and no data will be transferred.
+ *
+ *   rptType:
+ *      [OUT] indicator of what data is in the report.
+ *
+ *  flags
+ *      [OUT] a set odf flags indicating attributes of the record
+ *          NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST --    indicates this is the first record of a report.
+ *          NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST --     indicates this is the last record of the report.
+ *          NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID --  indicates this is the response contains a valid
+*               index range.
+ *              Note, this may be set when an error is returned indicating a valid range was found, but event of
+ *              the requested index was not.
+ *          NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID --   indicates this is the response contains valid data.
+ *
+ *   rptCount:
+ *      [OUT] number of entries returned in report.
+ *
+ *   owner:
+ *      [IN] Entries are only returned if they have the same owner as the specified owner or the specified 
+ *      owner Id is NV0000_CTRL_CMD_NVD_RPT_ANY_OWNER_ID.
+ *      if the requested index is not owned by the specified owner, the rptIdx
+ *      will be set to a value that does not match the reqIdx, and no data will
+ *      be transferred.  NV_ERR_INSUFFICIENT_PERMISSIONS is returned.
+ *
+ *   processId:
+ *      [IN] Deprecated
+ *   report:
+ *      [OUT] array of rptCount enum/value pair entries containing the data from the report.
+ *      entries beyond rptCount are undefined.
+ *
+ *
+ * Possible status values returned are:
+ *  NV_OK -- we found & transferred the requested record.
+ *  NV_ERR_MISSING_TABLE_ENTRY -- we don't find any records that meet the criteria.
+ *  NV_ERR_INVALID_INDEX -- the requested index was not found in the buffer.
+ *  NV_ERR_INSUFFICIENT_PERMISSIONS -- the requested record was found, but it did not meet the criteria.
+ *  NV_ERR_BUSY_RETRY -- We could not access the circular buffer.
+ *
+ */
+
+#define NV0000_CTRL_CMD_NVD_GET_RCERR_RPT                                            (0x607) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES                                    200
+
+// report types
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST                                      0
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS                                  1
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS                                 2
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS                          3
+
+// pseudo register enums                                                                                         attribute content
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY                                      0x00000000
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED                                 0x00000001                  // number of missed entries.
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG                              0x0000000f
+
+
+
+// Flags Definitions
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST                                0x00000001                  // indicates this is the first record of a report.
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST                                 0x00000002                  // indicates this is the last record of the report.
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID                              0x00000004                  // indicates this is the response contains a valid range
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID                               0x00000008                  // indicates this is the response contains valid data
+
+
+// Attribute Definitions
+#define TPC_REG_ATTR(gpcId, tpcId)                                                  ((gpcId << 8) | (tpcId))
+#define ROP_REG_ATTR(gpcId, ropId)                                                  ((gpcId << 8) | (ropId))
+#define SM_REG_ATTR(gpcId, tpcId, smId)                                             ((((gpcId) << 16) | ((tpcId) << 8)) | (smId))
+
+// Process Id Pseudo values
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID                                 0x00000000                  // get report for any process ID
+
+#define NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID                                   0xFFFFFFFF                  // get report for any owner ID
+
+
+typedef struct NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY {
+    NvU32 tag;
+    NvU32 value;
+    NvU32 attribute;
+} NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY;
+
+#define NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS {
+    NvU16                                   reqIdx;
+    NvU16                                   rptIdx;
+    NvU32                                   GPUTag;
+    NvU32                                   rptTime;     // time in seconds since 1/1/1970
+    NvU16                                   startIdx;
+    NvU16                                   endIdx;
+    NvU16                                   rptType;
+    NvU32                                   flags;
+    NvU16                                   rptCount;
+    NvU32                                   owner;       // indicating whose reports to get
+    NvU32                                   processId;       // deprecated field
+
+    NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY report[NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES];
+} NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS
+ *
+ * This command returns the time stamp information that are collected from
+ * the execution of various DPCs/ISRs. This time stamp information is for
+ * debugging purposes only and would help with analyzing regressions and
+ * latencies for DPC/ISR execution times.
+ *
+ *   tsBufferSize
+ *     This field specifies the size of the buffer that the caller allocates.
+ *   tsBuffer
+ *     THis field specifies a pointer in the callers address space to the
+ *     buffer into which the timestamp info on DPC/ISR is to be returned.
+ *     This buffer must at least be as big as tsBufferSize.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS (0x608) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS {
+    NvU32 tsBufferSize;
+    NV_DECLARE_ALIGNED(NvP64 pTSBuffer, 8);
+} NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS;
+
+/* _ctrl0000nvd_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h
new file mode 100644
index 0000000..9a48202
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h
@@ -0,0 +1,98 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000proc.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+#include "nvlimits.h"
+
+/*
+ * NV0000_CTRL_CMD_SET_SUB_PROCESS_ID
+ *
+ * Save the sub process ID and sub process name in client database
+ *  subProcID
+ *     Sub process ID
+ *  subProcessName
+ *     Sub process name
+ *
+ *     In vGPU environment, sub process means the guest user/kernel process running
+ *     within a single VM. It also refers to any sub process (or sub-sub process)
+ *     within a parent process.
+ *
+ *     Please refer to the wiki for more details about sub process concept: Resource_Server
+ *
+ * Possible return values are:
+ *   NV_OK
+ */
+#define NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS {
+    NvU32 subProcessID;
+    char  subProcessName[NV_PROC_NAME_MAX_LENGTH];
+} NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION
+ *
+ * Disable sub process USERD isolation.
+ *  bIsSubProcIsolated
+ *     NV_TRUE to disable sub process USERD isolation
+ *
+ *     USERD allocated by different domains should not be put into the same physical page.
+ *     This provides the basic security isolation because a physical page is the unit of
+ *     granularity at which OS can provide isolation between processes.
+ *
+ *     GUEST_USER:     USERD allocated by guest user process
+ *     GUEST_KERNEL:   USERD allocated by guest kernel process
+ *     GUEST_INSECURE: USERD allocated by guest/kernel process,
+ *                     INSECURE means there is no isolation between guest user and guest kernel
+ *     HOST_USER:      USERD allocated by host user process
+ *     HOST_KERNEL:    USERD allocated by host kernel process
+ *
+ *     When sub process USERD isolation is disabled, we won't distinguish USERD allocated by guest
+ *     user and guest kernel. They all belong to the GUEST_INSECURE domain.
+ *
+ *     Please refer to wiki for more details: RM_USERD_Isolation
+ *
+ * Possible return values are:
+ *   NV_OK
+ */
+#define NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS {
+    NvBool bIsSubProcessDisabled;
+} NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS;
+
+#define NV0000_CTRL_CMD_SET_SUB_PROCESS_ID                  (0x901) /* finn: Evaluated from "(FINN_NV01_ROOT_PROC_INTERFACE_ID << 8) | NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION (0x902) /* finn: Evaluated from "(FINN_NV01_ROOT_PROC_INTERFACE_ID << 8) | NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID" */
+
+/* _ctrl0000proc_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h
new file mode 100644
index 0000000..b8e921e
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h
@@ -0,0 +1,112 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+
+#include "ctrl/ctrlxxxx.h"
+#include "nvtypes.h"
+#include "nvlimits.h"
+
+/* --------------------------- Macros ----------------------------------------*/
+// There are at least 2 GPUs in a sync group. Hence max is half of max devices.
+#define NV0000_SYNC_GPU_BOOST_MAX_GROUPS       (0x10) /* finn: Evaluated from "((NV_MAX_DEVICES) >> 1)" */
+#define NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID 0xFFFFFFFF
+
+/*-------------------------Command Prototypes---------------------------------*/
+
+/*!
+ * Query whether SYNC GPU BOOST MANAGER is enabled or disabled.
+ */
+#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO    (0xa01) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0000_SYNC_GPU_BOOST_INFO_PARAMS {
+    // [out] Specifies if Sync Gpu Boost Manager is enabled or not.
+    NvBool bEnabled;
+} NV0000_SYNC_GPU_BOOST_INFO_PARAMS;
+
+/*!
+ *  Creates a Synchronized GPU-Boost Group (SGBG)
+ */
+#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE (0xa02) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID" */
+
+/*! 
+ * Describes a Synchronized GPU-Boost Group configuration
+ */
+typedef struct NV0000_SYNC_GPU_BOOST_GROUP_CONFIG {
+    // [in] Number of elements in @ref gpuIds
+    NvU32  gpuCount;
+
+    // [in] IDs of GPUs to be put in the Sync Boost Group
+    NvU32  gpuIds[NV_MAX_DEVICES];
+
+    // [out] Unique ID of the SGBG, if created
+    NvU32  boostGroupId;
+
+    // [in] If this group represents  bridgeless SLI
+    NvBool bBridgeless;
+} NV0000_SYNC_GPU_BOOST_GROUP_CONFIG;
+
+#define NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS {
+    NV0000_SYNC_GPU_BOOST_GROUP_CONFIG boostConfig;
+} NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS;
+
+/*!
+ *  Destroys a previously created Synchronized GPU-Boost Group(SGBG)
+ */
+#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY (0xa03) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID" */
+
+#define NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS {
+    // [[in] Unique ID of the SGBG to be destroyed
+    NvU32 boostGroupId;
+} NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS;
+
+/*!
+ * Get configuration information for all Synchronized Boost Groups in the system.
+ */
+#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO (0xa04) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS {
+    // [out] Number of groups retrieved. @ref NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS::boostGroups
+    NvU32                              groupCount;
+
+    // [out] @ref NV0000_SYNC_GPU_BOOST_GROUP_CONFIG
+    NV0000_SYNC_GPU_BOOST_GROUP_CONFIG pBoostGroups[NV0000_SYNC_GPU_BOOST_MAX_GROUPS];
+} NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS;
+
+/* _ctrl0000syncgpuboost_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
new file mode 100644
index 0000000..74b65c7
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
@@ -0,0 +1,2915 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000system.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl0000/ctrl0000base.h"
+
+/* NV01_ROOT (client) system control commands and parameters */
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_FEATURES
+ *
+ * This command returns a mask of supported features for the SYSTEM category
+ * of the 0000 class.
+ *
+ *     Valid features include:
+ *         
+ *       NV0000_CTRL_GET_FEATURES_SLI
+ *         When this bit is set, SLI is supported.
+ *       NV0000_CTRL_GET_FEATURES_UEFI
+ *         When this bit is set, it is a UEFI system.
+ *       NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT
+ *         When this bit is set, EFI has initialized core channel 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS {
+    NvU32 featuresMask;
+} NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS;
+
+
+
+/* Valid feature values */
+#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI                                 0:0
+#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE         (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE          (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI                                1:1
+#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE        (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE         (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT                         2:2
+#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE  (0x00000001U)
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION
+ *
+ * This command returns the current driver information.
+ * The first time this is called the size of strings is
+ * set with the greater of NV_BUILD_BRANCH_VERSION and
+ * NV_DISPLAY_DRIVER_TITLE. The client then allocates memory
+ * of size sizeOfStrings for pVersionBuffer and pTitleBuffer
+ * and calls the command again to receive driver info.
+ *
+ *   sizeOfStrings
+ *       This field returns the size in bytes of the pVersionBuffer and
+ *       pTitleBuffer strings.
+ *   pDriverVersionBuffer
+ *       This field returns the version (NV_VERSION_STRING).
+ *   pVersionBuffer
+ *       This field returns the version (NV_BUILD_BRANCH_VERSION).
+ *   pTitleBuffer
+ *       This field returns the title (NV_DISPLAY_DRIVER_TITLE).
+ *   changelistNumber
+ *       This field returns the changelist value (NV_BUILD_CHANGELIST_NUM).
+ *   officialChangelistNumber
+ *       This field returns the last official changelist value
+ *       (NV_LAST_OFFICIAL_CHANGELIST_NUM).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION          (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS {
+    NvU32 sizeOfStrings;
+    NV_DECLARE_ALIGNED(NvP64 pDriverVersionBuffer, 8);
+    NV_DECLARE_ALIGNED(NvP64 pVersionBuffer, 8);
+    NV_DECLARE_ALIGNED(NvP64 pTitleBuffer, 8);
+    NvU32 changelistNumber;
+    NvU32 officialChangelistNumber;
+} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO
+ *
+ * This command returns system CPU information.
+ *
+ *   type
+ *     This field returns the processor type.
+ *     Legal processor types include:
+ *       Intel processors:
+ *         P55       : P55C - MMX
+ *         P6        : PPro
+ *         P2        : PentiumII
+ *         P2XC      : Xeon & Celeron
+ *         CELA      : Celeron-A
+ *         P3        : Pentium-III
+ *         P3_INTL2  : Pentium-III w/integrated L2 (fullspeed, on die, 256K)
+ *         P4        : Pentium 4
+ *         CORE2     : Core2 Duo Conroe
+ *       AMD processors
+ *         K62       : K6-2 w/ 3DNow
+ *       IDT/Centaur processors
+ *         C6        : WinChip C6
+ *         C62       : WinChip 2 w/ 3DNow
+ *       Cyrix processors
+ *         GX        : MediaGX
+ *         M1        : 6x86
+ *         M2        : M2
+ *         MGX       : MediaGX w/ MMX
+ *       Transmeta processors
+ *         TM_CRUSOE : Transmeta Crusoe(tm)
+ *       PowerPC processors
+ *         PPC603    : PowerPC 603
+ *         PPC604    : PowerPC 604
+ *         PPC750    : PowerPC 750
+ *
+ *   capabilities
+ *     This field returns the capabilities of the processor.
+ *     Legal processor capabilities include:
+ *       MMX                 : supports MMX
+ *       SSE                 : supports SSE
+ *       3DNOW               : supports 3DNow
+ *       SSE2                : supports SSE2
+ *       SFENCE              : supports SFENCE
+ *       WRITE_COMBINING     : supports write-combining
+ *       ALTIVEC             : supports ALTIVEC
+ *       PUT_NEEDS_IO        : requires OUT inst w/PUT updates
+ *       NEEDS_WC_WORKAROUND : requires workaround for P4 write-combining bug
+ *       3DNOW_EXT           : supports 3DNow Extensions
+ *       MMX_EXT             : supports MMX Extensions
+ *       CMOV                : supports CMOV
+ *       CLFLUSH             : supports CLFLUSH
+ *       SSE3                : supports SSE3
+ *       NEEDS_WAR_124888    : requires write to GPU while spinning on
+ *                           : GPU value
+ *       HT                  : support hyper-threading
+ *   clock
+ *     This field returns the processor speed in MHz.
+ *   L1DataCacheSize
+ *     This field returns the level 1 data (or unified) cache size
+ *     in kilobytes.
+ *   L2DataCacheSize
+ *     This field returns the level 2 data (or unified) cache size
+ *     in kilobytes.
+ *   dataCacheLineSize
+ *     This field returns the bytes per line in the level 1 data cache.
+ *   numLogicalCpus
+ *     This field returns the number of logical processors.  On Intel x86
+ *     systems that support it, this value will incorporate the current state
+ *     of HyperThreading.
+ *   numPhysicalCpus
+ *     This field returns the number of physical processors.
+ *   name
+ *     This field returns the CPU name in ASCII string format.
+ *   family
+ *     Vendor defined Family and Extended Family combined
+ *   model
+ *     Vendor defined Model and Extended Model combined
+ *   stepping
+ *     Silicon stepping
+ *   bSEVEnabled
+ *     Secure Encrypted Virtualization enabled/disabled state
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
+    NvU32  type;                               /* processor type        */
+    NvU32  capabilities;                       /* processor caps        */
+    NvU32  clock;                              /* processor speed (MHz) */
+    NvU32  L1DataCacheSize;                    /* L1 dcache size (KB)   */
+    NvU32  L2DataCacheSize;                    /* L2 dcache size (KB)   */
+    NvU32  dataCacheLineSize;                  /* L1 dcache bytes/line  */
+    NvU32  numLogicalCpus;                     /* logial processor cnt  */
+    NvU32  numPhysicalCpus;                    /* physical processor cnt*/
+    NvU8   name[52];                           /* embedded cpu name     */
+    NvU32  family;                             /* Vendor defined Family and Extended Family combined */
+    NvU32  model;                              /* Vendor defined Model and Extended Model combined   */
+    NvU8   stepping;                           /* Silicon stepping      */
+    NvU32  coresOnDie;                         /* cpu cores per die     */
+    NvBool bSEVEnabled;                        /* SEV enabled on cpu    */
+} NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS;
+
+// Macros for CPU family information
+#define NV0000_CTRL_SYSTEM_CPU_FAMILY                         3:0
+#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY               11:4
+
+// Macros for CPU model information
+#define NV0000_CTRL_SYSTEM_CPU_MODEL                          3:0
+#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL                 7:4
+
+// Macros for AMD CPU information
+#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY                  0xF
+#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY         0xA
+#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL                   0x0
+#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL          0x4
+
+// Macros for Intel CPU information
+#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY                0x6
+#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY       0x0
+#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL          0x7
+#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL          0xA
+#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL        0x9
+
+/*  processor type values */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN            (0x00000000U)
+/* Intel types */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_P5                 (0x00000001U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_P55                (0x00000002U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_P6                 (0x00000003U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2                 (0x00000004U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC               (0x00000005U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA               (0x00000006U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3                 (0x00000007U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2           (0x00000008U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_P4                 (0x00000009U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2              (0x00000010U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H          (0x00000011U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM        (0x00000012U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM               (0x00000013U)
+/* AMD types */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_K5                 (0x00000030U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_K6                 (0x00000031U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_K62                (0x00000032U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_K63                (0x00000033U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_K7                 (0x00000034U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_K8                 (0x00000035U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_K10                (0x00000036U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_K11                (0x00000037U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN              (0x00000038U)
+/* IDT/Centaur types */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_C6                 (0x00000060U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_C62                (0x00000061U)
+/* Cyrix types */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_GX                 (0x00000070U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_M1                 (0x00000071U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_M2                 (0x00000072U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX                (0x00000073U)
+/* Transmeta types  */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE          (0x00000080U)
+/* IBM types */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603             (0x00000090U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604             (0x00000091U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750             (0x00000092U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN             (0x00000093U)
+/* Unknown ARM architecture CPU type */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN        (0xA0000000U)
+/* ARM Ltd types */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9             (0xA0000009U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15            (0xA000000FU)
+/* NVIDIA types */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0      (0xA0001000U)
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0      (0xA0002000U)
+
+/* Generic types */
+#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC     (0xA00FF000U)
+
+
+
+/* processor capabilities */
+#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX                 (0x00000001U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE                 (0x00000002U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW               (0x00000004U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2                (0x00000008U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE              (0x00000010U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING     (0x00000020U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC             (0x00000040U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO        (0x00000080U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT           (0x00000200U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT             (0x00000400U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV                (0x00000800U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH             (0x00001000U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854    (0x00002000U) /* deprecated */
+#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3                (0x00004000U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888    (0x00008000U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE          (0x00010000U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41               (0x00020000U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42               (0x00040000U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_AVX                 (0x00080000U)
+#define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS                (0x00100000U)
+
+/* feature mask (as opposed to bugs, requirements, etc.) */
+#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK        (0x1f5e7fU) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_CAPS
+ *
+ * This command returns the set of system capabilities in the
+ * form of an array of unsigned bytes.  System capabilities include
+ * supported features and required workarounds for the system,
+ * each represented by a byte offset into the table and a bit
+ * position within that byte.
+ *
+ *   capsTblSize
+ *     This parameter specifies the size in bytes of the caps table.
+ *     This value should be set to NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE.
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the system caps bits will be transferred by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS                (0x103U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */
+
+typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS {
+    NvU32 capsTblSize;
+    NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
+} NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS;
+
+/* extract cap bit setting from tbl */
+#define NV0000_CTRL_SYSTEM_GET_CAP(tbl,c)           (((NvU8)tbl[(1?c)]) & (0?c))
+
+/* caps format is byte_index:bit_mask */
+#define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED                 0:0x01
+
+/* size in bytes of system caps table */
+#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE        1U
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO
+ *
+ * This command returns system chipset information.
+ *
+ *   vendorId
+ *     This parameter returns the vendor identification for the chipset.
+ *     A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset
+ *     cannot be identified.
+ *   deviceId
+ *     This parameter returns the device identification for the chipset.
+ *     A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset
+ *     cannot be identified.
+ *   subSysVendorId
+ *     This parameter returns the subsystem vendor identification for the
+ *     chipset.  A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the
+ *     chipset cannot be identified.
+ *   subSysDeviceId
+ *     This parameter returns the subsystem device identification for the 
+ *     chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 
+ *     chipset cannot be identified.
+ *   HBvendorId
+ *     This parameter returns the vendor identification for the chipset's
+ *     host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates
+ *     the chipset's host bridge cannot be identified.
+ *   HBdeviceId
+ *     This parameter returns the device identification for the chipset's
+ *     host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates
+ *     the chipset's host bridge cannot be identified.
+ *   HBsubSysVendorId
+ *     This parameter returns the subsystem vendor identification for the
+ *     chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID
+ *     indicates the chipset's host bridge cannot be identified.
+ *   HBsubSysDeviceId
+ *     This parameter returns the subsystem device identification for the
+ *     chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID
+ *     indicates the chipset's host bridge cannot be identified.
+ *   sliBondId
+ *     This parameter returns the SLI bond identification for the chipset.
+ *   vendorNameString
+ *     This parameter returns the vendor name string.
+ *   chipsetNameString
+ *     This parameter returns the vendor name string.
+ *   sliBondNameString
+ *     This parameter returns the SLI bond name string.
+ *   flag
+ *     This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags:
+ *     _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1
+ *     should be disabled - bug 3440153
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum name string length */
+#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U)
+
+/* invalid id */
+#define NV0000_SYSTEM_CHIPSET_INVALID_ID        (0xffffU)
+
+#define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS {
+    NvU16 vendorId;
+    NvU16 deviceId;
+    NvU16 subSysVendorId;
+    NvU16 subSysDeviceId;
+    NvU16 HBvendorId;
+    NvU16 HBdeviceId;
+    NvU16 HBsubSysVendorId;
+    NvU16 HBsubSysDeviceId;
+    NvU32 sliBondId;
+    NvU8  vendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH];
+    NvU8  subSysVendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH];
+    NvU8  chipsetNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH];
+    NvU8  sliBondNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH];
+    NvU32 flags;
+} NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS;
+
+#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE                  0:0
+#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO  (0x00000000U)
+#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U)
+
+
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE
+ *
+ * This command is used to set the system memory size in pages.
+ *
+ *   memorySize
+ *     This parameter specifies the system memory size in pages.  All values
+ *     are considered legal.
+ *
+ * 
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE                                         (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS {
+    NvU32 memorySize;
+} NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST
+ *
+ * This command is used to retrieve the set of system-level classes
+ * supported by the platform.
+ *
+ *   numClasses
+ *     This parameter returns the number of valid entries in the returned
+ *     classes[] list.  This parameter will not exceed
+ *     Nv0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE.
+ *   classes
+ *     This parameter returns the list of supported classes
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST  (0x108U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */
+
+/* maximum number of classes returned in classes[] array */
+#define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32U)
+
+#define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS {
+    NvU32 numClasses;
+    NvU32 classes[NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE];
+} NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT
+ *
+ * This command is used to send triggered mobile related system events
+ * to the RM.
+ *
+ *   eventType
+ *     This parameter indicates the triggered event type.  This parameter
+ *     should specify a valid NV0000_CTRL_SYSTEM_EVENT_TYPE value.
+ *   eventData
+ *     This parameter specifies the type-dependent event data associated
+ *     with EventType.  This parameter should specify a valid
+ *     NV0000_CTRL_SYSTEM_EVENT_DATA value.
+ *   bEventDataForced
+ *     This parameter specifies what we have to do, Whether trust current
+ *     Lid/Dock state or not. This parameter should specify a valid
+ *     NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED value.
+
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ * Sync this up (#defines) with one in nvapi.spec!
+ * (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA)
+ */
+#define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS {
+    NvU32  eventType;
+    NvU32  eventData;
+    NvBool bEventDataForced;
+} NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS;
+
+/* valid eventType values */
+#define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE        (0x00000000U)
+#define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE     (0x00000001U)
+#define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE       (0x00000002U)
+#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID        (0x00000003U)
+#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK       (0x00000004U)
+
+/* valid eventData values */
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN         (0x00000000U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED       (0x00000001U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY    (0x00000000U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC         (0x00000001U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED         (0x00000000U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED           (0x00000001U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM    (0x00000000U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS    (0x00000001U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF   (0x00000002U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI   (0x00000003U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL   (0x00000004U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT  (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM   (0x00000000U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS   (0x00000001U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF  (0x00000002U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI  (0x00000003U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL  (0x00000004U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */
+
+/* valid bEventDataForced values */
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE     (0x00000000U)
+#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE      (0x00000001U)
+
+/*
+ * NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE
+ *
+ * This command is used to query the platform type.
+ *
+ *   systemType
+ *     This parameter returns the type of the system.
+ *     Legal values for this parameter include:
+ *       NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP
+ *         The system is a desktop platform.
+ *       NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC
+ *         The system is a mobile (non-Toshiba) platform.
+ *       NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP
+ *         The system is a mobile Toshiba platform.
+ *       NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC
+ *         The system is a system-on-a-chip (SOC) platform.
+ *
+
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE       (0x111U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS {
+    NvU32 systemType;
+} NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS;
+
+/* valid systemType values */
+#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP        (0x000000U)
+#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001U)
+#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002U)
+#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC            (0x000003U)
+
+
+
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL
+ *
+ * This command controls the current RmMsg filters. 
+ *
+ * It is only supported if RmMsg is enabled (e.g. debug builds).
+ *
+ *   cmd
+ *     GET - Gets the current RmMsg filter string.
+ *     SET - Sets the current RmMsg filter string.
+ *
+ *   count
+ *     The length of the RmMsg filter string.
+ *
+ *   data
+ *     The RmMsg filter string.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL     (0x121U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE         512U
+
+#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000U)
+#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001U)
+
+#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS {
+    NvU32 cmd;
+    NvU32 count;
+    NvU8  data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE];
+} NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS;
+
+/*
+ * NV0000_CTRL_SYSTEM_HWBC_INFO
+ *
+ * This structure contains information about the HWBC (BR04) specified by 
+ * hwbcId.
+ *   
+ *   hwbcId
+ *     This field specifies the HWBC ID.
+ *   firmwareVersion
+ *     This field returns the version of the firmware on the HWBC (BR04), if
+ *     present. This is a packed binary number of the form 0x12345678, which
+ *     corresponds to a firmware version of 12.34.56.78.
+ *   subordinateBus
+ *     This field returns the subordinate bus number of the HWBC (BR04).
+ *   secondaryBus
+ *     This field returns the secondary bus number of the HWBC (BR04).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO {
+    NvU32 hwbcId;
+    NvU32 firmwareVersion;
+    NvU32 subordinateBus;
+    NvU32 secondaryBus;
+} NV0000_CTRL_SYSTEM_HWBC_INFO;
+
+#define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID   (0xFFFFFFFFU)
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO
+ *
+ * This command returns information about all Hardware Broadcast (HWBC) 
+ * devices present in the system that are BR04s. To get the complete
+ * list of HWBCs in the system, all GPUs present in the system must be 
+ * initialized. See the description of NV0000_CTRL_CMD_GPU_ATTACH_IDS to 
+ * accomplish this.
+ *   
+ *   hwbcInfo
+ *     This field is an array of NV0000_CTRL_SYSTEM_HWBC_INFO structures into
+ *     which HWBC information is placed. There is one entry for each HWBC
+ *     present in the system. Valid entries are contiguous, invalid entries 
+ *     have the hwbcId equal to NV0000_CTRL_SYSTEM_HWBC_INVALID_ID. If no HWBC
+ *     is present in the system, all the entries would be marked invalid, but
+ *     the return value would still be SUCCESS.
+ *     
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_MAX_HWBCS         (0x00000080U)
+
+#define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS {
+    NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS];
+} NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL
+ *
+ * This command is used to control GPS functionality.  It allows control of
+ * GPU Performance Scaling (GPS), changing its operational parameters and read
+ * most GPS dynamic parameters.
+ *
+ *   command
+ *     This parameter specifies the command to execute.  Invalid commands
+ *     result in the return of an NV_ERR_INVALID_ARGUMENT status.
+ *   locale
+ *     This parameter indicates the specific locale to which the command
+ *     'command' is to be applied.
+ *     Supported range of CPU/GPU {i = 0, ..., 255}
+ *   data
+ *     This parameter contains a command-specific data payload.  It can
+ *     be used to input data as well as output data.
+ * 
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_COMMAND
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_DATA
+ *   NV_ERR_INVALID_REQUEST
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL (0x122U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS {
+    NvU16 command;
+    NvU16 locale;
+    NvU32 data;
+} NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS;
+
+/* 
+ *  Valid command values :
+ *  
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT
+ *    Is used to check if GPS was correctly initialized.
+ *    Possible return (OUT) values are:
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC
+ *    Are used to stop/start GPS functionality and to get current status.
+ *    Possible IN/OUT values are:
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS
+ *    Are used to control execution of GPS actions and to get current status.
+ *    Possible IN/OUT values are:
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC
+ *    Are used to switch current GPS logic and to retrieve current logic.
+ *    Possible IN/OUT values are:
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF
+ *        Will cause that all GPS actions will be NULL.
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY
+ *        Fuzzy logic will determine GPS actions based on current ruleset.
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC
+ *        Deterministic logic will define GPS actions based on current ruleset.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE
+ *    Are used to set/retrieve system control preference.
+ *    Possible IN/OUT values are:
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT
+ *    Are used to set/retrieve GPU2CPU pstate limits.
+ *    IN/OUT values are four bytes packed into a 32-bit data field.
+ *    The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap
+ *    index for the GPU pstate 3 is in the highest byte, etc.  One
+ *    special value is to disable the override to the GPU2CPU map:
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE
+ *    Is used to stop/start GPS PMU functionality.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE
+ *    Is used to get the current status of PMU GPS.
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER
+ *    Are used to set/retrieve max power [mW] that system can provide.
+ *    This is hardcoded GPS safety feature and logic/rules does not apply
+ *    to this threshold.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET
+ *    Are used to set/retrieve current system cooling budget [mW].
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD
+ *    Are used to set/retrieve integration interval [sec].
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT
+ *    Are used to set/retrieve used ruleset [#].  Value is checked
+ *    against MAX number of rules for currently used GPS logic. Also COUNT
+ *    provides a way to find out how many rules exist for the current control 
+ *    system.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST
+ *    Is used to set/get a delay relative to now during which to allow unbound 
+ *    CPU performance.  Units are seconds.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE
+ *    Is used to override/get the actual power supply mode (AC/Battery).
+ *    Possible IN/OUT values are:
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO
+ *    Is used to get the Ventura system information for VCT tool
+ *    Returned 32bit value should be treated as bitmask and decoded in
+ *    following way:
+ *    Encoding details are defined in objgps.h refer to
+ *    NV_GPS_SYS_SUPPORT_INFO and corresponding bit defines.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTION
+ *    Is used to get the supported sub-functions defined in SBIOS.  Returned
+ *    value is a bitmask where each bit corresponds to different function:
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE
+ *    Are used to retrieve appropriate power measurements and their derivatives
+ *    in [mW] for required locale.  _BURDEN is defined only for _LOCALE_SYSTEM.
+ *    _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as
+ *    index.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS
+ *    Is used to retrieve parameters when adjusting raw sensor power reading.
+ *    The values may come from SBIOS, VBIOS, registry or driver default.
+ *    Possible IN value is the index of interested parameter.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE
+ *    Are used to retrieve appropriate temperature measurements and their
+ *    derivatives in [1/1000 Celsius].
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX
+ *    Are used to retrieve CPU(x)/GPU(x) p-state or it's limits.
+ *    Not applicable to _LOCALE_SYSTEM.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION
+ *    Is used to retrieve last GPS action for given domain.
+ *    Not applicable to _LOCALE_SYSTEM.
+ *    Possible return (OUT) values are:
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM
+ *      NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE
+ *    Is used to set the power sensor simulator state.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE
+ *    Is used to get the power simulator sensor simulator state.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA
+ *    Is used to set power sensor simulator data
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA
+ *    Is used to get power sensor simulator data
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK
+ *    Is used to respond to the ACPI event triggered by SBIOS.  RM will
+ *    request value for budget and status, validate them, apply them
+ *    and send ACK back to SBIOS.
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT
+ *    Is a test cmd that should notify SBIOS to send ACPI event requesting
+ *    budget and status change.
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GPS_INVALID                       (0xFFFFU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT                  (0x0000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC                  (0x0001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC                  (0x0002U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS               (0x0003U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS               (0x0004U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC                 (0x0005U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC                 (0x0006U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE            (0x0007U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE            (0x0008U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT         (0x0009U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT         (0x000AU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE         (0x000BU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE         (0x000CU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER             (0x0100U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER             (0x0101U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET        (0x0102U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET        (0x0103U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD       (0x0104U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD       (0x0105U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET               (0x0106U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET               (0x0107U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT            (0x0108U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST             (0x0109U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST             (0x010AU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE       (0x010BU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE       (0x010CU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO      (0x010DU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS   (0x010EU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER                (0x0200U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA          (0x0201U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE         (0x0202U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG         (0x0203U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL       (0x0204U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN         (0x0205U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE   (0x0206U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS    (0x0210U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP                 (0x0220U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA           (0x0221U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE          (0x0222U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE               (0x0240U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP           (0x0241U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN           (0x0242U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX           (0x0243U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION        (0x0244U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT  (0x0245U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE      (0x0250U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE      (0x0251U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA       (0x0252U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA       (0x0253U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT     (0x0321U)
+
+/* valid LOCALE values */
+#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID                (0xFFFFU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM                 (0x0000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i)           (0x0100+((i)%0x100))
+#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i)           (0x0200+((i)%0x100))
+
+/* valid data values for enums */
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID               (0x80000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO               (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES              (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP             (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START            (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF           (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON            (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF             (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY           (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC   (0x00000002U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU        (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU        (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH       (0x00000002U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE       (0xFFFFFFFFU)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF     (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON      (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL       (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC    (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT  (0x00000002U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT          (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS    (0x00000002U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS           (0x00000004U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC           (0x00000008U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC           (0x00000010U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB        (0x00000020U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS        (0x00000040U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0     (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1      (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING    (0x00000002U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT   (0x00000003U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1      (0x00000004U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2      (0x00000005U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM    (0x00000006U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM   (0x00000007U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO      (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES     (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF  (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON   (0x00000001U)
+
+/*
+ *  NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL
+ *
+ *  This command allows execution of multiple GpsControl commands within one
+ *  RmControl call.  For practical reasons # of commands is limited to 16.
+ *  This command shares defines with NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL.
+ *
+ *    cmdCount
+ *      Number of commands that should be executed.
+ *      Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX.
+ * 
+ *    succeeded
+ *      Number of commands that were succesully executed.
+ *      Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX.
+ *      Failing commands return NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID
+ *      in their data field.
+ *
+ *    cmdData
+ *      Array of commands with following structure:
+ *        command
+ *          This parameter specifies the command to execute.
+ *          Invalid commands result in the return of an
+ *          NV_ERR_INVALID_ARGUMENT status.
+ *        locale
+ *          This parameter indicates the specific locale to which
+ *          the command 'command' is to be applied.
+ *          Supported range of CPU/GPU {i = 0, ..., 255}
+ *        data
+ *          This parameter contains a command-specific data payload.
+ *          It is used both to input data as well as to output data.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_REQUEST
+ *    NV_ERR_NOT_SUPPORTED
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL                 (0x123U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX             (16U)
+#define NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS {
+    NvU32 cmdCount;
+    NvU32 succeeded;
+
+    struct {
+        NvU16 command;
+        NvU16 locale;
+        NvU32 data;
+    } cmdData[NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX];
+} NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS;
+
+
+/*
+ * Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead.
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS          (0x127U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of
+ * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS due to Check RM parsing issues.
+ * NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS is the maximum size of GPU groups
+ * allowed for batched P2P caps queries provided by the RM control
+ * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX.
+ */
+#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS         32U
+#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024U
+#define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS        8U
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffffU
+
+/* P2P capabilities status index values */
+#define NV0000_CTRL_P2P_CAPS_INDEX_READ              0U
+#define NV0000_CTRL_P2P_CAPS_INDEX_WRITE             1U
+#define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK            2U
+#define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS           3U
+#define NV0000_CTRL_P2P_CAPS_INDEX_PROP              4U
+#define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK          5U
+#define NV0000_CTRL_P2P_CAPS_INDEX_PCI               6U
+#define NV0000_CTRL_P2P_CAPS_INDEX_C2C               7U
+#define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1          8U
+
+#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE        9U
+
+
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS {
+    NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
+    NvU32 gpuCount;
+    NvU32 p2pCaps;
+    NvU32 p2pOptimalReadCEs;
+    NvU32 p2pOptimalWriteCEs;
+    NvU8  p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
+    NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8);
+} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS;
+
+/* valid p2pCaps values */
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED                    0:0
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE           (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE            (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED                     1:1
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE            (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE             (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED                      2:2
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE             (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE              (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED                    3:3
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE           (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE            (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED                   4:4
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE          (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE           (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED                  5:5
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE         (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE          (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED                       6:6
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE              (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE               (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED           7:7
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE  (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE   (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED            8:8
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE   (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE    (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED          9:9
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE  (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED           10:10
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE  (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE   (0x00000001U)
+
+
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED                       12:12
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE              (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE               (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED                 13:13
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE         (0x00000000U)
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE          (0x00000001U)
+
+/* P2P status codes */
+#define NV0000_P2P_CAPS_STATUS_OK                                        (0x00U)
+#define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED                     (0x01U)
+#define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED                         (0x02U)
+#define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED                (0x03U)
+#define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY                        (0x04U)
+#define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED                             (0x05U)
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2
+ *
+ * This command returns peer to peer capabilities present between GPUs.  
+ * Valid requests must present a list of GPU Ids.
+ *
+ *   [in] gpuIds
+ *     This member contains the array of GPU IDs for which we query the P2P
+ *     capabilities. Valid entries are contiguous, beginning with the first 
+ *     entry in the list.
+ *   [in] gpuCount
+ *     This member contains the number of GPU IDs stored in the gpuIds[] array.
+ *   [out] p2pCaps
+ *     This member returns the peer to peer capabilities discovered between the
+ *     GPUs. Valid p2pCaps values include:
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED
+ *         When this bit is set, peer to peer writes between subdevices owned
+ *         by this device are supported.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED
+ *         When this bit is set, peer to peer reads between subdevices owned
+ *         by this device are supported.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED
+ *         When this bit is set, peer to peer PROP between subdevices owned
+ *         by this device are supported. This is enabled by default
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED
+ *         When this bit is set, PCI is supported for all P2P between subdevices
+ *         owned by this device.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED
+ *         When this bit is set, NVLINK is supported for all P2P between subdevices
+ *         owned by this device.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED
+ *         When this bit is set, peer to peer atomics between subdevices owned
+ *         by this device are supported.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED
+ *         When this bit is set, peer to peer loopback is supported for subdevices
+ *         owned by this device.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED
+ *         When this bit is set, indirect peer to peer writes between subdevices
+ *         owned by this device are supported.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED
+ *         When this bit is set, indirect peer to peer reads between subdevices
+ *         owned by this device are supported.
+ *      NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED
+ *         When this bit is set, indirect peer to peer atomics between
+ *         subdevices owned by this device are supported.
+ *      NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED
+ *         When this bit is set, indirect NVLINK is supported for subdevices
+ *         owned by this device.
+ *      NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED
+ *         When this bit is set, C2C P2P is supported between the GPUs
+ *      NV0000_CTRL_SYSTEM_GET_P2P_CAPS_BAR1_SUPPORTED
+ *         When this bit is set, BAR1 P2P is supported between the GPUs
+ *         mentioned in @ref gpuIds
+ *   [out] p2pOptimalReadCEs
+ *      For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink
+ *   [out] p2pOptimalWriteCEs
+ *      For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink
+ *   [out] p2pCapsStatus
+ *     This member returns status of all supported p2p capabilities. Valid
+ *     status values include:
+ *       NV0000_P2P_CAPS_STATUS_OK
+ *         P2P capability is supported.
+ *       NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED
+ *         Chipset doesn't support p2p capability.
+ *       NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED
+ *         GPU doesn't support p2p capability.
+ *       NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED
+ *         IOH topology isn't supported. For e.g. root ports are on different
+ *         IOH.
+ *       NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY
+ *         P2P Capability is disabled by a regkey.
+ *       NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED
+ *         P2P Capability is not supported.
+ *       NV0000_P2P_CAPS_STATUS_NVLINK_SETUP_FAILED
+ *         Indicates that NvLink P2P link setup failed.
+ *    [out] busPeerIds
+ *        Peer ID matrix. It is a one-dimentional array.
+ *        busPeerIds[X * gpuCount + Y] maps from index X to index Y in
+ *        the gpuIds[] table. For invalid or non-existent peer busPeerIds[]
+ *        has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
+ * 
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+
+
+#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2                           (0x12bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS {
+    NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
+    NvU32 gpuCount;
+    NvU32 p2pCaps;
+    NvU32 p2pOptimalReadCEs;
+    NvU32 p2pOptimalWriteCEs;
+    NvU8  p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
+    NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED];
+} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX
+ *
+ * This command returns peer to peer capabilities present between all pairs of
+ * GPU IDs {(a, b) : a in gpuIdGrpA and b in gpuIdGrpB}. This can be used to
+ * collect all P2P capabilities in the system - see the SRT:
+ *     NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX_TEST
+ * for a demonstration.
+ *
+ * The call will query for all pairs between set A and set B, and returns
+ * results in both link directions. The results are two-dimensional arrays where
+ * the first dimension is the index within the set-A array of one GPU ID under
+ * consideration, and the second dimension is the index within the set-B array
+ * of the other GPU ID under consideration.
+ *
+ * That is, the result arrays are *ALWAYS* to be indexed first with the set-A
+ * index, then with the set-B index. The B-to-A direction of results are put in
+ * the b2aOptimal(Read|Write)CEs. This makes it unnecessary to call the query
+ * twice, since the usual use case requires both directions.
+ *
+ * If a set is being compared against itself (by setting grpBCount to 0), then
+ * the result matrices are symmetric - it doesn't matter which index is first.
+ * However, the choice of indices is effectively a choice of which ID is "B" and
+ * which is "A" for the "a2b" and "b2a" directional results.
+ *
+ *   [in] grpACount
+ *     This member contains the number of GPU IDs stored in the gpuIdGrpA[]
+ *     array. Must be >= 0.
+ *   [in] grpBCount
+ *     This member contains the number of GPU IDs stored in the gpuIdGrpB[]
+ *     array. Can be == 0 to specify a check of group A against itself.
+ *   [in] gpuIdGrpA
+ *     This member contains the array of GPU IDs in "group A", each of which
+ *     will have its P2P capabilities returned with respect to each GPU ID in
+ *     "group B". Valid entries are contiguous, beginning with the first entry
+ *     in the list.
+ *   [in] gpuIdGrpB
+ *     This member contains the array of GPU IDs in "group B", each of which
+ *     will have its P2P capabilities returned with respect to each GPU ID in
+ *     "group A". Valid entries are contiguous, beginning with the first entry
+ *     in the list. May be equal to gpuIdGrpA, but best performance requires
+ *     that the caller specifies grpBCount = 0 in this case, and ignores this.
+ *   [out] p2pCaps
+ *     This member returns the peer to peer capabilities discovered between the
+ *     pairs of input GPUs between the groups, indexed by [A_index][B_index].
+ *     Valid p2pCaps values include:
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED
+ *         When this bit is set, peer to peer writes between subdevices owned
+ *         by this device are supported.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED
+ *         When this bit is set, peer to peer reads between subdevices owned
+ *         by this device are supported.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED
+ *         When this bit is set, peer to peer PROP between subdevices owned
+ *         by this device are supported. This is enabled by default
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED
+ *         When this bit is set, PCI is supported for all P2P between subdevices
+ *         owned by this device.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED
+ *         When this bit is set, NVLINK is supported for all P2P between subdevices
+ *         owned by this device.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED
+ *         When this bit is set, peer to peer atomics between subdevices owned
+ *         by this device are supported.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED
+ *         When this bit is set, peer to peer loopback is supported for subdevices
+ *         owned by this device.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED
+ *         When this bit is set, indirect peer to peer writes between subdevices
+ *         owned by this device are supported.
+ *       NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED
+ *         When this bit is set, indirect peer to peer reads between subdevices
+ *         owned by this device are supported.
+ *      NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED
+ *         When this bit is set, indirect peer to peer atomics between
+ *         subdevices owned by this device are supported.
+ *      NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED
+ *         When this bit is set, indirect NVLINK is supported for subdevices
+ *         owned by this device.
+ *   [out] a2bOptimalReadCes
+ *      For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink
+ *      in the A-to-B direction.
+ *   [out] a2bOptimalWriteCes
+ *      For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink
+ *      in the A-to-B direction.
+ *   [out] b2aOptimalReadCes
+ *      For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink
+ *      in the B-to-A direction.
+ *   [out] b2aOptimalWriteCes
+ *      For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink
+ *      in the B-to-A direction.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+
+
+#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */
+
+typedef NvU32 NV0000_CTRL_P2P_CAPS_MATRIX_ROW[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
+#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS {
+    NvU32                           grpACount;
+    NvU32                           grpBCount;
+    NvU32                           gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
+    NvU32                           gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
+    NV0000_CTRL_P2P_CAPS_MATRIX_ROW p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
+    NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
+    NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
+    NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
+    NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
+} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GPS_CTRL
+ *
+ * This command is used to execute general GPS Functions, most dealing with
+ * calling SBIOS, or retrieving cached sensor and GPS state data.
+ *
+ *   version
+ *     This parameter specifies the version of the interface.  Legal values
+ *     for this parameter are 1.
+ *   cmd
+ *     This parameter specifies the GPS API to be invoked. 
+ *     Valid values for this parameter are:
+ *       NV0000_CTRL_GPS_CMD_GET_THERM_LIMIT
+ *         This command gets the temperature limit for thermal controller. When
+ *         this command is specified the input parameter contains ???.
+ *      NV0000_CTRL_GPS_CMD_SET_THERM_LIMIT
+ *         This command set the temperature limit for thermal controller.  When
+ *         this command is specified the input parameter contains ???.
+ *   input
+ *     This parameter specifies the cmd-specific input value.
+ *   result
+ *     This parameter returns the cmd-specific output value.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CTRL (0x12aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID (0x2AU)
+
+typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS {
+    NvU32 cmd;
+    NvS32 input[2];
+    NvS32 result[4];
+} NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS;
+
+/* valid version values */
+#define NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION      (0x00010000U)
+
+/* valid cmd values */
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT               (0x00000002U)
+#define NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                     (0x00000000U)
+#define NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT                   (0x00000000U)
+#define NV0000_CTRL_GPS_RESULT_MIN_LIMIT                       (0x00000001U)
+#define NV0000_CTRL_GPS_RESULT_MAX_LIMIT                       (0x00000002U)
+#define NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE                    (0x00000003U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT               (0x00000003U)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT                    (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA    (0x00000004U)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA          (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA    (0x00000005U)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA           (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA      (0x00000006U)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA            (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA      (0x00000007U)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA             (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA        (0x00000008U)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA              (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA        (0x00000009U)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA               (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA    (0x0000000AU)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA          (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA    (0x0000000BU)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA           (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA       (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA        (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS          (0x00000016U)
+#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS                (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS          (0x00000017U)
+#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS                 (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM      (0x00000018U)
+#define NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM            (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM      (0x00000019U)
+#define NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM             (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR               (0x0000001AU)
+//      NV0000_CTRL_GPS_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL               (0x00000001U)
+#define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE               (0x00000000U)
+#define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE           (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI                     (0x0000001BU)
+#define NV0000_CTRL_GPS_INPUT_ACPI_CMD                         (0x00000000U)
+#define NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN                    (0x00000001U)
+#define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1                   (0x00000000U)
+#define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2                   (0x00000001U)
+#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS         (0x00000000U)
+#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION        (0x00000001U)
+#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ             (0x00000002U)
+#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ                     (0x00000000U)
+#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT                  (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO                (0x0000001CU)
+#define NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO                   (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD               (0x00000026U)
+#define NV0000_CTRL_GPS_INPUT_TEMP_PERIOD                      (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD               (0x00000027U)
+#define NV0000_CTRL_GPS_RESULT_TEMP_PERIOD                     (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR         (0x00000028U)
+#define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP                    (0x00000000U)
+#define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN                  (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR         (0x00000029U)
+#define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP                   (0x00000000U)
+#define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN                 (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES    (0x0000002AU)
+#define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD       (0x00000000U)
+#define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP       (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES    (0x0000002BU)
+#define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD      (0x00000000U)
+#define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP      (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS          (0x0000002CU)
+#define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER            (0x00000000U)
+#define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER            (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS          (0x0000002DU)
+#define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER           (0x00000000U)
+#define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER           (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE             (0x0000002EU)
+#define NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE                    (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE             (0x0000002FU)
+#define NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE                   (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS        (0x00000044U)
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1    (0x00000000U)
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2    (0x00000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS        (0x00000045U)
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1    (0x00000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT            (0x00000046U)
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ        (0000000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT            (0x00000047U)
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ        (0000000000U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM                       (0x00000048U)
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX                 (0000000000U)
+#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK        (0000000001U)
+
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM                       (0x00000049U)
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX                 (0000000000U)
+#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX             (2U)
+
+#define NV0000_CTRL_GPS_PPM_INDEX                                   7:0
+#define NV0000_CTRL_GPS_PPM_INDEX_MAXPERF                      (0U)
+#define NV0000_CTRL_GPS_PPM_INDEX_BALANCED                     (1U)
+#define NV0000_CTRL_GPS_PPM_INDEX_QUIET                        (2U)
+#define NV0000_CTRL_GPS_PPM_INDEX_INVALID                      (0xFFU)
+#define NV0000_CTRL_GPS_PPM_MASK                                    15:8
+#define NV0000_CTRL_GPS_PPM_MASK_INVALID                       (0U)
+
+/* valid PS_STATUS result values */
+#define NV0000_CTRL_GPS_CMD_PS_STATUS_OFF                      (0U)
+#define NV0000_CTRL_GPS_CMD_PS_STATUS_ON                       (1U)
+
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS
+ *
+ * This command allows privileged users to update the values of
+ * security settings governing RM behavior.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT,
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *
+ * Please note: as implied above, administrator privileges are
+ * required to modify security settings.
+ */
+#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS           (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x29" */
+
+#define GPS_MAX_COUNTERS_PER_BLOCK                             32U
+typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS {
+    NvU32 objHndl;
+    NvU32 blockId;
+    NvU32 nextExpectedSampleTimems;
+    NvU32 countersReq;
+    NvU32 countersReturned;
+    NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK];
+} NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS;
+
+#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS          (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2C" */
+
+#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2E" */
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI
+ *
+ * This command allows users to call GPS ACPI commands for testing purposes.
+ *
+ *   cmd
+ *      This parameter specifies the GPS ACPI command to execute.
+ * 
+ *   input
+ *      This parameter specified the cmd-dependent input value. 
+ *
+ *   resultSz
+ *      This parameter returns the size (in bytes) of the valid data
+ *      returned in  the result parameter.
+ *
+ *   result
+ *      This parameter returns the results of the specified cmd.
+ *      The maximum size (in bytes) of this returned data will
+ *      not exceed GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE
+ *
+ *   GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE
+ *      The size of buffer (result) in unit of NvU32.
+ *      The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 
+ *      Since the prior one is 24 bytes, and the later one is 48, 
+ *      this value cannot be smaller than 288.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT,
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *
+ */
+#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE                      288U
+#define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU)
+
+typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS {
+    NvU32 cmd;
+    NvU32 input;
+    NvU32 resultSz;
+    NvU32 result[GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE];
+} NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS;
+
+#define NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI       (0x12dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV0000_CTRL_SYSTEM_PARAM_*
+ *
+ * The following is a list of system-level parameters (often sensors) that the
+ * driver can be made aware of. They are primarily intended to be used by system
+ * power-balancing algorithms that require system-wide visibility in order to
+ * function. The names and values used here are established and specified in
+ * several different NVIDIA documents that are made externally available. Thus,
+ * updates to this list must be made with great caution. The only permissible
+ * change is to append new parameters. Reordering is strictly prohibited.
+ *
+ * Brief Parameter Summary:
+ *     TGPU - GPU temperature                   (NvTemp)
+ *     PDTS - CPU package temperature           (NvTemp)
+ *     SFAN - System fan speed                  (% of maximum fan speed)
+ *     SKNT - Skin temperature                  (NvTemp)
+ *     CPUE - CPU energy counter                (NvU32)
+ *     TMP1 - Additional temperature sensor 1   (NvTemp)
+ *     TMP2 - Additional temperature sensor 2   (NvTemp)
+ *     CTGP - Mode 2 power limit offset         (NvU32)
+ *     PPMD - Power mode data                   (NvU32)
+ */
+#define NV0000_CTRL_SYSTEM_PARAM_TGPU              (0x00000000U)
+#define NV0000_CTRL_SYSTEM_PARAM_PDTS              (0x00000001U)
+#define NV0000_CTRL_SYSTEM_PARAM_SFAN              (0x00000002U)
+#define NV0000_CTRL_SYSTEM_PARAM_SKNT              (0x00000003U)
+#define NV0000_CTRL_SYSTEM_PARAM_CPUE              (0x00000004U)
+#define NV0000_CTRL_SYSTEM_PARAM_TMP1              (0x00000005U)
+#define NV0000_CTRL_SYSTEM_PARAM_TMP2              (0x00000006U)
+#define NV0000_CTRL_SYSTEM_PARAM_CTGP              (0x00000007U)
+#define NV0000_CTRL_SYSTEM_PARAM_PPMD              (0x00000008U)
+#define NV0000_CTRL_SYSTEM_PARAM_COUNT             (0x00000009U)
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD
+ *
+ * This command is used to execute general ACPI methods.
+ *
+ *  method
+ *    This parameter identifies the MXM ACPI API to be invoked. 
+ *    Valid values for this parameter are:
+ *      NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS
+ *        This value specifies that the DSM NVOP subfunction OPTIMUSCAPS
+ *        API is to be invoked.
+ *      NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG
+ *        This value specifies that the DSM NVOP subfunction OPTIMUSFLAG
+ *        API is to be invoked. This API will set a Flag in sbios to Indicate 
+ *        that HD Audio Controller is disable/Enabled from GPU Config space.
+ *        This flag will be used by sbios to restore Audio state after resuming
+ *        from s3/s4.
+ *      NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS
+ *        This value specifies that the DSM JT subfunction FUNC_CAPS is to
+ *        to be invoked to get the SBIOS capabilities
+ *      NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY
+ *        This value specifies that the DSM JT subfunction FUNC_PLATPOLICY is
+ *        to be invoked to set and get the various platform policies for JT.
+ *        Refer to the JT spec in more detail on various policies.
+ *  inData
+ *    This parameter specifies the method-specific input buffer.  Data is
+ *    passed to the specified API using this buffer.
+ *  inDataSize
+ *    This parameter specifies the size of the inData buffer in bytes.
+ *  outStatus
+ *    This parameter returns the status code from the associated ACPI call.
+ *  outData
+ *    This parameter specifies the method-specific output buffer.  Data
+ *    is returned by the specified API using this buffer.
+ *  outDataSize
+ *    This parameter specifies the size of the outData buffer in bytes. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x130U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x30U)
+
+typedef struct NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS {
+    NvU32 method;
+    NV_DECLARE_ALIGNED(NvP64 inData, 8);
+    NvU16 inDataSize;
+    NvU32 outStatus;
+    NV_DECLARE_ALIGNED(NvP64 outData, 8);
+    NvU16 outDataSize;
+} NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS;
+
+/* valid method parameter values */
+#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000000U)
+#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000001U)
+#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS          (0x00000002U)
+#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY    (0x00000003U)
+/*
+ * NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS
+ *
+ * This command can be used to instruct the RM to enable/disable specific module
+ * of ETW events.
+ *
+ *   moduleMask
+ *     This parameter specifies the module of events we would like to 
+ *     enable/disable.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS                    (0x131U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID (0x31U)
+
+typedef struct NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS {
+    NvU32 moduleMask;
+} NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS;
+
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL         (0x00000001U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ      (0x00000002U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH       (0x00000004U)
+
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF        (0x00000010U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG        (0x00000020U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS       (0x00000040U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER       (0x00000080U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP        (0x00000100U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI       (0x00000200U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR        (0x00000400U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK        (0x00000800U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL   (0x00001000U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC     (0x00002000U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM       (0x00004000U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS         (0x00008000U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE        (0x00010000U)
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY (0x00020000U)
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA
+ *
+ * This command is used to read FRL data based on need.
+ *
+ *   nextSampleNumber
+ *     This parameter returns the counter of next sample which is being filled.
+ *   samples
+ *     This parameter returns the frame time, render time, target time, client ID 
+ *     with one reserve bit for future use.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA       (0x12fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE   64U
+
+typedef struct NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE {
+    NvU16 frameTime;
+    NvU16 renderTime;
+    NvU16 targetTime;
+    NvU8  sleepTime;
+    NvU8  sampleNumber;
+} NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE;
+
+#define NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x2FU)
+
+typedef struct NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS {
+    NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE];
+    NvU8                                   nextSampleNumber;
+} NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA
+ *
+ * This command is used to write FRM data based on need.
+ *
+ *   frameTime
+ *     This parameter contains the frame time of current frame.
+ *   renderTime
+ *     This parameter contains the render time of current frame.
+ *   targetTime
+ *     This parameter contains the target time of current frame.
+ *   sleepTime
+ *     This parameter contains the sleep duration inserted by FRL for the latest frame.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA (0x132U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x32U)
+
+typedef struct NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS {
+    NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE sampleData;
+} NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO
+ *
+ * This command returns the current host driver, host OS and 
+ * plugin information. It is only valid when VGX is setup.
+ *   szHostDriverVersionBuffer
+ *       This field returns the host driver version (NV_VERSION_STRING).
+ *   szHostVersionBuffer
+ *       This field returns the host driver version (NV_BUILD_BRANCH_VERSION).
+ *   szHostTitleBuffer
+ *       This field returns the host driver title (NV_DISPLAY_DRIVER_TITLE).
+ *   szPluginTitleBuffer
+ *       This field returns the plugin build title (NV_DISPLAY_DRIVER_TITLE).
+ *   szHostUnameBuffer
+ *       This field returns the call of 'uname' on the host OS.
+ *   iHostChangelistNumber
+ *       This field returns the changelist value of the host driver (NV_BUILD_CHANGELIST_NUM).
+ *   iPluginChangelistNumber
+ *       This field returns the changelist value of the plugin (NV_BUILD_CHANGELIST_NUM).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256U
+#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO             (0x133U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS {
+    char  szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
+    char  szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
+    char  szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
+    char  szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
+    char  szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
+    NvU32 iHostChangelistNumber;
+    NvU32 iPluginChangelistNumber;
+} NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS
+ *
+ * This command returns the power status of the GPUs in the system, successfully attached or not because of
+ * insufficient power. It is supported on Kepler and up only.
+ *   gpuCount
+ *       This field returns the count into the following arrays.
+ *   busNumber
+ *       This field returns the busNumber of a GPU.
+ *   gpuExternalPowerStatus
+ *       This field returns the corresponding external power status:
+ *          NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED
+ *          NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS {
+    NvU8 gpuCount;
+    NvU8 gpuBus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
+    NvU8 gpuExternalPowerStatus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
+} NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS;
+
+/* Valid gpuExternalPowerStatus values */
+#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED     0U
+#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1U
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS
+ * 
+ * This command returns the caller's API access privileges using
+ * this client handle.
+ *
+ *   privStatus
+ *     This parameter returns a mask of possible access privileges:
+ *       NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_USER_FLAG
+ *         The caller is running with elevated privileges
+ *       NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_ROOT_HANDLE_FLAG
+ *         Client is of NV01_ROOT class.
+ *       NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG
+ *         Client has PRIV bit set.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+
+#define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS               (0x135U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS {
+    NvU8 privStatusFlags;
+} NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS;
+
+
+/* Valid privStatus values */
+#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG     (0x00000001U)
+#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002U)
+#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG   (0x00000004U)
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS
+ *
+ * The fabric manager (FM) notifies RM that fabric (system) is ready for peer to
+ * peer (P2P) use or still initializing the fabric. This command allows clients
+ * to query fabric status to allow P2P operations.
+ *
+ * Note, on systems where FM isn't used, RM just returns _SKIP.
+ *
+ * fabricStatus
+ *     This parameter returns current fabric status:
+ *          NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP
+ *          NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED
+ *          NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS
+ *          NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS {
+    NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1,
+    NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2,
+    NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3,
+    NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4,
+} NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS;
+
+#define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS {
+    NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus;
+} NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS;
+
+/*
+ * NV0000_CTRL_VGPU_GET_VGPU_VERSION_INFO
+ *
+ * This command is used to query the range of VGX version supported.
+ *
+ *  host_min_supported_version
+ *     The minimum vGPU version supported by host driver
+ *  host_max_supported_version
+ *     The maximum vGPU version supported by host driver
+ *  user_min_supported_version
+ *     The minimum vGPU version set by user for vGPU support
+ *  user_max_supported_version
+ *     The maximum vGPU version set by user for vGPU support
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_REQUEST
+ */
+#define NV0000_CTRL_VGPU_GET_VGPU_VERSION (0x137U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV0000_CTRL_VGPU_GET_VGPU_VERSION
+ */
+#define NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x37U)
+
+typedef struct NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS {
+    NvU32 host_min_supported_version;
+    NvU32 host_max_supported_version;
+    NvU32 user_min_supported_version;
+    NvU32 user_max_supported_version;
+} NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS;
+
+/*
+ * NV0000_CTRL_VGPU_SET_VGPU_VERSION
+ *
+ * This command is used to query whether pGPU is live migration capable or not.
+ *
+ *  min_version
+ *      The minimum vGPU version to be supported being set
+ *  max_version
+ *      The maximum vGPU version to be supported being set
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_REQUEST
+ */
+#define NV0000_CTRL_VGPU_SET_VGPU_VERSION (0x138U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS
+ */
+#define NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x38U)
+
+typedef struct NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS {
+    NvU32 min_version;
+    NvU32 max_version;
+} NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS;
+
+/*
+ * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID
+ *
+ * This command is used to get a unique identifier for the instance of RM.
+ * The returned value will only change when the driver is reloaded. A previous
+ * value will never be reused on a given machine.
+ *
+ *  rm_instance_id;
+ *      The instance ID of the current RM instance
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS
+ */
+#define NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID (0x39U)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8);
+} NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO
+ *
+ * This API is used to get the TPP(total processing power) and 
+ * the rated TGP(total GPU power) from SBIOS.
+ *
+ * NVPCF is an acronym for Nvidia Platform Controllers and Framework 
+ * which implements platform level policies. NVPCF is implemented in
+ * a kernel driver on windows. It is implemented in a user mode app 
+ * called nvidia-powerd on Linux.
+ * 
+ *  gpuId
+ *      GPU ID
+ *  tpp
+ *      Total processing power including CPU and GPU
+ *  ratedTgp
+ *      Rated total GPU Power
+ *  subFunc
+ *      NVPCF subfunction id
+ *  ctgpOffsetmW
+ *      Configurable TGP offset, in mW
+ *  targetTppOffsetmW
+ *      TPP, as offset in mW.
+ *  maxOutputOffsetmW
+ *      Maximum allowed output, as offset in mW.
+ *  minOutputOffsetmW;
+ *      Minimum allowed output, as offset in mW.
+ *
+ *   Valid subFunc ids for NVPCF 1x include :
+ *   NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED
+ *   NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_REQUEST
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU)
+
+typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
+    NvU32 gpuId;
+    NvU32 tpp;
+    NvU32 ratedTgp;
+    NvU32 subFunc;
+    NvU32 ctgpOffsetmW;
+    NvU32 targetTppOffsetmW;
+    NvU32 maxOutputOffsetmW;
+    NvU32 minOutputOffsetmW;
+} NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
+
+/* Valid NVPCF subfunction case */
+#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE 0U
+#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE   1U
+#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U
+#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE   3U
+
+/* Valid NVPCF subfunction ids */
+#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED      (0x00000000)
+#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002)
+
+/*
+ *  Defines for get supported sub functions bit fields
+ */
+#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED        0:0
+#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES    1
+#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO     0
+
+/*!
+ * Config DSM 2x version specific defines
+ */
+#define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION                 (0x00000200)
+#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED      (0x00000000)
+#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002)
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT
+ *
+ * This API is used to sync the external fabric management status with
+ * GSP-RM
+ *
+ *  bExternalFabricMgmt
+ *      Whether fabric is externally managed
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT     (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU)
+
+typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS {
+    NvBool bExternalFabricMgmt;
+} NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS;
+
+/*
+ * NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO
+ *
+ * This API is used to get information about the RM client
+ * database.
+ *
+ * clientCount [OUT]
+ *  This field indicates the number of clients currently allocated.
+ *
+ * resourceCount [OUT]
+ *  This field indicates the number of resources currently allocated
+ *  across all clients.
+ *
+ */
+#define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS {
+    NvU32 clientCount;
+    NV_DECLARE_ALIGNED(NvU64 resourceCount, 8);
+} NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2
+ *
+ * This command returns the current driver information in
+ * statically sized character arrays.
+ *
+ *   driverVersionBuffer
+ *       This field returns the version (NV_VERSION_STRING).
+ *   versionBuffer
+ *       This field returns the version (NV_BUILD_BRANCH_VERSION).
+ *   titleBuffer
+ *       This field returns the title (NV_DISPLAY_DRIVER_TITLE).
+ *   changelistNumber
+ *       This field returns the changelist value (NV_BUILD_CHANGELIST_NUM).
+ *   officialChangelistNumber
+ *       This field returns the last official changelist value
+ *       (NV_LAST_OFFICIAL_CHANGELIST_NUM).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256U
+#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2             (0x13eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU)
+
+typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS {
+    char  driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE];
+    char  versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE];
+    char  titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE];
+    NvU32 changelistNumber;
+    NvU32 officialChangelistNumber;
+} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL
+ *
+ * This API is used to get/set RMCTRL cache mode
+ *
+ * cmd [IN]
+ *   GET - Gets RMCTRL cache mode
+ *   SET - Sets RMCTRL cache mode
+ *
+ * mode [IN/OUT]
+ *  On GET, this field is the output of current RMCTRL cache mode
+ *  On SET, this field indicates the mode to set RMCTRL cache to
+ *  Valid values for this parameter are:
+ *    NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE
+ *      No get/set action to cache.
+ *    NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE
+ *      Try to get from cache at the beginning of the control.
+ *      Set cache after control finished if the control has not been cached.
+ *    NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY
+ *      Do not get from cache. Set cache when control call finished.
+ *      When setting the cache, verify the value in the cache is the same
+ *      with the current control value if the control is already cached.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL (0x13fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID (0x3FU)
+
+typedef struct NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS {
+    NvU32 cmd;
+    NvU32 mode;
+} NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS;
+
+#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET          (0x00000000U)
+#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET          (0x00000001U)
+
+#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE     (0x00000000U)
+#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE      (0x00000001U)
+#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY (0x00000002U)
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL
+ *
+ * This command is used to control PFM_REQ_HNDLR functionality.  It allows control of
+ * GPU Performance Scaling (PFM_REQ_HNDLR), changing its operational parameters and read
+ * most PFM_REQ_HNDLR dynamic parameters.
+ *
+ *   command
+ *     This parameter specifies the command to execute.  Invalid commands
+ *     result in the return of an NV_ERR_INVALID_ARGUMENT status.
+ *   locale
+ *     This parameter indicates the specific locale to which the command
+ *     'command' is to be applied.
+*     Supported range of CPU/GPU {i = 0, ..., 255}
+ *   data
+ *     This parameter contains a command-specific data payload.  It can
+ *     be used to input data as well as output data.
+ * 
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_COMMAND
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_DATA
+ *   NV_ERR_INVALID_REQUEST
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL               (0x140U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID (0x40U)
+
+typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS {
+    NvU16 command;
+    NvU16 locale;
+    NvU32 data;
+} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS;
+
+/* 
+ *  Valid command values :
+ *  
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT
+ *    Is used to check if PFM_REQ_HNDLR was correctly initialized.
+ *    Possible return (OUT) values are:
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC
+ *    Are used to stop/start PFM_REQ_HNDLR functionality and to get current status.
+ *    Possible IN/OUT values are:
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS
+ *    Are used to control execution of PFM_REQ_HNDLR actions and to get current status.
+ *    Possible IN/OUT values are:
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC
+ *    Are used to switch current PFM_REQ_HNDLR logic and to retrieve current logic.
+ *    Possible IN/OUT values are:
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF
+ *        Will cause that all PFM_REQ_HNDLR actions will be NULL.
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY
+ *        Fuzzy logic will determine PFM_REQ_HNDLR actions based on current ruleset.
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC
+ *        Deterministic logic will define PFM_REQ_HNDLR actions based on current ruleset.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE
+ *    Are used to set/retrieve system control preference.
+ *    Possible IN/OUT values are:
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT
+ *    Are used to set/retrieve GPU2CPU pstate limits.
+ *    IN/OUT values are four bytes packed into a 32-bit data field.
+ *    The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap
+ *    index for the GPU pstate 3 is in the highest byte, etc.  One
+ *    special value is to disable the override to the GPU2CPU map:
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE
+ *    Is used to stop/start PFM_REQ_HNDLR PMU functionality.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE
+ *    Is used to get the current status of PMU PFM_REQ_HNDLR.
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER
+ *    Are used to set/retrieve max power [mW] that system can provide.
+ *    This is hardcoded PFM_REQ_HNDLR safety feature and logic/rules does not apply
+ *    to this threshold.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET
+ *    Are used to set/retrieve current system cooling budget [mW].
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD
+ *    Are used to set/retrieve integration interval [sec].
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT
+ *    Are used to set/retrieve used ruleset [#].  Value is checked
+ *    against MAX number of rules for currently used PFM_REQ_HNDLR logic. Also COUNT
+ *    provides a way to find out how many rules exist for the current control 
+ *    system.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST
+ *    Is used to set/get a delay relative to now during which to allow unbound 
+ *    CPU performance.  Units are seconds.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE
+ *    Is used to override/get the actual power supply mode (AC/Battery).
+ *    Possible IN/OUT values are:
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO
+ *    Is used to get the Ventura system information for VCT tool
+ *    Returned 32bit value should be treated as bitmask and decoded in
+ *    following way:
+ *    Encoding details are defined in objPFM_REQ_HNDLR.h refer to
+ *    NV_PFM_REQ_HNDLR_SYS_SUPPORT_INFO and corresponding bit defines.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTION
+ *    Is used to get the supported sub-functions defined in SBIOS.  Returned
+ *    value is a bitmask where each bit corresponds to different function:
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE
+ *    Are used to retrieve appropriate power measurements and their derivatives
+ *    in [mW] for required locale.  _BURDEN is defined only for _LOCALE_SYSTEM.
+ *    _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as
+ *    index.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS
+ *    Is used to retrieve parameters when adjusting raw sensor power reading.
+ *    The values may come from SBIOS, VBIOS, registry or driver default.
+ *    Possible IN value is the index of interested parameter.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE
+ *    Are used to retrieve appropriate temperature measurements and their
+ *    derivatives in [1/1000 Celsius].
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX
+ *    Are used to retrieve CPU(x)/GPU(x) p-state or it's limits.
+ *    Not applicable to _LOCALE_SYSTEM.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION
+ *    Is used to retrieve last PFM_REQ_HNDLR action for given domain.
+ *    Not applicable to _LOCALE_SYSTEM.
+ *    Possible return (OUT) values are:
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM
+ *      NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE
+ *    Is used to set the power sensor simulator state.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE
+ *    Is used to get the power simulator sensor simulator state.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA
+ *    Is used to set power sensor simulator data
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA
+ *    Is used to get power sensor simulator data
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK
+ *    Is used to respond to the ACPI event triggered by SBIOS.  RM will
+ *    request value for budget and status, validate them, apply them
+ *    and send ACK back to SBIOS.
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT
+ *    Is a test cmd that should notify SBIOS to send ACPI event requesting
+ *    budget and status change.
+ */
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID                             (0xFFFFU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT                        (0x0000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC                        (0x0001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC                        (0x0002U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS                     (0x0003U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS                     (0x0004U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC                       (0x0005U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC                       (0x0006U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE                  (0x0007U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE                  (0x0008U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT               (0x0009U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT               (0x000AU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE     (0x000BU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE     (0x000CU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER                   (0x0100U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER                   (0x0101U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET              (0x0102U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET              (0x0103U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD             (0x0104U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD             (0x0105U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET                     (0x0106U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET                     (0x0107U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT                  (0x0108U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST                   (0x0109U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST                   (0x010AU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE             (0x010BU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE             (0x010CU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO            (0x010DU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS         (0x010EU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER                      (0x0200U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA                (0x0201U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE               (0x0202U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG               (0x0203U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL             (0x0204U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN               (0x0205U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE         (0x0206U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS          (0x0210U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP                       (0x0220U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA                 (0x0221U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE                (0x0222U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE                     (0x0240U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP                 (0x0241U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN                 (0x0242U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX                 (0x0243U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION              (0x0244U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT        (0x0245U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE            (0x0250U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE            (0x0251U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA             (0x0252U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA             (0x0253U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK       (0x0320U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT           (0x0321U)
+
+/* valid LOCALE values */
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID                      (0xFFFFU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM                       (0x0000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i)           (0x0100+((i)%0x100))
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i)           (0x0200+((i)%0x100))
+
+/* valid data values for enums */
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID                     (0x80000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO                     (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES                    (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP                   (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START                  (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF                 (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON                  (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF                   (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY                 (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC         (0x00000002U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU              (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU              (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH             (0x00000002U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE             (0xFFFFFFFFU)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON  (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL             (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC          (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT        (0x00000002U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT                (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS          (0x00000002U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS                 (0x00000004U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC                 (0x00000008U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC                 (0x00000010U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB              (0x00000020U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS              (0x00000040U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0           (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1            (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING          (0x00000002U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT         (0x00000003U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1            (0x00000004U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2            (0x00000005U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM          (0x00000006U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM         (0x00000007U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO            (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES           (0x00000001U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF        (0x00000000U)
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON         (0x00000001U)
+
+/*
+ *  NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL
+ *
+ *  This command allows execution of multiple PFM_REQ_HNDLRControl commands within one
+ *  RmControl call.  For practical reasons # of commands is limited to 16.
+ *  This command shares defines with NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL.
+ *
+ *    cmdCount
+ *      Number of commands that should be executed.
+ *      Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX.
+ * 
+ *    succeeded
+ *      Number of commands that were succesully executed.
+ *      Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX.
+ *      Failing commands return NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID
+ *      in their data field.
+ *
+ *    cmdData
+ *      Array of commands with following structure:
+ *        command
+ *          This parameter specifies the command to execute.
+ *          Invalid commands result in the return of an
+ *          NV_ERR_INVALID_ARGUMENT status.
+ *        locale
+ *          This parameter indicates the specific locale to which
+ *          the command 'command' is to be applied.
+ *          Supported range of CPU/GPU {i = 0, ..., 255}
+ *        data
+ *          This parameter contains a command-specific data payload.
+ *          It is used both to input data as well as to output data.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_REQUEST
+ *    NV_ERR_NOT_SUPPORTED
+ */
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL                       (0x141U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX                   (16U)
+#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x41U)
+
+typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS {
+    NvU32 cmdCount;
+    NvU32 succeeded;
+
+    struct {
+        NvU16 command;
+        NvU16 locale;
+        NvU32 data;
+    } cmdData[NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX];
+} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL
+ *
+ * This command is used to execute general PFM_REQ_HNDLR Functions, most dealing with
+ * calling SBIOS, or retrieving cached sensor and PFM_REQ_HNDLR state data.
+ *
+ *   version
+ *     This parameter specifies the version of the interface.  Legal values
+ *     for this parameter are 1.
+ *   cmd
+ *     This parameter specifies the PFM_REQ_HNDLR API to be invoked. 
+ *     Valid values for this parameter are:
+ *       NV0000_CTRL_PFM_REQ_HNDLR_CMD_GET_THERM_LIMIT
+ *         This command gets the temperature limit for thermal controller. When
+ *         this command is specified the input parameter contains ???.
+ *      NV0000_CTRL_PFM_REQ_HNDLR_CMD_SET_THERM_LIMIT
+ *         This command set the temperature limit for thermal controller.  When
+ *         this command is specified the input parameter contains ???.
+ *   input
+ *     This parameter specifies the cmd-specific input value.
+ *   result
+ *     This parameter returns the cmd-specific output value.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL (0x142U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID (0x42U)
+
+typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS {
+    NvU32 cmd;
+    NvS32 input[2];
+    NvS32 result[4];
+} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS;
+
+/* valid version values */
+#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION      (0x00010000U)
+
+/* valid cmd values */
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT               (0x00000002U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                     (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT                   (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT                       (0x00000001U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT                       (0x00000002U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE                    (0x00000003U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT               (0x00000003U)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT                    (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA    (0x00000004U)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA          (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA    (0x00000005U)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA           (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA      (0x00000006U)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA            (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA      (0x00000007U)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA             (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA        (0x00000008U)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA              (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA        (0x00000009U)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA               (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA    (0x0000000AU)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA          (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA    (0x0000000BU)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA           (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA       (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA        (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS          (0x00000016U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS                (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS          (0x00000017U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS                 (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM      (0x00000018U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM            (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM      (0x00000019U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM             (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR               (0x0000001AU)
+//      NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX                          (0x00000000)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL               (0x00000001U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE               (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE           (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI                     (0x0000001BU)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD                         (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN                    (0x00000001U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1                   (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2                   (0x00000001U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS         (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION        (0x00000001U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ             (0x00000002U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ                     (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT                  (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO                (0x0000001CU)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO                   (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD               (0x00000026U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD                      (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD               (0x00000027U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD                     (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR         (0x00000028U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP                    (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN                  (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR         (0x00000029U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP                   (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN                 (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES    (0x0000002AU)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD       (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP       (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES    (0x0000002BU)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD      (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP      (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS          (0x0000002CU)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER            (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER            (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS          (0x0000002DU)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER           (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER           (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE             (0x0000002EU)
+#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE                    (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE             (0x0000002FU)
+#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE                   (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS        (0x00000044U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1    (0x00000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2    (0x00000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS        (0x00000045U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1    (0x00000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT            (0x00000046U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ        (0000000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT            (0x00000047U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ        (0000000000U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM                       (0x00000048U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX                 (0000000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK        (0000000001U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM                       (0x00000049U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX                 (0000000000U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX             (2U)
+
+#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX                                   7:0
+#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF                      (0U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED                     (1U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET                        (2U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID                      (0xFFU)
+#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK                                    15:8
+#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID                       (0U)
+
+/* valid PS_STATUS result values */
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF                      (0U)
+#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON                       (1U)
+
+#define PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK                             32U
+typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS {
+    NvU32 objHndl;
+    NvU32 blockId;
+    NvU32 nextExpectedSampleTimems;
+    NvU32 countersReq;
+    NvU32 countersReturned;
+    NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK];
+} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS;
+
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS          (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x46" */
+
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x47" */
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI
+ *
+ * This command allows users to call PFM_REQ_HNDLR ACPI commands for testing purposes.
+ *
+ *   cmd
+ *      This parameter specifies the PFM_REQ_HNDLR ACPI command to execute.
+ * 
+ *   input
+ *      This parameter specified the cmd-dependent input value. 
+ *
+ *   resultSz
+ *      This parameter returns the size (in bytes) of the valid data
+ *      returned in  the result parameter.
+ *
+ *   result
+ *      This parameter returns the results of the specified cmd.
+ *      The maximum size (in bytes) of this returned data will
+ *      not exceed PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE
+ *
+ *   PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE
+ *      The size of buffer (result) in unit of NvU32.
+ *      The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 
+ *      Since the prior one is 24 bytes, and the later one is 48, 
+ *      this value cannot be smaller than 288.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT,
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *
+ */
+#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE                      288U
+#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U)
+
+typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS {
+    NvU32 cmd;
+    NvU32 input;
+    NvU32 resultSz;
+    NvU32 result[PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE];
+} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS;
+
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI        (0x143U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR       (0x00008000U)
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA
+ *
+ * This command is used to read FRL data based on need.
+ *
+ *   nextSampleNumber
+ *     This parameter returns the counter of next sample which is being filled.
+ *   samples
+ *     This parameter returns the frame time, render time, target time, client ID 
+ *     with one reserve bit for future use.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA     (0x144U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE 64U
+
+typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE {
+    NvU16 frameTime;
+    NvU16 renderTime;
+    NvU16 targetTime;
+    NvU8  sleepTime;
+    NvU8  sampleNumber;
+} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE;
+
+#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x44U)
+
+typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS {
+    NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE];
+    NvU8                                             nextSampleNumber;
+} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA
+ *
+ * This command is used to write FRM data based on need.
+ *
+ *   frameTime
+ *     This parameter contains the frame time of current frame.
+ *   renderTime
+ *     This parameter contains the render time of current frame.
+ *   targetTime
+ *     This parameter contains the target time of current frame.
+ *   sleepTime
+ *     This parameter contains the sleep duration inserted by FRL for the latest frame.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA (0x145U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x45U)
+
+typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS {
+    NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE sampleData;
+} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS;
+
+/* _ctrl0000system_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h
new file mode 100644
index 0000000..d55703d
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h
@@ -0,0 +1,435 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000unix.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+
+#include "ctrl/ctrlxxxx.h"
+/* NV01_ROOT (client) Linux control commands and parameters */
+
+/*
+ * NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE
+ *
+ * This command may be used to force a cache flush for a range of virtual addresses in 
+ * memory. Can be used for either user or kernel addresses.
+ *
+ *   offset, length
+ *     These parameters specify the offset within the memory block
+ *     and the number of bytes to flush/invalidate
+ *   cacheOps
+ *     This parameter flags whether to flush, invalidate or do both.
+ *     Possible values are:
+ *       NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH
+ *       NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE
+ *       NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE
+ *   hDevice
+ *     This parameter is the handle to the device
+ *   hObject
+ *     This parameter is the handle to the memory structure being operated on.
+ *   internalOnly
+ *     Intended for internal use unless client is running in MODS UNIX environment, 
+ *     in which case this parameter specify the virtual address of the memory block 
+ *     to flush.
+ *
+ * Possible status values are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_COMMAND
+ *   NV_ERR_INVALID_LIMIT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE (0x3d02) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+    NV_DECLARE_ALIGNED(NvU64 length, 8);
+    NvU32    cacheOps;
+    NvHandle hDevice;
+    NvHandle hObject;
+    NV_DECLARE_ALIGNED(NvU64 internalOnly, 8);
+} NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS;
+
+#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH            (0x00000001)
+#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE       (0x00000002)
+#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE (0x00000003)
+
+
+/*
+ * NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR
+ *
+ * This command is used to get the control file descriptor.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *
+ */
+#define NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR   (0x3d04) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x4" */
+
+typedef struct NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS {
+    NvS32 fd;
+} NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS;
+
+typedef enum NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE {
+    NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = 0,
+    NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = 1,
+} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE;
+
+typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT {
+    NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE type;
+
+    union {
+        struct {
+            NvHandle hDevice;
+            NvHandle hParent;
+            NvHandle hObject;
+        } rmObject;
+    } data;
+} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT;
+
+/*
+ * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD
+ *
+ * This command may be used to export NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE
+ * object to file descriptor.
+ *
+ * Note that the 'fd' parameter is an input parameter at the kernel level, but
+ * an output parameter for usermode RMAPI clients -- the RMAPI library will
+ * open a new FD automatically if a usermode RMAPI client exports an object.
+ *
+ * Kernel-mode RM clients can export an object to an FD in two steps:
+ * 1. User client calls this RMControl with the flag 'EMPTY_FD_TRUE' to create
+ *    an empty FD to receive the object, then passes that FD to the kernel-mode
+ *    RM client.
+ * 2. Kernel-mode RM client fills in the rest of the
+ *    NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS as usual and calls RM to
+ *    associate its desired RM object with the empty FD from its usermode
+ *    client.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_PARAMETER
+ */
+#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (0x3d05) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS {
+    NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */
+    NvS32                             fd;                                 /* IN/OUT */
+    NvU32                             flags;                              /* IN */
+} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS;
+
+/*
+ * If EMPTY_FD is TRUE, the 'fd' will be created but no object will be
+ * associated with it.  The hDevice parameter is still required, to determine
+ * the correct device node on which to create the file descriptor.
+ * (An empty FD can then be passed to a kernel-mode driver to associate it with
+ * an actual object.)
+ */
+#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD       0:0
+#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE (0x00000000)
+#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE  (0x00000001)
+
+/*
+ * NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD
+ *
+ * This command may be used to import back
+ * NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE object from file descriptor.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_PARAMETER
+ */
+#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD                (0x3d06) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS {
+    NvS32                             fd;                                 /* IN */
+    NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */
+} NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_OS_GET_GPU_INFO
+ *
+ * This command will query the OS specific info for the specified GPU.
+ *
+ *  gpuId
+ *    This parameter should specify a valid GPU ID value.  If there
+ *    is no GPU present with the specified ID, a status of
+ *    NV_ERR_INVALID_ARGUMENT is returned.
+ *  minorNum
+ *    This parameter returns minor number of device node.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0000_CTRL_CMD_OS_GET_GPU_INFO (0x3d07) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x7" */
+
+typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS {
+    NvU32 gpuId;    /* IN */
+    NvU32 minorNum; /* OUT */
+} NV0000_CTRL_OS_GET_GPU_INFO_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO
+ *
+ * This command will query the deviceInstance for the specified FD
+ * which is referencing an exported object.
+ *
+ *  fd
+ *    File descriptor parameter is referencing an exported object on a Unix system.
+ *
+ *  deviceInstatnce
+ *    This parameter returns a deviceInstance on which the object is located.
+ *
+ *    NV_MAX_DEVICES is returned if the object is parented by a client instead
+ *    of a device.
+ *
+ *  maxObjects
+ *    This parameter returns the maximum number of object handles that may be
+ *    contained in the file descriptor.
+ *
+ *  metadata
+ *    This parameter returns the user metadata passed into the
+ *    _EXPORT_OBJECTS_TO_FD control call.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+
+#define NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO (0x3d08) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE    64
+
+#define NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS {
+    NvS32 fd;               /* IN  */
+    NvU32 deviceInstance;   /* OUT */
+    NvU16 maxObjects;       /* OUT */
+    NvU8  metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* OUT */
+} NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST
+ *
+ * This command will re-fetch probed GPUs information and update RMAPI library's
+ * internal detected GPU context information accordingly. Without this, GPUs
+ * attached to RM after RMAPI client initialization will not be accessible and
+ * all RMAPI library calls will fail on them.
+ * Currently this is used by NVSwitch Fabric Manager in conjunction with NVSwitch
+ * Shared Virtualization feature where GPUs are hot-plugged to OS/RM (by Hypervisor)
+ * and Fabric Manager is signaled externally by the Hypervisor to initialize those GPUs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+
+#define NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST       (0x3d09) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x9" */
+
+/*
+ * This control call has been deprecated. It will be deleted soon.
+ * Use NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (singular) or
+ * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (plural) instead.
+ */
+#define NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD         (0x3d0a) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE
+
+#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS {
+    NvHandle hDevice;                                                       /* IN */
+    NvU16    maxObjects;                                                       /* IN */
+    NvU8     metadata[NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */
+    NvS32    fd;                                                               /* IN/OUT */
+} NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD
+ *
+ * Exports RM handles to an fd that was provided, also creates an FD if
+ * requested.
+ *
+ * The objects in the 'handles' array are exported into the fd
+ * as the range [index, index + numObjects).
+ *
+ * If index + numObjects is greater than the maxObjects value used
+ * to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned.
+ *
+ * If 'numObjects and 'index' overlap with a prior call, the newer call's RM object
+ * handles will overwrite the previously exported handles from the previous call.
+ * This overlapping behavior can also be used to unexport a handle by setting
+ * the appropriate object in 'objects' to 0.
+ *
+ *  fd
+ *    A file descriptor. If -1, a new FD will be created.
+ *
+ *  hDevice
+ *    The owning device of the objects to be exported (must be the same for
+ *    all objects).
+ *
+ *  maxObjects
+ *    The total number of objects that the client wishes to export to the FD.
+ *    This parameter will be honored only when the FD is getting created.
+ *
+ *  metadata
+ *    A buffer for clients to write some metadata to and pass to the importing
+ *    client. This parameter will be honored only when the FD is getting
+ *    created.
+ *
+ *  objects
+ *    Array of RM object handles to export to the fd.
+ *
+ *  numObjects
+ *    The number of handles the user wishes to export in this call.
+ *
+ *  index
+ *    The index into the export fd at which to start exporting the handles in
+ *    'objects' (for use in iterative calls).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OUT_OF_RANGE
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ */
+#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD         (0x3d0b) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS 512
+
+#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS {
+    NvS32    fd;                                                               /* IN/OUT */
+    NvHandle hDevice;                                                       /* IN */
+    NvU16    maxObjects;                                                       /* IN */
+    NvU8     metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE];             /* IN */
+    NvHandle objects[NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */
+    NvU16    numObjects;                                                       /* IN */
+    NvU16    index;                                                            /* IN */
+} NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS;
+
+/*
+ * NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD
+ *
+ * This command can be used to import back RM handles
+ * that were exported to an fd using the
+ * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD control call.
+ *
+ * If index + numObjects is greater than the maxObjects value used
+ * to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned
+ * and no objects are imported.
+ *
+ * For each valid handle in the 'objects' array parameter at index 'i',
+ * the corresponding object handle at index ('i' + 'index') contained by
+ * the fd will be imported. If the object at index ('i' + 'index') has
+ * not been exported into the fd, no object will be imported.
+ *
+ * If any of handles contained in the 'objects' array parameter are invalid
+ * and the corresponding export object handle is valid,
+ * NV_ERR_INVALID_PARAMETER will be returned and no handles will be imported.
+ *
+ *  fd
+ *    The export fd on which to import handles out of.
+ *
+ *  hParent
+ *    The parent RM handle of which all of the exported objects will
+ *    be duped under.
+ *
+ *  objects
+ *    An array of RM handles. The exported objects will be duped under
+ *    these handles during the import process.
+ *
+ * objectTypes
+ *    An array of RM handle types. The type _NONE will be returned if
+ *    the object was not imported. Other possible object types are
+ *    mentioned below.
+ *
+ *  numObjects
+ *    The number of valid object handles in the 'objects' array. This should
+ *    be set to the number of objects that the client wishes to import.
+ *
+ *  index
+ *    The index into the fd in which to start importing from. For
+ *    use in iterative calls.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OUT_OF_RANGE
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_PARAMETER
+ */
+#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD       (0x3d0c) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID" */
+
+//
+// TODO Bump this back up to 512 after the FLA revamp is complete
+//
+#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS 128
+
+#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE      0
+#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM    1
+#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM    2
+#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC    3
+
+
+
+#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS {
+    NvS32    fd;                                                                   /* IN  */
+    NvHandle hParent;                                                           /* IN  */
+    NvHandle objects[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS];     /* IN  */
+    NvU8     objectTypes[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS];     /* OUT */
+    NvU16    numObjects;                                                           /* IN  */
+    NvU16    index;                                                                /* IN  */
+} NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS;
+
+/* _ctrl0000unix_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
new file mode 100644
index 0000000..671c1a3
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
@@ -0,0 +1,78 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn
+//
+
+#include "ctrl/ctrl0000/ctrl0000base.h"
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrla081.h"
+#include "class/cl0000.h"
+#include "nv_vgpu_types.h"
+/*
+ * NV0000_CTRL_CMD_VGPU_GET_START_DATA
+ *
+ * This command gets data associated with NV0000_NOTIFIERS_VGPU_MGR_START to
+ * start VGPU process.
+ *
+ *   mdevUuid
+ *     This parameter gives mdev device UUID for which nvidia-vgpu-mgr should
+ *     init process.
+ *
+ *   qemuPid
+ *     This parameter specifies the QEMU process ID of the VM.
+ *
+ *   gpuPciId
+ *     This parameter provides gpuId of GPU on which vgpu device is created.
+ *
+ *   configParams
+ *     This parameter specifies the configuration parameters for vGPU
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_EVENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_INVALID_CLIENT
+ *
+ */
+#define NV0000_CTRL_CMD_VGPU_GET_START_DATA (0xc01) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0000_CTRL_VGPU_GET_START_DATA_PARAMS {
+    NvU8  mdevUuid[VM_UUID_SIZE];
+    NvU8  configParams[1024];
+    NvU32 qemuPid;
+    NvU32 gpuPciId;
+    NvU16 vgpuId;
+    NvU32 gpuPciBdf;
+} NV0000_CTRL_VGPU_GET_START_DATA_PARAMS;
+
+/* _ctrl0000vgpu_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0002.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0002.h
new file mode 100644
index 0000000..046c931
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0002.h
@@ -0,0 +1,178 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0002.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#define NV0002_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x0002, NV0002_CTRL_##cat, idx)
+
+/* Client command categories (6bits) */
+#define NV0002_CTRL_RESERVED (0x00)
+#define NV0002_CTRL_DMA      (0x01)
+
+
+/*
+ * NV0002_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ */
+
+#define NV0002_CTRL_CMD_NULL (0x20000) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+/*
+ * NV0002_CTRL_CMD_UPDATE_CONTEXTDMA
+ *
+ * This command will update the parameters of the specified context dma.  The
+ * context dma must be bound to a display channel.  The update is limited
+ * to the display view of the context dma. Other use cases will continue to
+ * use the original allocation parameters.
+ *
+ * This is used on platforms where memory may be moved by the operating
+ * system after allocation.
+ *
+ * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag.
+ *
+ *   baseAddress
+ *     This parameter, if selected by flags, indicates the new baseAddress for
+ *     the ctxdma
+ *   limit
+ *     This parameter, if selected by flags, indicates the new limit of the
+ *     ctxdma.
+ *   hCtxDma
+ *     ContextDma handle on which to operate. Must match the handle given to the control
+ *     call.
+ *   hChannel
+ *     Display channel handle.  This field is ignored.
+ *   hintHandle
+ *     Hint value returned from HeapAllocHint which encodes information about
+ *     the surface.  This is used by chips without generic kind.  Newer chips
+ *     use the COMPR_INFO flag and the hintHandle must be zero.
+ *   flags
+ *     This parameter specifies flags which indicate which other parameters are
+ *     valid.
+ *       FLAGS_PAGESIZE updates the context DMA pagesize field, if not _DEFAULT
+ *       FLAGS_USE_COMPR_INFO uses the surface format specified in the params, instead of hintHandle.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_OBJECT
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NVOS_STATUS_NOT_SUPPORTED
+ */
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA (0x20101) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS_MESSAGE_ID" */
+
+#define NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 baseAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 limit, 8);
+    NvHandle hSubDevice;
+    NvHandle hCtxDma;
+    NvHandle hChannel;
+    NvHandle hintHandle;
+    NvU32    flags;
+} NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS;
+
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS                        0:0
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS_INVALID                (0x00000000)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS_VALID                  (0x00000001)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT                              1:1
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT_INVALID                      (0x00000000)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT_VALID                        (0x00000001)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT                               2:2
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT_INVALID                       (0x00000000)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT_VALID                         (0x00000001)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE                           4:3
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_DEFAULT                   (0x00000000)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_4K                        (0x00000001)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_BIG                       (0x00000002)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO                     6:5
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_NONE                (0x00000000)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_FORMAT_PITCH        (0x00000001)
+#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_FORMAT_BLOCK_LINEAR (0x00000002)
+
+/*
+ * NV0002_CTRL_CMD_BIND_CONTEXTDMA
+ *
+ * Bind a context dma to a display channel.  Binding is no longer required for
+ * Host channels, but does silently succeed.
+ *
+ * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag.
+ *
+ * This control replaces the obsolete RmBindContextDma() API.
+ *
+ * hChannel
+ *     The channel for ctxdma bind
+ *
+ * Possible error codes include
+ *   NV_OK
+ *   NV_ERR_TOO_MANY_PRIMARIES          hash table is full
+ *   NV_ERR_NO_MEMORY                   instance memory is full
+ *   NV_ERR_INVALID_OFFSET              surface is not correctly aligned
+ *   NV_ERR_STATE_IN_USE                context dma was already bound given channel
+ */
+#define NV0002_CTRL_CMD_BIND_CONTEXTDMA                                            (0x20102) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_BIND_CONTEXTDMA_PARAMS_MESSAGE_ID" */
+
+#define NV0002_CTRL_BIND_CONTEXTDMA_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0002_CTRL_BIND_CONTEXTDMA_PARAMS {
+    NvHandle hChannel;
+} NV0002_CTRL_BIND_CONTEXTDMA_PARAMS;
+
+/*
+ * NV0002_CTRL_CMD_UNBIND_CONTEXTDMA
+ *
+ * Unbind a context dma from a display channel.
+ *
+ * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag.
+ *
+ * hChannel
+ *     The display channel to unbind from
+ *
+ * Possible error codes include
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE               channel was not bound
+ */
+#define NV0002_CTRL_CMD_UNBIND_CONTEXTDMA (0x20103) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS_MESSAGE_ID" */
+
+#define NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS {
+    NvHandle hChannel;
+} NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS;
+
+/* _ctrl0002.h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0004.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0004.h
new file mode 100644
index 0000000..91431ce
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0004.h
@@ -0,0 +1,93 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0004.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV01_TIMER control commands and parameters */
+
+#define NV0004_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x0004, NV0004_CTRL_##cat, idx)
+
+/* NV01_TIMER command categories (8bits) */
+#define NV0004_CTRL_RESERVED (0x00)
+#define NV0004_CTRL_TMR      (0x01)
+
+/*
+ * NV0004_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0004_CTRL_CMD_NULL (0x40000) /* finn: Evaluated from "(FINN_NV01_TIMER_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+ * NV0004_CTRL_CMD_TMR_SET_ALARM_NOTIFY
+ *
+ * This command can be used to set a PTIMER alarm to trigger at the
+ * specified time in the future on the subdevice associated with this
+ * NV01_TIMER object instance.
+ *
+ *   hEvent
+ *     This parameter specifies the handle of an NV01_EVENT object instance
+ *     that is to be signaled when the alarm triggers.  This NV01_EVENT
+ *     object instance must have been allocated with this NV01_TIMER object
+ *     instance as its parent.  If this parameter is set to NV01_NULL_OBJECT
+ *     then all NV01_EVENT object instances associated with this NV01_TIMER
+ *     object instance are signaled.
+ *   alarmTimeUsecs
+ *     This parameter specifies the relative time in nanoseconds at which
+ *     the alarm should trigger.  Note that the accuracy between the alarm
+ *     trigger and the subsequent notification to the caller can vary
+ *     depending on system conditions.
+ *
+ * Possible status values returned include:
+ *   NVOS_STATUS_SUCCES
+ *   NVOS_STATUS_INVALID_PARAM_STRUCT
+ *   NVOS_STATUS_INVALID_OBJECT_HANDLE
+ */
+
+#define NV0004_CTRL_CMD_TMR_SET_ALARM_NOTIFY (0x40110) /* finn: Evaluated from "(FINN_NV01_TIMER_TMR_INTERFACE_ID << 8) | NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS_MESSAGE_ID" */
+
+#define NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS {
+    NvHandle hEvent;
+    NV_DECLARE_ALIGNED(NvU64 alarmTimeNsecs, 8);
+} NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS;
+
+/* _ctrl0004_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl000f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl000f.h
new file mode 100644
index 0000000..ecabf33
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl000f.h
@@ -0,0 +1,85 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl000f.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+
+#define NV000F_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x000f, NV000F_CTRL_##cat, idx)
+
+/* Client command categories (6bits) */
+#define NV000F_CTRL_RESERVED  (0x00U)
+#define NV000F_CTRL_FM        (0x01U)
+#define NV000F_CTRL_RESERVED2 (0x02U)
+
+/*
+ * NV000f_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ */
+#define NV000F_CTRL_CMD_NULL  (0xf0000U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+/*
+ * NV000F_CTRL_CMD_SET_FM_STATE
+ *
+ * This command will notify RM that the fabric manager is initialized.
+ *
+ * RM would block P2P operations such as P2P capability reporting, NV50_P2P object
+ * allocation etc. until the notification received.
+ *
+ * Possible status values returned are:
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_OBJECT_NOT_FOUND
+ *    NV_ERR_NOT_SUPPORTED
+ *    NV_OK
+ */
+#define NV000F_CTRL_CMD_SET_FM_STATE   (0xf0101U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID << 8) | 0x1" */
+
+/*
+ * NV000F_CTRL_CMD_CLEAR_FM_STATE
+ *
+ * This command will notify RM that the fabric manager is uninitialized.
+ *
+ * RM would block P2P operations such as P2P capability reporting, NV50_P2P object
+ * allocation etc. as soon as the notification received.
+ *
+ * Possible status values returned are:
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_OBJECT_NOT_FOUND
+ *    NV_ERR_NOT_SUPPORTED
+ *    NV_OK
+ */
+#define NV000F_CTRL_CMD_CLEAR_FM_STATE (0xf0102U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID << 8) | 0x2" */
+
+/* _ctrl000f.h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0020.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0020.h
new file mode 100644
index 0000000..60f6684
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0020.h
@@ -0,0 +1,80 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0020.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#define NV0020_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0x0020, NV0020_CTRL_##cat, idx)
+
+/* NV0020_GPU_MANAGEMENT command categories (6bits) */
+#define NV0020_CTRL_RESERVED      (0x00)
+#define NV0020_CTRL_GPU_MGMT      (0x01)
+
+/*
+ * NV0020_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0020_CTRL_CMD_NULL      (0x200000) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* Maximum possible number of bytes of GID information */
+#define NV0020_GPU_MAX_GID_LENGTH (0x00000100)
+
+/*
+ * NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE
+ *
+ * This command modifies GPU zero power state for the desired GPU in the
+ * database. This state is set by a privileged client, after the GPU is
+ * completely unregistered from RM as well as PCI subsystem. On Linux,
+ * clients perform this operation through pci-sysfs.
+ * This control call requires admin privileges.
+ *
+ *   uuid (INPUT)
+ *     The UUID of the gpu.
+ *     Supports binary format and SHA-1 type.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE (0x200101) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID << 8) | NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS {
+    NvU8 uuid[NV0020_GPU_MAX_GID_LENGTH];
+} NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS;
+
+/* _ctrl0020_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl003e.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl003e.h
new file mode 100644
index 0000000..880fcc8
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl003e.h
@@ -0,0 +1,191 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl003e.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV01_MEMORY_SYSTEM control commands and parameters */
+
+#define NV003E_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x003E, NV003E_CTRL_##cat, idx)
+
+/* NV01_MEMORY_SYSTEM command categories (6bits) */
+#define NV003E_CTRL_RESERVED (0x00)
+#define NV003E_CTRL_MEMORY   (0x01)
+
+/*
+ * NV003E_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV003E_CTRL_CMD_NULL (0x3e0000) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+ * NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR
+ *
+ * This command returns attributes associated with the memory object
+ * at the given offset. The architecture dependent return parameter
+ * comprFormat determines the meaningfulness (or not) of comprOffset.
+ *
+ * This call is currently only supported in the MODS environment.
+ *
+ *   memOffset
+ *     This parameter is both an input and an output. As input, this
+ *     parameter holds an offset into the memory surface. The return
+ *     value is the physical address of the surface at the given offset.
+ *   memFormat
+ *     This parameter returns the memory kind of the surface.
+ *   comprOffset
+ *     This parameter returns the compression offset of the surface.
+ *   comprFormat
+ *     This parameter returns the type of compression of the surface.
+ *   gpuCacheAttr
+ *     gpuCacheAttr returns the gpu cache attribute of the surface.
+ *     Legal return values for this field are
+ *       NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
+ *       NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
+ *       NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
+ *   gpuP2PCacheAttr
+ *     gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface.
+ *     Legal return values for this field are
+ *       NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
+ *       NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
+ *       NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
+ *   mmuContext
+ *     mmuContext returns the requested type of physical address
+ *     Legal return values for this field are
+ *       TEGRA_VASPACE_A  --  return the non-GPU device physical address ( the system physical address itself) for Tegra engines.
+ *                            returns the system physical address, may change to use a class value in future.
+ *       FERMI_VASPACE_A  --  return the GPU device physical address( the system physical address, or the SMMU VA) for Big GPU engines.
+ *                     0  --  return the GPU device physical address( the system physical address, or the SMMU VA) for Big GPU engines.
+ *                            use of zero may be deprecated in future.
+ *   contigSegmentSize
+ *     If the underlying surface is physically contiguous, this parameter
+ *     returns the size in bytes of the piece of memory starting from
+ *     the offset specified in the memOffset parameter extending to the last
+ *     byte of the surface.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_BAD_OBJECT_HANDLE
+ *   NVOS_STATUS_BAD_OBJECT_PARENT
+ *   NVOS_STATUS_NOT_SUPPORTED
+ *
+ */
+#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x3e0101) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */
+
+#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 memOffset, 8);
+    NvU32 memFormat;
+    NvU32 comprOffset;
+    NvU32 comprFormat;
+    NvU32 gpuCacheAttr;
+    NvU32 gpuP2PCacheAttr;
+    NvU32 mmuContext;
+    NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8);
+} NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS;
+
+/* valid gpuCacheAttr return values */
+#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000)
+#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED         (0x00000001)
+#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED       (0x00000002)
+
+/* NV003E_CTRL_CMD_GET_SURFACE_NUM_PHYS_PAGES
+ *
+ * This command returns the number of physical pages associated with the
+ * memory object.
+ *
+ * This call is currently only implemented on Linux and assumes that linux
+ * kernel in which RM module will be loaded has same page size as defined
+ * in linux kernel source with which RM module was built.
+ *
+ *   numPages
+ *     This parameter returns total number of physical pages associated with
+ *     the memory object.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV003E_CTRL_CMD_GET_SURFACE_NUM_PHYS_PAGES           (0x3e0102) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS_MESSAGE_ID" */
+
+#define NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS {
+    NvU32 numPages;
+} NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS;
+
+
+/* NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES
+ *
+ * This command returns physical pages associated with the memory object.
+ *
+ * This call is currently only implemented on Linux and assumes that linux
+ * kernel in which RM module will be loaded has same page size as defined
+ * in linux kernel source with which RM module was built.
+ *
+ *   pPages
+ *     This parameter returns physical pages associated with the memory object.
+ *
+ *   numPages
+ *     This parameter is both an input and an output. As an input parameter,
+ *     it's value indicates maximum number of physical pages to be copied to
+ *     pPages. As an output parameter, it's value indicates number of physical
+ *     pages copied to pPages.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES (0x3e0103) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS_MESSAGE_ID" */
+
+#define NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pPages, 8);
+    NvU32 numPages;
+} NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS;
+
+/* _ctrl003e_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0041.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0041.h
new file mode 100644
index 0000000..322393d
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0041.h
@@ -0,0 +1,450 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0041.finn
+//
+
+#include "nvos.h"
+#include "ctrl/ctrlxxxx.h"
+/* NV04_MEMORY control commands and parameters */
+
+#define NV0041_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x0041, NV0041_CTRL_##cat, idx)
+
+/* NV04_MEMORY command categories (6bits) */
+#define NV0041_CTRL_RESERVED (0x00)
+#define NV0041_CTRL_MEMORY   (0x01)
+
+/*
+ * NV0041_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0041_CTRL_CMD_NULL (0x410000) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+/*
+ * NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR
+ *
+ * This command returns attributes associated with the memory object
+ * at the given offset. The architecture dependent return parameter
+ * comprFormat determines the meaningfulness (or not) of comprOffset.
+ *
+ * This call is only currently supported in the MODS environment.
+ *
+ *   memOffset
+ *     This parameter is both an input and an output. As input, this
+ *     parameter holds an offset into the memory surface. The return
+ *     value is the physical address of the surface at the given offset.
+ *   memFormat
+ *     This parameter returns the memory kind of the surface.
+ *   comprOffset
+ *     This parameter returns the compression offset of the surface.
+ *   comprFormat
+ *     This parameter returns the type of compression of the surface.
+ *   memAperture
+ *     The aperture of the surface is returned in this field.
+ *     Legal return values for this parameter are
+ *       NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM
+ *       NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM
+ *   gpuCacheAttr
+ *     gpuCacheAttr returns the gpu cache attribute of the surface.
+ *     Legal return values for this field are
+ *       NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
+ *       NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
+ *       NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
+ *   gpuP2PCacheAttr
+ *     gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface.
+ *     Legal return values for this field are
+ *       NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
+ *       NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
+ *       NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
+ *   mmuContext
+ *     mmuContext indicates the type of physical address to be returned (input parameter).
+ *     Legal return values for this field are
+ *       TEGRA_VASPACE_A  --  return the device physical address for Tegra (non-GPU) engines. This is the system physical address itself.
+ *                            returns the system physical address. This may change to use a class value in future.
+ *       FERMI_VASPACE_A  --  return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address.
+ *                     0  --  return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address.
+ *                            use of zero may be deprecated in future.
+ *   contigSegmentSize
+ *     If the underlying surface is physically contiguous, this parameter
+ *     returns the size in bytes of the piece of memory starting from
+ *     the offset specified in the memOffset parameter extending to the last
+ *     byte of the surface.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_BAD_OBJECT_HANDLE
+ *   NVOS_STATUS_BAD_OBJECT_PARENT
+ *   NVOS_STATUS_NOT_SUPPORTED
+ *
+ */
+#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x410103) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */
+
+#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 memOffset, 8);
+    NvU32 memFormat;
+    NvU32 comprOffset;
+    NvU32 comprFormat;
+    NvU32 memAperture;
+    NvU32 gpuCacheAttr;
+    NvU32 gpuP2PCacheAttr;
+    NvU32 mmuContext;
+    NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8);
+} NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS;
+
+/* valid memAperture return values */
+#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM (0x00000000)
+#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM (0x00000001)
+
+/* valid gpuCacheAttr return values */
+#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN  (0x00000000)
+#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED          (0x00000001)
+#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED        (0x00000002)
+
+/*
+ * NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID
+ *
+ * This command returns the Z-cull identifier for a surface.
+ * The value of ~0 is returned if there is none associated.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_BAD_OBJECT_HANDLE
+ *   NVOS_STATUS_BAD_OBJECT_PARENT
+ *   NVOS_STATUS_NOT_SUPPORTED
+ *
+ */
+#define NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID                  (0x410104) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID" */
+
+#define NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS {
+    NvU32 zcullId;
+} NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS;
+
+
+// return values for 'tilingFormat'
+// XXX - the names for these are misleading
+#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_INVALID   (0x00000000)
+#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB        (0x00000001)
+#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_1HIGH  (0x00000002)
+#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_4HIGH  (0x00000003)
+#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_1HIGH (0x00000004)
+#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_4HIGH (0x00000005)
+
+/*
+ * NV0041_CTRL_SURFACE_INFO
+ *
+ * This structure represents a single 32bit surface value.  Clients
+ * request a particular surface value by specifying a unique surface
+ * information index.
+ *
+ * Legal surface information index values are:
+ *   NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS
+ *     This index is used to request the set of hw attributes associated
+ *     with the surface.  Each distinct attribute is represented by a
+ *     single bit flag in the returned value.
+ *     Legal flags values for this index are:
+ *       NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR
+ *         This surface has compression resources bound to it.
+ *       NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL
+ *         This surface has zcull resources bound to it.
+ *   NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE
+ *     This index is used to request the compression coverage (if any)
+ *     in units of 64K for the associated surface.  A value of zero indicates
+ *     there are no compression resources associated with the surface.
+ *     Legal return values range from zero to a maximum number of 64K units
+ *     that is GPU implementation dependent.
+ *   NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE
+ *     This index is used to request the physically allocated size in units
+ *     of 4K(NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR) for the associated
+ *     surface.
+ *   NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR
+ *     This index is used to request the surface attribute field. The returned
+ *     field value can be decoded using the NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_*
+ *     DRF-style macros provided below.
+ *   NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE
+ *     This index is used to request the surface address space type.
+ *     Returned values are described by NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE.
+ */
+typedef struct NV0041_CTRL_SURFACE_INFO {
+    NvU32 index;
+    NvU32 data;
+} NV0041_CTRL_SURFACE_INFO;
+
+/* valid surface info index values */
+#define NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS                           (0x00000001)
+#define NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE                  (0x00000005)
+#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE                       (0x00000007)
+#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR                       (0x00000008)
+#define NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE                 (0x00000009)
+
+/*
+ * This define indicates the scale factor of the reported physical size to the
+ * actual size in bytes. We use the scale factor to save space from the
+ * interface and account for large surfaces. To get the actual size,
+ * use `(NvU64)reported_size * NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR`.
+ */
+#define NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR                (0x1000)
+
+/* valid surface info attr flags */
+#define NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR                           (0x00000002)
+#define NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL                           (0x00000004)
+
+/* Valid surface info page size */
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE                   NVOS32_ATTR_PAGE_SIZE
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_DEFAULT           NVOS32_ATTR_PAGE_SIZE_DEFAULT
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_4KB               NVOS32_ATTR_PAGE_SIZE_4KB
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_BIG               NVOS32_ATTR_PAGE_SIZE_BIG
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_HUGE              NVOS32_ATTR_PAGE_SIZE_HUGE
+
+/* Valid surface info CPU coherency */
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY               NVOS32_ATTR_COHERENCY
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_UNCACHED      NVOS32_ATTR_COHERENCY_UNCACHED
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_CACHED        NVOS32_ATTR_COHERENCY_CACHED
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_COMBINE NVOS32_ATTR_COHERENCY_WRITE_COMBINE
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_THROUGH NVOS32_ATTR_COHERENCY_WRITE_THROUGH
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_PROTECT NVOS32_ATTR_COHERENCY_WRITE_PROTECT
+#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_BACK    NVOS32_ATTR_COHERENCY_WRITE_BACK
+
+/*
+ * NV0041_CTRL_CMD_GET_SURFACE_INFO
+ *
+ * This command returns surface information for the associated memory object.
+ * Requests to retrieve surface information use a list of one or more
+ * NV0041_CTRL_SURFACE_INFO structures.
+ *
+ *   surfaceInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     surfaceInfoList.
+ *   surfaceInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the surface information is to be returned.
+ *     This buffer must be at least as big as surfaceInfoListSize multiplied
+ *     by the size of the NV0041_CTRL_SURFACE_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV0041_CTRL_CMD_GET_SURFACE_INFO                               (0x410110) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV0041_CTRL_GET_SURFACE_INFO_PARAMS {
+    NvU32 surfaceInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 surfaceInfoList, 8);
+} NV0041_CTRL_GET_SURFACE_INFO_PARAMS;
+
+/*
+ * NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE
+ *
+ * This command returns the percentage of surface compression tag coverage.
+ * The value of 0 is returned if there are no tags associated.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_BAD_OBJECT_HANDLE
+ *   NVOS_STATUS_BAD_OBJECT_PARENT
+ *   NVOS_STATUS_NOT_SUPPORTED
+ *
+ */
+#define NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE (0x410112) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID" */
+
+#define NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS {
+    NvHandle hSubDevice; /* if non zero subDevice handle of local GPU */
+    NvU32    lineMin;
+    NvU32    lineMax;
+    NvU32    format;
+} NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS;
+
+/*
+ * NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR
+ *
+ * This command returns the BAR1 physical address of a
+ * Memory mapping made using NvRmMapMemory()
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_INVALID_DATA
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *
+ */
+#define NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR (0x410114) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID" */
+
+#define NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pLinearAddress, 8);  /* [in] Linear address of CPU mapping */
+    NV_DECLARE_ALIGNED(NvU64 busAddress, 8);  /* [out] BAR1 address */
+} NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS;
+
+/*
+ * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
+ * 
+ * This command flushes a cache on the GPU which all memory accesses go
+ * through.  The types of flushes supported by this API may not be supported by
+ * all hardware.  Attempting an unsupported flush type will result in an error.
+ *
+ *   flags
+ *     Contains flags to control various aspects of the flush.  Valid values
+ *     are defined in NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS*.  Not all
+ *     flags are valid for all GPUs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NVOS_STATUS_INVALID_ARGUMENT
+ *   NVOS_STATUS_INVALID_STATE
+ *
+ * See Also:
+ *   NV0080_CTRL_CMD_DMA_FLUSH 
+ *     Performs flush operations in broadcast for the GPU cache and other hardware
+ *     engines.  Use this call if you want to flush all GPU caches in a
+ *     broadcast device.
+ *   NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
+ *     Flushes the entire GPU cache or a set of physical addresses (if the
+ *     hardware supports it).  Use this call if you want to flush a set of
+ *     addresses or the entire GPU cache in unicast mode.
+ *
+ */
+#define NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE (0x410116) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
+
+#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS {
+    NvU32 flags;
+} NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS;
+
+#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK                0:0
+#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO  (0x00000000)
+#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001)
+#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE                1:1
+#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO  (0x00000000)
+#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001)
+
+/*
+ * NV0041_CTRL_CMD_GET_EME_PAGE_SIZE
+ *
+ * This command may be used to get the memory page size 
+ *
+ * Parameters:
+ *   pageSize [OUT]
+ *     pageSize with associated memory descriptor
+ *
+ * Possible status values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0041_CTRL_CMD_GET_MEM_PAGE_SIZE                        (0x410118) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS {
+    NvU32 pageSize;             /* [out] - page size */
+} NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS;
+
+/*
+ * NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION
+ *
+ * Acquire/release compression for surface
+ *
+ * Parameters:
+ *   bRelease [IN]
+ *     true = release compression; false = acquire compression
+ */
+#define NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION (0x410119) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID" */
+
+#define NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS {
+    NvBool bRelease;             /* [in] - acquire/release setting */
+} NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS;
+
+#define NV0041_CTRL_CMD_PRINT_LABELS_PARAMS_MESSAGE_ID (0x50U)
+
+typedef struct NV0041_CTRL_CMD_PRINT_LABELS_PARAMS {
+    NvU32 tag; /* [in] */
+} NV0041_CTRL_CMD_PRINT_LABELS_PARAMS;
+#define NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID (0x51U)
+
+typedef struct NV0041_CTRL_CMD_SET_LABEL_PARAMS {
+    NvU32 tag; /* [in] */
+} NV0041_CTRL_CMD_SET_LABEL_PARAMS;
+#define NV0041_CTRL_CMD_SET_LABEL (0x410151) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID" */
+#define NV0041_CTRL_CMD_GET_LABEL (0x410152) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID" */
+#define NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID (0x52U)
+
+typedef struct NV0041_CTRL_CMD_GET_LABEL_PARAMS {
+    NvU32 tag; /* [in] */
+} NV0041_CTRL_CMD_GET_LABEL_PARAMS;
+
+/*
+ * NV0041_CTRL_CMD_SET_TAG
+ *
+ * This command sets memory allocation tag used for debugging.
+* Every client has it's own memory allocation tag and tag is copying when object is duping.
+ * This control can be used for shared allocations to change it's tag.
+ */
+#define NV0041_CTRL_CMD_SET_TAG (0x410120) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID" */
+
+#define NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV0041_CTRL_CMD_SET_TAG_PARAMS {
+    NvU32 tag; /* [in] */
+} NV0041_CTRL_CMD_SET_TAG_PARAMS;
+
+/*
+ * NV0041_CTRL_CMD_GET_TAG
+ *
+ * This command returns memory allocation tag used for debugging.
+ */
+#define NV0041_CTRL_CMD_GET_TAG (0x410121) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID" */
+
+#define NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV0041_CTRL_CMD_GET_TAG_PARAMS {
+    NvU32 tag; /* [out] */
+} NV0041_CTRL_CMD_GET_TAG_PARAMS;
+
+/* _ctrl0041_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073.h
new file mode 100644
index 0000000..fa7d8f7
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073.h
@@ -0,0 +1,45 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2015,2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073.finn
+//
+
+
+
+
+#include "ctrl/ctrlxxxx.h"
+/* category-specific includes */
+#include "ctrl0073/ctrl0073system.h"
+#include "ctrl0073/ctrl0073specific.h"
+#include "ctrl0073/ctrl0073stereo.h"
+#include "ctrl0073/ctrl0073event.h"
+#include "ctrl0073/ctrl0073internal.h"
+#include "ctrl0073/ctrl0073dfp.h"
+#include "ctrl0073/ctrl0073dp.h"
+#include "ctrl0073/ctrl0073svp.h"
+#include "ctrl0073/ctrl0073dpu.h"
+#include "ctrl0073/ctrl0073psr.h"
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h
new file mode 100644
index 0000000..970ea3b
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h
@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073base.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV04_DISPLAY_COMMON control commands and parameters */
+
+#define NV0073_CTRL_CMD(cat,idx)                NVXXXX_CTRL_CMD(0x0073, NV0073_CTRL_##cat, idx)
+
+/* NV04_DISPLAY_COMMON command categories (6bits) */
+#define NV0073_CTRL_RESERVED (0x00U)
+#define NV0073_CTRL_SYSTEM   (0x01U)
+#define NV0073_CTRL_SPECIFIC (0x02U)
+#define NV0073_CTRL_EVENT    (0x03U)
+#define NV0073_CTRL_INTERNAL (0x04U)
+#define NV0073_CTRL_DFP      (0x11U)
+#define NV0073_CTRL_DP       (0x13U)
+#define NV0073_CTRL_SVP      (0x14U)
+#define NV0073_CTRL_DPU      (0x15U)
+#define NV0073_CTRL_PSR      (0x16U)
+#define NV0073_CTRL_STEREO   (0x17U)
+
+/*
+ * NV0073_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0073_CTRL_CMD_NULL (0x730000U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* _ctrl0073base_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
new file mode 100644
index 0000000..347b478
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
@@ -0,0 +1,1269 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073dfp.finn
+//
+
+#include "ctrl/ctrl0073/ctrl0073base.h"
+
+/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */
+
+/*
+ * NV0073_CTRL_CMD_DFP_GET_INFO
+ *
+ * This command can be used to determine the associated display type for
+ * the specified displayId.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the dfp
+ *     caps should be returned.  The display ID must be a dfp display
+ *     as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
+ *     If more than one displayId bit is set or the displayId is not a dfp,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   flags
+ *     This parameter returns the information specific to this dfp.  Here are
+ *     the possible fields:
+ *       NV0073_CTRL_DFP_FLAGS_SIGNAL
+ *         This specifies the type of signal used for this dfp.
+ *       NV0073_CTRL_DFP_FLAGS_LANES
+ *         This specifies whether the board supports 1, 2, or 4 lanes
+ *         for DISPLAYPORT signals.
+ *       NV0073_CTRL_DFP_FLAGS_LIMIT
+ *         Some GPUs were not qualified to run internal TMDS except at 60 HZ
+ *         refresh rates.  So, if LIMIT_60HZ_RR is set, then the client must
+ *         make sure to only allow 60 HZ refresh rate modes to the OS/User.
+ *       NV0073_CTRL_DFP_FLAGS_SLI_SCALER
+ *         While running in SLI, if SLI_SCALER_DISABLE is set, the GPU cannot
+ *         scale any resolutions.  So, the output timing must match the
+ *         memory footprint.
+ *       NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE
+ *         This specifies whether the DFP displayId is capable of
+ *         transmitting HDMI.
+ *       NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE
+ *         This specifies whether the displayId is capable of sending a
+ *         limited color range out from the board.
+ *       NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE
+ *         This specifies whether the displayId is capable of auto-configuring
+ *         the color range.
+ *       NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE
+ *         This specifies whether the displayId is capable of sending the
+ *         YCBCR422 color format out from the board.
+ *       NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE
+ *         This specifies whether the displayId is capable of sending
+ *         YCBCR444 color format out from the board.
+ *       NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH
+ *         This specifies whether the displayId is capable of doing high
+ *         bit-rate (2.7Gbps) or low bit-rate (1.62Gbps) if the DFP is
+ *         display port.
+ *       NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED
+ *         This specifies whether the DFP displayId is allowed to transmit HDMI
+ *         based on the VBIOS settings.
+ *       NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT
+ *         This specifies whether the DFP displayId is actually an embedded display
+ *         port based on VBIOS connector information AND ASSR cap.
+ *       NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT
+ *         This specifies whether the DFP displayId must be trained to RBR mode
+ *         (if it is using DP protocol) whenever possible.
+ *       NV0073_CTRL_DFP_FLAGS_LINK
+ *         This specifies whether the board supports single or dual links
+ *         for TMDS, LVDS, and SDI signals.
+ *       NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED
+ *         This specifies if PostCursor2 is disabled in the VBIOS
+ *       NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID
+ *         This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode).
+ *       NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE
+ *         This indicates whether this DFP supports Dynamic MUX
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID (0x40U)
+
+typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 flags;
+} NV0073_CTRL_DFP_GET_INFO_PARAMS;
+
+/* valid display types */
+#define NV0073_CTRL_DFP_FLAGS_SIGNAL                                       2:0
+#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS                    (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS                    (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI                     (0x00000002U)
+#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT             (0x00000003U)
+#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI                     (0x00000004U)
+#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK                    (0x00000005U)
+#define NV0073_CTRL_DFP_FLAGS_LANE                                         5:3
+#define NV0073_CTRL_DFP_FLAGS_LANE_NONE                      (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE                    (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL                      (0x00000002U)
+#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD                      (0x00000003U)
+#define NV0073_CTRL_DFP_FLAGS_LANE_OCT                       (0x00000004U)
+#define NV0073_CTRL_DFP_FLAGS_LIMIT                                        6:6
+#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE                  (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR                  (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER                                   7:7
+#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL              (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE             (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE                                 8:8
+#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE             (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE              (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE                        9:9
+#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE    (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE     (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE                         10:10
+#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE       (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE        (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE                    11:11
+#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE  (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE   (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE                    12:12
+#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE  (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE   (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED                               14:14
+#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE             (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE              (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT                       15:15
+#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE     (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE      (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT                         16:16
+#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE        (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR  (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW                                 19:17
+#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS            (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS            (0x00000002U)
+#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS            (0x00000003U)
+#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS            (0x00000004U)
+#define NV0073_CTRL_DFP_FLAGS_LINK                                       21:20
+#define NV0073_CTRL_DFP_FLAGS_LINK_NONE                      (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE                    (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL                      (0x00000002U)
+#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID                           22:22
+#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE         (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE          (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID                              24:23
+#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE         (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A            (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B            (0x00000002U)
+#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED       (0x00000003U)
+#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED                   25:25
+#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE  (0x00000001U)
+#define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT                      29:26
+#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE                        30:30
+#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE      (0x00000000U)
+#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE       (0x00000001U)
+
+
+
+/*
+ * NV0073_CTRL_CMD_DFP_GET_DP2TMDS_DONGLE_INFO
+ *
+ * This command can be used to determine information about dongles attached
+ * to a displayport connection.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the dfp display which owns the
+ *     panel power to adjust.  The display ID must be a dfp display
+ *     as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
+ *     If more than one displayId bit is set or the displayId is not a dfp,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   flags
+ *     This parameter provide state information about the dongle attachments.
+ *       NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_CAPABLE
+ *         Specifies if the connection is capable of a dongle.  This field
+ *         returns false in all cases of signal types except for those capable
+ *         of outputting TMDS.  Even then the if a gpio is not defined, the
+ *         the a statement of false will also be returned.
+ *       NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_ATTACHED
+ *         When attached, this value specifies that a dongle is detected and
+ *         attached.  The client should read the _TYPE field to determine
+ *         if it is a dp2hdmi or dp2dvi dongle.
+ *      NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_TYPE
+ *         _DP2DVI: no response to i2cAddr 0x80 per DP interop guidelines.
+ *                  clients MUST avoid outputting HDMI even if capable.
+ *         _DP2HDMI: dongle responds to i2cAddr 0x80 per DP interop guidelines.
+ *                   client is allowed to output HDMI when possible.
+ *         _LFH_DVI: DMS59-DVI breakout dongle is in use.
+ *         _LFH_VGA: DMS59-VGA breakout dongle is in use.
+ *      NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE
+ *         _1: Max TMDS Clock rate is 165 MHz for both DVI and HDMI.
+ *         _2: Max TMDS Clock rate will be specified in the dongle
+ *              address space at device address 0x80.
+ *              DVI  is up to 165 MHz
+ *              HDMI is up to 300 MHz
+ *              There are type 2 devices that support beyond 600 MHz
+ *              though not defined in the spec.
+ *   maxTmdsClkRateHz
+ *     This defines the max TMDS clock rate for dual mode adaptor in Hz.
+ */
+#define NV0073_CTRL_CMD_DFP_GET_DISPLAYPORT_DONGLE_INFO (0x731142U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID (0x42U)
+
+typedef struct NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 flags;
+    NvU32 maxTmdsClkRateHz;
+} NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS;
+
+#define  NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE                  0:0
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_FALSE         (0x00000000U)
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_TRUE          (0x00000001U)
+#define  NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED                 1:1
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_FALSE        (0x00000000U)
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_TRUE         (0x00000001U)
+#define  NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE                     7:4
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2DVI           (0x00000000U)
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2HDMI          (0x00000001U)
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_DVI          (0x00000002U)
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_VGA          (0x00000003U)
+#define  NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE      8:8
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_1 (0x00000000U)
+#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_2 (0x00000001U)
+
+
+
+/*
+ * NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS
+ *
+ * This command is used to inform hardware the receiver's audio capabilities
+ * using the new EDID Like Data (ELD) memory structure.  The ELD memory
+ * structure is read by the audio driver by issuing the ELD Data command verb.
+ * This mechanism is used for passing sink device' audio EDID information
+ * from graphics software to audio software.  ELD contents will contain a
+ * subset of the sink device's EDID information.
+ * The client should inform hardware at initial boot, a modeset, and whenever
+ * a hotplug event occurs.
+ *
+ *   displayId
+ *     This parameter indicates the digital display device's
+ *     mask. This comes as input to this command.
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be directed.
+ *     This parameter must specify a value between zero and the total number
+ *     of subdevices within the parent device.  This parameter should be set
+ *     to zero for default behavior.
+ *   numELDSize
+ *     This parameter specifies how many bytes of data RM should write to the
+ *     ELD buffer.  Section 7.3.3.36 of the ECN specifies that the ELD buffer
+ *     size of zero based.  HDAudio driver will then use this information to
+ *     determine how many bytes of the ELD buffer the HDAudio should read.
+ *     The maximum size of the buffer is 96 bytes.
+ *   bufferELD
+ *     This buffer contains data as defined in the ECR HDMI ELD memory structure.
+ *     Refer to the ELD Memory Structure Specification for more details.
+ *     The format should be:
+ *       - Header block is fixed at 4 bytes
+ *         The header block contains the ELD version and baseline ELD len as
+ *         well as some reserved fields.
+ *       - Baseline block for audio descriptors is 76 bytes
+ *         (15 SAD; each SAD=3 bytes requiring 45 bytes with 31 bytes to spare)
+ *         As well as some other bits used to denote the CEA version,
+ *         the speaker allocation data, monitor name, connector type, and
+ *         hdcp capabilities.
+ *       - Vendor specific block of 16 bytes
+ *   maxFreqSupported
+ *     Supply the maximum frequency supported for the overall audio caps.
+ *     This value should match CEA861-X defines for sample freq.
+ *   ctrl:
+ *     NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_PD:
+ *         Specifies the presence detect of the receiver.  On a hotplug
+ *         or modeset client should set this bit to TRUE.
+ *     NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_ELDV:
+ *         Specifies whether the ELD buffer contents are valid.
+ *         An intrinsic unsolicited response (UR) is generated whenever
+ *         the ELDV bit changes in value and the PD=1. When _PD=1(hotplug),
+ *         RM will set the ELDV bit after ELD buffer contents are written.
+ *         If _ELDV bit is set to false such as during a unplug, then the
+ *         contents of the ELD buffer will be cleared.
+ *   deviceEntry:
+ *     The deviceEntry number from which the SF should accept packets.
+ *     _NONE if disabling audio.
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS                         (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER                      96U
+
+#define NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID (0x44U)
+
+typedef struct NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 numELDSize;
+    NvU8  bufferELD[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER];
+    NvU32 maxFreqSupported;
+    NvU32 ctrl;
+    NvU32 deviceEntry;
+} NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS;
+
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0320KHZ (0x00000001U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0441KHZ (0x00000002U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0480KHZ (0x00000003U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0882KHZ (0x00000004U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0960KHZ (0x00000005U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1764KHZ (0x00000006U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1920KHZ (0x00000007U)
+
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD                                     0:0
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_FALSE              (0x00000000U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_TRUE               (0x00000001U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV                                   1:1
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_FALSE            (0x00000000U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_TRUE             (0x00000001U)
+
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_0             (0x00000000U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_1             (0x00000001U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_2             (0x00000002U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3             (0x00000003U)
+#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_NONE          (0x00000007U)
+
+
+
+/*
+ * NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM_STATUS
+ *
+ * This command is used to get spread spectrum status for a display device.
+ *
+ * displayId
+ *    Display ID for which the spread spectrum status is needed.
+ * checkRMSsState
+ *    Default is to check in Vbios. This flag lets this control call to check in register.
+ * status
+ *    Return status value.
+ */
+
+#define NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM (0x73114cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID (0x4CU)
+
+typedef struct NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS {
+    NvU32  displayId;
+    NvBool enabled;
+} NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE
+ *
+ * Update the Dynamic DFP with Bcaps read from remote display.
+ * Also updates hdcpFlags, gpu hdcp capable flags in DFP.
+ * If bResetDfp is true, all the flags are reset before making changes.
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ *     NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE (0x73114eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID (0x4EU)
+
+typedef struct NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  headIndex;
+    NvU8   bcaps;
+    NvU8   bksv[5];
+    NvU32  hdcpFlags;
+    NvBool bHdcpCapable;
+    NvBool bResetDfp;
+    NvU8   updateMask;
+} NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS;
+
+#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BCAPS 0x01U
+#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BKSV  0x02U
+#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_FLAGS 0x03U
+
+/*
+ * NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE
+ *
+ * This command sets the audio enable state of the DFP.  When disabled,
+ * no audio stream packets or audio timestamp packets will be sent.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the dfp
+ *     audio should be enabled or disabled.  The display ID must be a dfp display.
+ *     If the displayId is not a dfp, this call will return
+ *     NV_ERR_INVALID_ARGUMENT.
+ *   enable
+ *     This parameter specifies whether to enable (NV_TRUE) or disable (NV_FALSE)
+ *     audio to the display.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ *
+ */
+#define NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE                (0x731150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID (0x50U)
+
+typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvBool enable;
+} NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG
+ *
+ * This enum defines default/primary/secondary sor sublinks to be configured.
+ * These access modes are:
+ *
+ *  NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE
+ *    Default link config
+ *  NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK
+ *    Primary sor sublink to be configured
+ *  NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK
+ *    Secondary sor sublink to be configured
+ */
+typedef enum NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG {
+    NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE = 0,
+    NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK = 1,
+    NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK = 2,
+} NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG;
+
+/*
+ * NV0073_CTRL_DFP_ASSIGN_SOR_INFO
+ *
+ * This structure describes info about assigned SOR
+ *
+ *   displayMask
+ *     The displayMask for the SOR corresponding to its HW routings
+ *   sorType
+ *     This parameter specifies the SOR type
+ *          Here are the current defined fields:
+ *          NV0073_CTRL_DFP_SOR_TYPE_NONE
+ *              Unallocated SOR
+ *          NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY
+ *              Primary SOR for 2H1OR stream
+ *          NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY
+ *              Secondary SOR for 2H1OR stream
+ *          NV0073_CTRL_DFP_SOR_TYPE_SINGLE
+ *              Default Single SOR
+ * Note - sorType should only be referred to identify 2H1OR Primary and Secondary SOR
+ *
+ */
+
+typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO {
+    NvU32 displayMask;
+    NvU32 sorType;
+} NV0073_CTRL_DFP_ASSIGN_SOR_INFO;
+
+#define NV0073_CTRL_DFP_SOR_TYPE_NONE            (0x00000000U)
+#define NV0073_CTRL_DFP_SOR_TYPE_SINGLE          (0x00000001U)
+#define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY   (0x00000002U)
+#define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY (0x00000003U)
+
+/*
+ *  NV0073_CTRL_CMD_DFP_ASSIGN_SOR
+ *
+ *  This command is used by the clients to assign SOR to DFP for CROSS-BAR
+ *  when the default SOR-DFP routing that comes from vbios is not considered.
+ *  SOR shall be assigned to a DFP at the runtime. This call should be called
+ *  before a modeset is done on any dfp display and also before LinkTraining for DP displays.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     DisplayId of the primary display for which SOR is to be assigned. However, if
+ *     displayId is 0 then RM shall return the XBAR config it has stored in it's structures.
+ *   sorExcludeMask
+ *     sorMask of the SORs which should not be used for assignment. If this is 0,
+ *     then SW is free to allocate any available SOR.
+ *   slaveDisplayId
+ *      displayId of the slave device in case of dualSST mode. This ctrl call will
+ *      allocate SORs to both slave and the master if slaveDisplayId is set.
+ *   forceSublinkConfig
+ *      forces RM to configure primary or secondary sor sublink on the given diaplayId.
+ *      If not set, then RM will do the default configurations.
+ *   bIs2Head1Or
+ *      Specifies that SOR allocation is required for 2 head 1 OR. This will allocate
+ *      2 SOR for same displayId - one Master and one Slave. Slave SOR would be disconnected
+ *      from any padlink and get feedback clock from Master SOR's padlink.
+ *   sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]
+ *       returns the displayMask for all SORs corresponding to their HW routings.
+ *   sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]
+ *       returns the displayMask for all SORs corresponding to their HW routings along with
+ *       SOR type to identify 2H1OR Primary and Secondary SORs. SOR type would be identified by
+ *       NV0073_CTRL_DFP_SOR_TYPE. sorAssignList would look as below -
+ *       sorAssignListWithTag[] = { DisplayMask, SOR Type
+ *                                 {0x100,       SECONDARY_SOR}
+ *                                 {0x200,       SINGLE_SOR}
+ *                                 {0x100,       PRIMARY_SOR}
+ *                                 {0,           NONE}}
+ *                                }
+ *       Here, for display id = 0x100, SOR2 is Primary and SOR0 is Secondary.
+ *       Note - sorAssignList parameter would be removed after Bug 200749158 is resolved
+ *   reservedSorMask
+ *       returns the sorMask reserved for the internal panels.
+ *   flags
+ *       Other detail settings.
+ *           _AUDIO_OPTIMAL: Client requests trying to get audio SOR if possible.
+ *                           If there's no audio capable SOR and OD is HDMI/DP,
+ *                           RM will fail the control call.
+ *           _AUDIO_DEFAULT: RM does not check audio-capability of SOR.
+ *
+ *           _ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES : RM returns Active SOR which is not Audio capable.
+ *           _ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO  : RM is not returning 'Active non-audio capable SOR'.
+ *
+ *  Possible status values returned are: 
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+
+#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR           (0x731152U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS  4U
+
+#define NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID (0x52U)
+
+typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS {
+    NvU32                                 subDeviceInstance;
+    NvU32                                 displayId;
+    NvU8                                  sorExcludeMask;
+    NvU32                                 slaveDisplayId;
+    NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG forceSublinkConfig;
+    NvBool                                bIs2Head1Or;
+    NvU32                                 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS];
+    NV0073_CTRL_DFP_ASSIGN_SOR_INFO       sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS];
+    NvU8                                  reservedSorMask;
+    NvU32                                 flags;
+} NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS;
+
+#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO                                      0:0
+#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_OPTIMAL                    (0x00000001U)
+#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_DEFAULT                    (0x00000000U)
+#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE               1:1
+#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO  (0x00000000U)
+#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES (0x00000001U)
+
+/*
+*  NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK
+*
+*  This command will only be used by chipTB tests to get the padlinks corresponding
+*  to the given displayId. RM gets this information from vbios. This control call is
+*  only for verif purpose.
+*
+*   subDeviceInstance
+*     This parameter specifies the subdevice instance within the
+*     NV04_DISPLAY_COMMON parent device to which the operation should be
+*     directed. This parameter must specify a value between zero and the
+*     total number of subdevices within the parent device.  This parameter
+*     should be set to zero for default behavior.
+*   displayId
+*     DisplayId of the display for which the client needs analog link Mask
+*   padlinkMask
+*     analogLinkMask for the given displayId. This value returned is 0xffffffff if
+*     the given displayId is invalid else RM returns the corresponding padlinkMask.
+*   NV_OK
+*   NV_ERR_INVALID_ARGUMENT
+*   NV_ERR_NOT_SUPPORTED
+*/
+
+
+#define NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK                              (0x731153U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID (0x53U)
+
+typedef struct NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 padlinkMask;
+} NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE
+ *      This enum defines the functions that are supported for which a
+ *      corresponding GPIO pin number could be retrieved
+ *      Values copied from objgpio.h GPIO_FUNC_TYPE_LCD_*. Please keep the
+ *      values in sync between the 2 files
+ */
+
+typedef enum NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE {
+    // GPIO types of LCD GPIO functions common to all internal panels
+    NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BACKLIGHT = 268435456,
+    NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER = 285212672,
+    NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER_OK = 301989888,
+    NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_SELF_TEST = 318767104,
+    NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_LAMP_STATUS = 335544320,
+    NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BRIGHTNESS = 352321536,
+} NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE;
+
+/*
+ * NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM
+ *
+ * This command can be used to get the GPIO pin number that corresponds to one
+ * of the LCD functions
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the dfp display.
+ *     If more than one displayId bit is set or the displayId is not a dfp,
+ *     this call will return NVOS_STATUS_ERROR_INVALID_ARGUMENT.
+ *   funcType
+ *      The LDC function for which the GPIO pin number is needed
+ *   lcdGpioPinNum
+ *     The GPIO pin number that corresponds to the LCD function.
+ *
+*/
+#define NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM (0x731154U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID (0x54U)
+
+typedef struct NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS {
+    NvU32                                  subDeviceInstance;
+    NvU32                                  displayId;
+    NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE funcType;
+    NvU32                                  lcdGpioPinNum;
+} NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS;
+
+
+
+/*
+ *  NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR
+ *
+ *  This command is used for configuration of 2 head 1 OR.
+ *
+ *   subDeviceInstance
+ *      This parameter specifies the subdevice instance within the
+ *      NV04_DISPLAY_COMMON parent device to which the operation should be
+ *      directed. This parameter must specify a value between zero and the
+ *      total number of subdevices within the parent device.  This parameter
+ *      should be set to zero for default behavior.
+ *   displayId
+ *      Display Id of the panel for which Two Head One OR is going to be used
+ *   bEnable
+ *      Enable/Disable 2 Head 1 OR
+ *   masterSorIdx
+ *      Master SOR Index which will send pixels to panel
+ *   slaveSorIdx
+ *      Slave SOR Index which will take feedback clock from Master SOR's
+ *      padlink
+ *  Possible status values returned are:
+ *   NVOS_STATUS_SUCCESS
+ *   NVOS_STATUS_ERROR_INVALID_ARGUMENT
+ *   NVOS_STATUS_ERROR_NOT_SUPPORTED
+ */
+
+
+#define NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR (0x731156U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID (0x56U)
+
+typedef struct NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvBool bEnable;
+    NvU32  masterSorIdx;
+    NvU32  slaveSorIdx;
+} NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS;
+
+/*
+ *  NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL
+ *
+ *  This command is used to enable/disable CRC on the GPU or query the registers
+ *  related to it
+ *
+ *   subDeviceInstance
+ *      This parameter specifies the subdevice instance within the
+ *      NV04_DISPLAY_COMMON parent device to which the operation should be
+ *      directed. This parameter must specify a value between zero and the
+ *      total number of subdevices within the parent device.  This parameter
+ *      should be set to zero for default behavior.
+ *   headIndex
+ *      index of the head
+ *   cmd
+ *      specifying if setup or querying is done
+ *   bEnable
+ *      enable or disable CRC on the GPU
+ *   gpuCrc0
+ *      0-indexed CRC register of the GPU
+ *   gpuCrc1
+ *      1-indexed CRC register of the GPU
+ *   gpuCrc0
+ *      2-indexed CRC register of the GPU
+ *  Possible status values returned are:
+ *   NVOS_STATUS_SUCCESS
+ *   NVOS_STATUS_ERROR_NOT_SUPPORTED
+ */
+
+
+#define NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL (0x731157U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID (0x57U)
+
+typedef struct NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  headIndex;
+    NvU32  cmd;
+    NvBool bEnable;
+    NvU16  gpuCrc0;
+    NvU16  gpuCrc1;
+    NvU16  gpuCrc2;
+} NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS;
+
+#define NV0073_CTRL_DP_CRC_CONTROL_CMD                                     0:0
+#define NV0073_CTRL_DP_CRC_CONTROL_CMD_SETUP (0x00000000U)
+#define NV0073_CTRL_DP_CRC_CONTROL_CMD_QUERY (0x00000001U)
+
+/*
+ * NV0073_CTRL_CMD_DFP_INIT_MUX_DATA
+ *
+ * This control call is used to configure the display MUX related data
+ * for the given display device. Clients to RM are expected to call this
+ * control call to initialize the data related to MUX before any MUX related
+ * operations such mux switch or PSR entry/ exit are performed.
+ *
+ *   subDeviceInstance (in)
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   displayId (in)
+ *     ID of the display device for which the mux state has to be initialized
+ *   manfId (in)
+ *     Specifies the manufacturer ID of panel obtained from the EDID. This
+ *     parameter is expected to be non-zero only in case of internal panel.
+ *   productId (in)
+ *     Specifies the product ID of panel obtained from the EDID. This
+ *     parameter is expected to be non-zero only in case of internal panel.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA    (0x731158U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID (0x58U)
+
+typedef struct NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU16 manfId;
+    NvU16 productId;
+} NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX
+ *
+ * This command is used to switch the dynamic display mux between
+ * integrated GPU and discrete GPU.
+ *
+ *   subDeviceInstance (in)
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   displayId (in)
+ *     ID of the display device for which the display MUX has to be switched
+ *   flags (in)
+ *     Flags indicating the action to be performed. Here are the possible
+ *     valid values-
+ *       NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU
+ *         When set mux is switched from integrated to discrete GPU.
+ *       NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU
+ *         When set mux is switched from discrete to integrated GPU.
+ *       NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS
+ *         Set to true for PSR panels as we skip sideband access.
+ *   auxSettleDelay (in)
+ *     Time, in milliseconds, necessary for AUX channel to settle and become
+ *     accessible after a mux switch. Set to zero to use the default delay.
+ *   muxSwitchLatencyMs (out)
+ *     mux switch latency stats in milli-seconds
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX                   (0x731160U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID (0x60U)
+
+typedef struct NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 flags;
+    NvU32 auxSettleDelay;
+    NvU32 muxSwitchLatencyMs;
+} NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS;
+
+/* valid flags*/
+#define NV0073_CTRL_DFP_DISP_MUX_SWITCH                            0:0
+#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU               0x00000000
+#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU               0x00000001
+#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS       1:1
+#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_YES   0x00000001
+#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_NO    0x00000000
+
+/*
+ * NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS
+ *
+ * This command is used to perform all the operations that need to be
+ * performed before a mux switch is started.
+ *
+ *   subDeviceInstance (in)
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   displayId (in)
+ *     ID of the display device for which the pre mux switch operations have
+ *     to be performed.
+ *   flags (in)
+ *     Flags indicating the action to be performed. Here are the possible
+ *     valid values -
+ *       NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU
+ *         Indicates a switch from i to d is initiated
+ *       NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU
+ *         Indicates a switch from d to i is initiated
+ *       NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO
+ *         When set RM will execute the PSR enter sequence. By default RM will
+ *         not skip SR enter sequence
+ *       NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES
+ *         When set RM will skip the PSR enter sequence
+ *   iGpuBrightness (in)
+ *     iGPU brightness value (scale 0~100) before switching mux from I2D.
+ *     This is used to match brightness after switching mux to dGPU
+ *   preOpsLatencyMs (out)
+ *     premux switch operations latency stats in milli-seconds. This includes -
+ *      - disabling SOR sequencer and enable BL GPIO control
+ *      - toggling LCD VDD, BL EN and PWM MUX GPIOs
+ *      - PSR entry, if not skipped
+ *   psrEntryLatencyMs (out)
+ *     psr entry latency stats in milli-seconds
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS (0x731161U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x61U)
+
+typedef struct NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 flags;
+    NvU32 iGpuBrightness;
+    NvU32 preOpsLatencyMs;
+    NvU32 psrEntryLatencyMs;
+} NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS;
+
+/* valid flags*/
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE                   0:0
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU             0x00000000U
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU             0x00000001U
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP                 1:1
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO                     0x00000000U
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES                    0x00000001U
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING  2:2
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN   0x00000000
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN 0x00000001
+
+#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MIN                       0U
+#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MAX                       100U
+
+/*
+ * NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS
+ *
+ * This command is used to perform all the operations that need to be
+ * performed after a successful mux switch is completed.
+ *
+ *   subDeviceInstance (in)
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   displayId (in)
+ *     ID of the display device for which the post mux switch operations have
+ *     to be performed.
+ *   flags (in)
+ *     Flags indicating the action to be performed. Here are the possible
+ *     valid values -
+ *       NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU
+ *         Indicates a switch from i to d is initiated
+ *       NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU
+ *         Indicates a switch from d to i is initiated
+ *       NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO
+ *         When set RM will execute the PSR exit sequence. By default RM will
+ *         not skip SR exit sequence
+ *       NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES
+ *         When set RM will skip the PSR exit sequence
+ *       NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN
+ *         Indicates mux switches where we know when igpu powers up
+ *       NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN
+ *         Indicates mux switches where we don't know when igpu powers up
+ *   postOpsLatencyMs (out)
+ *     postmux switch operations latency stats in milli-seconds. This includes -
+  *     - restoring SOR sequencer and BL GPIO control
+ *      - toggling LCD VDD, BL EN and PWM MUX GPIOs
+ *      - PSR exit, if not skipped
+ *   psrExitLatencyMs (out)
+ *     psr exit latency stats in milli-seconds
+ *   psrExitTransitionToInactiveLatencyMs (out)
+ *     psr exit latency stats in milli-seconds, from state 2 (SR active) to state 4 (transition to inactive)
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_TIMEOUT in case of SR exit failure
+ */
+
+#define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS                    (0x731162U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x62U)
+
+typedef struct NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 flags;
+    NvU32 postOpsLatencyMs;
+    NvU32 psrExitLatencyMs;
+    NvU32 psrExitTransitionToInactiveLatencyMs;
+} NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS;
+
+/* valid flags*/
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE                   0:0
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP                  1:1
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO  0x00000000U
+#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES 0x00000001U
+
+/*
+ * NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS
+ *
+ * This command is used to query the display mux status for the given
+ * display device
+ *
+ *   subDeviceInstance (in)
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   displayId (in)
+ *     ID of the display device for which the post mux switch operations have
+ *     to be performed.
+ *   muxStatus (out)
+ *     status indicating the current state of the mux.
+ *     valid values -
+ *       NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU
+ *         Indicates that the MUX is currently switched to integrated GPU.
+ *       NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU
+ *         Indicates that the MUX is currently switched to discrete GPU.
+ *       NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY
+ *         Indicates that the MUX mode is set to discrete mode, where all displays
+ *         are driven by discrete GPU.
+ *       NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY
+ *         Indicates that the MUX mode is set to integrated mode, where all
+ *         displays are driven by Integrated GPU.
+ *       NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID
+ *         Indicates that the MUX mode is set to hybrid, where internal panel is
+ *         driven by integrated GPU, while external displays might be driven by
+ *         discrete GPU.
+ *       NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC
+ *         Indicates that the MUX mode is dynamic. It is only in this mode, the
+ *         display MUX can be toggled between discrete and hybrid dynamically.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS         (0x731163U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID (0x63U)
+
+typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 muxStatus;
+} NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS;
+
+/* valid flags */
+#define NV0073_CTRL_DFP_DISP_MUX_STATE                        1:0
+#define NV0073_CTRL_DFP_DISP_MUX_STATE_INVALID                  0x00000000U
+#define NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU           0x00000001U
+#define NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU             0x00000002U
+#define NV0073_CTRL_DFP_DISP_MUX_MODE                         4:2
+#define NV0073_CTRL_DFP_DISP_MUX_MODE_INVALID                   0x00000000U
+#define NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY           0x00000001U
+#define NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY             0x00000002U
+#define NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID                    0x00000003U
+#define NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC                   0x00000004U
+
+
+
+/*
+*  NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING
+*
+*  This command can be used to get DSI mode timing parameters.
+*
+*   subDeviceInstance
+*     This parameter specifies the subdevice instance within the
+*     NV04_DISPLAY_COMMON parent device to which the operation should be
+*     directed. This parameter must specify a value between zero and the
+*     total number of subdevices within the parent device.  This parameter
+*     should be set to zero for default behavior.
+*   displayId
+*     This parameter specifies the ID of the display on which the DSI
+*     info will be set. The display ID must be a DSI-capable display.
+*   hActive
+*     This parameter specifies the horizontal length of the active pixel
+*     data in the raster.
+*   vActive
+*     This parameter specifies the vertical lines of the active pixel
+*     data in the raster.
+*   hFrontPorch
+*     This parameter specifies the number of horizontal front porch
+*     blanking pixels in the raster.
+*   vFrontPorch
+*     This parameter specifies the numer of lines of the vertical front
+*     porch in the raster.
+*   hBackPorch
+*     This parameter specifies the number of horizontal back porch
+*     blanking pixels in the raster.
+*   vBackPorch
+*     This parameter specifies the numer of lines of the vertical back
+*     porch in the raster.
+*   hSyncWidth
+*     This parameter specifies the number of horizontal sync pixels in
+*     the raster.
+*   vSyncWidth
+*     This parameter specifies the numer of lines of the vertical sync
+*     in the raster.
+*   bpp
+*     This parameter specifies the depth (Bits per Pixel) of the output
+*     display stream.
+*   refresh
+*     This parameter specifies the refresh rate of the panel (in Hz).
+*   pclkHz
+*     This parameter specifies the pixel clock rate in Hz.
+*   numLanes
+*     Number of DSI data lanes.
+*   dscEnable
+*     Flag to indicate if DSC an be enabled, which in turn indicates if
+*     panel supports DSC.
+*   dscBpp
+*     DSC Bits per pixel
+*   dscNumSlices
+*     Number of slices for DSC.
+*   dscDuaDsc
+*     Flag to indicate if panel supports DSC streams from two DSI
+*     controllers.
+*   dscSliceHeight
+*     Height of DSC slices.
+*   dscBlockPrediction
+*     Flag to indicate if DSC Block Prediction needs to be enabled.
+*   dscDecoderVersionMajor
+*     Major version number of DSC decoder on Panel.
+*   dscDecoderVersionMinor
+*     Minor version number of DSC decoder on Panel.
+*   dscUseCustomPPS
+*     Flag to indicate if Panel uses custom PPS values which deviate from standard values.
+*   dscCustomPPSData
+*     32 bytes of custom PPS data required by Panel.
+*   dscEncoderCaps
+*     Capabilities of DSC encoder in SoC.
+*
+*  Possible status values returned are:
+*   NV_OK
+*   NV_ERR_INVALID_ARGUMENT
+*   NV_ERR_NOT_SUPPORTED
+*/
+
+#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING         (0x731166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT   32U
+
+#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U)
+
+typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvU32  hActive;
+    NvU32  vActive;
+    NvU32  hFrontPorch;
+    NvU32  vFrontPorch;
+    NvU32  hBackPorch;
+    NvU32  vBackPorch;
+    NvU32  hSyncWidth;
+    NvU32  vSyncWidth;
+    NvU32  bpp;
+    NvU32  refresh;
+    NvU32  pclkHz;
+    NvU32  numLanes;
+    NvU32  dscEnable;
+    NvU32  dscBpp;
+    NvU32  dscNumSlices;
+    NvU32  dscDualDsc;
+    NvU32  dscSliceHeight;
+    NvU32  dscBlockPrediction;
+    NvU32  dscDecoderVersionMajor;
+    NvU32  dscDecoderVersionMinor;
+    NvBool dscUseCustomPPS;
+    NvU32  dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT];
+
+    struct {
+        NvBool bDscSupported;
+        NvU32  encoderColorFormatMask;
+        NvU32  lineBufferSizeKB;
+        NvU32  rateBufferSizeKB;
+        NvU32  bitsPerPixelPrecision;
+        NvU32  maxNumHztSlices;
+        NvU32  lineBufferBitDepth;
+    } dscEncoderCaps;
+} NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING
+ *
+ * This control call is used to retrieve the display mode timing info that's
+ * specified for a given DFP from an offline configuration blob (e.g., Device Tree).
+ * This display timing info is intended to replace the timings exposed in a
+ * sink's EDID.
+ *
+ * subDeviceInstance (in)
+ *   This parameter specifies the subdevice instance within the
+ *   NV04_DISPLAY_COMMON parent device to which the operation should be
+ *   directed.
+ * displayId (in)
+ *   ID of the display device for which the timings should be retrieved.
+ * stream (in)
+ *   For MST connectors with static topologies (e.g., DP serializers),
+ *   this parameter further identifies the video stream for which the
+ *   timings should be retrieved.
+ * valid (out)
+ *   Indicates whether a valid display timing was found for this DFP.
+ * hActive (out)
+ *   Horizontal active width in pixels
+ * hFrontPorch (out)
+ *   Horizontal front porch
+ * hSyncWidth (out)
+ *   Horizontal sync width
+ * hBackPorch (out)
+ *   Horizontal back porch
+ * vActive (out)
+ *   Vertical active height in lines
+ * vFrontPorch (out)
+ *   Vertical front porch
+ * vSyncWidth (out)
+ *   Vertical sync width
+ * vBackPorch (out)
+ *   Vertical back porch
+ * pclkKHz (out)
+ *   Pixel clock frequency in KHz
+ * rrx1k (out)
+ *   Refresh rate in units of 0.001Hz
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */
+
+#define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U)
+
+typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvU8   stream;
+
+    NvBool valid;
+
+    NvU16  hActive;
+    NvU16  hFrontPorch;
+    NvU16  hSyncWidth;
+    NvU16  hBackPorch;
+
+    NvU16  vActive;
+    NvU16  vFrontPorch;
+    NvU16  vSyncWidth;
+    NvU16  vBackPorch;
+
+    NvU32  pclkKHz;
+    NvU32  rrx1k;
+} NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS;
+
+/* _ctrl0073dfp_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
new file mode 100644
index 0000000..e593227
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
@@ -0,0 +1,2767 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073dp.finn
+//
+
+#include "ctrl/ctrl0073/ctrl0073base.h"
+
+/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */
+
+/*
+ * NV0073_CTRL_CMD_DP_AUXCH_CTRL
+ *
+ * This command can be used to perform an aux channel transaction to the
+ * displayPort receiver.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the dfp
+ *     caps should be returned.  The display ID must a dfp display.
+ *     If more than one displayId bit is set or the displayId is not a dfp,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   bAddrOnly
+ *     If set to NV_TRUE, this parameter prompts an address-only
+ *     i2c-over-AUX transaction to be issued, if supported.  Else the
+ *     call fails with NVOS_STATUS_ERR_NOT_SUPPORTED.  The size parameter is
+ *     expected to be 0 for address-only transactions.
+ *   cmd
+ *     This parameter is an input to this command.  The cmd parameter follows
+ *     Section 2.4 AUX channel syntax in the DisplayPort spec.
+ *     Here are the current defined fields:
+ *       NV0073_CTRL_DP_AUXCH_CMD_TYPE
+ *         This specifies the request command transaction
+ *           NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C
+ *             Set this value to indicate a I2C transaction.
+ *           NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX
+ *             Set this value to indicate a DisplayPort transaction.
+ *       NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT
+ *         This field is dependent on NV0073_CTRL_DP_AUXCH_CMD_TYPE.
+ *         It is only valid if NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C
+ *         is specified above and indicates a middle of transaction.
+ *         In the case of AUX, this field should be set to zero.  The valid
+ *         values are:
+ *           NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE
+ *             The I2C transaction is not in the middle of a transaction.
+ *           NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE
+ *             The I2C transaction is in the middle of a transaction.
+ *       NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE
+ *         The request type specifies if we are doing a read/write or write
+ *         status request:
+ *           NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ
+ *             An I2C or AUX channel read is requested.
+ *           NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE
+ *             An I2C or AUX channel write is requested.
+ *           NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS
+ *             An I2C write status request desired.  This value should
+ *             not be set in the case of an AUX CH request and only applies
+ *             to I2C write transaction command.
+ *   addr
+ *     This parameter is an input to this command.  The addr parameter follows
+ *     Section 2.4 in DisplayPort spec and the client should refer to the valid
+ *     address in DisplayPort spec.  Only the first 20 bits are valid.
+ *   data[]
+ *     In the case of a read transaction, this parameter returns the data from
+ *     transaction request.  In the case of a write transaction, the client
+ *     should write to this buffer for the data to send.  The max # of bytes
+ *     allowed is NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE.
+ *   size
+ *     Specifies how many data bytes to read/write depending on the transaction type.
+ *     The input size value should be indexed from 0.  That means if you want to read
+ *     1 byte -> size = 0, 2 bytes -> size = 1, 3 bytes -> size = 2, up to 16 bytes
+ *     where size = 15.  On return, this parameter returns total number of data bytes
+ *     successfully read/written from/to the transaction (indexed from 1).  That is,
+ *     if you successfully requested 1 byte, you would send down size = 0.  On return,
+ *     you should expect size = 1 if all 1 byte were successfully read. (Note that
+ *     it is valid for a display to reply with fewer than the requested number of
+ *     bytes; in that case, it is up to the client to make a new request for the
+ *     remaining bytes.)
+ *   replyType
+ *     This parameter is an output to this command.  It returns the auxChannel
+ *     status after the end of the aux Ch transaction.  The valid values are
+ *     based on the DisplayPort spec:
+ *       NV0073_CTRL_DP_AUXCH_REPLYTYPE_ACK
+ *         In the case of a write,
+ *         AUX: write transaction completed and all data bytes written.
+ *         I2C: return size bytes has been written to i2c slave.
+ *         In the case of a read, return of ACK indicates ready to reply
+ *         another read request.
+ *       NV0073_CTRL_DP_AUXCH_REPLYTYPE_NACK
+ *         In the case of a write, first return size bytes have been written.
+ *         In the case of a read, implies that does not have requested data
+ *         for the read request transaction.
+ *       NV0073_CTRL_DP_AUXCH_REPLYTYPE_DEFER
+ *         Not ready for the write/read request and client should retry later.
+ *       NV0073_CTRL_DP_DISPLAYPORT_AUXCH_REPLYTYPE_I2CNACK
+ *         Applies to I2C transactions only.  For I2C write transaction:
+ *         has written the first return size bytes to I2C slave before getting
+ *         NACK.  For a read I2C transaction, the I2C slave has NACKED the I2C
+ *         address.
+ *       NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CDEFER
+ *         Applicable to I2C transactions.  For I2C write and read
+ *         transactions, I2C slave has yet to ACK or NACK the I2C transaction.
+ *       NV0073_CTRL_DP_AUXCH_REPLYTYPE_TIMEOUT
+ *         The receiver did not respond within the timeout period defined in
+ *         the DisplayPort 1.1a specification.
+ *   retryTimeMs
+ *     This parameter is an output to this command.  In case of
+ *     NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time
+ *     duration in milli-seconds after which client should retry this command.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NVOS_STATUS_ERROR_RETRY
+ */
+#define NV0073_CTRL_CMD_DP_AUXCH_CTRL      (0x731341U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE 16U
+#define NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID (0x41U)
+
+typedef struct NV0073_CTRL_DP_AUXCH_CTRL_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvBool bAddrOnly;
+    NvU32  cmd;
+    NvU32  addr;
+    NvU8   data[NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE];
+    NvU32  size;
+    NvU32  replyType;
+    NvU32  retryTimeMs;
+} NV0073_CTRL_DP_AUXCH_CTRL_PARAMS;
+
+#define NV0073_CTRL_DP_AUXCH_CMD_TYPE                          3:3
+#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C               (0x00000000U)
+#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX               (0x00000001U)
+#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT                       2:2
+#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE          (0x00000000U)
+#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE           (0x00000001U)
+#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE                      1:0
+#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE         (0x00000000U)
+#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ          (0x00000001U)
+#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS  (0x00000002U)
+
+#define NV0073_CTRL_DP_AUXCH_ADDR                             20:0
+
+#define NV0073_CTRL_DP_AUXCH_REPLYTYPE                         3:0
+#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_ACK              (0x00000000U)
+#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_NACK             (0x00000001U)
+#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_DEFER            (0x00000002U)
+#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_TIMEOUT          (0x00000003U)
+#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CNACK          (0x00000004U)
+#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CDEFER         (0x00000008U)
+
+//This is not the register field, this is software failure case when we
+//have invalid argument
+#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_INVALID_ARGUMENT (0xffffffffU)
+
+/*
+ * NV0073_CTRL_CMD_DP_AUXCH_SET_SEMA
+ *
+ * This command can be used to set the semaphore in order to gain control of
+ * the aux channel.  This control is only used in HW verification.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the dfp
+ *     caps should be returned.  The display ID must a dfp display
+ *     as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
+ *     If more than one displayId bit is set or the displayId is not a dfp,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   owner
+ *     This parameter is an input to this command.
+ *     Here are the current defined fields:
+ *       NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RM
+ *         Write the aux channel semaphore for resource manager to own the
+ *         the aux channel.
+ *       NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_VBIOS
+ *         Write the aux channel semaphore for vbios/efi to own the
+ *         the aux channel.  This value is used only for HW verification
+ *         and should not be used in normal driver operation.
+ *       NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_PMU
+ *         Write the aux channel semaphore for pmu to own the
+ *         the aux channel.  This value is used only by pmu
+ *         and should not be used in normal driver operation.
+ *       NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_DPU
+ *         Write the aux channel semaphore for dpu to own the
+ *         the aux channel and should not be used in normal
+ *         driver operation.
+ *       NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_SEC2
+ *         Write the aux channel semaphore for sec2 to own the
+ *         the aux channel and should not be used in normal
+ *         driver operation.
+ *       NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RELEASE
+ *         Write the aux channel semaphore for hardware to own the
+ *         the aux channel.  This value is used only for HW verification
+ *         and should not be used in normal driver operation.
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0073_CTRL_CMD_DP_AUXCH_SET_SEMA               (0x731342U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS_MESSAGE_ID (0x42U)
+
+typedef struct NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 owner;
+} NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS;
+
+#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER                 2:0
+#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RELEASE (0x00000000U)
+#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RM      (0x00000001U)
+#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_VBIOS   (0x00000002U)
+#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_PMU     (0x00000003U)
+#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_DPU     (0x00000004U)
+#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_SEC2    (0x00000005U)
+
+/*
+ * NV0073_CTRL_CMD_DP_CTRL
+ *
+ * This command is used to set various displayPort configurations for
+ * the specified displayId such a lane count and link bandwidth.  It
+ * is assumed that link training has already occurred.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the dfp
+ *     caps should be returned.  The display ID must a dfp display.
+ *     If more than one displayId bit is set or the displayId is not a dfp,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   cmd
+ *     This parameter is an input to this command.
+ *     Here are the current defined fields:
+ *       NV0073_CTRL_DP_CMD_SET_LANE_COUNT
+ *         Set to specify the number of displayPort lanes to configure.
+ *           NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE
+ *             No request to set the displayport lane count.
+ *           NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE
+ *             Set this value to indicate displayport lane count change.
+ *       NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH
+ *         Set to specify a request to change the link bandwidth.
+ *           NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_FALSE
+ *             No request to set the displayport link bandwidth.
+ *           NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_TRUE
+ *             Set this value to indicate displayport link bandwidth change.
+ *       NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH
+ *         Set to specify a request to change the link bandwidth.
+ *           NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_FALSE
+ *             No request to set the displayport link bandwidth.
+ *           NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_TRUE
+ *             Set this value to indicate displayport link bandwidth change.
+ *       NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD
+ *         Set to disable downspread during link training.
+ *           NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE
+ *             Downspread will be enabled.
+ *           NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE
+ *             Downspread will be disabled (e.g. for compliance testing).
+ *       NV0073_CTRL_DP_CMD_SET_FORMAT_MODE
+ *         This field specifies the DP stream mode.
+ *           NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM
+ *             This value indicates that single stream mode is specified.
+ *           NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM
+ *             This value indicates that multi stream mode is specified.
+ *       NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING
+ *         Set to do Fast link training (avoid AUX transactions for link
+ *         training). We need to restore all the previous trained link settings
+ *         (e.g. the drive current/preemphasis settings) before doing FLT.
+ *         During FLT, we send training pattern 1 followed by training pattern 2
+ *         each for a period of 500us.
+ *           NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO
+ *             Not a fast link training scenario.
+ *           NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES
+ *             Do fast link training.
+ *       NV0073_CTRL_DP_CMD_NO_LINK_TRAINING
+ *         Set to do No link training. We need to restore all the previous
+ *         trained link settings (e.g. the drive current/preemphasis settings)
+ *         before doing NLT, but we don't need to do the Clock Recovery and
+ *         Channel Equalization. (Please refer to NVIDIA PANEL SELFREFRESH
+ *         CONTROLLER SPECIFICATION 3.1.6 for detail flow)
+ *           NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO
+ *             Not a no link training scenario.
+ *           NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES
+ *             Do no link training.
+ *       NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING
+ *         Specifies whether RM should use the DP Downspread setting specified by
+ *         NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD command regardless of what the Display
+ *         is capable of. This is used along with the Fake link training option so that
+ *         we can configure the GPU to enable/disable spread when a real display is
+ *         not connected.
+ *           NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE
+ *              RM Always use the DP Downspread setting specified.
+ *           NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT
+ *              RM will enable Downspread only if the display supports it. (default)
+ *       NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING
+ *         Specifies whether RM should skip HW training of the link.
+ *         If this is the case then RM only updates its SW state without actually
+ *         touching any HW registers. Clients should use this ONLY if it has determined -
+ *         a. link is trained and not lost
+ *         b. desired link config is same as current trained link config
+ *         c. link is not in D3 (should be in D0)
+ *           NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO
+ *              RM doesn't skip HW LT as the current Link Config is not the same as the
+ *              requested Link Config.
+ *           NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES
+ *              RM skips HW LT and only updates its SW state as client has determined that
+ *              the current state of the link and the requested Link Config is the same.
+ *       NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG
+ *         Set if the client does not want link training to happen.
+ *         This should ONLY be used for HW verification.
+ *           NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE
+ *             This is normal production behaviour which shall perform
+ *             link training or follow the normal procedure for lane count
+ *             reduction.
+ *           NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE
+ *             Set this value to not perform link config steps, this should
+ *             only be turned on for HW verif testing.  If _LINK_BANDWIDTH
+ *             or _LANE_COUNT is set, RM will only write to the TX DP registers
+ *             and perform no link training.
+ *       NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED
+ *         This field specifies if source grants Post Link training Adjustment request or not.
+ *           NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO
+ *              Source does not grant Post Link training Adjustment request
+ *           NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES
+ *              Source grants Post Link training Adjustment request
+ *              Source wants to link train LT Tunable Repeaters
+ *       NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING
+ *         This field specifies if fake link training is to be done. This will
+ *         program enough of the hardware to avoid any hardware hangs and
+ *         depending upon option chosen by the client, OR will be enabled for
+ *         transmisssion.
+ *           NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO
+ *              No Fake LT will be performed
+ *           NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION
+ *              SOR will be not powered up during Fake LT
+ *           NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON
+ *              SOR will be powered up during Fake LT
+ *       NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER
+ *         This field specifies if source wants to link train LT Tunable Repeaters or not.
+ *           NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO
+ *              Source does not want to link train LT Tunable Repeaters
+ *           NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES
+ *       NV0073_CTRL_DP_CMD_BANDWIDTH_TEST
+ *         Set if the client wants to reset the link after the link
+ *         training is done. As a part of uncommtting a DP display.
+ *           NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO
+ *             This is for normal operation, if DD decided not to reset the link.
+ *           NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES
+ *             This is to reset the link, if DD decided to uncommit the display because
+ *             the link is no more required to be enabled, as in a DP compliance test.
+ *       NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE
+ *         Set if the client does not want link training to happen.
+ *         This should ONLY be used for HW verification if necessary.
+ *           NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE
+ *             This is normal production behaviour which shall perform
+ *             pre link training checks such as if both rx and tx are capable
+ *             of the requested config for lane and link bw.
+ *           NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE
+ *             Set this value to bypass link config check, this should
+ *             only be turned on for HW verif testing.  If _LINK_BANDWIDTH
+ *             or _LANE_COUNT is set, RM will not check TX and DX caps.
+ *       NV0073_CTRL_DP_CMD_FALLBACK_CONFIG
+ *         Set if requested config by client fails and if link if being
+ *         trained for the fallback config.
+ *           NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE
+ *             This is the normal case when the link is being trained for a requested config.
+ *           NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE
+ *             Set this value in case the link configuration for requested config fails
+ *             and the link is being trained for a fallback config.
+ *       NV0073_CTRL_DP_CMD_ENABLE_FEC
+ *         Specifies whether RM should set NV_DPCD14_FEC_CONFIGURATION_FEC_READY
+ *         before link training if client has determined that FEC is required(for DSC).
+ *         If required to be enabled RM sets FEC enable bit in panel, start link training.
+ *         Enabling/disabling FEC on GPU side is not done during Link training
+ *         and RM Ctrl call NV0073_CTRL_CMD_DP_CONFIGURE_FEC has to be called
+ *         explicitly to enable/disable FEC after LT(including PostLT LQA).
+ *         If enabled, FEC would be disabled while powering down the link.
+ *         Client has to make sure to account for 3% overhead of transmitting
+ *         FEC symbols while calculating DP bandwidth.
+ *           NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE
+ *             This is the normal case when FEC is not required
+ *           NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE
+ *             Set this value in case FEC needs to be enabled
+ *   data
+ *     This parameter is an input and output to this command.
+ *     Here are the current defined fields:
+ *       NV0073_CTRL_DP_DATA_SET_LANE_COUNT
+ *         This field specifies the desired setting for lane count.  A client
+ *         may choose any lane count as long as it does not exceed the
+ *         capability of DisplayPort receiver as indicated in the
+ *         receiver capability field.  The valid values for this field are:
+ *           NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0
+ *             For zero-lane configurations, link training is shut down.
+ *           NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1
+ *             For one-lane configurations, lane0 is used.
+ *           NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2
+ *             For two-lane configurations, lane0 and lane1 is used.
+ *           NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4
+ *             For four-lane configurations, all lanes are used.
+ *           NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8
+ *             For devices that supports 8-lane DP.
+ *         On return, the lane count setting is returned which may be
+ *         different from the requested input setting.
+ *       NV0073_CTRL_DP_DATA_SET_LINK_BW
+ *         This field specifies the desired setting for link bandwidth.  There
+ *         are only four supported main link bandwidth settings.  The
+ *         valid values for this field are:
+ *           NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS
+ *           NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS
+ *           NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS
+ *           NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS
+ *         On return, the link bandwidth setting is returned which may be
+ *         different from the requested input setting.
+ *       NV0073_CTRL_DP_DATA_TARGET
+ *         This field specifies which physical repeater or sink to be trained.
+ *         Client should make sure
+ *             1. Physical repeater should be targeted in order, start from the one closest to GPU.
+ *             2. All physical repeater is properly trained before targets sink.
+ *         The valid values for this field are:
+ *           NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_X
+ *               'X' denotes physical repeater index. It's a 1-based index to
+ *                   reserve 0 for _SINK.
+ *               'X' can't be more than 8.
+ *           NV0073_CTRL_DP_DATA_TARGET_SINK
+ *   err
+ *     This parameter specifies provides info regarding the outcome
+ *     of this calling control call.  If zero, no errors were found.
+ *     Otherwise, this parameter will specify the error detected.
+ *     The valid parameter is broken down as follows:
+ *        NV0073_CTRL_DP_ERR_SET_LANE_COUNT
+ *          If set to _ERR, set lane count failed.
+ *        NV0073_CTRL_DP_ERR_SET_LINK_BANDWIDTH
+ *          If set to _ERR, set link bandwidth failed.
+ *        NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD
+ *          If set to _ERR, disable downspread failed.
+ *        NV0073_CTRL_DP_ERR_INVALID_PARAMETER
+ *          If set to _ERR, at least one of the calling functions
+ *          failed due to an invalid parameter.
+ *        NV0073_CTRL_DP_ERR_SET_LINK_TRAINING
+ *          If set to _ERR, link training failed.
+ *        NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER
+ *          If set to _ERR, the operation to Link Train repeater is failed.
+ *        NV0073_CTRL_DP_ERR_ENABLE_FEC
+ *          If set to _ERR, the operation to enable FEC is failed.
+ *   retryTimeMs
+ *     This parameter is an output to this command.  In case of
+ *     NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time
+ *     duration in milli-seconds after which client should retry this command.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NVOS_STATUS_ERROR_RETRY
+ */
+
+#define NV0073_CTRL_CMD_DP_CTRL                     (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID (0x43U)
+
+typedef struct NV0073_CTRL_DP_CTRL_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 cmd;
+    NvU32 data;
+    NvU32 err;
+    NvU32 retryTimeMs;
+    NvU32 eightLaneDpcdBaseAddr;
+} NV0073_CTRL_DP_CTRL_PARAMS;
+
+#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT                           0:0
+#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE                         (0x00000000U)
+#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE                          (0x00000001U)
+#define NV0073_CTRL_DP_CMD_SET_LINK_BW                              1:1
+#define NV0073_CTRL_DP_CMD_SET_LINK_BW_FALSE                            (0x00000000U)
+#define NV0073_CTRL_DP_CMD_SET_LINK_BW_TRUE                             (0x00000001U)
+#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD                       2:2
+#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE                     (0x00000000U)
+#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE                      (0x00000001U)
+#define NV0073_CTRL_DP_CMD_UNUSED                                   3:3
+#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE                          4:4
+#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM                (0x00000000U)
+#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM                 (0x00000001U)
+#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING                       5:5
+#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO                        (0x00000000U)
+#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES                       (0x00000001U)
+#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING                         6:6
+#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO                          (0x00000000U)
+#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES                         (0x00000001U)
+#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING                     7:7
+#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_FALSE                   (0x00000000U)
+#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_TRUE                    (0x00000001U)
+#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING                   8:8
+#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT               (0x00000000U)
+#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE                 (0x00000001U)
+#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING                      9:9
+#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO                       (0x00000000U)
+#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES                      (0x00000001U)
+#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED                10:10
+#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO                   (0x00000000U)
+#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES                  (0x00000001U)
+#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING                     12:11
+#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO                        (0x00000000U)
+#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U)
+#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON    (0x00000002U)
+#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER                     13:13
+#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO                        (0x00000000U)
+#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES                       (0x00000001U)
+#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG                        14:14
+#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE                        (0x00000000U)
+#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_TRUE                         (0x00000001U)
+#define NV0073_CTRL_DP_CMD_ENABLE_FEC                             15:15
+#define NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE                             (0x00000000U)
+#define NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE                              (0x00000001U)
+
+#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST                         29:29
+#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO                            (0x00000000U)
+#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES                           (0x00000001U)
+#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE              30:30
+#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE              (0x00000000U)
+#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE               (0x00000001U)
+#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG                    31:31
+#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE                    (0x00000000U)
+#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE                     (0x00000001U)
+
+#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT                          4:0
+#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0                            (0x00000000U)
+#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1                            (0x00000001U)
+#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2                            (0x00000002U)
+#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4                            (0x00000004U)
+#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8                            (0x00000008U)
+#define NV0073_CTRL_DP_DATA_SET_LINK_BW                            15:8
+#define NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS                        (0x00000006U)
+#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_16GBPS                        (0x00000008U)
+#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_43GBPS                        (0x00000009U)
+#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS                        (0x0000000AU)
+#define NV0073_CTRL_DP_DATA_SET_LINK_BW_3_24GBPS                        (0x0000000CU)
+#define NV0073_CTRL_DP_DATA_SET_LINK_BW_4_32GBPS                        (0x00000010U)
+#define NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS                        (0x00000014U)
+#define NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS                        (0x0000001EU)
+#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING                  18:18
+#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_NO                     (0x00000000U)
+#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_YES                    (0x00000001U)
+#define NV0073_CTRL_DP_DATA_TARGET                                22:19
+#define NV0073_CTRL_DP_DATA_TARGET_SINK                                 (0x00000000U)
+#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_0                       (0x00000001U)
+#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_1                       (0x00000002U)
+#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_2                       (0x00000003U)
+#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_3                       (0x00000004U)
+#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_4                       (0x00000005U)
+#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_5                       (0x00000006U)
+#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_6                       (0x00000007U)
+#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_7                       (0x00000008U)
+
+#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT                           0:0
+#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT_NOERR                         (0x00000000U)
+#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT_ERR                           (0x00000001U)
+#define NV0073_CTRL_DP_ERR_SET_LINK_BW                              1:1
+#define NV0073_CTRL_DP_ERR_SET_LINK_BW_NOERR                            (0x00000000U)
+#define NV0073_CTRL_DP_ERR_SET_LINK_BW_ERR                              (0x00000001U)
+#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD                       2:2
+#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD_NOERR                     (0x00000000U)
+#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD_ERR                       (0x00000001U)
+#define NV0073_CTRL_DP_ERR_UNUSED                                   3:3
+#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY                           4:4
+#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY_NOERR                         (0x00000000U)
+#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY_ERR                           (0x00000001U)
+#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION                     5:5
+#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION_NOERR                   (0x00000000U)
+#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION_ERR                     (0x00000001U)
+#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER                       6:6
+#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER_NOERR                     (0x00000000U)
+#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER_ERR                       (0x00000001U)
+#define NV0073_CTRL_DP_ERR_ENABLE_FEC                               7:7
+#define NV0073_CTRL_DP_ERR_ENABLE_FEC_NOERR                             (0x00000000U)
+#define NV0073_CTRL_DP_ERR_ENABLE_FEC_ERR                               (0x00000001U)
+#define NV0073_CTRL_DP_ERR_CR_DONE_LANE                            11:8
+#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_0_LANE                          (0x00000000U)
+#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_1_LANE                          (0x00000001U)
+#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_2_LANE                          (0x00000002U)
+#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_4_LANE                          (0x00000004U)
+#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_8_LANE                          (0x00000008U)
+#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE                           15:12
+#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_0_LANE                          (0x00000000U)
+#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_1_LANE                          (0x00000001U)
+#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_2_LANE                          (0x00000002U)
+#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_4_LANE                          (0x00000004U)
+#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_8_LANE                          (0x00000008U)
+#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER                      30:30
+#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER_NOERR                      (0x00000000U)
+#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER_ERR                        (0x00000001U)
+#define NV0073_CTRL_DP_ERR_LINK_TRAINING                          31:31
+#define NV0073_CTRL_DP_ERR_LINK_TRAINING_NOERR                          (0x00000000U)
+#define NV0073_CTRL_DP_ERR_LINK_TRAINING_ERR                            (0x00000001U)
+
+/*
+ * NV0073_CTRL_DP_LANE_DATA_PARAMS
+ *
+ * This structure provides lane characteristics.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the dfp
+ *     caps should be returned.  The display ID must a dfp display.
+ *     If more than one displayId bit is set or the displayId is not a dfp,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   numLanes
+ *      Indicates number of lanes for which the data is valid
+ *   data
+ *     This parameter is an input to this command.
+ *     Here are the current defined fields:
+ *       NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS
+ *         This field specifies the preemphasis level set in the lane.
+ *         The valid values for this field are:
+ *           NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE
+ *             No-preemphais for this lane.
+ *           NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1
+ *             Preemphasis set to 3.5 dB.
+ *           NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2
+ *             Preemphasis set to 6.0 dB.
+ *           NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3
+ *             Preemphasis set to 9.5 dB.
+ *       NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT
+ *         This field specifies the drive current set in the lane.
+ *         The valid values for this field are:
+ *           NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0
+ *             Drive current level is set to 8 mA
+ *           NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1
+ *             Drive current level is set to 12 mA
+ *           NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2
+ *             Drive current level is set to 16 mA
+ *           NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3
+ *             Drive current level is set to 24 mA
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_MAX_LANES                                           8U
+
+typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 numLanes;
+    NvU32 data[NV0073_CTRL_MAX_LANES];
+} NV0073_CTRL_DP_LANE_DATA_PARAMS;
+
+#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS                   1:0
+#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE    (0x00000000U)
+#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1  (0x00000001U)
+#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2  (0x00000002U)
+#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3  (0x00000003U)
+#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT                  3:2
+#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 (0x00000000U)
+#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 (0x00000001U)
+#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 (0x00000002U)
+#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 (0x00000003U)
+
+/*
+ * NV0073_CTRL_CMD_GET_DP_LANE_DATA
+ *
+ * This command is used to get the current pre-emphasis and drive current
+ * level values for the specified number of lanes.
+ *
+ * The command takes a NV0073_CTRL_DP_LANE_DATA_PARAMS structure as the
+ * argument with the appropriate subDeviceInstance and displayId filled.
+ * The arguments of this structure and the format of  preemphasis and drive-
+ * current levels are described above.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ * NOTE: This control call is only for testing purposes and
+ *       should not be used in normal DP operations. Preemphais
+ *       and drive current level will be set during Link training
+ *       in normal DP operations
+ *
+ */
+
+#define NV0073_CTRL_CMD_DP_GET_LANE_DATA             (0x731345U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x45" */
+
+
+/*
+ * NV0073_CTRL_CMD_SET_DP_LANE_DATA
+ *
+ * This command is used to set the pre-emphasis and drive current
+ * level values for the specified number of lanes.
+ *
+ * The command takes a NV0073_CTRL_DP_LANE_DATA_PARAMS structure as the
+ * argument with the appropriate subDeviceInstance, displayId, number of
+ * lanes, preemphasis and drive current values filled in.
+ * The arguments of this structure and the format of  preemphasis and drive-
+ * current levels are described above.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ * NOTE: This control call is only for testing purposes and
+ *       should not be used in normal DP operations. Preemphais
+ *       and drivecurrent will be set during Link training in
+ *       normal DP operations
+ *
+ */
+
+#define NV0073_CTRL_CMD_DP_SET_LANE_DATA             (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x46" */
+
+/*
+ * NV0073_CTRL_DP_CSTM
+ *
+ * This structure specifies the 80 bit DP CSTM Test Pattern data
+ * The fields of this structure are to be specified as follows:
+ *      lower   takes bits 31:0
+ *      middle  takes bits 63:32
+ *      upper   takes bits 79:64
+ *
+ */
+typedef struct NV0073_CTRL_DP_CSTM {
+    NvU32 lower;
+    NvU32 middle;
+    NvU32 upper;
+} NV0073_CTRL_DP_CSTM;
+
+/*
+ * NV0073_CTRL_DP_TESTPATTERN
+ *
+ * This structure specifies the possible test patterns available in
+ * display port. The field testPattern can be one of the following
+ * values.
+ *          NV0073_CTRL_DP_SET_TESTPATTERN_DATA_NONE
+ *              No test pattern on the main link
+ *          NV0073_CTRL_DP_SET_TESTPATTERN_DATA_D10_2
+ *              D10.2 pattern on the main link
+ *          NV0073_CTRL_DP_SET_TESTPATTERN_DATA_SERMP
+ *              SERMP pattern on main link
+ *          NV0073_CTRL_DP_SET_TESTPATTERN_DATA_PRBS_7
+ *              PRBS7 pattern on the main link
+ *
+ */
+
+typedef struct NV0073_CTRL_DP_TESTPATTERN {
+    NvU32 testPattern;
+} NV0073_CTRL_DP_TESTPATTERN;
+
+#define NV0073_CTRL_DP_TESTPATTERN_DATA                              2:0
+#define NV0073_CTRL_DP_TESTPATTERN_DATA_NONE           (0x00000000U)
+#define NV0073_CTRL_DP_TESTPATTERN_DATA_D10_2          (0x00000001U)
+#define NV0073_CTRL_DP_TESTPATTERN_DATA_SERMP          (0x00000002U)
+#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_7         (0x00000003U)
+#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM           (0x00000004U)
+#define NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE (0x00000005U)
+#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT3     (0x00000006U)
+
+/*
+ * NV0073_CTRL_CMD_DP_SET_TESTPATTERN
+ *
+ * This command forces the main link to output the selected test patterns
+ * supported in DP specs.
+ *
+ * The command takes a NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS structure as the
+ * argument with the appropriate subDeviceInstance, displayId and test pattern
+ * to be set as inputs.
+ * The arguments of this structure and the format of  test patterns are
+ * described above.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the dfp
+ *     caps should be returned.  The display ID must a dfp display.
+ *     If more than one displayId bit is set or the displayId is not a dfp,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   testPattern
+ *     This parameter is of type NV0073_CTRL_DP_TESTPATTERN and specifies
+ *     the testpattern to set on displayport. The format of this structure
+ *     is described above.
+ *   laneMask
+ *     This parameter specifies the bit mask of DP lanes on which test
+ *     pattern is to be applied.
+ *   lower
+ *     This parameter specifies the lower 64 bits of the CSTM test pattern
+ *   upper
+ *     This parameter specifies the upper 16 bits of the CSTM test pattern
+ *   bIsHBR2
+ *     This Boolean parameter is set to TRUE if HBR2 compliance test is
+ *     being performed.
+  *   bSkipLaneDataOverride
+ *      skip override of pre-emp and drive current
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ * NOTE: This control call is only for testing purposes and
+ *       should not be used in normal DP operations. Preemphais
+ *       and drivecurrent will be set during Link training in
+ *       normal DP operations
+ *
+ */
+
+#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_MESSAGE_ID (0x47U)
+
+typedef struct NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS {
+    NvU32                      subDeviceInstance;
+    NvU32                      displayId;
+    NV0073_CTRL_DP_TESTPATTERN testPattern;
+    NvU8                       laneMask;
+    NV0073_CTRL_DP_CSTM        cstm;
+    NvBool                     bIsHBR2;
+    NvBool                     bSkipLaneDataOverride;
+} NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS;
+
+#define NV0073_CTRL_CMD_DP_SET_TESTPATTERN (0x731347U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM0    31:0
+#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM1    63:32
+#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM2    15:0
+
+/*
+ * NV0073_CTRL_CMD_GET_DP_TESTPATTERN
+ *
+ * This command returns the current test pattern set on the main link of
+ * Display Port.
+ *
+ * The command takes a NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS structure as the
+ * argument with the appropriate subDeviceInstance, displayId as inputs and
+ * returns the current test pattern in testPattern field of the structure.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the dfp
+ *     caps should be returned.  The display ID must a dfp display.
+ *     If more than one displayId bit is set or the displayId is not a dfp,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   testPattern
+ *     This parameter is of type NV0073_CTRL_DP_TESTPATTERN and specifies the
+ *     testpattern set on displayport. The format of this structure is
+ *     described above.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ * NOTE: This control call is only for testing purposes and
+ *       should not be used in normal DP operations.
+ *
+ */
+
+#define NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS_MESSAGE_ID (0x48U)
+
+typedef struct NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS {
+    NvU32                      subDeviceInstance;
+    NvU32                      displayId;
+    NV0073_CTRL_DP_TESTPATTERN testPattern;
+} NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS;
+
+
+#define NV0073_CTRL_CMD_DP_GET_TESTPATTERN  (0x731348U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA
+ *
+ * This structure specifies the Pre-emphasis/Drive Current/Postcursor2/TxPu information
+ * for a display port device. These are the the current values that RM is
+ * using to map the levels for Pre-emphasis and Drive Current for Link
+ * Training.
+ *   preEmphasis
+ *     This field specifies the preemphasis values.
+ *   driveCurrent
+ *     This field specifies the driveCurrent values.
+ *   postcursor2
+ *     This field specifies the postcursor2 values.
+ *   TxPu
+ *     This field specifies the pull-up current source drive values.
+ */
+#define NV0073_CTRL_MAX_DRIVECURRENT_LEVELS 4U
+#define NV0073_CTRL_MAX_PREEMPHASIS_LEVELS  4U
+#define NV0073_CTRL_MAX_POSTCURSOR2_LEVELS  4U
+
+typedef struct NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1 {
+    NvU32 preEmphasis;
+    NvU32 driveCurrent;
+    NvU32 postCursor2;
+    NvU32 TxPu;
+} NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1;
+
+typedef NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1 NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE1[NV0073_CTRL_MAX_PREEMPHASIS_LEVELS];
+
+typedef NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE1 NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE2[NV0073_CTRL_MAX_DRIVECURRENT_LEVELS];
+
+typedef NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE2 NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA[NV0073_CTRL_MAX_POSTCURSOR2_LEVELS];
+
+
+/*
+ * NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA
+ *
+ * This command is used to override the Pre-emphasis/Drive Current/PostCursor2/TxPu
+ * data in the RM.
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the digital display for which the
+ *     data should be returned.  The display ID must a digital display.
+ *     If more than one displayId bit is set or the displayId is not a DP,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   dpData
+ *     This parameter is of type NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA
+ *     and specifies the Pre-emphasis/Drive Current/Postcursor2/TxPu information
+ *     for a display port device.
+ * The command takes a NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS
+ * structure as the argument with the appropriate subDeviceInstance, displayId,
+ * and dpData.  The fields of this structure are described above.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID (0x51U)
+
+typedef struct NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS {
+    NvU32                                                    subDeviceInstance;
+    NvU32                                                    displayId;
+    NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA dpData;
+} NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS;
+
+#define NV0073_CTRL_CMD_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA (0x731351U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA
+ *
+ * This command is used to get the Pre-emphasis/Drive Current/PostCursor2/TxPu data.
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the digital display for which the
+ *     data should be returned.  The display ID must a digital display.
+ *     If more than one displayId bit is set or the displayId is not a DP,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ * The command takes a NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS
+ * structure as the argument with the appropriate subDeviceInstance, displayId,
+ * and dpData.  The fields of this structure are described above.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID (0x52U)
+
+typedef struct NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS {
+    NvU32                                                    subDeviceInstance;
+    NvU32                                                    displayId;
+    NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA dpData;
+} NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS;
+
+#define NV0073_CTRL_CMD_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA (0x731352U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID" */
+
+
+
+/*
+ * NV0073_CTRL_CMD_DP_MAIN_LINK_CTRL
+ *
+ * This command is used to set various Main Link configurations for
+ * the specified displayId such as powering up/down Main Link.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the DP display which owns
+ *     the Main Link to be adjusted.  The display ID must a DP display
+ *     as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
+ *     If more than one displayId bit is set or the displayId is not a DP,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   ctrl
+ *     Here are the current defined fields:
+ *       NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERDOWN
+ *         This value will power down Main Link.
+ *       NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERUP
+ *         This value will power up Main Link.
+ *
+*/
+#define NV0073_CTRL_CMD_DP_MAIN_LINK_CTRL                       (0x731356U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS_MESSAGE_ID (0x56U)
+
+typedef struct NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 ctrl;
+} NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS;
+
+#define  NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE                          0:0
+#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERDOWN (0x00000000U)
+#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERUP   (0x00000001U)
+
+
+
+/*
+ * NV0073_CTRL_CMD_DP_GET_AUDIO_MUTESTREAM
+ *
+ * This command returns the current audio mute state on the main link of Display Port
+ *
+ * The command takes a NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS structure as the
+ * argument with the appropriate subDeviceInstance, displayId as inputs and returns the
+ * current mute status in mute field of the structure.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the audio stream
+ *     state should be returned.  The display ID must a DP display.
+ *     If the display ID is invalid or if it is not a DP display,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   mute
+ *     This parameter will return one of the following values:
+ *       NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE
+ *         Audio mute is currently disabled.
+ *       NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE
+ *         Audio mute is currently enabled.
+ *       NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO
+ *         Audio mute is automatically controlled by hardware.
+ *       NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_UNKNOWN
+ *         Audio mute is currently in an unknown state.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ *
+ */
+#define NV0073_CTRL_CMD_DP_GET_AUDIO_MUTESTREAM                        (0x731358U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x58U)
+
+typedef struct NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 mute;
+} NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS;
+
+#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE (0x00000000U)
+#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE  (0x00000001U)
+#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO    (0x00000002U)
+#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_UNKNOWN (0x00000003U)
+
+/*
+ * NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM
+ *
+ * This command sets the current audio mute state on the main link of Display Port
+ *
+ * The command takes a NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS structure as the
+ * argument with the appropriate subDeviceInstance, displayId as inputs and whether to enable
+ * or disable mute in the parameter - mute.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the audio stream
+ *     state should be returned.  The display ID must a DP display.
+ *     If the display ID is invalid or if it is not a DP display,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   mute
+ *     This parameter is an input to this command.
+ *     Here are the current defined values:
+ *       NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE
+ *         Audio mute will be disabled.
+ *       NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE
+ *         Audio mute will be enabled.
+ *       NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO
+ *         Audio mute will be automatically controlled by hardware.
+ *
+ *      Note:  Any other value for mute in NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS is not allowed and
+ *              the API will return an error.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ *
+ */
+#define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM      (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x59U)
+
+typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 mute;
+} NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_DP_ASSR_CTRL
+ *
+ * This command is used to control and query DisplayPort ASSR
+ * settings for the specified displayId.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the DP display which owns
+ *     the Main Link to be adjusted.  The display ID must a DP display
+ *     as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
+ *     If more than one displayId bit is set or the displayId is not a DP,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   cmd
+ *     This input parameter specifies the command to execute.  Legal
+ *     values for this parameter include:
+ *       NV0073_CTRL_DP_ASSR_CMD_QUERY_STATE
+ *         This field can be used to query ASSR state. When used the ASSR
+ *         state value is returned in the data parameter.
+ *       NV0073_CTRL_DP_ASSR_CMD_DISABLE
+ *         This field can be used to control the ASSR disable state.
+ *       NV0073_CTRL_DP_ASSR_CMD_FORCE_STATE
+ *         This field can be used to control ASSR State without looking at
+ *         whether the display supports it. Used in conjunction with
+ *         Fake link training. Note that this updates the state on the
+ *         source side only. The sink is assumed to be configured for ASSR
+ *         by the client (DD).
+ *   data
+ *     This parameter specifies the data associated with the cmd
+ *     parameter.
+ *       NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED
+ *         This field indicates the state of ASSR when queried using cmd
+ *         parameter. When used to control the State, it indicates whether
+ *         ASSR should be enabled or disabled.
+ *           NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_NO
+ *             When queried this flag indicates that ASSR is not enabled on the sink.
+ *             When used as the data for CMD_FORCE_STATE, it requests ASSR to
+ *             to be disabled on the source side.
+ *           NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_YES
+ *             When queried this flag indicates that ASSR is not enabled on the sink.
+ *             When used as the data for CMD_FORCE_STATE, it requests ASSR to
+ *             to be enabled on the source side.
+ *   err
+ *     This output parameter specifies any errors associated with the cmd
+ *     parameter.
+ *       NV0073_CTRL_DP_ASSR_ERR_CAP
+ *         This field indicates the error pertaining to ASSR capability of
+ *         the sink device.
+ *           NV0073_CTRL_DP_ASSR_ERR_CAP_NOERR
+ *             This flag indicates there is no error.
+ *           NV0073_CTRL_DP_ASSR_ERR_CAP_ERR
+ *             This flag indicates that the sink is not ASSR capable.
+ *
+ *  Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV0073_CTRL_CMD_DP_ASSR_CTRL (0x73135aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID (0x5AU)
+
+typedef struct NV0073_CTRL_DP_ASSR_CTRL_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 cmd;
+    NvU32 data;
+    NvU32 err;
+} NV0073_CTRL_DP_ASSR_CTRL_PARAMS;
+
+#define  NV0073_CTRL_DP_ASSR_CMD                                31:0
+#define NV0073_CTRL_DP_ASSR_CMD_QUERY_STATE             (0x00000001U)
+#define NV0073_CTRL_DP_ASSR_CMD_DISABLE                 (0x00000002U)
+#define NV0073_CTRL_DP_ASSR_CMD_FORCE_STATE             (0x00000003U)
+#define NV0073_CTRL_DP_ASSR_CMD_ENABLE                  (0x00000004U)
+#define  NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED                  0:0
+#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_NO       (0x00000000U)
+#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_YES      (0x00000001U)
+#define  NV0073_CTRL_DP_ASSR_ERR_CAP                             0:0
+#define NV0073_CTRL_DP_ASSR_ERR_CAP_NOERR               (0x00000000U)
+#define NV0073_CTRL_DP_ASSR_ERR_CAP_ERR                 (0x00000001U)
+
+/*
+ * NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID
+ *
+ * This command is used to assign a displayId from the free pool
+ * to a specific AUX Address in a DP 1.2 topology.  The topology
+ * is uniquely identified by the DisplayId of the DP connector.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This is the DisplayId of the DP connector to which the topology
+ *     is rooted.
+ *   preferredDisplayId
+ *      Client can sent a preferredDisplayID which RM can use during allocation
+ *      if available. If this Id is a part of allDisplayMask in RM then we return
+ *      a free available Id to the client. However, if this is set to
+ *      NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID then we return allDisplayMask value.
+ *   useBFM
+ *      Set to true if DP-BFM is used during emulation/RTL Sim.
+ *
+ *   [out] displayIdAssigned
+ *     This is the out field that will receive the new displayId.  If the
+ *     function fails this is guaranteed to be 0.
+ *   [out] allDisplayMask
+ *      This is allDisplayMask RM variable which is returned only when
+ *      preferredDisplayId is set to NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID
+ *
+ *
+ *  Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID  (0x73135bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID" */
+
+/*
+ *  There cannot be more than 128 devices in a topology (also by DP 1.2 specification)
+ *  NOTE: Temporarily lowered to pass XAPI RM tests. Should be reevaluated!
+ */
+#define NV0073_CTRL_CMD_DP_MAX_TOPOLOGY_NODES           120U
+#define NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID 0xffffffffU
+
+#define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID (0x5BU)
+
+typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvU32  preferredDisplayId;
+
+    NvBool force;
+    NvBool useBFM;
+
+    NvU32  displayIdAssigned;
+    NvU32  allDisplayMask;
+} NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID
+ *
+ * This command is used to return a multistream displayid to the unused pool.
+ * You must not call this function while either the ARM or ASSEMBLY state cache
+ * refers to this display-id.  The head must not be attached.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This is the displayId to free.
+ *
+ *  Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *
+ *
+ */
+#define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID (0x73135cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID (0x5CU)
+
+typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+} NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_CMD_DP_GET_LINK_CONFIG
+ *
+ * This command is used to query DisplayPort link config
+ * settings on the transmitter side.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the DP display which owns
+ *     the Main Link to be queried.
+ *     If more than one displayId bit is set or the displayId is not a DP,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   laneCount
+ *     Number of lanes the DP transmitter hardware is set up to drive.
+ *   linkBW
+ *     The BW of each lane that the DP transmitter hardware is set up to drive.
+ *     The values returned will be according to the DP specifications.
+ *
+ */
+#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG (0x731360U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID (0x60U)
+
+typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 laneCount;
+    NvU32 linkBW;
+} NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS;
+
+#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT                          3:0
+#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_0     (0x00000000U)
+#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_1     (0x00000001U)
+#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_2     (0x00000002U)
+#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_4     (0x00000004U)
+#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW                             3:0
+#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_1_62GBPS (0x00000006U)
+#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_70GBPS (0x0000000aU)
+
+/*
+ * NV0073_CTRL_CMD_DP_GET_EDP_DATA
+ *
+ * This command is used to query Embedded DisplayPort information.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the eDP display which owns
+ *     the Main Link to be queried.
+ *     If more than one displayId bit is set or the displayId is not a eDP,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   data
+ *     This output parameter specifies the data associated with the eDP display.
+ *     It is only valid if this function returns NV_OK.
+ *       NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER
+ *         This field indicates the state of the eDP panel power.
+ *           NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER_OFF
+ *             This eDP panel is powered off.
+ *           NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER_ON
+ *             This eDP panel is powered on.
+ *       NV0073_CTRL_CMD_DP_GET_EDP_DATA_DPCD_POWER_OFF
+ *         This field tells the client if DPCD power off command
+ *         should be used for the current eDP panel.
+ *           NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_ENABLE
+ *             This eDP panel can use DPCD to power off the panel.
+ *           NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_DISABLE
+ *             This eDP panel cannot use DPCD to power off the panel.
+ *       NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER
+ *         This field tells the client current eDP panel DPCD SET_POWER (0x600) status
+ *            NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER_D0
+ *              This eDP panel is current up and in full power mode.
+ *            NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER_D3
+ *              This eDP panel is current standby.
+ */
+#define NV0073_CTRL_CMD_DP_GET_EDP_DATA                     (0x731361U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID (0x61U)
+
+typedef struct NV0073_CTRL_DP_GET_EDP_DATA_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 data;
+} NV0073_CTRL_DP_GET_EDP_DATA_PARAMS;
+
+#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER                                0:0
+#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER_OFF        (0x00000000U)
+#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER_ON         (0x00000001U)
+#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF                             1:1
+#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_ENABLE  (0x00000000U)
+#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_DISABLE (0x00000001U)
+#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE                           2:2
+#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE_D0    (0x00000000U)
+#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE_D3    (0x00000001U)
+/*
+ * NV0073_CTRL_CMD_DP_CONFIG_STREAM
+ *
+ * This command sets various multi/single stream related params for
+ * for a given head.
+ *
+ *   subDeviceInstance
+ *          This parameter specifies the subdevice instance within the
+ *          NV04_DISPLAY_COMMON parent device to which the operation should be
+ *          directed. This parameter must specify a value between zero and the
+ *          total number of subdevices within the parent device.  This parameter
+ *          should be set to zero for default behavior.
+ *      Head
+ *          Specifies the head index for the stream.
+ *      sorIndex
+ *          Specifies the SOR index for the stream.
+ *      dpLink
+ *          Specifies the DP link: either 0 or 1 (A , B)
+ *      bEnableOverride
+ *          Specifies whether we're manually configuring this stream.
+ *          If not set, none of the remaining settings have any effect.
+ *      bMST
+ *          Specifies whether in Multistream or Singlestream mode.
+ *      MST/SST
+ *          Structures for passing in either Multistream or Singlestream params
+ *      slotStart
+ *          Specifies the start value of the timeslot
+ *      slotEnd
+ *          Specifies the end value of the timeslot
+ *      PBN
+ *          Specifies the PBN for the timeslot.
+ *      minHBlank
+ *          Specifies the min HBlank
+ *      minVBlank
+ *          Specifies the min VBlank
+ *      sendACT   -- deprecated. A new control call has been added.
+ *          Specifies whether ACT has to be sent or not.
+ *      tuSize
+ *          Specifies TU size value
+ *      watermark
+ *          Specifies stream watermark.
+ *      linkClkFreqHz -- moving to MvidWarParams. Use that instead.
+ *          Specifies the link freq in Hz. Note that this is the byte clock.
+ *          eg: = (5.4 Ghz / 10)
+ *      actualPclkHz; -- moving to MvidWarParams. Use that instead.
+ *          Specifies the actual pclk freq in Hz.
+ *      mvidWarEnabled
+ *          Specifies whether MVID WAR is enabled.
+ *      MvidWarParams
+ *          Is valid if mvidWarEnabled is true.
+ *      bEnableTwoHeadOneOr
+ *          Whether two head one OR is enabled. If this is set then RM will
+ *          replicate SF settings of Master head on Slave head. Head index
+ *          passed should be of Master Head.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC: when this command has already been called
+ *
+ */
+#define NV0073_CTRL_CMD_DP_CONFIG_STREAM                   (0x731362U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID (0x62U)
+
+typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  head;
+    NvU32  sorIndex;
+    NvU32  dpLink;
+
+    NvBool bEnableOverride;
+    NvBool bMST;
+    NvU32  singleHeadMultistreamMode;
+    NvU32  hBlankSym;
+    NvU32  vBlankSym;
+    NvU32  colorFormat;
+    NvBool bEnableTwoHeadOneOr;
+
+    struct {
+        NvU32  slotStart;
+        NvU32  slotEnd;
+        NvU32  PBN;
+        NvU32  Timeslice;
+        NvBool sendACT;          // deprecated -Use NV0073_CTRL_CMD_DP_SEND_ACT
+        NvU32  singleHeadMSTPipeline;
+        NvBool bEnableAudioOverRightPanel;
+    } MST;
+
+    struct {
+        NvBool bEnhancedFraming;
+        NvU32  tuSize;
+        NvU32  waterMark;
+        NvU32  actualPclkHz;     // deprecated  -Use MvidWarParams
+        NvU32  linkClkFreqHz;    // deprecated  -Use MvidWarParams
+        NvBool bEnableAudioOverRightPanel;
+        struct {
+            NvU32  activeCnt;
+            NvU32  activeFrac;
+            NvU32  activePolarity;
+            NvBool mvidWarEnabled;
+            struct {
+                NvU32 actualPclkHz;
+                NvU32 linkClkFreqHz;
+            } MvidWarParams;
+        } Legacy;
+    } SST;
+} NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_DP_SET_RATE_GOV
+ *
+ * This command enables rate governing for a MST.
+ *
+ *      subDeviceInstance
+ *          This parameter specifies the subdevice instance within the
+ *          NV04_DISPLAY_COMMON parent device to which the operation should be
+ *          directed. This parameter must specify a value between zero and the
+ *          total number of subdevices within the parent device.  This parameter
+ *          should be set to zero for default behavior.
+ *      Head
+ *          Specifies the head index for the stream.
+ *      sorIndex
+ *          Specifies the SOR index for the stream.
+ *      flags
+ *          Specifies Rate Governing, trigger type and wait on trigger and operation type.
+ *
+ *     _FLAGS_OPERATION: whether this control call should program or check for status of previous operation.
+ *
+ *     _FLAGS_STATUS: Out only. Caller should check the status for _FLAGS_OPERATION_CHECK_STATUS through
+ *                    this bit.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC: when this command has already been called
+ *
+ */
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV (0x731363U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS_MESSAGE_ID (0x63U)
+
+typedef struct NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 head;
+    NvU32 sorIndex;
+    NvU32 flags;
+} NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS;
+
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG                0:0
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG_OFF          (0x00000000U)
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG_ON           (0x00000001U)
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE             1:1
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE_LOADV     (0x00000000U)
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE_IMMEDIATE (0x00000001U)
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER             2:2
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER_OFF       (0x00000000U)
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER_ON        (0x00000001U)
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION                3:3
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION_PROGRAM      (0x00000000U)
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION_CHECK_STATUS (0x00000001U)
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS                   31:31
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS_FAIL            (0x00000000U)
+#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS_PASS            (0x00000001U)
+
+/*
+ * NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT
+ *
+ *  This call is used by the displayport library.  Once
+ *  all of the platforms have ported, this call will be
+ *  deprecated and made the default behavior.
+ *
+ *   Disables automatic watermark programming
+ *   Disables automatic DP IRQ handling (CP IRQ)
+ *   Disables automatic retry on defers
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *
+ *
+ *  Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT                    (0x731365U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID (0x65U)
+
+typedef struct NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS {
+    NvU32 subDeviceInstance;
+} NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_DP_SET_ECF
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   sorIndex
+ *     This parameter specifies the Index of sor for which ecf
+ *     should be updated.
+ *   ecf
+ *      This parameter has the ECF bit mask.
+ *
+ *  Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV0073_CTRL_CMD_DP_SET_ECF (0x731366U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_ECF_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_SET_ECF_PARAMS_MESSAGE_ID (0x66U)
+
+typedef struct NV0073_CTRL_CMD_DP_SET_ECF_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  sorIndex;
+    NV_DECLARE_ALIGNED(NvU64 ecf, 8);
+    NvBool bForceClearEcf;
+    NvBool bAddStreamBack;
+} NV0073_CTRL_CMD_DP_SET_ECF_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_DP_SEND_ACT
+ *
+ * This command sends ACT.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *
+ *   displayId
+ *      Specifies the root port displayId for which the trigger has to be done.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC: when this command has already been called
+ *
+ */
+#define NV0073_CTRL_CMD_DP_SEND_ACT (0x731367U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS_MESSAGE_ID (0x67U)
+
+typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+} NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_CMD_DP_GET_CAPS
+ *
+ * This command returns the following info
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   sorIndex
+ *     Specifies the SOR index.
+ *   dpVersionsSupported
+ *     Specified the DP versions supported by the GPU
+ *   bIsMultistreamSupported
+ *     Returns NV_TRUE if MST is supported by the GPU else NV_FALSE
+ *   bIsSCEnabled
+ *     Returns NV_TRUE if Stream cloning is supported by the GPU else NV_FALSE
+ *   maxLinkRate
+ *     Returns Maximum allowed orclk for DP mode of SOR
+ *     1 signifies 5.40(HBR2), 2 signifies 2.70(HBR), 3 signifies 1.62(RBR)
+ *   bHasIncreasedWatermarkLimits
+ *     Returns NV_TRUE if the GPU uses higher watermark limits, else NV_FALSE
+ *   bIsPC2Disabled
+ *     Returns NV_TRUE if VBIOS flag to disable PostCursor2 is set, else NV_FALSE
+ *   bFECSupported
+ *     Returns NV_TRUE if GPU supports FEC, else NV_FALSE
+ *   bIsTrainPhyRepeater
+ *     Returns NV_TRUE if LTTPR Link Training feature is set
+ *   bOverrideLinkBw
+ *     Returns NV_TRUE if DFP limits defined in DCB have to be honored, else NV_FALSE
+ *
+ *   DSC caps -
+ *      bDscSupported
+ *          If GPU supports DSC or not
+ *
+ *      encoderColorFormatMask
+ *          Mask of all color formats for which DSC
+ *          encoding is supported by GPU
+ *
+ *      lineBufferSizeKB
+ *          Size of line buffer.
+ *
+ *      rateBufferSizeKB
+ *          Size of rate buffer per slice.
+ *
+ *      bitsPerPixelPrecision
+ *          Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp
+ *
+ *      maxNumHztSlices
+ *          Maximum number of horizontal slices supported by DSC encoder
+ *
+ *      lineBufferBitDepth
+ *          Bit depth used by the GPU to store the reconstructed pixels within
+ *          the line buffer
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_NOT_SUPPORTED
+ *
+ */
+
+#define NV0073_CTRL_CMD_DP_GET_CAPS   (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U)
+
+typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  sorIndex;
+    NvU32  maxLinkRate;
+    NvU32  dpVersionsSupported;
+    NvBool bIsMultistreamSupported;
+    NvBool bIsSCEnabled;
+    NvBool bHasIncreasedWatermarkLimits;
+    NvBool bIsPC2Disabled;
+    NvBool isSingleHeadMSTSupported;
+    NvBool bFECSupported;
+    NvBool bIsTrainPhyRepeater;
+    NvBool bOverrideLinkBw;
+
+    struct {
+        NvBool bDscSupported;
+        NvU32  encoderColorFormatMask;
+        NvU32  lineBufferSizeKB;
+        NvU32  rateBufferSizeKB;
+        NvU32  bitsPerPixelPrecision;
+        NvU32  maxNumHztSlices;
+        NvU32  lineBufferBitDepth;
+    } DSC;
+} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS;
+
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2                0:0
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO              (0x00000000U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES             (0x00000001U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4                1:1
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO              (0x00000000U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES             (0x00000001U)
+
+
+
+#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE                           2:0
+#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE                          (0x00000000U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62                          (0x00000001U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_2_70                          (0x00000002U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40                          (0x00000003U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10                          (0x00000004U)
+
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB                (0x00000001U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444        (0x00000002U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420 (0x00000008U)
+
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_16           (0x00000001U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_8            (0x00000002U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_4            (0x00000003U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2            (0x00000004U)
+#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1              (0x00000005U)
+
+#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES                                   (0x73136aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_LOW                     (0U)
+#define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_HIGH                    (1U)
+
+typedef struct NV0073_CTRL_DP_MSA_PROPERTIES_MASK {
+    NvU8   miscMask[2];
+    NvBool bRasterTotalHorizontal;
+    NvBool bRasterTotalVertical;
+    NvBool bActiveStartHorizontal;
+    NvBool bActiveStartVertical;
+    NvBool bSurfaceTotalHorizontal;
+    NvBool bSurfaceTotalVertical;
+    NvBool bSyncWidthHorizontal;
+    NvBool bSyncPolarityHorizontal;
+    NvBool bSyncHeightVertical;
+    NvBool bSyncPolarityVertical;
+    NvBool bReservedEnable[3];
+} NV0073_CTRL_DP_MSA_PROPERTIES_MASK;
+
+typedef struct NV0073_CTRL_DP_MSA_PROPERTIES_VALUES {
+    NvU8  misc[2];
+    NvU16 rasterTotalHorizontal;
+    NvU16 rasterTotalVertical;
+    NvU16 activeStartHorizontal;
+    NvU16 activeStartVertical;
+    NvU16 surfaceTotalHorizontal;
+    NvU16 surfaceTotalVertical;
+    NvU16 syncWidthHorizontal;
+    NvU16 syncPolarityHorizontal;
+    NvU16 syncHeightVertical;
+    NvU16 syncPolarityVertical;
+    NvU8  reserved[3];
+} NV0073_CTRL_DP_MSA_PROPERTIES_VALUES;
+
+#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID (0x6AU)
+
+typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS {
+    NvU32                                subDeviceInstance;
+    NvU32                                displayId;
+    NvBool                               bEnableMSA;
+    NvBool                               bStereoPhaseInverse;
+    NvBool                               bCacheMsaOverrideForNextModeset;
+    NV0073_CTRL_DP_MSA_PROPERTIES_MASK   featureMask;
+    NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues;
+    NV_DECLARE_ALIGNED(struct NV0073_CTRL_DP_MSA_PROPERTIES_VALUES *pFeatureDebugValues, 8);
+} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT
+ *
+ * This command can be used to invoke a fake interrupt for the operation of DP1.2 branch device
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   interruptType
+ *     This parameter specifies the type of fake interrupt to be invoked. Possible values are:
+ *     0 => IRQ
+ *     1 => HPDPlug
+ *     2 => HPDUnPlug
+ *   displayId
+ *     should be for DP only
+ *
+ */
+
+#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT (0x73136bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS_MESSAGE_ID (0x6BU)
+
+typedef struct NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 interruptType;
+} NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS;
+
+#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_IRQ    (0x00000000U)
+#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PLUG   (0x00000001U)
+#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_UNPLUG (0x00000002U)
+
+/*
+ * NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG
+ *
+ * This command sets the MS displayId lit up by driver for further use of VBIOS
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     should be for DP only
+ *   activeDevAddr
+ *     Active MS panel address
+ *   sorIndex
+ *     SOR Index
+ *   dpLink
+ *     DP Sub Link Index
+ *   hopCount
+ *     Maximum hopcounts in MS address
+ *   dpMsDevAddrState
+ *     DP Multistream Device Address State. The values can be
+ *
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_TIMEOUT
+ *
+ */
+#define NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG         (0x73136cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS_MESSAGE_ID (0x6CU)
+
+typedef struct NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 activeDevAddr;
+    NvU32 sorIndex;
+    NvU32 dpLink;
+    NvU32 hopCount;
+    NvU32 dpMsDevAddrState;
+} NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS;
+
+
+
+/*
+* NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT
+*
+* This command configures a new bit, NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT
+* to indicate which pipeline will handle the
+* time slots allocation in single head MST mode
+*
+*      subDeviceInstance
+*          This parameter specifies the subdevice instance within the
+*          NV04_DISPLAY_COMMON parent device to which the operation should be
+*          directed. This parameter must specify a value between zero and the
+*          total number of subdevices within the parent device.  This parameter
+*          should be set to zero for default behavior
+*      Head
+*          Specifies the head index for the stream
+*      sorIndex
+*          Specifies the SOR index for the stream
+*      streamIndex
+*          Stream Identifier
+*
+*
+* Possible status values returned are:
+*      NV_OK
+*      NV_ERR_INVALID_ARGUMENT
+*      NV_ERR_GENERIC: when this command has already been called
+*
+*/
+#define NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT (0x73136fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS_MESSAGE_ID (0x6FU)
+
+typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 head;
+    NvU32 sorIndex;
+    NvU32 singleHeadMSTPipeline;
+} NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS;
+
+/*
+* NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM
+*
+*  This call is used by the displayport library.& clients of RM
+*  Its main function is to configure single Head Multi stream mode
+ * this call configures internal RM datastructures to support required mode.
+*
+*   subDeviceInstance
+*     This parameter specifies the subdevice instance within the
+*     NV04_DISPLAY_COMMON parent device to which the operation should be
+*     directed. This parameter must specify a value between zero and the
+*     total number of subdevices within the parent device.  This parameter
+*     should be set to zero for default behavior.
+*
+*   displayIDs
+*     This parameter specifies array of DP displayIds to be configured which are driven out from a single head.
+*
+*   numStreams
+*     This parameter specifies number of streams driven from a single head
+*     ex: for 2SST & 2MST its value is 2.
+*
+*   mode
+*     This parameter specifies single head multi stream mode to be configured.
+*
+*   bSetConfigure
+*     This parameter configures single head multistream mode
+*     if TRUE it sets SST or MST based on 'mode' parameter and updates internal driver data structures with the given information.
+*     if FALSE clears the configuration of single head multi stream mode.
+*
+*   vbiosPrimaryDispIdIndex
+*    This parameter specifies vbios master displayID index in displayIDs input array.
+*
+*  Possible status values returned are:
+*   NV_OK
+*   NV_ERR_INVALID_ARGUMENT
+*   NV_ERR_NOT_SUPPORTED
+*
+*/
+#define NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM (0x73136eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MAX_STREAMS         (0x00000002U)
+#define NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS_MESSAGE_ID (0x6EU)
+
+typedef struct NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayIDs[NV0073_CTRL_CMD_DP_SINGLE_HEAD_MAX_STREAMS];
+    NvU32  numStreams;
+    NvU32  mode;
+    NvBool bSetConfig;
+    NvU8   vbiosPrimaryDispIdIndex;
+} NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS;
+
+#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_NONE     (0x00000000U)
+#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST (0x00000001U)
+#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST (0x00000002U)
+
+/*
+* NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL
+*
+* This command configures a new bit, NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL
+* to indicate which if all the pipelines to take affect on ACT (sorFlushUpdates)
+* in single head MST mode
+*
+*      subDeviceInstance
+*          This parameter specifies the subdevice instance within the
+*          NV04_DISPLAY_COMMON parent device to which the operation should be
+*          directed. This parameter must specify a value between zero and the
+*          total number of subdevices within the parent device.  This parameter
+*          should be set to zero for default behavior
+*      Head
+*          Specifies the head index for the stream
+*      sorIndex
+*          Specifies the SOR index for the stream
+*      streamIndex
+*          Stream Identifier
+*
+*
+* Possible status values returned are:
+*      NV_OK
+*      NV_ERR_INVALID_ARGUMENT
+*      NV_ERR_GENERIC: when this command has already been called
+*
+*/
+#define NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL                   (0x731370U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS_MESSAGE_ID (0x70U)
+
+typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  head;
+    NvBool enable;
+} NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS;
+
+
+
+/*
+* NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA
+*
+* This command collects the DP AUX log from the RM aux buffer and
+* sends it to the application.
+*
+*      dpAuxBufferReadSize
+*          Specifies the number of logs to be read from the
+*          AUX buffer in RM
+*      dpNumMessagesRead
+*          Specifies the number of logs read from the AUX buffer
+*      dpAuxBuffer
+*          The local buffer to copy the specified number of logs
+*          from RM to user application
+*
+*
+* Possible status values returned are:
+*      NV_OK
+*      NV_ERR_INVALID_ARGUMENT
+*      NV_ERR_GENERIC: when this command has already been called
+*
+*
+*DPAUXPACKET - This structure holds the log information
+* auxPacket - carries the hex dump of the message transaction
+* auxEvents - Contains the information as in what request and reply type where
+* auxRequestTimeStamp - Request timestamp
+* auxMessageReqSize - Request Message size
+* auxMessageReplySize - Reply message size(how much information was actually send by receiver)
+* auxOutPort - DP port number
+* auxPortAddress - Address to which data was requested to be read or written
+* auxReplyTimeStamp - Reply timestamp
+* auxCount - Serial number to keep track of transactions
+*/
+
+/*Maximum dp messages size is 16 as per the protocol*/
+#define DP_MAX_MSG_SIZE                          16U
+#define MAX_LOGS_PER_POLL                        50U
+
+/* Various kinds of DP Aux transactions */
+#define NV_DP_AUXLOGGER_REQUEST_TYPE                     3:0
+#define NV_DP_AUXLOGGER_REQUEST_TYPE_NULL        0x00000000U
+#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CWR       0x00000001U
+#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CREQWSTAT 0x00000002U
+#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTWR       0x00000003U
+#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTREQWSTAT 0x00000004U
+#define NV_DP_AUXLOGGER_REQUEST_TYPE_AUXWR       0x00000005U
+#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CRD       0x00000006U
+#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTRD       0x00000007U
+#define NV_DP_AUXLOGGER_REQUEST_TYPE_AUXRD       0x00000008U
+#define NV_DP_AUXLOGGER_REQUEST_TYPE_UNKNOWN     0x00000009U
+
+#define NV_DP_AUXLOGGER_REPLY_TYPE                       7:4
+#define NV_DP_AUXLOGGER_REPLY_TYPE_NULL          0x00000000U
+#define NV_DP_AUXLOGGER_REPLY_TYPE_SB_ACK        0x00000001U
+#define NV_DP_AUXLOGGER_REPLY_TYPE_RETRY         0x00000002U
+#define NV_DP_AUXLOGGER_REPLY_TYPE_TIMEOUT       0x00000003U
+#define NV_DP_AUXLOGGER_REPLY_TYPE_DEFER         0x00000004U
+#define NV_DP_AUXLOGGER_REPLY_TYPE_DEFER_TO      0x00000005U
+#define NV_DP_AUXLOGGER_REPLY_TYPE_ACK           0x00000006U
+#define NV_DP_AUXLOGGER_REPLY_TYPE_ERROR         0x00000007U
+#define NV_DP_AUXLOGGER_REPLY_TYPE_UNKNOWN       0x00000008U
+
+#define NV_DP_AUXLOGGER_EVENT_TYPE                       9:8
+#define NV_DP_AUXLOGGER_EVENT_TYPE_AUX           0x00000000U
+#define NV_DP_AUXLOGGER_EVENT_TYPE_HOT_PLUG      0x00000001U
+#define NV_DP_AUXLOGGER_EVENT_TYPE_HOT_UNPLUG    0x00000002U
+#define NV_DP_AUXLOGGER_EVENT_TYPE_IRQ           0x00000003U
+
+#define NV_DP_AUXLOGGER_AUXCTL_CMD                       15:12
+#define NV_DP_AUXLOGGER_AUXCTL_CMD_INIT          0x00000000U
+#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CWR         0x00000000U
+#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CRD         0x00000001U
+#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CREQWSTAT   0x00000002U
+#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTWR         0x00000004U
+#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTRD         0x00000005U
+#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTREQWSTAT   0x00000006U
+#define NV_DP_AUXLOGGER_AUXCTL_CMD_AUXWR         0x00000008U
+#define NV_DP_AUXLOGGER_AUXCTL_CMD_AUXRD         0x00000009U
+
+
+typedef struct DPAUXPACKET {
+    NvU32 auxEvents;
+    NvU32 auxRequestTimeStamp;
+    NvU32 auxMessageReqSize;
+    NvU32 auxMessageReplySize;
+    NvU32 auxOutPort;
+    NvU32 auxPortAddress;
+    NvU32 auxReplyTimeStamp;
+    NvU32 auxCount;
+    NvU8  auxPacket[DP_MAX_MSG_SIZE];
+} DPAUXPACKET;
+typedef struct DPAUXPACKET *PDPAUXPACKET;
+
+#define NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA (0x731373U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS_MESSAGE_ID (0x73U)
+
+typedef struct NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS {
+    //In
+    NvU32       subDeviceInstance;
+    NvU32       dpAuxBufferReadSize;
+
+    //Out
+    NvU32       dpNumMessagesRead;
+    DPAUXPACKET dpAuxBuffer[MAX_LOGS_PER_POLL];
+} NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS;
+
+
+
+
+/* NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES
+ *
+ * This setup link rate table for target display to enable indexed link rate
+ * and export valid link rates back to client. Client may pass empty table to
+ * reset previous setting.
+ *
+ * subDeviceInstance
+ *    client will give a subdevice to get right pGpu/pDisp for it
+ * displayId
+ *    DisplayId of the display for which the client targets
+ * linkRateTbl
+ *    Link rates in 200KHz as native granularity from eDP 1.4
+ * linkBwTbl
+ *    Link rates in 270MHz and valid for client to apply to
+ * linkBwCount
+ *    Total valid link rates
+ *
+ * Possible status values returned include:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES (0x731377U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES        8U
+
+#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID (0x77U)
+
+typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS {
+    // In
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES];
+
+    // Out
+    NvU8  linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES];
+    NvU8  linkBwCount;
+} NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS;
+
+
+/*
+ * NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES
+ *
+ * This command is used to not depend on supervisor interrupts for setting the
+ * stereo msa params. We will not cache the values and can toggle stereo using
+ * this ctrl call on demand. Note that this control call will only change stereo
+ * settings and will leave other settings as is.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     should be for DP only
+ *   bEnableMSA
+ *     To enable or disable MSA
+ *   bStereoPhaseInverse
+ *     To enable or disable Stereo Phase Inverse value
+ *   featureMask
+ *     Enable/Disable mask of individual MSA property.
+ *   featureValues
+ *     MSA property value to write
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_NOT_SUPPORTED
+ *      NV_ERR_TIMEOUT
+ *
+ */
+#define NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES (0x731378U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS_MESSAGE_ID (0x78U)
+
+typedef struct NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS {
+    NvU32                                subDeviceInstance;
+    NvU32                                displayId;
+    NvBool                               bEnableMSA;
+    NvBool                               bStereoPhaseInverse;
+    NV0073_CTRL_DP_MSA_PROPERTIES_MASK   featureMask;
+    NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues;
+} NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_CMD_DP_CONFIGURE_FEC
+ *
+ * This command is used to enable/disable FEC on DP Mainlink.
+ * FEC is a prerequisite to DSC. This should be called only
+ * after LT completes (including PostLT LQA) while enabling.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *
+ *   displayId
+ *     Can only be 1 and must be DP.
+ *
+ *   bEnableFec
+ *     To enable or disable FEC
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV0073_CTRL_CMD_DP_CONFIGURE_FEC (0x73137aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS_MESSAGE_ID (0x7AU)
+
+typedef struct NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvBool bEnableFec;
+} NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior
+ *   cmd
+ *     This parameter is an input to this command.
+ *     Here are the current defined fields:
+ *       NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER
+ *         Set to specify what operation to run.
+ *           NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_UP
+ *             Request to power up pad.
+ *           NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_DOWN
+ *             Request to power down the pad.
+ *   linkBw
+ *     This parameter is used to pass in the link bandwidth required to run the
+ *     power up sequence. Refer enum DP_LINK_BANDWIDTH for valid values.
+ *   laneCount
+ *     This parameter is used to pass the lanecount.
+ *   sorIndex
+ *     This parameter is used to pass the SOR index.
+ *   sublinkIndex
+ *     This parameter is used to pass the sublink index. Please refer
+ *     enum DFPLINKINDEX for valid values
+ *   priPadLinkIndex
+ *     This parameter is used to pass the padlink index for primary link.
+ *     Please refer enum DFPPADLINK for valid index values for Link A~F.
+ *   secPadLinkIndex
+ *     This parameter is used to pass the padlink index for secondary link.
+ *     For Single SST pass in NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PADLINK_INDEX_INVALID
+ *   bEnableSpread
+ *     This parameter is boolean value used to indicate if spread is to be enabled or disabled.
+ */
+
+#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD (0x73137bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID (0x7BU)
+
+typedef struct NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  cmd;
+    NvU32  linkBw;
+    NvU32  laneCount;
+    NvU32  sorIndex;
+    NvU32  sublinkIndex;          // sublink A/B
+    NvU32  priPadLinkIndex;       // padlink A/B/C/D/E/F
+    NvU32  secPadLinkIndex;       // padlink A/B/C/D/E/F for secondary link in DualSST case.
+    NvBool bEnableSpread;
+} NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS;
+
+#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER                        0:0
+#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_UP          (0x00000000U)
+#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_DOWN        (0x00000001U)
+
+#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PADLINK_INDEX_INVALID (0x000000FFU)
+
+/*
+ * NV0073_CTRL_CMD_DP_AUXCH_CTRL
+ *
+ * This command can be used to perform the I2C Bulk transfer over
+ * DP Aux channel. This is the display port specific implementation
+ * for sending bulk data over the DpAux channel, by splitting up the
+ * data into pieces and retrying for pieces that aren't ACK'd.
+ *
+ *   subDeviceInstance [IN]
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId [IN]
+ *     This parameter specifies the ID of the display for which the dfp
+ *     caps should be returned.  The display ID must a dfp display.
+ *     If more than one displayId bit is set or the displayId is not a dfp,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   addr [IN]
+ *     This parameter is an input to this command.  The addr parameter follows
+ *     Section 2.4 in DisplayPort spec and the client should refer to the valid
+ *     address in DisplayPort spec.  Only the first 20 bits are valid.
+ *   bWrite [IN]
+ *     This parameter specifies whether the command is a I2C write (NV_TRUE) or
+ *     a I2C read (NV_FALSE).
+ *   data [IN/OUT]
+ *     In the case of a read transaction, this parameter returns the data from
+ *     transaction request.  In the case of a write transaction, the client
+ *     should write to this buffer for the data to send.
+ *   size [IN/OUT]
+ *     Specifies how many data bytes to read/write depending on the
+ *     transaction type.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_DP_AUXCH_I2C_TRANSFER_CTRL                (0x73137cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE           256U
+
+#define NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS_MESSAGE_ID (0x7CU)
+
+typedef struct NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvU32  addr;
+    NvBool bWrite;
+    NvU8   data[NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE];
+    NvU32  size;
+} NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_DP_ENABLE_VRR
+ *
+ * The command is used to enable VRR.
+ *
+ *   subDeviceInstance [IN]
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior
+ *   displayId [IN]
+ *     This parameter is an input to this command, specifies the ID of the display
+ *     for client targeted to.
+ *     The display ID must a DP display.
+ *     If more than one displayId bit is set or the displayId is not a DP,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   cmd [IN]
+ *     This parameter is an input to this command.
+ *
+ *      _STAGE: specifies the stage id to execute in the VRR enablement sequence.
+ *        _MONITOR_ENABLE_BEGIN:      Send command to the monitor to start monitor
+ *                                    enablement procedure.
+ *        _MONITOR_ENABLE_CHALLENGE:  Send challenge to the monitor
+ *        _MONITOR_ENABLE_CHECK:      Read digest from the monitor, and verify
+ *                                    if the result is valid.
+ *        _DRIVER_ENABLE_BEGIN:       Send command to the monitor to start driver
+ *                                    enablement procedure.
+ *        _DRIVER_ENABLE_CHALLENGE:   Read challenge from the monitor and write back
+ *                                    corresponding digest.
+ *        _DRIVER_ENABLE_CHECK:       Check if monitor enablement worked.
+ *        _RESET_MONITOR:             Set the FW state m/c to a known state.
+ *        _INIT_PUBLIC_INFO:          Send command to the monitor to prepare public info.
+ *        _GET_PUBLIC_INFO:           Read public info from the monitor.
+ *        _STATUS_CHECK:              Check if monitor is ready for next command.
+ *   result [OUT]
+ *     This is an output parameter to reflect the result of the operation.
+ */
+#define NV0073_CTRL_CMD_DP_ENABLE_VRR (0x73137dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS_MESSAGE_ID (0x7DU)
+
+typedef struct NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 cmd;
+    NvU32 result;
+} NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS;
+
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE                                   3:0
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_BEGIN     (0x00000000U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHALLENGE (0x00000001U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHECK     (0x00000002U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_BEGIN      (0x00000003U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHALLENGE  (0x00000004U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHECK      (0x00000005U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_RESET_MONITOR            (0x00000006U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_INIT_PUBLIC_INFO         (0x00000007U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_GET_PUBLIC_INFO          (0x00000008U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_STATUS_CHECK             (0x00000009U)
+
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_OK                          (0x00000000U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_PENDING                     (0x80000001U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_READ_ERROR                  (0x80000002U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_WRITE_ERROR                 (0x80000003U)
+#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_DEVICE_ERROR                (0x80000004U)
+
+/*
+ * NV0073_CTRL_CMD_DP_GET_GENERIC_INFOFRAME
+ *
+ * This command is used to capture the display output packets for DP protocol.
+ * Common supported packets are Dynamic Range and mastering infoframe SDP for HDR,
+ * VSC SDP for colorimetry and pixel encoding info.
+ *
+ *   displayID (in)
+ *     This parameter specifies the displayID for the display resource to configure.
+ *   subDeviceInstance (in)
+ *     This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON
+ *     parent device to which the operation should be directed.
+ *   infoframeIndex (in)
+ *     HW provides support to program 2 generic infoframes per frame for DP.
+ *     This parameter indicates which infoframe packet is to be captured.
+ *     Possible flags are as follows:
+ *       NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE
+ *         This flag indicates the INFOFRAME that needs to be read.
+ *         Set to _INFOFRAME0 if RM should read GENERIC_INFOFRAME
+ *         Set to _INFOFRAME1 if RM should read GENERIC_INFOFRAME1
+ *   packet (out)
+ *     pPacket points to the memory for reading the infoframe packet.
+ *   bTransmitControl (out)
+ *     This gives the transmit mode of infoframes.
+ *       If set, means infoframe will be sent as soon as possible and then on
+ *       every frame during vblank.
+ *       If cleared, means the infoframe will be sent once as soon as possible.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_DP_GET_GENERIC_INFOFRAME                         (0x73137eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_GENERIC_INFOFRAME_MAX_PACKET_SIZE                 36U
+
+#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS_MESSAGE_ID (0x7EU)
+
+typedef struct NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvU32  infoframeIndex;
+    NvU8   packet[NV0073_CTRL_DP_GENERIC_INFOFRAME_MAX_PACKET_SIZE];
+    NvBool bTransmitControl;
+} NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS;
+
+
+#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE                       0:0
+#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE_INFOFRAME0 (0x0000000U)
+#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE_INFOFRAME1 (0x0000001U)
+
+
+/*
+ * NV0073_CTRL_CMD_DP_GET_MSA_ATTRIBUTES
+ *
+ * This command is used to capture the various data attributes sent in the MSA for DP protocol.
+ * Refer table 2-94 'MSA Data Fields' in DP1.4a spec document for MSA data field description.
+ *
+ *   displayID (in)
+ *     This parameter specifies the displayID for the display resource to configure.
+ *   subDeviceInstance (in)
+ *     This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON
+ *     parent device to which the operation should be directed.
+ *   mvid, nvid (out)
+ *     Video timestamp used by DP sink for regenerating pixel clock.
+ *   misc0, misc1 (out)
+ *     Miscellaneous MSA attributes.
+ *   hTotal, vTotal (out)
+ *     Htotal measured in pixel count and vtotal measured in line count.
+ *   hActiveStart, vActiveStart (out)
+ *     Active start measured from start of leading edge of the sync pulse.
+ *   hActiveWidth, vActiveWidth (out)
+ *     Active video width and height.
+ *   hSyncWidth, vSyncWidth (out)
+ *     Width of sync pulse.
+ *   hSyncPolarity, vSyncPolarity (out)
+ *     Polarity of sync pulse.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_DP_GET_MSA_ATTRIBUTES                        (0x73137fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_DP_MSA_MAX_DATA_SIZE                             7U
+
+#define NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS_MESSAGE_ID (0x7FU)
+
+typedef struct NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvU32  mvid;
+    NvU32  nvid;
+    NvU8   misc0;
+    NvU8   misc1;
+    NvU16  hTotal;
+    NvU16  vTotal;
+    NvU16  hActiveStart;
+    NvU16  vActiveStart;
+    NvU16  hActiveWidth;
+    NvU16  vActiveWidth;
+    NvU16  hSyncWidth;
+    NvU16  vSyncWidth;
+    NvBool hSyncPolarity;
+    NvBool vSyncPolarity;
+} NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS;
+
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MVID                              23:0
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_NVID                              23:0
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MISC0                              7:0
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MISC1                             15:8
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HTOTAL                            15:0
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VTOTAL                           31:16
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HACTIVE_START                     15:0
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VACTIVE_START                    31:16
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HACTIVE_WIDTH                     15:0
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VACTIVE_WIDTH                    31:16
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HSYNC_WIDTH                       14:0
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HSYNC_POLARITY                   15:15
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VSYNC_WIDTH                      30:16
+#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VSYNC_POLARITY                   31:31
+
+/*
+ * NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL
+ *
+ * This command is used to query OD capability and status as well as
+ * control OD functionality of eDP LCD panels.
+ *
+ *   subDeviceInstance [in]
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId [in]
+ *     This parameter specifies the ID of the DP display which owns
+ *     the Main Link to be adjusted.  The display ID must a DP display
+ *     as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
+ *     If more than one displayId bit is set or the displayId is not a DP,
+ *     this call will return NV_ERR_INVALID_ARGUMENT.
+ *   cmd [in]
+ *     This parameter is an input to this command.  The cmd parameter tells
+ *     whether we have to get the value of a specific field or set the
+ *     value in case of a writeable field.
+ *   control [in]
+ *     This parameter is input by the user. It is used by the user to decide the control
+ *     value to be written to change the Sink OD mode. The command to write is
+ *     the NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET command.
+ *   bOdCapable [out]
+ *     This parameter reflects the OD capability of the Sink which can be
+ *     fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_CAPABLE_QUERY command.
+ *   bOdControlCapable [out]
+ *     This parameter reflects the OD control capability of the Sink which can be
+ *     fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_CAPABLE_QUERY command.
+ *   bOdStatus [out]
+ *     This parameter reflects the Sink OD status which can be
+ *     fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_STATUS_QUERY command.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL (0x731380U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS_MESSAGE_ID (0x80U)
+
+typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvU8   control;
+    NvU8   cmd;
+    NvBool bOdCapable;
+    NvBool bOdControlCapable;
+    NvBool bOdStatus;
+} NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS;
+
+/* valid commands */
+#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CAPABLE       0x00000000
+#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CTL_CAPABLE   0x00000001
+#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_STATUS        0x00000002
+#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET            0x00000003
+
+/* valid state values */
+#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_AUTONOMOUS 0x00000000
+#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_DISABLE_OD 0x00000002
+#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_ENABLE_OD  0x00000003
+
+/*
+ * NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES
+ *
+ * This command returns the following info
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     should be for DP only
+ *   bEnableMSA
+ *     To enable or disable MSA
+ *   bStereoPhaseInverse
+ *     To enable or disable Stereo Phase Inverse value
+ *   bCacheMsaOverrideForNextModeset
+ *     Cache the values and don't apply them until next modeset
+ *   featureMask
+ *     Enable/Disable mask of individual MSA property
+ *   featureValues
+ *     MSA property value to write
+ *   bDebugValues
+ *     To inform whether actual MSA values need to be returned
+ *   pFeatureDebugValues
+ *     It will actual MSA property value being written on HW.
+ *     If its NULL then no error but return nothing
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_NOT_SUPPORTED
+ *      NV_ERR_TIMEOUT
+ *
+ */
+#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2 (0x731381U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID (0x81U)
+
+typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS {
+    NvU32                                subDeviceInstance;
+    NvU32                                displayId;
+    NvBool                               bEnableMSA;
+    NvBool                               bStereoPhaseInverse;
+    NvBool                               bCacheMsaOverrideForNextModeset;
+    NV0073_CTRL_DP_MSA_PROPERTIES_MASK   featureMask;
+    NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues;
+    NvBool                               bDebugValues;
+    NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues;
+} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS;
+/* _ctrl0073dp_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h
new file mode 100644
index 0000000..1ac3e6f
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073dpu.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h
new file mode 100644
index 0000000..a2423a8
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073event.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
new file mode 100644
index 0000000..2b4965d
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073internal.finn
+//
+
+#include "ctrl/ctrl0073/ctrl0073base.h"
+#include "ctrl/ctrl0073/ctrl0073system.h"
+
+#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID" */
+
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS {
+    NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS params;
+} NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS;
+
+
+/* ctrl0073internal_h */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h
new file mode 100644
index 0000000..7ac6f6e
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073psr.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
new file mode 100644
index 0000000..74ace22
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
@@ -0,0 +1,1909 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073specific.finn
+//
+
+#include "ctrl/ctrl0073/ctrl0073base.h"
+
+#include "ctrl/ctrlxxxx.h"
+/* NV04_DISPLAY_COMMON display-specific control commands and parameters */
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_TYPE
+ *
+ * This command can be used to determine the associated display type for
+ * the specified displayId.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should  be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the display
+ *     type is to be returned. Only one display may be indicated in this
+ *     parameter.
+ *   displayType
+ *     This parameter returns the display type associated with the specified
+ *     displayId parameter.  Valid displayType values are:
+ *       NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT
+ *       NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP
+ *       NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_TV
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_GET_TYPE (0x730240U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS_MESSAGE_ID (0x40U)
+
+typedef struct NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 displayType;
+} NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS;
+
+/* valid display types */
+#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_UNKNOWN    (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT        (0x00000001U)
+#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP        (0x00000002U)
+#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_TV         (0x00000003U)
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2
+ *
+ * This command can be used to request the EDID for the specified displayId.
+ *
+ *   [in] subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the total
+ *     number of subdevices within the parent device.  This parameter should
+ *     be set to zero for default behavior.
+ *   [in] displayId
+ *     This parameter specifies the display to read the EDID. The display ID
+ *     must specify a display with a positive connect state as determined
+ *     with the NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE command.  Only one
+ *     display may be indicated in this parameter.  If a more than one
+ *     display Id is used, the RM will return NV_ERR_INVALID_ARGUMENT.
+ *   [out] bufferSize
+ *     This parameter returns the number of bytes copied into edidBuffer after
+ *     performing the requested EDID operations.
+ *   [out] edidBuffer
+ *     The array of EDIDs that RM will fill after the requested operations. If
+ *     the size of the array is not large enough to hold the number of bytes to
+ *     be copied, NV_ERR_INVALID_ARGUMENT will be returned.
+ *   [in] flags
+ *     This parameter defines the specific operations that will be performed
+ *     in reading the EDID.
+ *     Here are the current defined fields:
+ *       NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE
+ *         A client uses this field to indicate whether to return the cached
+ *         copy of the EDID or to use DDC to read the EDID from the display.
+ *         Possible values are:
+ *           NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_NO
+ *             The RM will use DDC to grab the EDID.
+ *           NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_YES
+ *             The RM will copy the last EDID found into the clients
+ *             buffer.  No DDC will be performed.
+ *       NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE
+ *         A client uses this field to indicate whether to read from
+ *         the HW and return the EDID w/o any patching
+ *         Possible values are:
+ *           NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_COOKED
+ *             Use the _COPY_CACHE policy
+ *           NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_RAW
+ *             Perform the read and return an unadulterated EDID.
+ *       NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE
+ *         A client uses this field to indicate whether to read EDID
+ *         from SBIOS using ACPI sub function for display dynamic switching 
+ *         feature. This flag should only be set on internal display with 
+ *         dynamic switching feature enabled.
+ *         Possible values are:
+ *           NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_ACPI
+ *             RM reads the EDID from SBIOS and returns the raw EDID provided
+ *             by SBIOS.
+ *           NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_DEFAULT
+ *             EDID is read based on rest of the 'flags' that are passed to
+ *             this function.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2         (0x730245U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES 2048U
+
+#define NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID (0x45U)
+
+typedef struct NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 bufferSize;
+    NvU32 flags;
+    NvU8  edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES];
+} NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE                           0:0
+#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_NO             0x00000000U
+#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_YES            0x00000001U
+
+#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE                            1:1
+#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_COOKED          0x00000000U
+#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_RAW             0x00000001U
+
+#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE                    3:2
+#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_DEFAULT 0x00000000U
+#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_ACPI    0x00000001U
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_SET_EDID_V2
+ *
+ * This command can be used to set or remove a complete EDID for the
+ * specified displayId.  Once the EDID is set, any requests
+ * to read the EDID or use DDC detection will always use a cached copy of
+ * the EDID.  That is, the EDID becomes static until disabled by calling
+ * this same function with edidBuffer.  Note, that DDC based
+ * detection will always pass for any displayId that has set an EDID. Also,
+ * this path will not store any value across reboots.  If an EDID needs to
+ * remain set after a reboot, RM clients must call this function again.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the total
+ *     number of subdevices within the parent device.  This parameter should
+ *     be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the display to store or the EDID.  Only one
+ *     display may be indicated in this parameter.  If more than one displayId
+ *     is used, the RM will return NV_ERR_INVALID_ARGUMENT.
+ *     If the displayId does not use DDC and hence would not have an EDID,
+ *     then the RM could also return NV_ERR_INVALID_ARGUMENT.
+ *   bufferSize
+ *     This parameter specifies the size of the EDID buffer pointed to by
+ *     pEdidBuffer.  If the EDID write contains more bytes than bufferSize,
+ *     the RM will extend the bufferSize of the EDID inside the RM to match.
+ *     Note a bufferSize of 0 would mean no bytes will be copied, but set the
+ *     current cached EDID as static.
+ *   edidBuffer
+ *     This parameter specifies the EDID buffer that the RM will copy into
+ *     the RM buffer. If the EDID buffer is empty, the RM will remove any
+ *     previous set EDID and allow further detection and EDID reads to use DDC.
+ *     The RM will not check to see if the EDID is valid here or not.
+ *     The client should validate the EDID if needed before calling this function.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+
+#define NV0073_CTRL_CMD_SPECIFIC_SET_EDID_V2                          (0x730246U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS_MESSAGE_ID (0x46U)
+
+typedef struct NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 bufferSize;
+    NvU8  edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES];
+} NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE
+ *
+ * This Control Cmd is for providing the Faking device(s) support from RM.
+ * This command serves as the entry point for all interaction of RM with
+ * user mode component of the any internal [test] tool. The Faking framework
+ * in RM will be activated only after the usermode app sends in a proper ENABLE
+ * cmd first. Any attempt to issue other cmds while the faking code has not
+ * been enabled will result in RM err _INVALID_DATA.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the total
+ *     number of subdevices within the parent device.  This parameter should
+ *     be set to zero for default behavior.
+ *   cmd
+ *     This field will carry the command to be executed by the framework.
+ *     This includes Enabling/Disabling the test framework and faking devices
+ *     like CRT/DVI/TV.
+ *   data
+ *     This field is to carry the data required for executing the cmd.
+ *     Except for Enable and Disable, the other faking device commands will
+ *     require the device mask of the device to be faked/removed.
+ *   tvType
+ *     This field specifies a specific TV type while faking a TV.
+ *     Possible values are:
+ *       NV0073_FAKE_DEVICE_TV_NONE
+ *       NV0073_FAKE_DEVICE_TV_SVIDEO
+ *       NV0073_FAKE_DEVICE_TV_COMPOSITE
+ *       NV0073_FAKE_DEVICE_TV_COMPONENT
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_DATA
+ *
+ */
+
+#define NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE (0x730243U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS_MESSAGE_ID" */
+
+/* valid fake device TV connector types */
+#define NV0073_FAKE_DEVICE_TV_NONE           (0U)
+#define NV0073_FAKE_DEVICE_TV_SVIDEO         (1U)
+#define NV0073_FAKE_DEVICE_TV_COMPOSITE      (2U)
+#define NV0073_FAKE_DEVICE_TV_COMPONENT      (3U)
+
+#define NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS_MESSAGE_ID (0x43U)
+
+typedef struct NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 cmd;
+    NvU32 data;
+    NvU32 tvType;
+} NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS;
+
+/* Faking Support commands */
+/* some random value to enable/disable test code */
+#define NV0073_FAKE_DEVICE_SUPPORT_ENABLE                       0x11faU
+#define NV0073_FAKE_DEVICE_SUPPORT_DISABLE                      0x99ceU
+#define NV0073_FAKE_DEVICE_SUPPORT_ATTACH_DEVICES               0x100U
+#define NV0073_FAKE_DEVICE_SUPPORT_REMOVE_DEVICES               0x101U
+
+
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID
+ *
+ * This command returns the I2C portID for the specified display device.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the display for which information is to be
+ *     returned.  Only one display may be indicated in this parameter.
+ *     If more than one displayId is used a failing status of
+ *     NV_ERR_INVALID_ARGUMENT will be returned.
+ *   commPortId
+ *      This parameter returns the I2C communication port ID of the
+ *      display device indicated by the displayId parameter.
+ *   ddcPortId
+ *      This parameter returns the I2C DDC port ID of the display device
+ *      indicated by the displayId parameter.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID                        (0x730211U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 commPortId;
+    NvU32 ddcPortId;
+} NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_I2C_PORT_NONE            (0x0U)
+
+
+
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA
+ *
+ * This command can be used to get display connector data.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the display for which information is to be
+ *     returned.  Only one display may be indicated in this parameter.
+ *     If more than one displayId is used a failing status of
+ *     NV_ERR_INVALID_ARGUMENT will be returned.
+ *   DDCPartners
+ *     This parameter specifies an NV0073_DISPLAY_MASK value describing
+ *     the set of displays that share the same DDC line as displayId.  This
+ *     parameter will always be returned even if we also return the
+ *     NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_NO flag.
+ *   flags
+ *     This parameter specifies optional flags to be used while retrieving
+ *     the connector data for a given displayId.
+ *     Legal values for this parameter include:
+ *       NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT
+ *         This flag describes whether the connector data is present
+ *         inside the firmware.
+ *   count
+ *     This parameter returns the number of connectors associated with
+ *     the displayId argument.  This value indicates the number of
+*      valid entries returned in the data parameter.
+ *   data
+ *     This parameter returns an array of structures containing the connector
+ *     data associated with each connector for the given displayId argument.
+ *     The count field specifies how many entries in this array are returned.
+ *     Each entry in the array contains the following members:
+ *       index
+ *         This value is the index associated with the given connector. If
+ *         two displayIds share the same index, then they share the same
+ *         connector.
+ *       type
+ *         This value defines the type of connector associated with the
+ *         displayId argument.
+ *       location
+ *         This value provides a possible means to determine the relative
+ *         location of the connector in association to other connectors.
+ *         For desktop boards, a value of zero defines the south most
+ *         connector (the connector closest to the bus slot into which
+ *         the board is inserted).
+ *   platform
+ *     This value defines the type of system with which to associate the
+ *     location of each connector.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+
+#define NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA   (0x730250U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID" */
+
+/* maximum number of connectors */
+#define NV0073_CTRL_MAX_CONNECTORS                    4U
+
+#define NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID (0x50U)
+
+typedef struct NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 flags;
+    NvU32 DDCPartners;
+    NvU32 count;
+    struct {
+        NvU32 index;
+        NvU32 type;
+        NvU32 location;
+    } data[NV0073_CTRL_MAX_CONNECTORS];
+    NvU32 platform;
+} NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS;
+
+/* defines for the flags field */
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT            0:0
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_NO                           0x00000000U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_YES                          0x00000001U
+
+/* defines for the data[].type field */
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_VGA_15_PIN                            0x00000000U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_COMPOSITE                          0x00000010U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_SVIDEO                             0x00000011U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_HDTV_COMPONENT                     0x00000013U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_SCART                              0x00000014U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_COMPOSITE_SCART_OVER_EIAJ4120_BLUE 0x00000016U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_HDTV_EIAJ4120                      0x00000017U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_HDTV_YPRPB                     0x00000018U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_SVIDEO                         0x00000019U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_COMPOSITE                      0x0000001AU
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I_TV_SVIDEO                       0x00000020U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I_TV_COMPOSITE                    0x00000021U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I                                 0x00000030U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_D                                 0x00000031U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_ADC                                   0x00000032U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DVI_I_1                           0x00000038U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DVI_I_2                           0x00000039U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_SPWG                                  0x00000040U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_OEM                                   0x00000041U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_EXT                                0x00000046U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_INT                                0x00000047U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_MINI_EXT                           0x00000048U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_SERIALIZER                         0x00000049U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_HDMI_A                                0x00000061U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_HDMI_C_MINI                           0x00000063U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DP_1                              0x00000064U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DP_2                              0x00000065U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_VIRTUAL_WFD                           0x00000070U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_USB_C                                 0x00000071U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DSI                                   0x00000072U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_STEREO_3PIN_DIN                       0x00000073U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_UNKNOWN                               0xFFFFFFFFU
+
+/* defines for the platform field */
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_DEFAULT_ADD_IN_CARD                    0x00000000U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_TWO_PLATE_ADD_IN_CARD                  0x00000001U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_CONFIGURABLE                           0x00000002U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_DESKTOP_FULL_DP                        0x00000007U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_ADD_IN_CARD                     0x00000008U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MXM                                    0x00000009U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK                            0x00000010U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK_LEFT                       0x00000011U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK_DOCK                       0x00000018U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_CRUSH_DEFAULT                          0x00000020U
+#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_UNKNOWN                                0xFFFFFFFFU
+
+
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE
+ *
+ * This command is used to signal the resource manager that the upcoming mode
+ * shall be hdmi vs dvi.  This is required since the resource manager
+ * does not read the display edid. The resource manager shall enable hdmi
+ * components such as turning on the audio engine for instance.  This should
+ * be called prior to every modeset in which the displayId is capable of hdmi.
+ *   displayId
+ *     This parameter specifies the displayId of HDMI resource to configure.
+ *     This comes as input to this command.
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which operation should be directed.
+ *     This parameter must specify a value between zero and the total number
+ *     of subdevices within the parent device.  This parameter should be set
+ *     to zero for default behavior.
+ *   enable
+ *     This field specifies the legal values:
+ *       NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_TRUE
+ *       NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_FALSE
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE (0x730273U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID (0x73U)
+
+typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS {
+    NvU8  subDeviceInstance;
+    NvU32 displayId;
+    NvU8  enable;
+} NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_FALSE (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_TRUE  (0x00000001U)
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_CTRL_HDMI
+ *
+ * This command can be used to enable HDMI communication on the associated GPU.
+ * This should be called prior to every modeset in which the displayId is capable of HDMI.
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which operation should be directed.
+ *     This parameter must specify a value between zero and the total number
+ *     of subdevices within the parent device.  This parameter should be set
+ *     to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the displayId of HDMI resource to configure.
+ *     This comes as input to this command.
+ *   enable
+ *     This field specifies the legal values:
+ *       NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE
+ *       NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE
+ *
+ *  Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_CTRL_HDMI         (0x730274U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS_MESSAGE_ID (0x74U)
+
+typedef struct NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS {
+    NvU8   subDeviceInstance;
+    NvU32  displayId;
+    NvBool bEnable;
+} NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE             (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE              (0x00000001U)
+
+
+
+/*
+ * NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING
+ *
+ * This structure defines the mapping between the ACPI ID and the corresponding
+ * display ID of a display device
+ *
+ *     subDeviceInstance
+ *       This parameter specifies the subdevice instance within the
+ *       NV04_DISPLAY_COMMON parent device to which the operation should be
+ *       directed. This parameter must specify a value between zero and the
+ *       total number of subdevices within the parent device.  This parameter
+ *       should be set to zero for default behavior.
+ *     acpiId
+ *       The ACPI ID of the display device
+ *     displayId
+ *       The corresponding display ID
+ *     dodIndex
+ *       The corresponding DOD index
+ */
+typedef struct NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING {
+    NvU32 subDeviceInstance;
+    NvU32 acpiId;
+    NvU32 displayId;
+    NvU32 dodIndex;
+} NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING;
+
+/*
+ * NV0073_CTRL_CMD_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT
+ *
+ * This call will return the Display Port Attachment value
+ * per displayID as defined by Nvidia that is directly
+ * associated with the ACPI 3.0 _DOD entry's Display Port
+ * Attachment field.  This should help clients map the
+ * _DOD ACPI ID to each displayID. Note, that some systems
+ * do not have a standard in place for this field.  On those
+ * systems, the RM will return NV_ERR_NOT_SUPPORTED.
+ *
+ * Note that this "Display Port" attachment field has nothing
+ * to do with DisplayPort/DP.  It's an unfortunate name inside
+ * the ACPI 3.0 spec that coincides with the name of DisplayPort.
+ *
+ *
+ * Possible status values returned are:
+ * NV_OK
+ * NV_ERR_INVALID_PARAM_STRUCT
+ * NV_ERR_NOT_SUPPORTED
+ *
+*/
+
+#define NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID (0x85U)
+
+typedef struct NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 dispPortAttachment;
+} NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS;
+
+
+#define NV0073_CTRL_CMD_SPECIFIC_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT (0x730285U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID" */
+
+// defines for dispPortAttachment
+#define NV0073_DISPLAY_PORT_ATTACHMENT_ANALOG                         (0x00000000U)
+#define NV0073_DISPLAY_PORT_ATTACHMENT_LVDS                           (0x00000001U)
+#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_A                           (0x00000002U)
+#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_B                           (0x00000003U)
+#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_C                           (0x00000004U)
+#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_D                           (0x00000005U)
+#define NV0073_DISPLAY_PORT_ATTACHMENT_UNKNOWN                        (0xFFFFFFFFU)
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_SET_ACPI_ID_MAPPING
+ *
+ * This call will update the RM data structure which holds the
+ * ACPI ID to display ID mapping of the display devices
+ *
+ * The input parameter is an array of structures of type
+ * NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING
+ *
+ * If some of the array elements remain unused, the acpiId field of the
+ * structure must be set to 0x0000
+ *
+ * The size of the array is given by
+ * NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES (defined below)
+ *
+ * Possible status values returned are:
+ * NV_OK
+ * NV_ERR_INVALID_PARAM_STRUCT
+ *
+*/
+#define NV0073_CTRL_CMD_SPECIFIC_SET_ACPI_ID_MAPPING                  (0x730284U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES                         16U
+
+#define NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS_MESSAGE_ID (0x84U)
+
+typedef struct NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS {
+    NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING mapTable[NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES];
+} NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK
+ *
+ * This call will return all head mask.
+ *
+ *     subDeviceInstance
+ *       This parameter specifies the subdevice instance within the
+ *       NV04_DISPLAY_COMMON parent device to which the operation should be
+ *       directed. This parameter must specify a value between zero and the
+ *       total number of subdevices within the parent device. This parameter
+ *       should be set to zero for default behavior.
+ *     headMask
+ *       headMask is the mask of all heads that are usable. For example, if
+ *       head 0 and head 2 are present, headMask would be NVBIT(0)|NVBIT(2). This
+ *       parameter returns to the client.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK (0x730287U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID (0x87U)
+
+typedef struct NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 headMask;
+} NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET
+ *
+ * This command is used to program the display output packets.
+ * Currently it supports DP and HDMI.
+ * Common supported packets are AVI infoframes, Audio Infoframes, Gamma
+ * Metadata, Vendor Specific infoframes and General Control Packets (GCP).
+ * + GCP AVMute Enable should be performed before the start of the modeset.
+ * + GCP AVMute Disable should be performed after the end of the modeset.
+ *   GCP AVMute should contain HDR + 7 bytes.
+ * + AVI infoframes should occur after the modeset but before a GCP AVMute
+ *   Disable.  AVI infoframe should contain HDR + 14 bytes
+ * + Audio infoframes should occur after the modeset but before a GCP AVMute
+ *   Enable.
+ *   Audio infoframe should contain HDR + 11 bytes.
+ * + Gamma Metadata packets should contain HDR + 28 bytes.
+ * + Vendor Specific packets are variable length.
+ *   By HDMI 1.4 June 5 2009 spec, payload can be 5 bytes, 6 bytes, 7 bytes or
+ *   16 bytes, depending on the packets spec.
+ * Unused data bytes should be zero-ed out.
+ *
+ *   displayID
+ *     This parameter specifies the displayID for the display resource to
+ *     configure.
+ *     This comes as input to this command.
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *     This parameter must specify a value between zero and the total number
+ *     of subdevices within the parent device.  This parameter should be set
+ *     to zero for default behavior.
+ *   transmitControl
+ *     This parameter controls how the packet is to be sent by setting the
+ *     control bits.
+ *     Possible flags are as follows:
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE
+ *         Set to _ENABLE to start sending the packet at next frame, set to
+ *         _DISABLE to stop sending.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME
+ *         Set to _ENABLE to send the packet at other frame, set to _DISABLE to
+ *         send at every frame.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME
+ *         Set to _ENABLE to send once next frame, set to _DISABLE to send at
+ *         every frame.
+ *       Note: A setting to set both _OTHER_FRAME and _SINGLE_FRAME is invalid
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK
+ *         Set to _ENABLE to send the packet once on next HBLANK, set to
+ *         _DISABLE to send on VBLANK.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE
+ *         Set to _ENABLE to send the info frame packet as soon as possible.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT
+ *         Set to _SW_CONTROLLED to set HDMI_Video_Format field and 3D_Structure field
+ *         from NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 and PB5, if it is set to _HW_CONTROLLED
+ *         then HW will get them based on the state of the setHdmiCtrl method.
+ *         Btw this applies only for stereo ovverides.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY
+ *         Set to TRUE to send Vendor specific info frame used for 3D stereo LR sync.
+ *         Set PACKET_TYPE=pktType_VendorSpecInfoFrame along with this flag.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING
+ *         Set to TRUE to send Vendor specific info frame used for Self Refresh panels
+ *         Set PACKET_TYPE=pktType_VendorSpecInfoFrame along with this flag.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE
+ *         HW provides support to program 2 generic infoframes per frame for DP with GP10X+.
+ *         This flag indicates the INFOFRAME that needs to be programmed.
+ *         Set to _INFOFRAME0 if RM should program GENERIC_INFOFRAME
+ *         Set to _INFOFRAME1 if RM should program GENERIC_INFOFRAME1
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE
+ *         This option is reserved for backward compatibility with
+ *         NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_PACKET and
+ *         NV0073_CTRL_CMD_DP_SET_PACKET.
+ *         It is temporal and will be deprecated soon.
+ *   packetSize
+ *     packet size of packets in pPacket to send, including header and payload.
+ *   targetHead 
+ *     Specifies the target head number for which SDP needs to be updated. 
+ *   bUsePsrHeadforSdp
+ *     Indicates use targetHead field for setting SDP or infoframe packet instead 
+ *     of deriving the active head from displayID.
+ *   pPacket
+ *     pPacket points to the packets to send.
+ *     For HDMI 1.1, the maximum allowed bytes is 31.
+ *     The packet array includes the 3 bytes of header + data depending on
+ *     the type of packet.  For an infoframe, the header bytes refer to type,
+ *     version and length respectively.  This comes as input to this command.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET (0x730288U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SET_OD_MAX_PACKET_SIZE     36U
+
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID (0x88U)
+
+typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvU32  transmitControl;
+    NvU32  packetSize;
+    NvU32  targetHead;
+    NvBool bUsePsrHeadforSdp;
+    NvU8   aPacket[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE];
+} NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE                                     0:0
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO                      (0x0000000U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES                     (0x0000001U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME                                1:1
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE            (0x0000000U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE             (0x0000001U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME                               2:2
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE           (0x0000000U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE            (0x0000001U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK                                 3:3
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE              (0x0000000U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE               (0x0000001U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE                                  4:4
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_DISABLE              (0x0000000U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_ENABLE               (0x0000001U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT                                  5:5
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED        (0x0000000U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED        (0x0000001U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY                        6:6
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE      (0x0000000U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE       (0x0000001U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING                   7:7
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE (0x0000000U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE  (0x0000001U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE                         9:8
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME0  (0x0000000U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME1  (0x0000001U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE                     31:31
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO        (0x0000000U)
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES       (0x0000001U)
+
+
+/*
+ * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS
+ *
+ * This command is used to enable/disable sending of display output packets.
+ * Currently it supports HDMI only.
+ * Unused data bytes should be zero-ed out.
+ *
+ *   displayID
+ *     This parameter specifies the displayID for the display output resource to
+ *     configure.
+ *     This comes as input to this command.
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be directed.
+ *     This parameter must specify a value between zero and the total number
+ *     of subdevices within the parent device.  This parameter should be set
+ *     to zero for default behavior.
+ *   type
+ *     The client shall specify the type of display output packet. For HDMI, set
+ *     this according to HDMI specification 1.4.
+ *     This comes as input to this command.
+ *   transmitControl
+ *     This parameter controls how the packet is to be sent by setting the control
+ *     bits.
+ *     Possible flags are as follows:
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE
+ *         Set to _ENABLE to start sending the packet at next frame, set to
+ *         _DISABLE to stop sending.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME
+ *         Set to _ENABLE to send the packet at other frame, set to _DISABLE to
+ *         send at every frame.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME
+ *         Set to _ENABLE to send once next frame, set to _DISABLE to send at
+ *         every frame.
+ *       Note: A setting to set both _OTHER_FRAME and _SINGLE_FRAME is invalid
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK
+ *         Set to _ENABLE to send the packet once on next HBLANK, set to _DISABLE
+ *         to send on VBLANK.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT
+ *         Set to _SW_CONTROLLED to set HDMI_Video_Format field and 3D_Structure field
+ *         from NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 and PB5, if it is set to _HW_CONTROLLED
+ *         then HW will get them based on the state of the setHdmiCtrl method.
+ *         Btw this applies only for stereo ovverides.
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY
+ *         Set to TRUE to enable Vendor specific info frame used for 3D stereo LR sync
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING
+ *         Set to TRUE to enable Vendor specific info frame used for Self Refresh panels
+ *       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE
+ *         This option is reserved for backward compatibility with
+ *         NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_PACKET and
+ *         NV0073_CTRL_CMD_DP_SET_PACKET.
+ *         It is temporal and will be deprecated soon.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET_CTRL                                        (0x730289U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS_MESSAGE_ID (0x89U)
+
+typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 type;
+    NvU32 transmitControl;
+} NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE                      NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE_NO                      NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE_YES                     NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME                 NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE            NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE             NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME                NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE           NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE            NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK                   NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK_DISABLE              NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK_ENABLE               NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT                   NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED        NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED        NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY         NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE      NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING         NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE  NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE        NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO        NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO
+#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES       NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_PCLK_LIMIT
+ *
+ * This command returns the maximum supported pixel clock rate that is
+ * supported by the specified display device.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the display for which information is to be
+ *     returned.  Only one display may be indicated in this parameter.
+ *     If more than one displayId is used a failing status of
+ *     NV_ERR_INVALID_ARGUMENT will be returned.
+ *   pclkLimit
+ *     This parameter returns the min of orPclkLimit and vbPclkLimit in KHz.
+ *     It may be used for SLI configs that use a video bridge. For non-SLI
+ *     configs and bridgeless SLI configs, the client should use orPclkLimit instead.
+ *   orPclkLimit
+ *     This parameter returns the maximum pixel clock frequency of OR in KHz.
+ *   vbPclkLimit
+ *     This parameter returns the maximum pixel clock frequency of the
+ *     video bridge (SLI) in KHz (or zero if there is no video bridge).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_GET_PCLK_LIMIT                                                 (0x73028aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS_MESSAGE_ID (0x8AU)
+
+typedef struct NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 pclkLimit;
+    NvU32 orPclkLimit;
+    NvU32 vbPclkLimit;
+} NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO
+ *
+ * This command returns output resource information for the specified display
+ * device.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the display for which information is to be
+ *     returned.  Only one display may be indicated in this parameter.
+ *     If more than one displayId is used a failing status of
+ *     NV_ERR_INVALID_ARGUMENT will be returned.
+ *   type
+ *     This parameter returns the output resource type.  Legal values for
+ *     this parameter include:
+ *       NV0073_CTRL_SPECIFIC_OR_TYPE_DAC
+ *         The output resource is a DAC.
+ *       NV0073_CTRL_SPECIFIC_OR_TYPE_SOR
+ *         The output resource is a serial output resource.
+ *       NV0073_CTRL_SPECIFIC_OR_TYPE_DSI
+ *         The output resource is a Display Serial Interface output resource.
+ *       NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR
+ *         The output resource is a parallel input output resource.
+ *   index
+ *     This parameter returns the type-specific index of the output
+ *     resource associated with the specified displayId.
+ *   protocol
+ *     This parameter returns the type-specific protocol used by the
+ *     output resource.  Legal values for this parameter include:
+ *       NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT
+ *       NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM
+ *       NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A
+ *       NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B
+ *       NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS
+ *       NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A
+ *       NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B
+ *       NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC
+ *       NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI
+ *       NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN
+ *   ditherType
+ *     This parameter returns the dither type for the output resource.
+ *     Legal values for this parameter include:
+ *       NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS
+ *       NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS
+ *       NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_10_BITS
+ *       NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF
+ *   ditherAlgo
+ *     This parameter returns the dithering algorithm used by the output
+ *     resource.  Legal values for this parameter include:
+ *       NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_DYNAMIC_ERR_ACC
+ *       NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_STATIC_ERR_ACC
+ *       NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_DYNAMIC_2X2
+ *       NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_STATIC_2X2
+ *       NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_TEMPORAL
+ *       NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_UNKNOWN
+ *   location
+ *     This parameter returns the physical location of the output resource.
+ *     Legal values for this parameter include:
+ *       NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP
+ *       NV0073_CTRL_SPECIFIC_OR_LOCATION_BOARD
+ *   rootPortId
+ *     This parameter specifies the Root-Port ID for the given display.
+ *   dcbIndex
+ *     This parameter returns the DCB index of the display device.
+ *   vbiosAddress
+ *      This parameter is the VBIOS IP address which will have valid value
+ *      only if displayId is allocated by VBIOS.
+ *   bIsLitByVbios
+ *     This parameter specifies that whether displayID allocation was
+ *     requested by VBIOS or not.
+ *   bIsDispDynamic
+ *     Returns NV_TRUE if DisplayID is allocated Dynamically else NV_FALSE
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO (0x73028bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID (0x8BU)
+
+typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvU32  index;
+    NvU32  type;
+    NvU32  protocol;
+    NvU32  ditherType;
+    NvU32  ditherAlgo;
+    NvU32  location;
+    NvU32  rootPortId;
+    NvU32  dcbIndex;
+    NV_DECLARE_ALIGNED(NvU64 vbiosAddress, 8);
+    NvBool bIsLitByVbios;
+    NvBool bIsDispDynamic;
+} NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS;
+
+/* valid type values */
+#define NV0073_CTRL_SPECIFIC_OR_TYPE_NONE                   (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_OR_TYPE_DAC                    (0x00000001U)
+#define NV0073_CTRL_SPECIFIC_OR_TYPE_SOR                    (0x00000002U)
+#define NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR                   (0x00000003U)
+
+
+#define NV0073_CTRL_SPECIFIC_OR_TYPE_DSI                    (0x00000005U)
+
+/* valid DAC protocol values */
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT        (0x00000000U)
+
+
+
+/* valid SOR protocol values */
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM    (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A  (0x00000001U)
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B  (0x00000002U)
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS      (0x00000005U)
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A           (0x00000008U)
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B           (0x00000009U)
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DSI            (0x00000010U)
+
+/* valid DSI protocol values */
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI                (0x00000011U)
+
+/* valid PIOR protocol values */
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC  (0x00000000U)
+
+/* valid UNKNOWN protocol value */
+#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN            (0xFFFFFFFFU)
+
+/* valid ditherType values */
+#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS          (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS          (0x00000001U)
+#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_10_BITS         (0x00000002U)
+#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF             (0x00000003U)
+
+/* valid ditherAlgo values */
+#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_ERR_ACC (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_ERR_ACC  (0x00000001U)
+#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_2X2     (0x00000002U)
+#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_2X2      (0x00000003U)
+#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_TEMPORAL        (0x00000004U)
+#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN         (0xFFFFFFFFU)
+
+/* valid location values */
+#define NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP               (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_OR_LOCATION_BOARD              (0x00000001U)
+
+
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS
+ * NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS
+ *
+ * These commands retrieve and set the user backlight brightness for
+ * the specified display.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   displayId
+ *     Display for which brightness is to be retrieved or set.
+ *   brightness
+ *     The backlight brightness in the range [0,100], inclusive.  This
+ *     is an input for SET_BACKLIGHT_BRIGHTNESS, and an output for
+ *     GET_BACKLIGHT_BRIGHTNESS.
+ *
+ *
+ * Possible status values returned include:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x91" */
+
+#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x92" */
+
+#define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MIN_VALUE        0U
+#define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MAX_VALUE        100U
+
+typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 brightness;
+} NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS
+ *
+ * This command is used to inform RM about the scrambling, clock mode, FRL and
+ * DSC caps of the HDMI sink device.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed..
+ *   displayID
+ *     This parameter specifies the displayID for the display output resource to
+ *     configure.
+ *   caps
+ *     This parameter specifies the sink caps.
+ *       GT_340MHZ_CLOCK_SUPPORTED refers to whether sink supports TMDS clock (sorClk) rate greater than 340 MHz
+ *       LTE_340MHZ_SCRAMBLING_SUPPORTED refers to whether scrambling is supported for clock rate at or below 340 MHz
+ *       SCDC_SUPPORTED refers to whether SCDC access is supported on sink
+ *       MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL rate supported
+ *       DSC_12_SUPPORTED refers to whether VESA DSC v1.2a is supported
+ *       DSC_12_MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL rate supported when VESA DSC v1.2a is supported
+ *
+ *
+ * Possible status values returned include:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS (0x730293U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID (0x93U)
+
+typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 caps;
+} NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS;
+
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED                           0:0
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_FALSE       (0x00000000U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_TRUE        (0x00000001U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED                     1:1
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_FALSE (0x00000000U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_TRUE  (0x00000001U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED                                      2:2
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_FALSE                  (0x00000000U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_TRUE                   (0x00000001U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED                              5:3
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_NONE           (0x00000000U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_3G      (0x00000001U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_6G      (0x00000002U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_6G      (0x00000003U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_8G      (0x00000004U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_10G     (0x00000005U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_12G     (0x00000006U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED                                    6:6
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_FALSE                (0x00000000U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_TRUE                 (0x00000001U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED                          9:7
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_NONE       (0x00000000U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_3G  (0x00000001U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_6G  (0x00000002U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_6G  (0x00000003U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_8G  (0x00000004U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U)
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U)
+
+
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_SET_MONITOR_POWER
+ *
+ * This command sets monitor power on/off.
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   displayId
+ *     This parameter specifies the displayID for the display output resource to
+ *     configure.
+ *   powerState
+ *     This parameter should be one of the valid
+ *     NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_* values.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_SET_MONITOR_POWER               (0x730295U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID (0x95U)
+
+typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 powerState;
+} NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_OFF     (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_ON      (0x00000001U)
+
+
+
+/*
+* NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG
+*
+* This command is used to perform HDMI FRL link training and enable FRL mode for
+* the specified displayId. The link configuration will be returned after link
+* training success.
+*
+*   subDeviceInstance
+*     This parameter specifies the subdevice instance within the
+*     NV04_DISPLAY_COMMON parent device to which the operation should be
+*     directed.
+*   displayID
+*     This parameter specifies the displayID for the display output resource to
+*     configure.
+*   data
+*     This parameter is an input and output to this command.
+*     Here are the current defined fields:
+*       NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE
+*         This field specifies the desired setting for lane count. A client may
+*         choose any lane count as long as it does not exceed the capability of
+*         HDMI FRL sink as indicated in the sink capability field.
+*         The valid values for this field are:
+*           NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE
+*             For 0 lane configuration, link training is shut down (disable FRL).
+*           NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G
+*             For FRL 3-lane configuration and 3 Gbps bandwidth per lane.
+*           NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G
+*             For FRL 3-lane configuration and 6 Gbps bandwidth per lane.
+*           NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G
+*             For FRL 4-lane configuration and 6 Gbps bandwidth per lane.
+*           NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G
+*             For FRL 4-lane configuration and 8 Gbps bandwidth per lane.
+*           NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G
+*             For FRL 4-lane configuration and 10 Gbps bandwidth per lane.
+*           NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G
+*             For FRL 4-lane configuration and 12 Gbps bandwidth per lane.
+*         On return, the link bandwidth setting is returned which may be 
+*         different from the requested input setting.
+*   bFakeLt
+*     This flag as input to this command.
+*     It indicates the FRL link training is a fake link training or not.
+*     TRUE if the FRL link training is fake and no real sink device attached.
+*   bLtSkipped
+*     The flag returned indicating whether link training is skipped or not.
+*     TRUE if link training is skipped due to the link config is not changed.
+*
+* Possible status values returned include:
+* NV_OK -
+*   Affter finishing link tranning, NV_OK status will be returned along with
+*   the updated link congiration. In case of link training failure, FRL_RATE_NONE
+*   will be returned with NV_OK.
+* NV_ERR_NOT_SUPPORTED -
+*   If the GPU/sink is not capable for HDMI FRL, NV_ERR_NOT_SUPPORTED status
+*   will be returned.
+* NV_ERR_INVALID_ARGUMENT
+*   If any argument is valid for this control call, NV_ERR_INVALID_ARGUMENT
+*   status will be returned.
+*/
+#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG (0x73029aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS_MESSAGE_ID (0x9AU)
+
+typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvU32  data;
+    NvBool bFakeLt;
+    NvBool bLtSkipped;
+} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS;
+
+#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE                                           2:0
+#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE                (0x00000000U)
+#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G           (0x00000001U)
+#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G           (0x00000002U)
+#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G           (0x00000003U)
+#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G           (0x00000004U)
+#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G          (0x00000005U)
+#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G          (0x00000006U)
+
+
+
+#define NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS                                  9U
+
+#define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID (0xA0U)
+
+typedef struct NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 regionCrcs[NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS];
+    NvU16 reqRegionCrcMask;
+} NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS
+ *
+ * This command is used to capture the active viewport region CRCs
+ * 
+ *  [in]subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device. This parameter
+ *     should be set to zero for default behavior.
+ *
+ *  [in]displayId
+ *     This parameter specifies the displayId of panel, for which region CRC to be captured
+.*
+ *  [out]regionCrcs
+ *      This field holds the region CRC values to be returned after successful completion of the control command.
+ *
+ *  [in]reqRegionCrcMask
+ *     This parameter specifies BIT mask value of requested CRC regions.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS      (0x7302a0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID" */
+
+/*
+* NV0073_CTRL_CMD_SPECIFIC_APPLY_EDID_OVERRIDE_V2
+*
+* Apply EDID override on specific OD.
+*
+*   subDeviceInstance
+*     This parameter specifies the subdevice instance within the
+*     NV04_DISPLAY_COMMON parent device to which the operation should be
+*     directed.
+*   displayId (in)
+*     ID of panel on which the operation is to be performed.
+*   bufferSize (in)
+*     Size of the EDID buffer.
+*   edidBuffer (in/out)
+*     The buffer which stores the EDID before and after override.
+*
+* Possible status values returned are:
+*   NV_OK
+*   NV_ERR_INVALID_PARAMETER
+*/
+#define NV0073_CTRL_CMD_SPECIFIC_APPLY_EDID_OVERRIDE_V2 (0x7302a1U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS_MESSAGE_ID (0xA1U)
+
+typedef struct NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU32 bufferSize;
+    NvU8  edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES];
+} NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS
+ *
+ * This command is used to get the HDMI FRL caps of GPU side.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   caps
+ *     This parameter specifies the GPU caps.
+ *       MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL link rate supported
+ *
+ *
+ * Possible status values returned include:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS (0x7302a2U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS_MESSAGE_ID (0xA2U)
+
+typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 caps;
+} NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS;
+
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED                           2:0
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_NONE       (0x00000000U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_3LANES_3G  (0x00000001U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_3LANES_6G  (0x00000002U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_6G  (0x00000003U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_8G  (0x00000004U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_10G (0x00000005U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_12G (0x00000006U)
+
+
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_DISPLAY_CHANGE
+ * 
+ * Notifies the system that a display change is about to begin/end.
+ * Also performs the necessary synchronizations for the same.
+ * 
+ * The command takes a NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS structure as an
+ * argument with appropriate subDeviceInstance.
+ * 
+ *  [in]subDeviceInstance
+ *   The sub-device instance
+ *  [in]newDevices
+ *   Bitmask of devices that are planned on being enabled with the
+ *   pending device change. See NV_CFGEX_GET_DEVICES_CONFIGURATION for bit defs.
+ *  [in]properties
+ *   Bitmask of display attributes for new configuration (none used at the moment).
+ *  [in]enable
+ *   Parameter to decide between display change start and end. Can take values
+ *   NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_START or NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_END.
+ * Possible return values:
+ *  NV_OK
+ *  NV_ERR_INVALID_ARGUMENT
+ *
+ */
+
+#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS_MESSAGE_ID (0xA4U)
+
+typedef struct NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS {
+
+    NvU32 subDeviceInstance;
+    NvU32 newDevices;
+    NvU32 properties;
+    NvU32 enable;
+} NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_END                 (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_START               (0x00000001U)
+
+#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PROPERTIES_SPANNING (0x00000001U)
+
+#define NV0073_CTRL_CMD_SPECIFIC_DISPLAY_CHANGE                 (0x7302a4U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS_MESSAGE_ID" */
+
+
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA
+ *
+ * This command is used to get the HDMI sink status/caps via Status and Control
+ * Data Channel (SCDC).
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   displayId
+ *     This parameter specifies the displayId of HDMI sink. 
+ *   offset
+ *     This parameter specifies the SCDC offset which the read operation
+ *     should be used.
+ *   data
+ *     This field specifies the return data from sink for reading the specified
+ *     SCDC offset.
+ *
+ *
+ * Possible status values returned include:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA         (0x7302a6U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS_MESSAGE_ID (0xA6U)
+
+typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+    NvU8  offset;
+    NvU8  data;
+} NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS;
+
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET                                       7:0
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_NONE                      (0x00000000U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SINK_VERSION              (0x00000001U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SOURCE_VERSION            (0x00000002U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_UPDATE_FLAGS_0            (0x00000010U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_TMDS_CONFIGURATION        (0x00000020U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SCRAMBLER_STATUS          (0x00000021U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CONFIGURATION_0           (0x00000030U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CONFIGURATION_1           (0x00000031U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SOURCE_TEST_CONFIGURATION (0x00000035U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_0            (0x00000040U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_1            (0x00000041U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_2            (0x00000042U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_0                     (0x00000050U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_1                     (0x00000051U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_2                     (0x00000052U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_3                     (0x00000053U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_4                     (0x00000054U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_5                     (0x00000055U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_6                     (0x00000056U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_7                     (0x00000057U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_8                     (0x00000058U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_RSED_0                    (0x00000059U)
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_RSED_1                    (0x0000005AU)
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_IS_DIRECTMODE_DISPLAY
+ *
+ * This command is used to query whether the specified monitor should be used
+ * with directmode.
+ *
+ *   [in]manufacturerID
+ *     This parameter specifies the 16-bit EDID Manufacturer ID.
+ *   [in]productID
+ *     This parameter specifies the 16-bit EDID Product ID.
+ *   [out]bIsDirectmode;
+ *     This indicates whether the monitor should be used with directmode.
+ * Possible return values:
+ *  NV_OK
+ */
+
+#define NV0073_CTRL_CMD_SPECIFIC_IS_DIRECTMODE_DISPLAY                               (0x7302a7U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS_MESSAGE_ID (0xA7U)
+
+typedef struct NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS {
+    NvU16  manufacturerID;
+    NvU16  productID;
+    NvBool bIsDirectmode;
+} NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION
+ *
+ * This command is used to get the HDMI FRL capacity computation result.
+ *
+ *   [in] cmd
+ *     This parameter specifies the command for the HDMI FRL capacity computation.
+ *   [in] input
+ *     This parameter specifies the input data for the HDMI FRL capacity
+ *     computation.   
+ *   [out] result
+ *     This indicates the computation result of HDMI FRL capacity computation.
+ *   [in/out] preCalc
+ *     This indicates the pre-caculation result of HDMI FRL capacity computation.
+ *   [in/out] dsc
+ *     This indicates the DSC parameters of HDMI FRL capacity computation.
+ * Possible return values:
+ *  NV_OK
+ */
+
+#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION (0x7302a8U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS_MESSAGE_ID" */
+
+typedef struct NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS {
+    NvU32 numLanes;
+    NvU32 frlBitRateGbps;
+    NvU32 pclk10KHz;
+    NvU32 hTotal;
+    NvU32 hActive;
+    NvU32 bpc;
+    NvU32 pixelPacking;
+    NvU32 audioType;
+    NvU32 numAudioChannels;
+    NvU32 audioFreqKHz;
+
+    struct {
+        NvU32 bppTargetx16;
+        NvU32 hSlices;
+        NvU32 sliceWidth;
+        NvU32 dscTotalChunkKBytes;
+    } compressionInfo;
+} NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS;
+
+typedef struct NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT {
+    NvU32  frlRate;
+    NvU32  bppTargetx16;
+    NvBool engageCompression;
+    NvBool isAudioSupported;
+    NvBool dataFlowDisparityReqMet;
+    NvBool dataFlowMeteringReqMet;
+    NvBool isVideoTransportSupported;
+    NvU32  triBytesBorrowed;
+    NvU32  hcActiveBytes;
+    NvU32  hcActiveTriBytes;
+    NvU32  hcBlankTriBytes;
+    NvU32  tBlankToTTotalX1k;
+} NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT;
+
+typedef struct NV0073_CTRL_FRL_PRE_CALC_CONFIG {
+    NvU32  vic;
+    NvU32  packing;
+    NvU32  bpc;
+    NvU32  frlRate;
+    NvU32  bppX16;
+    NvBool bHasPreCalcFRLData;
+} NV0073_CTRL_FRL_PRE_CALC_CONFIG;
+
+typedef struct NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS {
+    NvU32  maxSliceCount;
+    NvU32  maxSliceWidth;
+    NvBool bIsDSCPossible;
+} NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS_MESSAGE_ID (0xA8U)
+
+typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS {
+    NvU8                                        cmd;
+    NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS input;
+    NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT result;
+    NV0073_CTRL_FRL_PRE_CALC_CONFIG             preCalc;
+    NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS      dsc;
+} NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_NULL                               (0x00000000U)
+#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_UNCOMPRESSED_VIDEO                 (0x00000001U)
+#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_COMPRESSED_VIDEO                   (0x00000002U)
+#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_HAS_PRECAL_FRL_DATA                (0x00000003U)
+#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_GET_PRECAL_UNCOMPRESSED_FRL_CONFIG (0x00000004U)
+#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_GET_PRECAL_COMPRESSED_FRL_CONFIG   (0x00000005U)
+#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_IS_FRL_DSC_POSSIBLE                (0x00000006U)
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET
+ *
+ * This command is used to program the display output packets.
+ * This generic packets can be used for both HDMI and DP.
+ * HW has added 6 new generic packets for each head because some usecases have
+ * requirement to send infoframe in particular location (vsync, vblank, loadV).
+ * 
+ * Note: 1. Client first needs to reserve or acquire a free infoframe index
+ *          using NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET.
+ *       2. Client needs to update the SDP index for head through control call
+ *          NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET
+ *       3. Client needs to Release the infoframe index using control call
+ *          NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET
+ *
+ *   [in]subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *     This parameter must specify a value between zero and the total number
+ *     of subdevices within the parent device.  This parameter should be set
+ *     to zero for default behavior.
+ *   [in]transmitControl
+ *     This parameter controls how the packet is to be sent by setting the
+ *     control bits.
+ *     Possible flags are as follows:
+ *       NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE
+ *         Setting this field to _YES will enable this generic infoframe,
+ *         Setting this field to _NO will disable this generic infoframe.
+ *       NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE
+ *        Set to _YES will cause new infoframe to be transmitted exactly once.
+ *        Set to _NO will cause new infoframe to be transmitted every frame.
+ *       NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC
+ *         SDP can be sent in 3 different locations: 
+ *           VBLANK - new infoframe will be sent at Vblank.
+ *           VSYNC - new infoframe will be sent at Vsync.
+ *           LOADV - new infoframe will be triggered by LOADV, and sent at Vsync
+ *       NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE
+ *         _ENABLE: override DB1 bit1 with existence of loadv (for Panel Self Refresh)
+ *         _DISABLE: do not override shared generic infoframe subpacker DB1 bit1.
+ *       NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE
+ *        _ENABLE: override DB1 bit3 with existence of loadv (for Panel Replay)
+ *        _DISABLE: do not override shared generic infoframe subpacker DB1 bit3.
+ *   [in]packetSize
+ *     size of packets in Packet array to send, including header and payload.
+ *   [in]infoframeIndex 
+ *     Specifies the target head number for which SDP needs to be updated.
+ *   [in]infoframeIndex 
+ *     Specifies the index of infoframe.
+ *   [in]packet
+ *     pPacket points to the packets to send.
+ *     For HDMI 1.1, the maximum allowed bytes is 31.
+ *     The packet array includes the 3 bytes of header + data depending on
+ *     the type of packet.  For an infoframe, the header bytes refer to type,
+ *     version and length respectively.  This comes as input to this command.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET                                            (0x7302a9) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xA9U)
+
+typedef struct NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 transmitControl;
+    NvU32 packetSize;
+    NvU32 targetHeadIndex;
+    NvU32 infoframeIndex;
+    NvU8  packet[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE];
+} NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE                                               0:0
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE_NO                                     (0x0000000)
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE_YES                                    (0x0000001)
+
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE                                               1:1
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE_NO                                     (0x0000000)
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE_YES                                    (0x0000001)
+
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC                                                  5:2
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_VBLANK                                    (0x0000000)
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_VSYNC                                     (0x0000001)
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_LOADV                                     (0x0000002)
+
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE                               6:6
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE_DISABLE                (0x0000000)
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE_ENABLE                 (0x0000001)
+
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE                          7:7
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_DISABLE           (0x0000000)
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_ENABLE            (0x0000001)
+
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE                8:8
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_DISABLE (0x0000000)
+#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_ENABLE  (0x0000001)
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET
+ *
+ * This command is used to reserve the infoframe for head and RM would assign 
+ * free infoframe index and return the index of infoframe. Later client needs
+ * to call control call NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET 
+ * to release the index.
+ *
+ *   [in]subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *     This parameter must specify a value between zero and the total number
+ *     of subdevices within the parent device.  This parameter should be set
+ *     to zero for default behavior.
+ *   [in]targetHeadIndex
+ *     target Head for which SDP needs to be sent
+ *   [out]infoframeIndex
+ *     return Infoframe Index for head.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFIENT_RESOURCES
+ */
+
+#define NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET (0x7302aa) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xAAU)
+
+typedef struct NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 targetHeadIndex;
+    NvU32 infoframeIndex;
+} NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET
+ *
+ * This command is used to release the infoframe index which was acquired by
+ * client.
+ *
+ *   [in]subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *     This parameter must specify a value between zero and the total number
+ *     of subdevices within the parent device.  This parameter should be set
+ *     to zero for default behavior.
+ *   [in]targetHeadIndex
+ *     Specifies the target head number for which SDP needs to be updated. 
+ *   [in]infoframeIndex
+ *     Infoframe index for the target head
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET (0x7302ab) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xABU)
+
+typedef struct NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 targetHeadIndex;
+    NvU32 infoframeIndex;
+} NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE
+ *
+ * This command is used to do I2C R/W to slave on display i2c instance.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed. This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   i2cPort
+ *      This parameter specifies the I2C CCB port ID.
+ *   i2cSlaveAddress
+ *      This parameter specifies the I2C slave address.
+ *   readWriteFlag
+ *      This parameter specifies whether its read/write operation.
+ *   readWriteLen
+ *      This parameter specifies the length of the read/write buffer
+ *   readBuffer
+ *      This parameter reads the data from slave address and copies to this
+ *      buffer
+ *   writeBuffer
+ *      This parameter specifies this buffer data that would be written to
+ *      slave address
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE     (0x7302acU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN 128U
+
+#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID (0xACU)
+
+typedef struct NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 i2cPort;
+    NvU32 i2cSlaveAddress;
+    NvU32 readWriteFlag;
+    NvU32 readWriteLen;
+    NvU8  readBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN];
+    NvU8  writeBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN];
+} NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS;
+
+#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE                   (0x00000001)
+#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE                  (0x00000000)
+
+/*
+ * NV0073_CTRL_CMD_GET_VALID_HEAD_WINDOW_ASSIGNMENT
+ *
+ * This command returns the valid window head assignment mask
+ *
+ * windowHeadMask [out]
+ *   This out parameter is an array which holds the head mask for
+ *   each window. The Nth element in the array would be a bitmask
+ *   of which heads can possibly drive window N.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_GENERIC
+ */
+#define NV0073_CTRL_CMD_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT (0x7302ad) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SPECIFIC_MAX_WINDOWS                          32U
+#define NV0073_CTRL_SPECIFIC_FLEXIBLE_HEAD_WINDOW_ASSIGNMENT      (0xFFU)
+
+#define NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID (0xADU)
+
+typedef struct NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU8  windowHeadMask[NV0073_CTRL_SPECIFIC_MAX_WINDOWS];
+} NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS;
+
+/* _ctrl0073specific_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h
new file mode 100644
index 0000000..9a585aa
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h
@@ -0,0 +1,166 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073stereo.finn
+//
+
+#include "ctrl/ctrl0073/ctrl0073base.h"
+
+
+
+/*
+ * NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS
+ *
+ * Sets new video mode timings
+ * E.g. from display driver on mode set
+ *
+ * Parameters:
+ * [IN]  subDeviceInstance - This parameter specifies the subdevice instance 
+ *        within the NV04_DISPLAY_COMMON parent device to which the operation 
+ *        should be directed.  This parameter must specify a value between 
+ *        zero and the total number of subdevices within the parent device.  
+ *        This parameter should be set to zero for default behavior.
+ * [IN]  head      - head to be passed to stereoDongleControl 
+ * [IN]  timings   - new timings to be set
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED    - stereo is not initialized on the GPU
+ */
+#define NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS (0x731703U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID" */
+
+typedef struct NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS {
+    NvU32 PixelClock;
+    NvU16 TotalWidth;
+    NvU16 VisibleImageWidth;
+    NvU16 HorizontalBlankStart;
+    NvU16 HorizontalBlankWidth;
+    NvU16 HorizontalSyncStart;
+    NvU16 HorizontalSyncWidth;
+    NvU16 TotalHeight;
+    NvU16 VisibleImageHeight;
+    NvU16 VerticalBlankStart;
+    NvU16 VerticalBlankHeight;
+    NvU16 VerticalSyncStart;
+    NvU16 VerticalSyncHeight;
+    NvU16 InterlacedMode;
+    NvU16 DoubleScanMode;
+
+    NvU16 MonitorVendorId;
+    NvU16 MonitorProductId;
+} NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS;
+
+#define NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS {
+    NvU32                                 subDeviceInstance;
+    NvU32                                 head;
+    NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS timings;
+} NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE
+ *
+ * stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_YES
+ * Updates sbios of 3D stereo state active
+ *
+ * Parameters:
+ * [IN]  subDeviceInstance - This parameter specifies the subdevice instance 
+ *        within the NV04_DISPLAY_COMMON parent device to which the operation 
+ *        should be directed.  This parameter must specify a value between 
+ *        zero and the total number of subdevices within the parent device.  
+ *        This parameter should be set to zero for default behavior.
+ * [IN]  head                   - head to be passed to stereoDongleActivate
+ * [IN]  bSDA                   - enable stereo on DDC SDA
+ * [IN]  bWorkStation           - is workstation stereo?
+ * [IN]  bDLP                   - is checkerboard DLP Stereo?
+ * [IN]  IRPower                - IR power value
+ * [IN]  flywheel               - FlyWheel value
+ * [IN]  bRegIgnore             - use reg?
+ * [IN]  bI2cEmitter            - Sets NV_STEREO_DONGLE_ACTVATE_DATA_I2C_EMITTER_YES and pStereo->bAegisDT
+ * [IN]  bForcedSupported       - Sets NV_STEREO_DONGLE_FORCED_SUPPORTED_YES and pStereo->GPIOControlledDongle
+ * [IN]  bInfoFrame             - Aegis DT with DP InfoFrame
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT    - if (head > OBJ_MAX_HEADS)
+ *   NV_ERR_NOT_SUPPORTED       - stereo is not initialized on the GPU
+ */
+#define NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE (0x731704U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  head;
+    NvBool bSDA;
+    NvBool bWorkStation;
+    NvBool bDLP;
+    NvU8   IRPower;
+    NvU8   flywheel;
+    NvBool bRegIgnore;
+    NvBool bI2cEmitter;
+    NvBool bForcedSupported;
+    NvBool bInfoFrame;
+} NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE
+ *
+ * stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_NO
+ *
+ * If active count<=0 then no 3D app is running which indicates 
+ * that we have really deactivated the stereo, updates sbios of 3D stereo state NOT ACTIVE.
+ *
+ * Parameters:
+ * [IN]  subDeviceInstance - This parameter specifies the subdevice instance 
+ *        within the NV04_DISPLAY_COMMON parent device to which the operation 
+ *        should be directed.  This parameter must specify a value between 
+ *        zero and the total number of subdevices within the parent device.  
+ *        This parameter should be set to zero for default behavior.
+ * [IN]  head                   - head to be passed to stereoDongleActivate
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT    - if (head > OBJ_MAX_HEADS)
+ *   NV_ERR_NOT_SUPPORTED       - stereo is not initialized on the GPU
+ */
+#define NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE (0x731705U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 head;
+} NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS;
+
+
+
+/* _ctrl0073stereo_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h
new file mode 100644
index 0000000..08a06ae
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073svp.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
new file mode 100644
index 0000000..d25501a
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
@@ -0,0 +1,1480 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0073/ctrl0073system.finn
+//
+
+#include "ctrl/ctrl0073/ctrl0073base.h"
+
+/* NV04_DISPLAY_COMMON system-level control commands and parameters */
+
+/* extract cap bit setting from tbl */
+#define NV0073_CTRL_SYSTEM_GET_CAP(tbl,c)         (((NvU8)tbl[(1?c)]) & (0?c))
+
+/* Caps format is byte_index:bit_mask.
+ * Important: keep the number of bytes needed for these fields in sync with
+ * NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE
+ */
+#define NV0073_CTRL_SYSTEM_CAPS_AA_FOS_GAMMA_COMP_SUPPORTED        0:0x01
+#define NV0073_CTRL_SYSTEM_CAPS_TV_LOWRES_BUG_85919                0:0x02
+#define NV0073_CTRL_SYSTEM_CAPS_DFP_GPU_SCALING_BUG_154102         0:0x04
+#define NV0073_CTRL_SYSTEM_CAPS_SLI_INTERLACED_MODE_BUG_235218     0:0x08 // Deprecated
+#define NV0073_CTRL_SYSTEM_CAPS_STEREO_DIN_AVAILABLE               0:0x10
+#define NV0073_CTRL_SYSTEM_CAPS_OFFSET_PCLK_DFP_FOR_EMI_BUG_443891 0:0x20
+#define NV0073_CTRL_SYSTEM_CAPS_GET_DMI_SCANLINE_SUPPORTED         0:0x40
+/*
+ * Indicates support for HDCP Key Selection Vector (KSV) list and System
+ * Renewability Message (SRM) validation
+*/
+#define NV0073_CTRL_SYSTEM_CAPS_KSV_SRM_VALIDATION_SUPPORTED       0:0x80
+
+#define NV0073_CTRL_SYSTEM_CAPS_SINGLE_HEAD_MST_SUPPORTED          1:0x01
+#define NV0073_CTRL_SYSTEM_CAPS_SINGLE_HEAD_DUAL_SST_SUPPORTED     1:0x02
+#define NV0073_CTRL_SYSTEM_CAPS_HDMI_2_0_SUPPORTED                 1:0x04
+#define NV0073_CTRL_SYSTEM_CAPS_CROSS_BAR_SUPPORTED                1:0x08
+#define NV0073_CTRL_SYSTEM_CAPS_RASTER_LOCK_NEEDS_MIO_POWER        1:0x10
+/*
+ * Indicates that modesets where no heads are increasing resource requirements,
+ * or no heads are decreasing resource requirements, can be done glitchlessly.
+ */
+#define NV0073_CTRL_SYSTEM_CAPS_GLITCHLESS_MODESET_SUPPORTED       1:0x20
+/* Indicates the SW ACR is enabled for HDMI 2.1 due to Bug 3275257. */
+#define NV0073_CTRL_SYSTEM_CAPS_HDMI21_SW_ACR_BUG_3275257          1:0x40
+
+/* Size in bytes of display caps table. Keep in sync with # of fields above. */
+#define NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE   2U
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_CAPS_V2
+ *
+ * This command returns the set of display capabilities for the parent device
+ * in the form of an array of unsigned bytes.  Display capabilities
+ * include supported features and required workarounds for the display
+ * engine(s) within the device, each represented by a byte offset into the
+ * table and a bit position within that byte.  The set of display capabilities
+ * will be normalized across all GPUs within the device (a feature capability
+ * will be set only if it's supported on all GPUs while a required workaround
+ * capability will be set if any of the GPUs require it).
+ *
+ *   [out] capsTbl
+ *     The display caps bits will be transferred by the RM into this array of
+ *     unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_CAPS_V2 (0x730138U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x38U)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS {
+    NvU8 capsTbl[NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE];
+} NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS
+ *
+ * This commands returns the number of heads supported by the specified
+ * subdevice and available for use by displays.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   flags
+ *     This parameter specifies optional flags to be used to while retrieving
+ *     the number of heads.
+ *     Possible valid flags are:
+ *       NV0073_CTRL_SYSTEM_GET_NUM_HEADS_CLIENT
+ *         This flag is used to request the number of heads that are
+ *         currently in use by an NV client using a user display class
+ *         instance (see NV15_VIDEO_LUT_CURSOR_DAC for an examle).  If this
+ *         flag is disabled then the total number of heads supported is
+ *         returned.
+ *   numHeads
+ *     This parameter returns the number of usable heads for the specified
+ *     subdevice.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS (0x730102U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 flags;
+    NvU32 numHeads;
+} NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS;
+
+/* valid get num heads flags */
+#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT              0:0
+#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT_DISABLE (0x00000000U)
+#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT_ENABLE  (0x00000001U)
+
+
+
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE
+ *
+ * This command returns the current RG scanline of the specified head on the
+ * specified subdevice. To get the DMI scanline on supported chips, use
+ * NV0073_CTRL_CMD_SYSTEM_GET_DMI_SCANLINE
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   head
+ *     This parameter specifies the head for which the active display
+ *     should be retrieved.  This value must be between zero and the
+ *     maximum number of heads supported by the subdevice.
+ *   currentScanline
+ *     This parameter returns the current RG scanline value for the specified
+ *     head.  If the head does not have a valid mode enabled then a scanline
+ *     value of 0xffffffff is returned.
+ *   bStereoEyeSupported (out)
+ *     This parameter specifies whether stereoEye reporting is supported (this
+ *     is hw dependent). Note that this value doesn't actually reflect whether
+ *     given head is really in stereo mode.
+ *   stereoEye (out)
+ *     If supported (ie bStereoEyeSupported is TRUE), this parameter returns
+ *     either NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_RIGHT_EYE or
+ *     NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_LEFT_EYE, reflecting the
+ *     stereo eye that is currently scanned out. Although this value typically
+ *     changes at the beginning of vblank, the exact guarantee isn't more
+ *     accurate than "somewhere in vblank".
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE           (0x730108U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE_RIGHT_EYE 0x00000000U
+#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE_LEFT_EYE  0x00000001U
+
+#define NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  head;
+    NvU32  currentScanline;
+    NvBool bStereoEyeSupported;
+    NvU32  stereoEye;
+} NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_COUNTER
+ *
+ * This command returns the current VBlank counter of the specified head on the
+ * specified subdevice.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   head
+ *     This parameter specifies the head for which the vblank counter
+ *     should be retrieved.  This value must be between zero and the
+ *     maximum number of heads supported by the subdevice.
+ *   verticalBlankCounter
+ *     This parameter returns the vblank counter value for the specified
+ *     head. If the display mode is not valid or vblank not active then
+ *     the verticalBlankCounter value is undefined.
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_COUNTER (0x730109U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 head;
+    NvU32 verticalBlankCounter;
+} NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_ENABLE
+ *
+ * This command returns the current VBlank enable status for the specified
+ * head.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   head
+ *     This parameter specifies the head for which the vblank status
+ *     should be retrieved.  This value must be between zero and the
+ *     maximum number of heads supported by the subdevice.
+ *   bEnabled
+ *     This parameter returns the vblank enable status for the specified head.
+ *     A value of NV_FALSE indicates that vblank interrupts are not currently
+ *     enabled while a value of NV_TRUE indicates that vblank are currently
+ *     enabled.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_ENABLE (0x73010aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  head;
+    NvBool bEnabled;
+} NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED
+ *
+ * This command returns the set of supported display IDs for the specified
+ * subdevice in the form of a 32bit display mask.  State from internal
+ * display connectivity tables is used to determine the set of possible
+ * display connections for the GPU.  The presence of a display in the
+ * display mask only indicates the display is supported.  The connectivity
+ * status of the display should be determined using the
+ * NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE command.  The displayMask
+ * value returned by NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED is static
+ * and will remain consistent across boots of the system.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayMask
+ *     This parameter returns a NV0073_DISPLAY_MASK value describing the set
+ *     of displays supported by the subdevice.  An enabled bit in displayMask
+ *     indicates the support of a display device with that displayId.
+ *   displayMaskDDC
+ *     This parameter returns a NV0073_DISPLAY_MASK value, indicating the
+ *     subset of displayMask that supports DDC.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED (0x730120U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayMask;
+    NvU32 displayMaskDDC;
+} NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE
+ *
+ * This command can be used to check the presence of a mask of display
+ * devices on the specified subdevice.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   flags
+ *     This parameter specifies optional flags to be used while retrieving
+ *     the connection state information.
+ *     Here are the current defined fields:
+ *       NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD
+ *         A client uses this field to indicate what method it wishes the
+ *         system to use when determining the presence of attached displays.
+ *         Possible values are:
+ *            NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_DEFAULT
+ *              The system decides what method to use.
+ *            NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_CACHED
+ *              Return the last full detection state for the display mask.
+ *                   safety.)
+ *            NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_ECONODDC
+ *              Ping the DDC address of the given display mask to check for
+ *              a connected device. This is a lightweight method to check
+ *              for a present device.
+ *       NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC
+ *         A client uses this field to indicate whether to allow DDC during
+ *         this detection or to not use it.
+ *         Possible values are:
+ *            NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DEFAULT
+ *              The system will use DDC as needed for each display.
+ *            NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DISABLE
+ *              The system will not use DDC for any display. If DDC is
+ *              disabled, this detection state will not be cached.
+ *       NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD
+ *         A client uses this field to indicate whether to detect loads
+ *         during this detection or to not use it.
+ *         Possible values are:
+ *            NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DEFAULT
+ *              The system will use load detection as needed for each display.
+ *            NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DISABLE
+ *              The system will not use load detection for any display. If
+ *              load detection is disabled, this detection state will not
+ *              be cached.
+ *   displayMask
+ *     This parameter specifies an NV0073_DISPLAY_MASK value describing
+ *     the set of displays for which connectivity status is to be checked.
+ *     If a display is present then the corresponding bit in the display
+ *     mask is left enabled.  If the display is not present then the
+ *     corresponding bit in the display mask is disabled.  Upon return this
+ *     parameter contains the subset of displays in the mask that are
+ *     connected.
+ *
+ *     If displayMask includes bit(s) that correspond to a TV encoder, the
+ *     result will be simply 'yes' or 'no' without any indication of which
+ *     connector(s) are actually attached.  For fine-grained TV attachment
+ *     detection, please see NV0073_CTRL_CMD_TV_GET_ATTACHMENT_STATUS.
+ *   retryTimeMs
+ *     This parameter is an output to this command.  In case of
+ *     NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time
+ *     duration in milli-seconds after which client should retry this command.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NVOS_STATUS_ERROR_RETRY
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE (0x730122U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 flags;
+    NvU32 displayMask;
+    NvU32 retryTimeMs;
+} NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS;
+
+/* valid get connect state flags */
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD                  1:0
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_DEFAULT  (0x00000000U)
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_CACHED   (0x00000001U)
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_ECONODDC (0x00000002U)
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC                     4:4
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DEFAULT     (0x00000000U)
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DISABLE     (0x00000001U)
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD                    5:5
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DEFAULT    (0x00000000U)
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DISABLE    (0x00000001U)
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK                  6:6
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK_DEFAULT  (0x00000000U)
+#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK_SAFE     (0x00000001U)
+
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_CONFIG
+ *
+ * This command can be used to retrieve dynamic hotplug state information that
+ * are currently recorded by the RM. This information can be used by the client
+ * to determine which displays to detect after a hotplug event occurs.  Or if
+ * the client knows that this device generates a hot plug/unplug signal on all
+ * connectors, then this can be used to cull displays from detection.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   flags
+ *     This parameter specifies optional flags to be used while retrieving
+ *     or changing the hotplug configuration.
+ *       No flags are currently defined.
+ *   hotplugEventMask
+ *     For _GET_HOTPLUG_CONFIG, this returns which connectors the client
+ *     has asked for notifications for, when a hotplug event is detected.
+ *     Events can only be provided for connectors whose displayID is set
+ *     by the system in the hotplugInterruptible field.
+ *   hotplugPollable
+ *     For _GET_HOTPLUG_CONFIG, this returns which connectors are pollable
+ *     in some non-destructive fashion.
+ *   hotplugInterruptible
+ *     For _GET_HOTPLUG_CONFIG, this returns which connectors are capable
+ *     of generating interrupts.
+ *
+ *     This display mask specifies an NV0073_DISPLAY_MASK value describing
+ *     the set of displays that have seen a hotplug or hotunplug event
+ *     sometime after the last valid EDID read.  If the device never has
+ *     a valid EDID read, then it will always be listed here.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+
+#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_CONFIG                  (0x730123U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 flags;
+    NvU32 hotplugEventMask;
+    NvU32 hotplugPollable;
+    NvU32 hotplugInterruptible;
+    NvU32 hotplugAlwaysAttached;
+} NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP
+ *
+ * This command can be used to retrieve the suggested head routing map
+ * for the specified display mask.  A head routing map describes the
+ * suggested crtc (or head) assignments for each display in the specified
+ * mask.
+ *
+ * Up to MAX_DISPLAYS displays may be specified in the display mask.  Displays
+ * are numbered from zero beginning with the lowest bit position set in the
+ * mask.  The corresponding head assignment for each of specified displays can
+ * then be found in the respective per-device field in the routing map.
+ *
+ * If a particular display cannot be successfully assigned a position in the
+ * head routing map then it is removed from the display mask.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayMask
+ *     This parameter specifies the NV0073_DISPLAY_MASK value for which
+ *     the head routing map is desired.  Each enabled bit indicates
+ *     a display device to include in the routing map. Enabled bits
+ *     must represent supported displays as indicated by the
+ *     NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED command.  If a particular
+ *     display cannot be included in the routing map then it's corresponding
+ *     bit in the displayMask will be disabled.  A return value of 0 in
+ *     displayMask indicates that a head routing map could not be constructed
+ *     with the given display devices.
+ *   oldDisplayMask
+ *     This optional parameter specifies a prior display mask to be
+ *     used when generating the head routing map to be returned in
+ *     headRoutingMap.  Displays set in oldDisplayMask are retained
+ *     if possible in the new routing map.
+ *   oldHeadRoutingMap
+ *     This optional parameter specifies a prior head routing map to be
+ *     used when generating the new routing map to be returned in
+ *     headRoutingMap.  Head assignments in oldHeadRoutingMap are
+ *     retained if possible in the new routing map.
+ *   headRoutingMap
+ *     This parameter returns the new head routing map.  This parameter
+ *     is organized into eight distinct fields, each containing the head
+ *     assignment for the corresponding display in display mask.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP           (0x730125U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayMask;
+    NvU32 oldDisplayMask;
+    NvU32 oldHeadRoutingMap;
+    NvU32 headRoutingMap;
+} NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS;
+
+/* maximum number of allowed displays in a routing map */
+#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_MAX_DISPLAYS (8U)
+
+/* per-display head assignments in a routing map */
+#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY0               3:0
+#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY1               7:4
+#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY2               11:8
+#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY3               15:12
+#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY4               19:16
+#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY5               23:20
+#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY6               27:24
+#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY7               31:28
+
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE
+ *
+ * This command returns the active display ID for the specified head
+ * on the specified subdevice.  The active display may be established
+ * at system boot by low-level software and can then be later modified
+ * by an NV client using a user display class instance (see
+ * NV15_VIDEO_LUT_CURSOR_DAC).
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   head
+ *     This parameter specifies the head for which the active display
+ *     should be retrieved.  This value must be between zero and the
+ *     maximum number of heads supported by the subdevice.
+ *   flags
+ *     This parameter specifies optional flags to be used to while retrieving
+ *     the active display information.
+ *     Possible valid flags are:
+ *       NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT
+ *         This flag is used to limit the search for the active display to
+ *         that established by an NV client.  If this flag is not specified,
+ *         then any active display is returned (setup at system boot by
+ *         low-level software or later by an NV client).
+ *   displayId
+ *     This parameter returns the displayId of the active display.  A value
+ *     of zero indicates no display is active.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE                (0x730126U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID (0x26U)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 head;
+    NvU32 flags;
+    NvU32 displayId;
+} NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS;
+
+/* valid get active flags */
+#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT                 0:0
+#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT_DISABLE (0x00000000U)
+#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT_ENABLE  (0x00000001U)
+
+
+
+/*
+ * NV0073_CTRL_SYSTEM_ACPI_ID_MAP
+ *
+ * This structure defines the mapping between the RM's displayId and the
+ * defined ACPI IDs for each display.
+ *   displayId
+ *     This parameter is a handle to a single display output path from the
+ *     GPU pins to the display connector.  Each display ID is defined by one bit.
+ *     A zero in this parameter indicates a skip entry.
+ *   acpiId
+ *     This parameter defines the corresponding ACPI ID of the displayId.
+ *   flags
+ *     This parameter specifies optional flags that describe the association
+ *     between the display ID and the ACPI ID.
+ *       NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN
+ *         This field describes where the ACPI was found.
+ *           NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM
+ *             The ACPI ID was generated by RM code.
+ *           NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD
+ *             The ACPI ID was found via the ACPI _DOD call.
+ *           NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT
+ *             The ACPI ID was generated by RM Client and sent to RM. Note this
+ *             must be set on a NV0073_CTRL_CMD_SYSTEM_SET_ACPI_ID_MAP call.
+ *       NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED
+ *         This flag explains that the ACPI ID is only valid when the system
+ *         is undocked.  If this flag is not set, the ACPI ID is valid always.
+ *       NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED
+ *         This flag explains that the ACPI ID is only valid when the system
+ *         is docked.  If this flag is not set, the ACPI ID is valid always.
+ *       NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT
+ *         This flag is set only if the _DOD returns that the device can be
+ *         detected by the system BIOS.  This flag is copied directly from
+ *         the ACPI spec.
+ *       NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT
+ *         This flag is set only if the _DOD returns that the device is
+ *         a non-VGA device whose power is related to the VGA device.
+ *         i.e. TV tuner, DVD decoder, Video capture. This flag is copied
+ *         directly from the ACPI spec.
+ *       NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID
+ *         This value is set only if the _DOD returns it.  The number
+ *         indicates the head output of a multi-head device. This has no
+ *         relation to the term, Head, currently used in the RM today.
+ *         This is strictly a copy of the value directly from the ACPI spec.
+ *       NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME
+ *         This flag is set only if the _DOD returns that the acpiID follows
+ *         the ACPI 3.0 spec.  This flag is copied directly from
+ *         the ACPI spec.
+ *
+ */
+
+typedef struct NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS {
+    NvU32 displayId;
+    NvU32 acpiId;
+    NvU32 flags;
+} NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS;
+
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN                            1:0
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM                0x00000000U
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD               0x00000001U
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT            0x00000002U
+
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED                     2:2
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_FALSE      0x00000000U
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_TRUE       0x00000001U
+
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED                       3:3
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_FALSE        0x00000000U
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_TRUE         0x00000001U
+
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT                 16:16
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_FALSE    0x00000000U
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_TRUE     0x00000001U
+
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT              17:17
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_FALSE 0x00000000U
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_TRUE  0x00000001U
+
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID                20:18
+
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME                      31:31
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_VENDOR        0x00000000U
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_30            0x00000001U
+
+#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS             (16U)
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP
+ *
+ * This command retrieves the mapping between the RM's displayId and the
+ * defined ACPI IDs for each display.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and
+ *     the total number of subdevices within the parent device.  It should
+ *     be set to zero for default behavior.
+ *   NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS
+ *     An array of display ID to ACPI ids with flags for each description.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *     Only returned if subdeviceInstance was not valid.
+ */
+
+#define NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP                  (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID" */
+
+
+#define NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID (0x5AU)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS {
+    NvU32                                 subDeviceInstance;
+    NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS acpiIdMap[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
+} NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS
+ *
+ * This command returns the set of internal (safe) display IDs for the specified
+ * subdevice in the form of a 32bit display mask. Safe means the displays do
+ * not require copy protection as they are on the motherboard.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   internalDisplaysMask
+ *     This parameter returns a NV0073_DISPLAY_MASK value describing the set
+ *     of displays that are internal (safe) and which do not require copy
+ *     protection schemes.
+ *   availableInternalDisplaysMask
+ *     This parameter returns a NV0073_DISPLAY_MASK value describing the set
+ *     of displays that are internal and available for use.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS (0x73015bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID (0x5BU)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 internalDisplaysMask;
+    NvU32 availableInternalDisplaysMask;
+} NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS
+ *
+ * This command returns a mask of boot display IDs.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   bootDisplayMask
+ *     This parameter returns the mask of boot display IDs.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS                         (0x730166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID (0x66U)
+
+typedef struct NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 bootDisplayMask;
+} NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD
+ *
+ * This command is used to execute general MXM ACPI methods.
+ *
+ * method
+ *   This parameter identifies the MXM ACPI API to be invoked.
+ *   Valid values for this parameter are:
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMI
+ *       This value specifies that the MXMI API is to invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMS
+ *       This value specifies that the MXMS API is to invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX
+ *       This value specifies that the MXMX API is to invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON
+ *       This value specifies that the Hybrid GPU ON API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF
+ *       This value specifies that the Hybrid GPU OFF API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA
+ *       This value specifies that the Hybrid GPU STA API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS
+ *       This value specifies that the Hybrid GPU MXDS API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX
+ *       This value specifies that the Hybrid GPU MXMX API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS
+ *       This value specifies that the Hybrid GPU DOS API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM
+ *       This value specifies that the Hybrid GPU ROM API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD
+ *       This value specifies that the Hybrid GPU DOD API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT
+ *       This value specifies that the Hybrid GPU DSM subfunction SUPPORT
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS
+ *       This value specifies that the Hybrid GPU DSM subfunction SUPPORT
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT
+ *       This value specifies that the Hybrid GPU DSM subfunction POLICYSELECT
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL
+ *       This value specifies that the Hybrid GPU DSM subfunction POWERCONTROL
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY
+ *       This value specifies that the Hybrid GPU DSM subfunction PLATPOLICY
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS
+ *       This value specifies that the Hybrid GPU DSM subfunction DISPLAYSTATUS
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL
+ *       This value specifies that the Hybrid GPU DSM subfunction MDTL
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST
+ *       This value specifies that the Hybrid GPU DSM subfunction HCSMBLIST
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR
+ *       This value specifies that the Hybrid GPU DSM subfunction HCSMBADDR
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE
+ *       This value specifies that the Hybrid GPU DSM subfunction HCREADBYTE
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE
+ *       This value specifies that the Hybrid GPU DSM subfunction HCSENDBYTES
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS
+ *       This value specifies that the Hybrid GPU DSM subfunction HCGETSTATUS
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC
+ *       This value specifies that the Hybrid GPU DSM subfunction HCTRIGDDC
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC
+ *       This value specifies that the Hybrid GPU DSM subfunction HCGETDDC
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS
+ *       This value specifies that the Hybrid GPU DCS API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS
+ *       This value specifies that the DSM MXM subfunction MXSS
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI
+ *       This value specifies that the DSM MXM subfunction MXMI
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS
+ *       This value specifies that the DSM MXM subfunction MXMS
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP
+ *       This value specifies that the DSM MXM subfunction MXPP
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP
+ *       This value specifies that the DSM MXM subfunction MXDP
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL
+ *       This value specifies that the DSM MXM subfunction MDTL
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB
+ *       This value specifies that the DSM MXM subfunction MXCB
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC
+ *       This value specifies the DSM generic remapping should return function
+ *       and subfunction when this API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_HYBRIDCAPS
+ *       This value specifies that the generic DSM subfunction HYBRIDCAPS
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_POLICYSELECT
+ *       This value specifies that the generic DSM subfunction POLICYSELECT
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_PLATPOLICY
+ *       This value specifies that the generic DSM subfunction PLATPOLICY
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS
+ *       This value specifies that the generic DSM subfunction DISPLAYSTATUS
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL
+ *       This value specifies that the generic DSM subfunction MDTL
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE
+ *       This value specifies that the generic DSM subfunction GETOBJBYTYPE
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS
+ *       This value specifies that the generic DSM subfunction GETALLOBJS
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST
+ *       This value specifies that the generic DSM subfunction GETEVENTLIST
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT
+ *       This value specifies that the generic DSM subfunction GETBACKLIGHT
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED
+ *       This value specifies the testIfDsmSubFunctionEnabled test should
+ *       be done for the func/subfunction when this API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC
+ *       This value specifies the list of supported generic dsm functions
+ *       should be returned.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS
+ *       This value specifies that the DSM NVOP subfunction OPTIMUSCAPS
+ *       API is to be invoked.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG
+ *       This value specifies that the DSM NVOP subfunction OPTIMUSFLAG
+ *       API is to be invoked. This API will set a Flag in sbios to Indicate
+ *       that HD Audio Controller is disable/Enabled from GPU Config space.
+ *       This flag will be used by sbios to restore Audio state after resuming
+ *       from s3/s4.
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON
+ *      This value specifies that the WMMX (WMI-ACPI) GPON methods has to be invoked
+ *      this call should happen below DPC level from any client.
+ * inData
+ *   This parameter specifies the method-specific input buffer.  Data is
+ *   passed to the specified API using this buffer.  For display related
+ *   APIs the associated display mask can be found at a byte offset within
+ *   the inData buffer using the following method-specific values:
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET
+ *     NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET
+ * inDataSize
+ *   This parameter specifies the size of the inData buffer in bytes.
+ * outStatus
+ *   This parameter returns the status code from the associated ACPI call.
+ * outData
+ *   This parameter specifies the method-specific output buffer.  Data
+ *   is returned by the specified API using this buffer.
+ * outDataSize
+ *   This parameter specifies the size of the outData buffer in bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x730168U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x68U)
+
+typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS {
+    NvU32 method;
+    NV_DECLARE_ALIGNED(NvP64 inData, 8);
+    NvU16 inDataSize;
+    NvU32 outStatus;
+    NV_DECLARE_ALIGNED(NvP64 outData, 8);
+    NvU16 outDataSize;
+} NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS;
+
+
+/* valid method parameter values */
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX                               (0x00000002U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET              (0x00000001U)
+
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON                              (0x00000003U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF                             (0x00000004U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA                             (0x00000005U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS                               (0x00000006U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX                          (0x00000007U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS                                (0x00000008U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM                                (0x00000009U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD                                (0x0000000aU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT                        (0x0000000bU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS                     (0x0000000cU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT                   (0x0000000dU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL                   (0x0000000eU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY                     (0x0000000fU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS                  (0x00000010U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL                           (0x00000011U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST                      (0x00000012U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR                      (0x00000013U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE                     (0x00000014U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE                     (0x00000015U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS                    (0x00000016U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC                      (0x00000017U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC                       (0x00000018U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS                                (0x00000019U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS                       (0x0000001aU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI                       (0x0000001bU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS                       (0x0000001cU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP                       (0x0000001dU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP                       (0x0000001eU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL                       (0x0000001fU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB                       (0x00000020U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_GETEVENTLIST               (0x00000021U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMTABLE                    (0x00000022U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMCFG                      (0x00000023U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETOBJBYTYPE                   (0x00000024U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETALLOBJS                     (0x00000025U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC          (0x00000026U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS          (0x0000002aU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL                   (0x0000002bU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE           (0x0000002cU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS             (0x0000002dU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST           (0x0000002eU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT           (0x0000002fU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED (0x00000030U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC   (0x00000031U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS               (0x00000032U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON                    (0x00000033U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG               (0x00000034U)
+
+
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETCALLBACKS           (0x00000036U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_SUPPORTFUNCS              (0x00000037U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATCAPS                  (0x00000038U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATPOLICY                (0x00000039U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MSTL                   (0x0000003aU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVGPS_FUNC_SUPPORT             (0x0000003bU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS                          (0x0000003cU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM                          (0x0000003dU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID                          (0x0000003eU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST                          (0x0000003fU)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID                           (0x00000040U)
+
+/* valid input buffer offset values */
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET              (0x00000004U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET         (0x00000004U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET               (0x00000004U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS_DISP_MASK_OFFSET         (0x00000004U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM_DISP_MASK_OFFSET         (0x00000004U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID_DISP_MASK_OFFSET         (0x00000004U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET         (0x00000004U)
+#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID_DISP_MASK_OFFSET          (0x00000004U)
+
+
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE
+ *
+ * This command can be used to retrieve hotplug and unplug state
+ * information that are currently recorded by the RM. This information is
+ * used by the client to determine which displays to detect after a
+ * hotplug event occurs. Or if  the client knows that this device generates
+ * a hot plug/unplug signal on all connectors, then this can be used to call
+ * displays from detection. The displayIds on which hotplug/unplug has
+ * happened will be reported only ONCE to the client. That is if the call
+ * is done multiple times for the same event update, then for consequent
+ * calls the display mask will be reported as 0.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   flags
+ *     This parameter specifies optional flags to be used while retrieving
+ *     the hotplug state information.
+ *     Here are the current defined fields:
+ *       NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID
+ *         A client uses this field to determine the lid state.
+ *         Possible values are:
+ *       NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN
+ *              The lid is open.
+ *       NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED
+ *              The lid is closed.  The client should remove devices a
+ *              reported inside the
+ *              NV0073_CTRL_SYSTEM_GET_CONNECT_POLICY_PARAMS.lidClosedMask.
+ *   hotPlugMask
+ *     This display mask specifies an NV0073_DISPLAY_MASK value describing
+ *     the set of displays that have seen a hotplug.
+ *   hotUnplugMask
+ *     This display mask specifies an NV0073_DISPLAY_MASK value describing
+ *     the set of displays that have seen a hot unplug
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73017bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x7B" */
+
+typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 flags;
+    NvU32 hotPlugMask;
+    NvU32 hotUnplugMask;
+} NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS;
+
+/* valid get hoplug state flags */
+#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID                   0:0
+#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID_OPEN   (0x00000000U)
+#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID_CLOSED (0x00000001U)
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK
+ *
+ * This command instructs the RM to explicitly clear any
+ * ELV block.  Clients should call this before attempting core-channel
+ * updates when in VRR one-shot mode.  ELV block mode will be
+ * properly restored to its appropriate setting based on the stall-lock
+ * in Supervisor3 after the core channel update
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *
+ *   displayId
+ *     The public ID of the Output Display which is to be used for VRR.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_INVALID_STATE
+ */
+
+#define NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK                       (0x73017dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID (0x7DU)
+
+typedef struct NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 displayId;
+} NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR
+ *
+ * This command arms the display modeset supervisor to operate in
+ * a lightweight mode.  By calling this, the client is implicitly
+ * promising not to make any changes in the next modeset that require
+ * the full supervisor.  After SV3, the LWSV will disarm and any subsequent
+ * modesets will revert to full supervisors.  This must be called separately
+ * for every display that will be part of the modeset.
+ * It is recommended that the client explicitly disarm the lightweight
+ * supervisor after every modeset as null modesets will not trigger the
+ * supervisor interrupts and the RM will not be able to disarm automatically
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.  This parameter must specify a value between zero and the
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *
+ *   displayId
+ *     The public ID of the Output Display which is to be used for VRR.
+ *
+ *   bArmLWSV
+ *     If this is set to NV_TRUE, the RM will arm the lightweight supervisor
+ *     for the next modeset.
+ *     If this is set to NV_FALSE, the RM will disarm the lightweight supervisor
+ *
+ *   bVrrState
+ *     VRR state to be changed.
+ *
+ *   vActive
+ *      GPU-SRC vertical active value
+ *
+ *   vfp
+ *      GPU-SRC vertical front porch
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_INVALID_STATE
+ */
+
+#define NV0073_CTRL_CMD_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR (0x73017eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID (0x7EU)
+
+typedef struct NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvBool bArmLWSV;
+    NvBool bVrrState;
+    NvU32  vActive;
+    NvU32  vfp;
+} NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS;
+
+
+
+/*
+* NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS
+*
+* This command is used to configure pstate switch parameters on VRR monitors
+*   subDeviceInstance
+*     This parameter specifies the subdevice instance within the
+*     NV04_DISPLAY_COMMON parent device to which the operation should be
+*     directed.This parameter must specify a value between zero and the
+*     total number of subdevices within the parent device.This parameter
+*     should be set to zero for default behavior.
+*
+*   displayId
+*     DisplayId of the monitor being vrr configured
+*
+*   bVrrState
+*     When set to NV_TRUE, signifies that the vrr is about to become active.
+*     When set to NV_FALSE, signifies that the vrr is about to become suspended.
+*
+*   bVrrDirty
+*     When set to NV_TRUE, indicates that vrr configuration has been changed
+*     When set to NV_FALSE, this will indicate transitions from One shot mode to 
+*     Continuous mode and vice versa 
+*
+*   bVrrEnabled
+*     When set to NV_TRUE, indicates that vrr has been enabled, i.e. vBp extended by 2 lines
+*
+*   maxVblankExtension
+*     When VRR is enabled, this is the maximum amount of lines that the vblank can be extended.
+*     Only updated when bVrrDirty = true
+*
+*   internalVRRHeadVblankStretch
+*     When VRR is enabled, this is the maximum amount of lines that the vblank can be extended.
+*     On NVSR and DD panels . Only updated when bVrrDirty = true
+*
+*   minVblankExtension
+*     When VRR is enabled, this is the minimum amount of lines that should be present in the Vblank. The purpose is to cap the maximum refresh (currently only for HDMI 2.1 VRR compliance)
+*/
+#define NV0073_CTRL_CMD_SYSTEM_CONFIG_VRR_PSTATE_SWITCH (0x730184U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID (0x84U)
+
+typedef struct NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvBool bVrrState;
+    NvBool bVrrDirty;
+    NvBool bVrrEnabled;
+    NvU32  maxVblankExtension;
+    NvU32  internalVRRHeadVblankStretch;
+    NvU32  minVblankExtension;
+} NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX
+ *
+ * This command is used to query the display mask of all displays
+ * that support dynamic display MUX.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   displayMask (out)
+ *     Mask of all displays that support dynamic display MUX
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX (0x730190U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID (0x90U)
+
+typedef struct NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 muxDisplayMask;
+} NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS;
+
+
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH
+ *
+ * This command allocates a specified amount of ISO memory bandwidth for
+ * display.  If the requested amount of bandwidth cannot be allocated (either
+ * because it exceeds the total bandwidth available to the system, or because
+ * too much bandwidth is already allocated to other clients), the call will
+ * fail and NV_ERR_INSUFFICIENT_RESOURCES will be returned.
+ * 
+ * If bandwidth has already been allocated via a prior call, and a new
+ * allocation is requested, the new allocation will replace the old one.  (If
+ * the new allocation fails, the old allocation remains in effect.)
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *   averageBandwidthKBPS
+ *     This parameter specifies the amount of ISO memory bandwidth requested.
+ *   floorBandwidthKBPS
+ *     This parameter specifies the minimum required (i.e., floor) dramclk
+ *     frequency, multiplied by the width of the pipe over which the display
+ *     data will travel.  (It is understood that the bandwidth calculated by
+ *     multiplying the clock frequency by the pipe width will not be
+ *     realistically achievable, due to overhead in the memory subsystem.  The
+ *     API will not actually use the bandwidth value, except to reverse the
+ *     calculation to get the required dramclk frequency.)
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_GENERIC
+ */
+
+#define NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH (0x730196U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x96U)
+
+typedef struct NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 averageBandwidthKBPS;
+    NvU32 floorBandwidthKBPS;
+} NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS;
+
+/*
+ * NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS
+ *
+ * This structure represents the hotplug event config control parameters.
+ *
+ *   subDeviceInstance
+ *     This parameter should specify the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *
+ *   deviceMapFilter
+ *     This parameter returns (in GET) or should specify (in SET) a device map
+ *     indicating device(s) to sense.
+ *
+ *   hotPluginSense
+ *     This parameter returns (in GET) or should specify (in SET) a device map
+ *     indicating device(s) plugged in that caused the most recent hotplug
+ *     event.
+ *
+ *   hotUnplugSense
+ *     This parameter returns (in GET) or should specify (in SET) a device map
+ *     indicating device(s) un plugged that caused the most recent hotplug
+ *     event.
+ */
+
+typedef struct NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS {
+    NvU32 subDeviceInstance;
+    NvU32 deviceMapFilter;
+    NvU32 hotPluginSense;
+    NvU32 hotUnplugSense;
+} NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG
+ *
+ * This command fetches the hotplug event configuration.
+ *
+ * See @ref NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS for documentation on
+ * the parameters.
+ */
+
+#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG  (0x730197U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x97" */
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG
+ *
+ * This command sets the hotplug event configuration.
+ *
+ * See @ref NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS for documentation on
+ * the parameters.
+ */
+
+#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG  (0x730198U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x98" */
+
+
+
+/*
+*  NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS
+*
+*  This command is used to read Core channel, Cursor channel, Window channel, and Head register values and encode these values with ProtoDmp.
+*
+*  subDeviceInstance (in)
+*    This parameter specifies the subdevice instance within the
+*    NV04_DISPLAY_COMMON parent device to which the operation should be
+*    directed.
+*  headMask (in)
+*    Head mask representing which register values should be encoded
+*  windowMask (in)
+*    Window channel mask whose register values should be encoded
+*  bRecordCoreChannel (in)
+*    Indicates whether or not to encode core channel register values
+*  bRecordCursorChannel (in)
+*    Indicates whether or not to encode cursor channel register values
+*
+*  Possible status values returned are:
+*    NV_OK
+*    NV_ERR_INVALID_ARGUMENT
+*    NV_ERR_NOT_SUPPORTED
+*/
+#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS (0x73019bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID (0x9BU)
+
+typedef struct NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  headMask;
+    NvU32  windowMask;
+    NvBool bRecordCoreChannel;
+    NvBool bRecordCursorChannel;
+} NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT
+ *
+ * This command is used to query the display mux status for the given
+ * display device
+ *
+ *   subDeviceInstance (in)
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be
+ *     directed.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT (0x73019cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID (0x9CU)
+
+typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS {
+    NvU32  subDeviceInstance;
+    NvBool bIsSidebandI2cSupported;
+} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS;
+
+/*
+ * NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT
+ *
+ * This command is used to query if SIDEBAND SR can be used with the
+ * given display device. If PSR API is supported on the system,
+ * then sideband SR support is set to false.
+ *
+ *    subDeviceInstance (in)
+ *        This parameter specifies the subdevice instance within the
+ *        NV04_DISPLAY_COMMON parent device to which the operation
+ *        should be directed.
+ *    displayId (in)
+ *        This parameter inputs the displayId of the active display. A value
+ *        of zero indicates no display is active.
+ *    bIsSidebandSrSupported
+ *        If it is true, it means that sideband is supported and not PSR API. 
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_PARAM_STRUCT
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ */
+#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT (0x73019dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID" */
+
+#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID (0x9DU)
+
+typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvBool bIsSidebandSrSupported;
+} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS;
+
+/* _ctrl0073system_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080.h
new file mode 100644
index 0000000..238c0d6
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080.h
@@ -0,0 +1,51 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080.finn
+//
+
+
+
+
+#include "ctrl0080/ctrl0080bif.h"
+#include "ctrl0080/ctrl0080gpu.h"
+#include "ctrl0080/ctrl0080clk.h"
+#include "ctrl0080/ctrl0080dma.h"
+#include "ctrl0080/ctrl0080gr.h"
+#include "ctrl0080/ctrl0080cipher.h"
+#include "ctrl0080/ctrl0080fb.h"
+#include "ctrl0080/ctrl0080fifo.h"
+#include "ctrl0080/ctrl0080host.h"
+
+
+#include "ctrl0080/ctrl0080perf.h"
+#include "ctrl0080/ctrl0080msenc.h"
+#include "ctrl0080/ctrl0080bsp.h"
+#include "ctrl0080/ctrl0080rc.h"
+#include "ctrl0080/ctrl0080nvjpg.h"
+#include "ctrl0080/ctrl0080unix.h"
+#include "ctrl0080/ctrl0080internal.h"
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h
new file mode 100644
index 0000000..4b20dc1
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h
@@ -0,0 +1,73 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080base.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV01_DEVICE_XX/NV03_DEVICE control commands and parameters */
+
+#define NV0080_CTRL_CMD(cat,idx)                NVXXXX_CTRL_CMD(0x0080, NV0080_CTRL_##cat, idx)
+
+/* GPU device command categories (6bits) */
+#define NV0080_CTRL_RESERVED                   (0x00)
+#define NV0080_CTRL_BIF                        (0x01)
+#define NV0080_CTRL_GPU                        (0x02)
+#define NV0080_CTRL_CLK                        (0x10)
+#define NV0080_CTRL_GR                         (0x11)
+#define NV0080_CTRL_CIPHER                     (0x12)
+#define NV0080_CTRL_FB                         (0x13)
+#define NV0080_CTRL_HOST                       (0x14)
+#define NV0080_CTRL_VIDEO                      (0x15)
+#define NV0080_CTRL_FIFO                       (0x17)
+#define NV0080_CTRL_DMA                        (0x18)
+#define NV0080_CTRL_PERF                       (0x19)
+#define NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0x99) /* finn: Evaluated from "(NV0080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV0080_CTRL_MSENC                      (0x1B)
+#define NV0080_CTRL_BSP                        (0x1C)
+#define NV0080_CTRL_RC                         (0x1D)
+#define NV0080_CTRL_OS_UNIX                    (0x1E)
+#define NV0080_CTRL_NVJPG                      (0x1F)
+#define NV0080_CTRL_INTERNAL                   (0x20)
+#define NV0080_CTRL_NVLINK                     (0x21)
+
+/*
+ * NV0080_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0080_CTRL_CMD_NULL                   (0x800000) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* _ctrl0080base_h_ */
+
+/* extract device cap setting from specified category-specific caps table */
+#define NV0080_CTRL_GET_CAP(cat,tbl,c)    \
+    NV0080_CTRL_##cat##_GET_CAP(tbl, NV0080_CTRL_##cat##_CAPS_##c)
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
new file mode 100644
index 0000000..05a18bf
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
@@ -0,0 +1,138 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080bif.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+/*
+ * NV0080_CTRL_CMD_BIF_RESET
+ *
+ * This command initiates the specified reset type on the GPU.
+ *
+ *   flags
+ *     Specifies various arguments to the reset operation.
+ *
+ *     Supported fields include:
+ *
+ *       NV0080_CTRL_BIF_RESET_FLAGS_TYPE
+ *         When set to _SW_RESET, a SW (fullchip) reset is performed. When set
+ *         to _SBR, a secondary-bus reset is performed. When set to
+ *         _FUNDAMENTAL, a fundamental reset is performed.
+ *
+ *         NOTE: _FUNDAMENTAL is not yet supported.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0080_CTRL_CMD_BIF_RESET (0x800102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
+    NvU32 flags;
+} NV0080_CTRL_BIF_RESET_PARAMS;
+
+#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE                2:0
+#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET    (0x00000001)
+#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR         (0x00000002)
+#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL (0x00000003)
+
+/*
+ * NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR
+ *
+ * baseDmaSysmemAddr
+ *    This parameter represents the base DMA address for sysmem which will be
+ *    added to all DMA accesses issued by GPU. Currently GPUs do not support 64-bit physical address,
+ *    hence if sysmem is greater than max GPU supported physical address width, this address
+ *    will be non-zero
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_OBJECT_PARENT
+ */
+
+#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 baseDmaSysmemAddr, 8);
+} NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS;
+
+/*
+ * NV0080_CTRL_BIF_SET_ASPM_FEATURE
+ *
+ * aspmFeatureSupported
+ *    ASPM feature override by client
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE (0x800104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS {
+    NvU32 aspmFeatureSupported;
+} NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS;
+
+#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S                0:0
+#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED  0x000000001
+#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED 0x000000000
+#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1                 1:1
+#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED   0x000000001
+#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED  0x000000000
+
+/*
+ * NV0080_CTRL_BIF_ASPM_CYA_UPDATE
+ *
+ * bL0sEnable
+ * bL1Enable
+ *    ASPM CYA update by client
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE          (0x800105) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS {
+    NvBool bL0sEnable;
+    NvBool bL1Enable;
+} NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS;
+
+/* _ctrl0080bif_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h
new file mode 100644
index 0000000..d4911f5
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h
@@ -0,0 +1,112 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080bsp.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+/* NV01_DEVICE_XX/NV03_DEVICE bit stream processor control commands and parameters */
+
+/*
+ * NV0080_CTRL_CMD_BSP_GET_CAPS
+ *
+ * This command returns the set of BSP capabilities for the device
+ * in the form of an array of unsigned bytes.  BSP capabilities
+ * include supported features and required workarounds for the decoder
+ * within the device, each represented by a byte offset into the
+ * table and a bit position within that byte.
+ *
+ *   capsTblSize
+ *     This parameter specifies the size in bytes of the caps table.
+ *     This value should be set to NV0080_CTRL_BSP_CAPS_TBL_SIZE.
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the BSP caps bits will be transferred by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *   instanceId
+ *     This parameter specifies the instance Id of NVDEC for which
+ *     cap bits are requested. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0080_CTRL_CMD_BSP_GET_CAPS (0x801c01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BSP_INTERFACE_ID << 8) | NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS {
+    NvU32 capsTblSize;
+    NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
+    NvU32 instanceId;
+} NV0080_CTRL_BSP_GET_CAPS_PARAMS;
+
+
+
+/*
+ * Size in bytes of bsp caps table. This value should be one greater
+ * than the largest byte_index value above.
+ */
+#define NV0080_CTRL_BSP_CAPS_TBL_SIZE   8
+
+/*
+ * NV0080_CTRL_CMD_BSP_GET_CAPS_V2
+ *
+ * This command returns the set of BSP capabilities for the device
+ * in the form of an array of unsigned bytes.  BSP capabilities
+ * include supported features and required workarounds for the decoder
+ * within the device, each represented by a byte offset into the
+ * table and a bit position within that byte.
+ * (The V2 version flattens the capsTbl array pointer).
+ *
+ *   capsTbl
+ *     This parameter is an array of unsigned bytes where the BSP caps bits
+ *     will be transferred by the RM.
+ *   instanceId
+ *     This parameter specifies the instance Id of NVDEC for which
+ *     cap bits are requested. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0080_CTRL_CMD_BSP_GET_CAPS_V2 (0x801c02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BSP_INTERFACE_ID << 8) | NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID" */
+
+#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID (0x2U)
+
+typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 {
+    NvU8  capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE];
+    NvU32 instanceId;
+} NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2;
+
+/* _ctrl0080bsp_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h
new file mode 100644
index 0000000..279151b
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080cipher.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h
new file mode 100644
index 0000000..de61930
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080clk.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
new file mode 100644
index 0000000..b209ca2
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
@@ -0,0 +1,908 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080dma.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+/* NV01_DEVICE_XX/NV03_DEVICE dma control commands and parameters */
+
+/*
+ * NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK
+ *
+ *    This parameter returns the parameters specific to a PTE as follows:
+ *       pageSize
+ *           GET: This parameter returns the page size of the PTE information
+ *                being returned.  If 0, then this pteBlock[] array entry is
+ *                invalid or not used.  (pteBlock[0] is always used.)
+ *           SET: This parameter specifies the page size of the PTE information
+ *                to be set.  If 0, then this pteBlock[] array entry is invalid
+ *                or not used.  (pteBlock[0] is always used.)
+ *       pteEntrySize
+ *           GET: This parameter returns the size of the PTE in bytes for this GPU.
+ *           SET: N/A
+ *       comptagLine
+ *           GET: This parameter returns the comptagline field of the corresponding PTE.
+ *           SET: This parameter sets the comptagline field of the corresponding PTE.
+ *                Incorrect values may lead to dire consequences.
+ *       kind
+ *           GET: This parameter returns the kind field of the corresponding PTE.
+ *           SET: This parameter sets the kind field of the corresponding PTE.
+ *                Incorrect values may lead to undesirable consequences.
+ *       pteFlags
+ *           This parameter returns various fields from the PTE, these are:
+ *           FLAGS_VALID:
+ *               GET: This flag returns the valid bit of the PTE.
+ *               SET: This flag sets the valid bit of the PTE.
+ *           FLAGS_ENCRYPTED:
+ *               GET: This flag returns the encrypted bit of the PTE. Not all GPUs
+ *                  support encryption. If not supported, this flag will be set to
+ *                  NOT_SUPPORTED.
+ *               SET: This flag sets the encrypted bit of the PTE.
+ *           FLAGS_APERTURE:
+ *               GET: This flag returns the aperture field of the PTE. See
+ *                    NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values.
+ *               SET: This flag sets the aperture field of the PTE.  See
+ *                    NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values.
+ *           FLAGS_COMPTAGS:
+ *               GET: This flag returns the comptags field of the PTE.  (Not used on Fermi)
+ *               SET: N/A
+ *           FLAGS_GPU_CACHED:
+ *               GET: This flag returns the GPU cacheable bit of the PTE. GPU caching of
+ *                    sysmem was added in iGT21a and Fermi. If not supported, this flag
+ *                    will be set to NOT_SUPPORTED.
+ *               SET: N/A for specific chips, e.g., GF100
+ *           FLAGS_SHADER_ACCESS:
+ *               GET: This flag returns the shader access control of the PTE. This feature
+ *                    was introduced in Kepler.  If not supported, this flag will be set to
+ *                    NOT_SUPPORTED.
+ *               SET: N/A
+ */
+
+typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK {
+    NvU32 pageSize;
+    NV_DECLARE_ALIGNED(NvU64 pteEntrySize, 8);
+    NvU32 comptagLine;
+    NvU32 kind;
+    NvU32 pteFlags;
+} NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK;
+
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID                                     0:0
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE                         (0x00000000U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE                          (0x00000001U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED                                 2:1
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE                     (0x00000000U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE                      (0x00000001U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED             (0x00000002U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE                                  6:3
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY               (0x00000000U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY                (0x00000001U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY     (0x00000002U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS                                  10:7
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE                       (0x00000000U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1                          (0x00000001U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2                          (0x00000002U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4                          (0x00000004U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED                                12:11
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE                    (0x00000000U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE                     (0x00000001U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED            (0x00000002U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS                             14:13
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE            (0x00000000U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY             (0x00000001U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY            (0x00000002U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED         (0x00000003U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY                                 15:15
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE                     (0x00000000U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE                      (0x00000001U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC                                    16:16
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE                      (0x00000000U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE                       (0x00000001U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING                           17:17
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE             (0x00000000U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE              (0x00000001U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED                                18:18
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE                    (0x00000000U)
+#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE                     (0x00000001U)
+
+/*
+ * NV0080_CTRL_DMA_GET_PTE_INFO
+ *
+ * This command queries PTE information for the specified GPU virtual address.
+ *
+ *   gpuAddr
+ *      This parameter specifies the GPU virtual address for which PTE
+ *      information is to be returned.
+ *   skipVASpaceInit
+ *      This parameter specifies(true/false) whether the VA Space
+ *      initialization should be skipped in this ctrl call.
+ *   pteBlocks
+ *      This parameter returns the page size-specific attributes of a PTE.
+ *      Please see NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK.
+ *   hVASpace
+ *      handle for the allocated VA space that this control call should operate
+ *      on. If it's 0, it assumes to use the implicit allocated VA space.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_GENERIC
+ */
+
+#define NV0080_CTRL_CMD_DMA_GET_PTE_INFO                                          (0x801801U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS                                   4U
+
+#define NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
+    NvU32    subDeviceId;
+    NvU8     skipVASpaceInit;
+    NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS], 8);
+    NvHandle hVASpace;
+} NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS;
+
+/*
+ * NV0080_CTRL_DMA_SET_PTE_INFO
+ *
+ * This command sets PTE information for the specified GPU virtual address.
+ * Usage of parameter and field definitions is identical to that of
+ * NV0080_CTRL_DMA_GET_PTE_INFO, with the following exception:
+ *
+ * - pteFlags field NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS is ignored,
+ *   as this setting is specified via the kind specification.
+ * - pteEntrySize is ignored, as this setting is read-only in the GET case.
+ * - hVASpace
+ *    handle for the allocated VA space that this control call should operate
+ *    on. If it's 0, it assumes to use the implicit allocated VA space.
+ *
+ */
+
+#define NV0080_CTRL_CMD_DMA_SET_PTE_INFO        (0x80180aU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 4U
+
+#define NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
+    NvU32    subDeviceId;
+    NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS], 8);
+    NvHandle hVASpace;
+} NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS;
+
+
+#define NV0080_CTRL_CMD_DMA_FILL_PTE_MEM (0x801802U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS {
+    NvU32 pageCount;
+    struct {
+        NvHandle hClient;
+        NvHandle hDevice;
+        NvHandle hMemory;
+        NvU32    subDeviceId;
+    } hwResource;
+    struct {
+        NvU32 fbKind;
+        NvU32 sysKind;
+        NvU32 compTagStartOffset;
+    } comprInfo;
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+    NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
+    NV_DECLARE_ALIGNED(NvP64 pageArray, 8);
+    NV_DECLARE_ALIGNED(NvP64 pteMem, 8);
+    NvU32    pteMemPfn;
+    NvU32    pageSize;
+    NvU32    startPageIndex;
+    NvU32    flags;
+    NvHandle hSrcVASpace;
+    NvHandle hTgtVASpace;
+    NvU32    peerId;
+} NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS;
+
+
+
+/*
+ * NV0080_CTRL_DMA_FLUSH
+ *
+ * This command flushes the specified target unit
+ *
+ *   targetUnit
+ *      The unit to flush, either L2 cache or compression tag cache.
+ *      This field is a logical OR of the individual fields such as
+ *      L2 cache or compression tag cache. Also L2 invalidation for
+ *      either SYSMEM/PEERMEM is triggered. But this invalidation is 
+ *      for FERMI.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_GENERIC
+ *
+ * See Also:
+ *   NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
+ *     Flushes the entire GPU cache or a set of physical addresses (if the
+ *     hardware supports it).  Use this call if you want to flush a set of
+ *     addresses or the entire GPU cache in unicast mode.
+ *   NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
+ *     Flushes memory associated with a single allocation if the hardware
+ *     supports it.  Use this call if you want to flush a single allocation and
+ *     you have a memory object describing the physical memory.
+ */
+#define NV0080_CTRL_CMD_DMA_FLUSH                                                     (0x801805U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV0080_CTRL_DMA_FLUSH_PARAMS {
+    NvU32 targetUnit;
+} NV0080_CTRL_DMA_FLUSH_PARAMS;
+
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2                         0:0
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE            (0x00000000U)
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE             (0x00000001U)
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG                    1:1
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE       (0x00000000U)
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE        (0x00000001U)
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB                         2:2
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE            (0x00000000U)
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE             (0x00000001U)
+
+// This is exclusively for Fermi
+// The selection of non-zero valued bit-fields avoids the routing 
+// into the above cases and vice-versa
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE              4:3
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM  (0x00000001U)
+#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM (0x00000002U)
+
+
+/**
+ * NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS
+ *
+ * This command returns information about the VA caps on the GPU
+ *
+ *   vaBitCount
+ *     Returns number of bits in a virtual address
+ *   pdeCoverageBitCount
+ *     Returns number of VA bits covered in each PDE.  One PDE covers
+ *     2^pdeCoverageBitCount bytes.
+ *
+ *   bigPageSize
+ *     Size of the big page
+ *   compressionPageSize
+ *     Size of region each compression tag covers
+ *   dualPageTableSupported
+ *     TRUE if one page table can map with both 4KB and big pages
+ *
+ *   numPageTableFormats
+ *     Returns the number of different page table sizes supported by the RM
+ *   pageTableBigFormat
+ *   pageTable4KFormat[]
+ *     Returns size in bytes and number of VA bits covered by each page table
+ *     format.  Up to MAX_NUM_PAGE_TABLE_FORMATS can be returned.  The most
+ *     compact format will be pageTableSize[0] and the least compact format
+ *     will be last.
+ *   hVASpace
+ *     handle for the allocated VA space that this control call should operate
+ *     on. If it's 0, it assumes to use the implicit allocated VA space.
+ *   vaRangeLo 
+ *     Indicates the start of usable VA range.
+ *
+ *   hugePageSize
+ *     Size of the huge page if supported, 0 otherwise.
+ *
+ *   vaSpaceId
+ *     Virtual Address Space id assigned by RM.
+ *     Only relevant on AMODEL.
+ *
+ *   pageSize512MB
+ *     Size of the 512MB page if supported, 0 otherwise.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_GENERIC
+ */
+#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS               (0x801806U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID" */
+
+typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT {
+    NvU32 pageTableSize;
+    NvU32 pageTableCoverage;
+} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT;
+
+#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS (16U)
+#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS {
+    NvU32                                                   vaBitCount;
+    NvU32                                                   pdeCoverageBitCount;
+    NvU32                                                   num4KPageTableFormats;
+    NvU32                                                   bigPageSize;
+    NvU32                                                   compressionPageSize;
+    NvU32                                                   dualPageTableSupported;
+    NvU32                                                   idealVRAMPageSize;
+    NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTableBigFormat;
+    NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS];
+    NvHandle                                                hVASpace;
+    NV_DECLARE_ALIGNED(NvU64 vaRangeLo, 8);
+    NvU32                                                   hugePageSize;
+    NvU32                                                   vaSpaceId;
+    NvU32                                                   pageSize512MB;
+} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS;
+
+/*
+ * Adding a version define to allow clients to access valid
+ * parameters based on version.
+ */
+#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO 0x1U
+
+/*
+ * NV0080_CTRL_DMA_GET_PDE_INFO
+ *
+ * This command queries PDE information for the specified GPU virtual address.
+ *
+ *   gpuAddr
+ *       This parameter specifies the GPU virtual address for which PDE
+ *       information is to be returned.
+ *   pdeVirtAddr
+ *       This parameter returns the GPU virtual address of the PDE.
+ *   pdeEntrySize
+ *       This parameter returns the size of the PDE in bytes for this GPU.
+ *   pdeAddrSpace
+ *       This parameter returns the GPU address space of the PDE.
+ *   pdeSize
+ *       This parameter returns the fractional size of the page table(s) as
+ *       actually set in the PDE, FULL, 1/2, 1/4 or 1/8.  (This amount may
+ *       differ from that derived from pdeVASpaceSize.)  Intended for VERIF only.
+ *   pteBlocks
+ *       This parameter returns the page size-specific parameters as follows:
+ *       ptePhysAddr
+ *           This parameter returns the GPU physical address of the page table.
+ *       pteCacheAttrib
+ *           This parameter returns the caching attribute of the
+ *           GPU physical address of the page table.
+ *       pteEntrySize
+ *           This parameter returns the size of the PTE in bytes for this GPU.
+ *       pageSize
+ *           This parameter returns the page size of the page table.
+ *           If pageSize == 0, then this PTE block is not valid.
+ *       pteAddrSpace
+ *           This parameter returns the GPU address space of the page table.
+ *       pdeVASpaceSize
+ *           This parameter returns the size of the VA space addressable by
+ *           the page table if fully used (i.e., if all PTEs marked VALID).
+ *   pdbAddr
+ *       This parameter returns the PDB address for the PDE.
+ *   hVASpace
+ *       handle for the allocated VA space that this control call should operate
+ *       on. If it's 0, it assumes to use the implicit allocated VA space.
+ *   
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_GENERIC
+ */
+#define NV0080_CTRL_CMD_DMA_GET_PDE_INFO                           (0x801809U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID" */
+
+typedef struct NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK {
+    NV_DECLARE_ALIGNED(NvU64 ptePhysAddr, 8);
+    NvU32 pteCacheAttrib;
+    NvU32 pteEntrySize;
+    NvU32 pageSize;
+    NvU32 pteAddrSpace;
+    NvU32 pdeVASpaceSize;
+    NvU32 pdeFlags;
+} NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK;
+
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY               (0x00000000U)
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY     (0x00000001U)
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U)
+
+#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS                                           4U
+
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 pdeVirtAddr, 8);
+    NvU32    pdeEntrySize;
+    NvU32    pdeAddrSpace;
+    NvU32    pdeSize;
+    NvU32    subDeviceId;
+    NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS], 8);
+    NV_DECLARE_ALIGNED(NvU64 pdbAddr, 8);
+    NvHandle hVASpace;
+} NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS;
+
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY               (0x00000000U)
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY     (0x00000001U)
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U)
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL                             1U
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF                             2U
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER                          3U
+#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH                           4U
+
+/*
+ * NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET
+ *
+ * This command invalidates PDB target setting in hardware.
+ * After execeution of this command PDB target would be in undefined state.
+ *
+ * Returns error if the PDB target can not be invalidate.
+ *
+ * This call is only supported on chips fermi and later chips.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET                                     (0x80180bU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | 0xB" */
+
+/*
+ * NV0080_CTRL_CMD_DMA_INVALIDATE_TLB
+ *
+ * This command invalidates the GPU TLB. This is intended to be used
+ * for RM clients that manage their own TLB consistency when updating
+ * page tables on their own, or with DEFER_TLB_INVALIDATION options
+ * to other RM APIs.
+ *
+ *   hVASpace
+ *     This parameter specifies the VASpace object whose MMU TLB entries
+ *     needs to be invalidated, if the flag is set to NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE.
+ *     Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace.
+ *     Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC.
+ *
+ *   flags
+ *     This parameter can be used to specify any flags needed
+ *     for the invlalidation request.
+ *       NV0080_CTRL_DMA_INVALIDATE_TLB_ALL
+ *         When set to TRUE this flag requests a global invalidate.
+ *         When set to FALSE this flag requests a chip-specfic
+ *         optimization to invalidate only the address space bound
+ *         to the associated hDevice.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_TIMEOUT_RETRY
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV0080_CTRL_CMD_DMA_INVALIDATE_TLB                                            (0x80180cU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS {
+    NvHandle hVASpace;
+    NvU32    flags;
+} NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS;
+
+#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL                     0:0
+#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE (0x00000000U)
+#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE  (0x00000001U)
+
+/**
+ * NV0080_CTRL_CMD_DMA_GET_CAPS
+ *
+ * This command returns the set of DMA capabilities for the device
+ * in the form of an array of unsigned bytes.  DMA capabilities
+ * include supported features and required workarounds for address
+ * translation system within the device, each represented by a byte
+ * offset into the table and a bit position within that byte.
+ *
+ *   capsTblSize
+ *     This parameter specifies the size in bytes of the caps table.
+ *     This value should be set to NV0080_CTRL_DMA_CAPS_TBL_SIZE.
+ *
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the framebuffer caps bits will be transferred by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ * 32BIT_POINTER_ENFORCED
+ *     If this property is TRUE NVOS32 and NVOS46 calls with
+ *     32BIT_POINTER_DISABLED will return addresses above 4GB.
+ *
+ * SHADER_ACCESS_SUPPORTED
+ *     If this property is set, the MMU in the system supports the independent
+ *     access bits for the shader.  This is accessed with the following fields:
+ *         NVOS46_FLAGS_SHADER_ACCESS
+ *         NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_FLAGS_SHADER_ACCESS
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0080_CTRL_CMD_DMA_GET_CAPS             (0x80180dU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID" */
+/* size in bytes of fb caps table */
+#define NV0080_CTRL_DMA_CAPS_TBL_SIZE            8U
+#define NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV0080_CTRL_DMA_GET_CAPS_PARAMS {
+    NvU32 capsTblSize;
+    NvU8  capsTbl[NV0080_CTRL_DMA_CAPS_TBL_SIZE];
+} NV0080_CTRL_DMA_GET_CAPS_PARAMS;
+
+/* extract cap bit setting from tbl */
+#define NV0080_CTRL_DMA_GET_CAP(tbl,c)              (((NvU8)tbl[(1?c)]) & (0?c))
+
+/* caps format is byte_index:bit_mask */
+#define NV0080_CTRL_DMA_CAPS_32BIT_POINTER_ENFORCED                0:0x01
+#define NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED               0:0x04
+#define NV0080_CTRL_DMA_CAPS_SPARSE_VIRTUAL_SUPPORTED              0:0x08
+#define NV0080_CTRL_DMA_CAPS_MULTIPLE_VA_SPACES_SUPPORTED          0:0x10
+
+/*
+ * NV0080_CTRL_DMA_SET_VA_SPACE_SIZE
+ *
+ *   Change the size of an existing VA space.
+ *   NOTE: Currently this only supports growing the size, not shrinking.
+ *
+ *   1. Allocate new page directory able to map extended range.
+ *   2. Copy existing PDEs from old directory to new directory.
+ *   3. Initialize new PDEs to invalid.
+ *   4. Update instmem to point to new page directory.
+ *   5. Free old page directory.
+ *
+ *   vaSpaceSize
+ *      On input, the requested size of the VA space in bytes.
+ *      On output, the actual resulting VA space size.
+ *
+ *      The actual size will be greater than or equal to the requested size,
+ *      unless NV0080_CTRL_DMA_GROW_VA_SPACE_SIZE_MAX is requested, which
+ *      requests the maximum available.
+ *      
+ *      NOTE: Specific size requests (e.g. other than SIZE_MAX) must account
+ *            for the VA hole at the beginning of the range which is used to
+ *            distinguish NULL pointers. This region is not counted as part
+ *            of the vaSpaceSize since it is not allocatable.
+ *
+ *   hVASpace
+ *      handle for the allocated VA space that this control call should operate
+ *      on. If it's 0, it assumes to use the implicit allocated VA space
+ *      associated with the client/device pair.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ */
+#define NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE (0x80180eU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8);
+    NvHandle hVASpace;
+} NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS;
+
+#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX (0xFFFFFFFFFFFFFFFFULL)
+
+/*
+ * NV0080_CTRL_DMA_UPDATE_PDE_2
+ *
+ * This command updates a single PDE for the given (hClient, hDevice)
+ * with specific attributes.
+ * This command is only available on Windows and MODS platforms.
+ * This command can be called by kernel clients only.
+ *
+ * The VA range the PDE maps must be contained by a VA allocation marked with
+ * NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED.
+ * However if the MODS-only FORCE_OVERRIDE flag is set this restriction is relaxed.
+ *
+ * RM does not track the PDE's attributes in SW - this control simply stuffs
+ * the PDE in memory after translating and checking the parameters.
+ *
+ * Parameters are checked for relative consistency (e.g. valid domains),
+ * but it is the client's responsibility to provide correct page table
+ * addresses, e.g. global consistency is not checked.
+ *
+ * It is also the client's responsibility to flush/invalidate the MMU
+ * when appropriate, either by setting the _FLUSH_PDE_CACHE flag for this
+ * call or by flushing through other APIs.
+ * This control does not flush automatically to allow batches of calls
+ * to be made before a single flush.
+ *
+ *   ptParams
+ *      Page-size-specific parameters, as follows:
+ *
+ *      physAddr
+ *         Base address of physically contiguous memory of page table.
+ *         Must be aligned sufficiently for the PDE address field.
+ *      numEntries
+ *         Deprecated and ignored.
+ *         Use FLAGS_PDE_SIZE that applies to the tables for all page sizes.
+ *      aperture
+ *         Address space the base address applies to.
+ *         Can be left as INVALID to ignore this page table size.
+ *
+ *   pdeIndex
+ *      The PDE index this update applies to.
+ *   flags
+ *      See NV0080_CTRL_DMA_UPDATE_PDE_FLAGS_*.
+ *   hVASpace
+ *      handle for the allocated VA space that this control call should operate
+ *      on. If it's 0, it assumes to use the implicit allocated VA space
+ *      associated with the client/device pair.
+ *   pPdeBuffer [out]
+ *      Kernel pointer to 64 bit unsigned integer representing a Page Dir Entry
+ *      that needs to be updated. It should point to memory as wide as the Page Dir
+ *      Entry.
+ *
+ *      If NULL, Page Dir Entry updates will go to the internally managed Page Dir.
+ *      If not NULL, the updates will be written to this buffer.
+ *
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0080_CTRL_CMD_DMA_UPDATE_PDE_2      (0x80180fU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID" */
+
+typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
+    NvU32 numEntries;   // deprecated
+    NvU32 aperture;
+} NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS;
+
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID                    (0x00000000U)
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY               (0x00000001U)
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY     (0x00000002U)
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U)
+
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL                           0U
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG                             1U
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE                           2U
+
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS {
+    NvU32    pdeIndex;
+    NvU32    flags;
+    NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE], 8);
+    NvHandle hVASpace;
+    NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_DUAL_PDE__SIZE
+    NvU32    subDeviceId; // ID+1, 0 for BC
+} NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS;
+
+/*!
+ * If set a PDE cache flush (MMU invalidate) will be performed.
+ */
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE          0:0
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE (0x00000000U)
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE  (0x00000001U)
+
+/*!
+ * For verification purposes (MODS-only) this flag may be set to modify any PDE
+ * in the VA space (RM managed or externally managed).
+ * It is up to caller to restore any changes properly (or to expect faults).
+ */
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE           1:1
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE  (0x00000000U)
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE   (0x00000001U)
+
+/*!
+ * Directly controls the PDE_SIZE field (size of the page tables pointed to by this PDE).
+ */
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE                 3:2
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL         (0x00000000U)
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF         (0x00000001U)
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER      (0x00000002U)
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH       (0x00000003U)
+
+/*! 
+ * Used to specify if the allocation is sparse. Applicable only in case of 
+ * VA Space managed by OS, as in WDDM2.0
+ */
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE                   4:4
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE          (0x00000000U)
+#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE           (0x00000001U)
+
+/*
+ * NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE
+ * This interface will create a corresponding privileged
+ * kernel address space that will mirror user space allocations in this
+ * VASPACE.
+ * The user can either pass a FERMI_VASPACE_A handle or RM will use the 
+ * vaspace associated with the client/device if hVaspace is passed as 
+ * NULL.
+ * Once this property is set, the user will not be able to make allocations
+ * from  the top most PDE of this address space.
+ *
+ * The user is expected to call this function as soon as he has created 
+ * the device/Vaspace object. If the user has already made VA allocations 
+ * in this vaspace then this call will return a failure 
+ * (NV_ERR_INVALID_STATE). 
+ * The Vaspace should have no VA allocations when this call is made.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+*/
+#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE                  (0x801810U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS {
+    NvHandle hVASpace;
+} NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS;
+
+/*
+ * NV0080_CTRL_DMA_SET_DEFAULT_VASPACE
+ * This is a special control call provided for KMD to use. 
+ * It will associate an allocated Address Space Object as the 
+ * default address space of the device.
+ * 
+ * This is added so that the USER can move to using address space objects when they 
+ * want to specify the size of the big page size they want to use but still want
+ * to use the rest of the relevant RM apis without specifying the hVASpace.
+ * 
+ * This call will succeed only if there is already no VASPACE associated with the 
+ * device. This means the user will have to call this before he has made any allocations
+ * on this device/address space.
+ *
+ * The hVASpace that is passed in to be associated shoould belong to the parent device that
+ * this call is made for. This call will fail if we try to associate a VASpace belonging to 
+ * some other client/device.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ *  
+ */
+#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE (0x801812U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS {
+    NvHandle hVASpace;
+} NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS;
+
+/*!
+ * NV0080_CTRL_DMA_SET_PAGE_DIRECTORY
+ *
+ * Move an existing VA space to an externally-managed top-level page directory.
+ * The VA space must have been created in SHARED_MANAGEMENT mode.
+ * For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h.
+ *
+ * RM will propagate the update to all channels using the VA space.
+ *
+ * NOTE: All channels using this VA space are expected to be idle and unscheduled prior
+ *       to and during this control call - it is responsibility of caller to ensure this.
+ *
+ *   physAddress
+ *      Physical address of the new page directory within the aperture specified by flags.
+ *   numEntries
+ *      Number of entries in the new page directory.
+ *      The backing phyical memory must be at least this size (multiplied by entry size).
+ *   flags
+ *      APERTURE
+ *          Specifies which physical aperture the page directory resides.
+ *      PRESERVE_PDES
+ *          Deprecated - RM will always copy the RM-managed PDEs from the old page directory
+ *          to the new page directory.
+ *      ALL_CHANNELS
+ *          If true, RM will update the instance blocks for all channels using
+ *          the VAS and ignore the chId parameter.
+ *      EXTEND_VASPACE
+ *          If true, RM will use the client VA for client VA requests in VASPACE_SHARED_MANAGEMENT mode
+ *          If false, RM will use the internal VA for client VA requests.
+ *      IGNORE_CHANNEL_BUSY
+ *          If true, RM will ignore the channel busy status during set page
+ *          directory operation.
+ *   hVASpace
+ *      handle for the allocated VA space that this control call should operate
+ *      on. If it's 0, it assumes to use the implicit allocated VA space
+ *      associated with the client/device pair.
+ *   chId
+ *      ID of the Channel to be updated.
+ *   pasid
+ *      PASID (Process Address Space IDentifier) of the process corresponding to
+ *      the VA space. Ignored unless the VA space has ATS enabled.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_LIMIT
+ *   NV_ERR_GENERIC
+ */
+#define NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (0x801813U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
+    NvU32    numEntries;
+    NvU32    flags;
+    NvHandle hVASpace;
+    NvU32    chId;
+    NvU32    subDeviceId; // ID+1, 0 for BC
+    NvU32    pasid;
+} NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS;
+
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE                  1:0
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM           (0x00000000U)
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH       (0x00000001U)
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH    (0x00000002U)
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES             2:2
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE       (0x00000000U)
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE        (0x00000001U)
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS              3:3
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE        (0x00000000U)
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE         (0x00000001U)
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY       4:4
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE (0x00000000U)
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE  (0x00000001U)
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE            5:5
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE      (0x00000000U)
+#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE       (0x00000001U)
+
+/*!
+ * NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY
+ *
+ * Restore an existing VA space to an RM-managed top-level page directory.
+ * The VA space must have been created in SHARED_MANAGEMENT mode and
+ * previously relocated to an externally-managed page directory with
+ * NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (these two API are symmetric operations).
+ * For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h.
+ *
+ * RM will propagate the update to all channels using the VA space.
+ *
+ * NOTE: All channels using this VA space are expected to be idle and unscheduled prior
+ *       to and during this control call - it is responsibility of caller to ensure this.
+ *
+ *   hVASpace
+ *      handle for the allocated VA space that this control call should operate
+ *      on. If it's 0, it assumes to use the implicit allocated VA space
+ *      associated with the client/device pair.
+ */
+#define NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY                           (0x801814U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS {
+    NvHandle hVASpace;
+    NvU32    subDeviceId; // ID+1, 0 for BC
+} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS;
+
+
+
+/* _ctrl0080dma_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
new file mode 100644
index 0000000..7fcc696
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
@@ -0,0 +1,232 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080fb.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+/* NV01_DEVICE_XX/NV03_DEVICE fb control commands and parameters */
+
+/**
+ * NV0080_CTRL_CMD_FB_GET_CAPS
+ *
+ * This command returns the set of framebuffer capabilities for the device
+ * in the form of an array of unsigned bytes.  Framebuffer capabilities
+ * include supported features and required workarounds for the framebuffer
+ * engine(s) within the device, each represented by a byte offset into the
+ * table and a bit position within that byte.
+ *
+ *   capsTblSize
+ *     This parameter specifies the size in bytes of the caps table.
+ *     This value should be set to NV0080_CTRL_FB_CAPS_TBL_SIZE.
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the framebuffer caps bits will be transferred by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_POINTER
+ */
+#define NV0080_CTRL_CMD_FB_GET_CAPS (0x801301) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0080_CTRL_FB_GET_CAPS_PARAMS {
+    NvU32 capsTblSize;
+    NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
+} NV0080_CTRL_FB_GET_CAPS_PARAMS;
+
+/* extract cap bit setting from tbl */
+#define NV0080_CTRL_FB_GET_CAP(tbl,c)              (((NvU8)tbl[(1?c)]) & (0?c))
+
+/* caps format is byte_index:bit_mask */
+#define NV0080_CTRL_FB_CAPS_SUPPORT_RENDER_TO_SYSMEM                                0:0x01
+#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR                                             0:0x02
+#define NV0080_CTRL_FB_CAPS_SUPPORT_SCANOUT_FROM_SYSMEM                             0:0x04
+#define NV0080_CTRL_FB_CAPS_SUPPORT_CACHED_SYSMEM                                   0:0x08
+#define NV0080_CTRL_FB_CAPS_SUPPORT_C24_COMPRESSION                                 0:0x10 // Deprecated
+#define NV0080_CTRL_FB_CAPS_SUPPORT_SYSMEM_COMPRESSION                              0:0x20
+#define NV0080_CTRL_FB_CAPS_NISO_CFG0_BUG_534680                                    0:0x40 // Deprecated
+#define NV0080_CTRL_FB_CAPS_ISO_FETCH_ALIGN_BUG_561630                              0:0x80 // Deprecated
+
+#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR_GOBS_512                                    1:0x01
+#define NV0080_CTRL_FB_CAPS_L2_TAG_BUG_632241                                       1:0x02
+#define NV0080_CTRL_FB_CAPS_SINGLE_FB_UNIT                                          1:0x04 // Deprecated
+#define NV0080_CTRL_FB_CAPS_CE_RMW_DISABLE_BUG_897745                               1:0x08 // Deprecated
+#define NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB                             1:0x10
+#define NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET                                  1:0x20 // Deprecated
+#define NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641  1:0x40
+
+#define NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803                        2:0x01
+#define NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED                               2:0x02
+#define NV0080_CTRL_FB_CAPS_DISABLE_PLC_GLOBALLY                                    2:0x04
+#define NV0080_CTRL_FB_CAPS_PLC_BUG_3046774                                         2:0x08
+
+
+/* size in bytes of fb caps table */
+#define NV0080_CTRL_FB_CAPS_TBL_SIZE         3
+
+
+
+/*!
+ * NV0080_CTRL_CMD_FB_COMPBIT_STORE_GET_INFO
+ *
+ * This command returns compbit backing store-related information.
+ *
+ *   size
+ *     [out] Size of compbit store, in bytes
+ *   address
+ *     [out] Address of compbit store
+ *   addressSpace
+ *     [out] Address space of compbit store (corresponds to type NV_ADDRESS_SPACE in nvrm.h)
+ *   maxCompbitLine
+ *     [out] Maximum compbitline possible, determined based on size
+ *   comptagsPerCacheLine
+ *     [out] Number of compression tags per compression cache line, across all
+ *           L2 slices.
+ *   cacheLineSize
+ *     [out] Size of compression cache line, across all L2 slices. (bytes)
+ *   cacheLineSizePerSlice
+ *     [out] Size of the compression cache line per slice (bytes)
+ *   cacheLineFetchAlignment
+ *     [out] Alignment used while fetching the compression cacheline range in FB.
+ *           If start offset of compcacheline in FB is S and end offset is E, then
+ *           the range to fetch to ensure entire compcacheline data is extracted is:
+ *           (align_down(S) , align_up(E))
+ *           This is needed in GM20X+ because of interleaving of data in Linear FB space.
+ *           Example - In GM204 every other 1K FB chunk of data is offset by 16K.
+ *   backingStoreBase
+ *     [out] Address of start of Backing Store in linear FB Physical Addr space.
+ *           This is the actual offset in FB which HW starts using as the Backing Store and
+ *           in general will be different from the start of the region that driver allocates
+ *           as the backing store. This address is expected to be 2K aligned.
+ *   gobsPerComptagPerSlice
+ *     [out] (Only on Pascal) Number of GOBS(512 bytes of surface PA) that correspond to one 64KB comptgaline, per slice.
+ *           One GOB stores 1 byte of compression bits.
+ *           0 value means this field is not applicable for the current architecture.
+ *   backingStoreCbcBase
+ *     [out] 2KB aligned base address of CBC (post divide address)
+ *   comptaglineAllocationPolicy
+ *     [out] Policy used to allocate comptagline from CBC for the device
+ *   privRegionStartOffset
+ *     [out] Starting offset for any priv region allocated by clients. only used by MODS
+ *   Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO (0x801306) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 Size, 8);
+    NV_DECLARE_ALIGNED(NvU64 Address, 8);
+    NvU32 AddressSpace;
+    NvU32 MaxCompbitLine;
+    NvU32 comptagsPerCacheLine;
+    NvU32 cacheLineSize;
+    NvU32 cacheLineSizePerSlice;
+    NvU32 cacheLineFetchAlignment;
+    NV_DECLARE_ALIGNED(NvU64 backingStoreBase, 8);
+    NvU32 gobsPerComptagPerSlice;
+    NvU32 backingStoreCbcBase;
+    NvU32 comptaglineAllocationPolicy;
+    NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8);
+} NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS;
+
+#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN
+#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM  1 // ADDR_SYSMEM
+#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM   2 // ADDR_FBMEM
+
+// Policy used to allocate comptaglines
+/**
+ * Legacy mode allocates a comptagline for 64kb page. This mode will always allocate
+ * contiguous comptaglines from a ctag heap.
+ */
+#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY         0
+/**
+ * 1TO1 mode allocates a comptagline for 64kb page. This mode will calculate
+ * comptagline offset based on physical address. This mode will allocate
+ * contiguous comptaglines if the surface is contiguous and non-contiguous
+ * comptaglines for non-contiguous surfaces.
+ */
+#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1           1
+/**
+ * 1TO4_Heap mode allocates a comptagline for 256kb page granularity. This mode
+ * will allocate comptagline from a heap. This mode will align the surface allocations
+ * to 256kb before allocating comptaglines. The comptaglines allocated will always be
+ * contiguous here.
+ * TODO: For GA10x, this mode will support < 256kb surface allocations, by sharing
+ * a comptagline with at most 3 different 64Kb allocations. This will result in
+ * miixed-contiguity config where comptaglines will be allocated contiguously as well
+ * as non-contiguous when shared with other allocations.
+ */
+#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4           2
+/**
+ * Rawmode will transfer allocation of comptaglines to HW, where HW manages
+ * comptaglines based on physical offset. The comptaglines are cleared when SW
+ * issues physical/virtual scrub to the surface before reuse.
+ */
+#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE        3
+
+/**
+ * NV0080_CTRL_CMD_FB_GET_CAPS_V2
+ *
+ * This command returns the same set of framebuffer capabilities for the
+ * device as @ref NV0080_CTRL_CMD_FB_GET_CAPS. The difference is in the structure
+ * NV0080_CTRL_FB_GET_CAPS_V2_PARAMS, which contains a statically sized array,
+ * rather than a caps table pointer and a caps table size in
+ * NV0080_CTRL_FB_GET_CAPS_PARAMS.
+ *
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the framebuffer caps bits will be written by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_POINTER
+ */
+#define NV0080_CTRL_CMD_FB_GET_CAPS_V2                                  (0x801307) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS {
+    NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE];
+} NV0080_CTRL_FB_GET_CAPS_V2_PARAMS;
+
+
+
+
+/* _ctrl0080fb_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h
new file mode 100644
index 0000000..823cc0c
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h
@@ -0,0 +1,642 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080fifo.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+/* NV01_DEVICE_XX/NV03_DEVICE fifo control commands and parameters */
+
+/**
+ * NV0080_CTRL_FIFO_GET_CAPS
+ *
+ * This command returns the set of FIFO engine capabilities for the device
+ * in the form of an array of unsigned bytes.  FIFO capabilities
+ * include supported features and required workarounds for the FIFO
+ * engine(s) within the device, each represented by a byte offset into the
+ * table and a bit position within that byte.
+ *
+ *   capsTblSize
+ *     This parameter specifies the size in bytes of the caps table.
+ *     This value should be set to NV0080_CTRL_FIFO_CAPS_TBL_SIZE.
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the framebuffer caps bits will be transferred by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0080_CTRL_CMD_FIFO_GET_CAPS (0x801701) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0080_CTRL_FIFO_GET_CAPS_PARAMS {
+    NvU32 capsTblSize;
+    NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
+} NV0080_CTRL_FIFO_GET_CAPS_PARAMS;
+
+/* extract cap bit setting from tbl */
+#define NV0080_CTRL_FIFO_GET_CAP(tbl,c)            (((NvU8)tbl[(1?c)]) & (0?c))
+
+/* caps format is byte_index:bit_mask */
+#define NV0080_CTRL_FIFO_CAPS_SUPPORT_SCHED_EVENT                    0:0x01
+#define NV0080_CTRL_FIFO_CAPS_SUPPORT_PCI_PB                         0:0x02
+#define NV0080_CTRL_FIFO_CAPS_SUPPORT_VID_PB                         0:0x04
+#define NV0080_CTRL_FIFO_CAPS_USERD_IN_SYSMEM                        0:0x40
+/* do not use pipelined PTE BLITs to update PTEs:  call the RM */
+#define NV0080_CTRL_FIFO_CAPS_NO_PIPELINED_PTE_BLIT                  0:0x80
+#define NV0080_CTRL_FIFO_CAPS_GPU_MAP_CHANNEL                        1:0x01
+#define NV0080_CTRL_FIFO_CAPS_BUFFEREDMODE_SCHEDULING                1:0x02 // Deprecated
+#define NV0080_CTRL_FIFO_CAPS_WFI_BUG_898467                         1:0x08 // Deprecated
+#define NV0080_CTRL_FIFO_CAPS_HAS_HOST_LB_OVERFLOW_BUG_1667921       1:0x10
+/*
+ * To indicate Volta subcontext support with multiple VA spaces in a TSG.
+ * We are not using "subcontext" tag for the property, since we also use
+ * subcontext to represent pre-VOlta SCG feature, which only allows a single
+ * VA space in a TSG.
+ */
+#define NV0080_CTRL_FIFO_CAPS_MULTI_VAS_PER_CHANGRP                  1:0x20
+
+
+#define NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING              1:0x40
+
+/* size in bytes of fifo caps table */
+#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE           2
+
+/*
+ * NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS
+ *
+ * This command enables the GPU to place various scheduling events in the
+ * off chip event buffer (with optional interrupt) for those GPUs that support
+ * it.
+ *
+ *   record
+ *     This parameter specifies a mask of event types to record.
+ *   interrupt
+ *     This parameter specifies a mask of event types for which to interrupt
+ *     the CPU when the event occurs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS (0x801703) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x3" */
+
+typedef struct NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS {
+    NvU32 record;
+    NvU32 interrupt;
+} NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS;
+
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX             0:0
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_DISABLE   (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_ENABLE    (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX               1:1
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_DISABLE     (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_ENABLE      (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST           2:2
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_DISABLE (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_ENABLE  (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE           3:3
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_DISABLE (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_ENABLE  (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT            4:4
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_DISABLE  (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_ENABLE   (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT               5:5
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_DISABLE     (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_ENABLE      (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD                 6:6
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_DISABLE       (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_ENABLE        (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX              7:7
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_DISABLE    (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_ENABLE     (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI                8:8
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_DISABLE      (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_ENABLE       (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED           9:9
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_DISABLE (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_ENABLE  (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC                 10:10
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_DISABLE       (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_ENABLE        (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT            11:11
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_DISABLE  (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_ENABLE   (0x00000001)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL                   11:0
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_DISABLE         (0x00000000)
+#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_ENABLE          (0x00000fff)
+
+/*
+ * NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS
+ *
+ * This command allows the caller to request that a set of channels
+ * be added to the runlist.
+ *
+ *   fifoStartChannelListSize
+ *     Size of the fifoStartChannelList.  The units are in entries, not
+ *     bytes.
+ *   fifoStartChannelList
+ *     This will be a list of NV0080_CTRL_FIFO_CHANNEL data structures, 
+ *     one for each channel that is to be started.
+ *   channelHandle
+ *     deprecated
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+/*
+ *   hChannel
+ *     This is the handle to the channel that is scheduled to be started.
+ */
+typedef struct NV0080_CTRL_FIFO_CHANNEL {
+    NvHandle hChannel;
+} NV0080_CTRL_FIFO_CHANNEL;
+
+#define NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS (0x801705) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS {
+    NvU32    fifoStartChannelListCount;
+    NvHandle channelHandle[8];
+    NV_DECLARE_ALIGNED(NvP64 fifoStartChannelList, 8);
+} NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS;
+
+#define NV0080_CTRL_FIFO_ENGINE_ID_GRAPHICS                                               (0x00000000)
+#define NV0080_CTRL_FIFO_ENGINE_ID_MPEG                                                   (0x00000001)
+#define NV0080_CTRL_FIFO_ENGINE_ID_MOTION_ESTIMATION                                      (0x00000002)
+#define NV0080_CTRL_FIFO_ENGINE_ID_VIDEO                                                  (0x00000003)
+#define NV0080_CTRL_FIFO_ENGINE_ID_BITSTREAM                                              (0x00000004)
+#define NV0080_CTRL_FIFO_ENGINE_ID_ENCRYPTION                                             (0x00000005)
+#define NV0080_CTRL_FIFO_ENGINE_ID_FGT                                                    (0x00000006)
+
+/*
+ * NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES
+ *
+ * This command is used to provide the caller with the alignment and size
+ * of the context save region for an engine
+ *
+ *   engineId
+ *     This parameter is an input parameter specifying the engineId for which
+ *     the alignment/size is requested.
+ *   alignment
+ *     This parameter is an output parameter which will be filled in with the
+ *     minimum alignment requirement.
+ *   size
+ *     This parameter is an output parameter which will be filled in with the
+ *     minimum size of the context save region for the engine.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES                                (0x801707) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID                          4:0
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS                 (0x00000000)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD                      (0x00000001)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO                    (0x00000002)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG                     (0x00000003)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE                  (0x00000004)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY                  (0x00000005)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION               (0x00000006)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS              (0x00000007)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL           (0x00000008)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM              (0x00000009)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT          (0x0000000a)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT         (0x0000000b)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL           (0x0000000c)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL        (0x0000000d)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB          (0x0000000e)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV             (0x0000000f)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH           (0x00000010)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB       (0x00000011)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL (0x00000012)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB    (0x00000013)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL   (0x00000014)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL       (0x00000015)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK   (0x00000016)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT      (0x00000017)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP (0x00000018)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT                    (0x00000019)
+#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS {
+    NvU32 engineId;
+    NvU32 alignment;
+    NvU32 size;
+} NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS;
+
+/*
+ * NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS      <Deprecated since Fermi+>
+ *
+ * This command allows the caller to group two sets of channels.  A channel 
+ * set includes one or more channels.  After grouping, the grouped channel IDs 
+ * are set to next to each other in the runlist.  This command can be used 
+ * several times to group more than two channels. 
+ *
+ * Using a NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE after 
+ * NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the general usage.  A 
+ * NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a 
+ * NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not 
+ * allowed.
+ *
+ * NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS defines the max channels in a 
+ * group.
+ *
+ *   hChannel1
+ *     This parameter specifies the handle of the channel that belongs to the 
+ *     base set of channels.
+ *   hChannel2
+ *     This parameter specifies the handle of the channel that belongs to the 
+ *     additional set of channels.
+
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_CHANNEL
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS (0x801709) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x9" */
+
+typedef struct NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM {
+    NvHandle hChannel1;
+    NvHandle hChannel2;
+} NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM;
+
+#define NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS   (8)
+
+/*
+ * NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE        <Deprecated since Fermi+>
+ *
+ * This command allows the caller to divide the timeslice (DMA_TIMESLICE) of a 
+ * channel between the channels in the group in which the channel resides.  
+ * After applying this command, a timeslice divided channel (group) has a
+ * short timeslice and repeats more than once in the runlist.  The total
+ * available execution time is not changed.
+ *
+ * Using this command after NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the 
+ * general usage.  A NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a 
+ * NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not 
+ * allowed.
+ *
+ *   hChannel
+ *     This parameter specifies the handle of the channel for the channel
+ *     group to which the divided timeslice operation will apply.
+ *   tsDivisor
+ *     This parameter specifies the timeslice divisor value.  This value
+ *     should not exceed NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_CHANNEL
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ */
+#define NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE (0x80170b) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xB" */
+
+typedef struct NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM {
+    NvHandle hChannel;
+    NvU32    tsDivisor;
+} NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM;
+
+#define NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR (12)
+
+/*
+ * NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST                 <Deprecated since Fermi+>
+ *
+ * This command preepmts the engine represented by the specified runlist.
+ * 
+ *   hRunlist
+ *     This parameter specifies the per engine runlist handle. This
+ *     parameter is being retained to maintain backwards compatibility
+ *     with clients that have not transitioned over to using runlists
+ *     on a per subdevice basis.
+ *
+ *   engineID
+ *     This parameter specifies the engine to be preempted. Engine defines
+ *     can be found in cl2080.h. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST           (0x80170c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xC" */
+
+typedef struct NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS {
+    NvHandle hRunlist;
+    NvU32    engineID;
+} NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS;
+
+
+/*
+ * NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST
+ *
+ * Takes a list of hChannels as input and returns the
+ * corresponding Channel IDs that they corresponding to
+ * on hw.
+ * 
+ *   numChannels
+ *     Size of input hChannellist
+ *   pChannelHandleList
+ *     List of input channel handles
+ *   pChannelList
+ *     List of Channel ID's corresponding to the
+ *     each entry in the hChannelList.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST (0x80170d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS {
+    NvU32 numChannels;
+    NV_DECLARE_ALIGNED(NvP64 pChannelHandleList, 8);
+    NV_DECLARE_ALIGNED(NvP64 pChannelList, 8);
+} NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS;
+
+
+/*
+ * NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE
+ *
+ *  This control call is used to return the number of gp methods(gpsize) and push buffer methods(pbsize)
+ *  allocated to each engine.
+ *
+ *engineID
+ *  The engine ID which is an input
+ *
+ *gpEntries
+ *  number of gp entries
+ *
+ *pbEntries
+ *  number of pb entries (in units of 32B rows)
+ *
+ */
+
+
+#define NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE (0x80170e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS {
+    NvU32 engineID;
+    NvU32 gpEntries;
+    NvU32 pbEntries;
+} NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS;
+
+#define NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL (0xffffffff)
+
+/*
+ * NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES
+ * 
+ * This command allows internal properties of the channel
+ * to be modified even when the channel is active. Most of these properties 
+ * are not meant to be modified during normal runs hence have been
+ * kept separate from channel alloc params. It is the
+ * responsibility of the underlying hal routine to make
+ * sure the channel properties are changed while the channel
+ * is *NOT* in a transient state.
+ * 
+ *   hChannel
+ *     The handle to the channel.
+ *
+ *   property
+ *     The channel property to be modified.
+ *     NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_xxx provides the entire list
+ *     of properties.
+ *
+ *   value
+ *     The new value for the property.
+ *     When property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS
+ *          value    = timeslice in microseconds
+ *          desc:      Used to change a channel's engine timeslice in microseconds
+ *
+ *          property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS
+ *          value    = timeslice in microseconds
+ *          desc:      Used to change a channel's pbdma timeslice in microseconds
+ *
+ *          property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE
+ *          value    is ignored
+ *          desc:      Disables a channel from being timesliced out from an engine.
+ *                     Other scheduling events like explicit yield, acquire failures will
+ *                     switch out the channel though.
+ *
+ *          property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE
+ *          value    is ignored
+ *          desc:      Disables a channel from being timesliced out from its pbdma.
+ *
+ *          property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET
+ *          value    is ignored
+ *          desc:      Override the channel's page directory pointer table with an
+ *                     erroneous aperture value. (TODO: make test calls NV_VERIF_FEATURES
+ *                     only)(VERIF ONLY)
+ *                     
+ *          property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT
+ *          value    = engineID of engine that will have its context pointer reset.
+ *                     engineID defines can be found in cl2080.h
+ *                     (e.g., NV2080_ENGINE_TYPE_GRAPHICS)
+ *          desc:      Override the channel's engine context pointer with a non existent
+ *                     buffer forcing it to fault. (VERIF ONLY)
+ *                     
+ *          property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT
+ *          value    = engineID of engine that will have its context pointer reset.
+ *                     engineID defines can be found in cl2080.h
+ *                     (e.g., NV2080_ENGINE_TYPE_GRAPHICS)
+ *          desc:      Override the channel's engine context pointer with a non existent
+ *                     buffer forcing it to fault. However the channel will not be preempted
+ *                     before having its channel state modified.(VERIF ONLY)
+ *
+ *          property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP
+ *          value    is ignored
+ *          desc:      does not change any channel state exercises a full channel preempt/
+ *                     unbind/bind op. (VERIF ONLY)
+ *          
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_CHANNEL
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES      (0x80170f) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS {
+    NvHandle hChannel;
+    NvU32    property;
+    NV_DECLARE_ALIGNED(NvU64 value, 8);
+} NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS;
+
+#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS (0x00000000)
+#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS  (0x00000001)
+#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE        (0x00000002)
+#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE         (0x00000003)
+#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET         (0x00000004)
+#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT            (0x00000005)
+#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP                          (0x00000007)
+#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT  (0x00000008)
+
+
+
+/*
+ * NV0080_CTRL_CMD_FIFO_STOP_RUNLIST
+ *
+ * Stops all processing on the runlist for the given engine.  This is only
+ * valid in per-engine round-robin scheduling mode.
+ * 
+ *   engineID
+ *     This parameter specifies the engine to be stopped. Engine defines
+ *     can be found in cl2080.h. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV0080_CTRL_CMD_FIFO_STOP_RUNLIST (0x801711) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS {
+    NvU32 engineID;
+} NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS;
+
+/*
+ * NV0080_CTRL_CMD_FIFO_START_RUNLIST
+ *
+ * Restarts a runlist previously stopped with NV0080_CTRL_CMD_FIFO_STOP_RUNLIST.
+ * This is only valid for per-engine round-robin mode.
+ * 
+ *   engineID
+ *     This parameter specifies the engine to be started. Engine defines
+ *     can be found in cl2080.h. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV0080_CTRL_CMD_FIFO_START_RUNLIST (0x801712) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV0080_CTRL_FIFO_START_RUNLIST_PARAMS {
+    NvU32 engineID;
+} NV0080_CTRL_FIFO_START_RUNLIST_PARAMS;
+
+/**
+ * NV0080_CTRL_FIFO_GET_CAPS_V2
+ *
+ * This command returns the same set of FIFO engine capabilities for the device
+ * as @ref NV0080_CTRL_FIFO_GET_CAPS. The difference is in the structure
+ * NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS, which contains a statically sized array,
+ * rather than a caps table pointer and a caps table size in
+ * NV0080_CTRL_FIFO_GET_CAPS_PARAMS.
+ *
+ *   capsTbl
+ *     This parameter is an array of the client's caps table buffer.
+ *     The framebuffer caps bits will be written by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 (0x801713) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS {
+    NvU8 capsTbl[NV0080_CTRL_FIFO_CAPS_TBL_SIZE];
+} NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS;
+
+/**
+ * NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS
+ *
+ * @brief This command idles (deschedules and waits for pending work to complete) channels
+ *        belonging to a particular device.
+ *
+ *   numChannels
+ *     Number of channels to idle
+ *
+ *   hChannels
+ *     Array of channel handles to idle
+ *
+ *   flags
+ *     NVOS30_FLAGS that control aspects of how the channel is idled
+ *
+ *   timeout
+ *     GPU timeout in microseconds, for each CHID Manager's idling operation
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_TIMEOUT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_LOCK_STATE
+ */
+#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS              (0x801714) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
+#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS 4096
+
+#define NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS {
+    NvU32    numChannels;
+    NvHandle hChannels[NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS];
+    NvU32    flags;
+    NvU32    timeout;
+} NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS;
+
+/* _ctrl0080fifo_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
new file mode 100644
index 0000000..5ce19e5
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
@@ -0,0 +1,585 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080gpu.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+#include "nvlimits.h"
+
+
+/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */
+
+/*
+ * NV0080_CTRL_CMD_GPU_GET_CLASSLIST
+ *
+ * This command returns supported class information for the specified device.
+ * If the device is comprised of more than one GPU, the class list represents
+ * the set of supported classes common to all GPUs within the device.
+ *
+ * It has two modes:
+ *
+ * If the classList pointer is NULL, then this command returns the number
+ * of classes supported by the device in the numClasses field.  The value
+ * should then be used by the client to allocate a classList buffer
+ * large enough to hold one 32bit value per numClasses entry.
+ *
+ * If the classList pointer is non-NULL, then this command returns the
+ * set of supported class numbers in the specified buffer.
+ *
+ *   numClasses
+ *     If classList is NULL, then this parameter will return the
+ *     number of classes supported by the device.  If classList is non-NULL,
+ *     then this parameter indicates the number of entries in classList.
+ *   classList
+ *     This parameter specifies a pointer to the client's buffer into
+ *     which the supported class numbers should be returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST (0x800201) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS {
+    NvU32 numClasses;
+    NV_DECLARE_ALIGNED(NvP64 classList, 8);
+} NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS;
+
+/**
+ * NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES
+ *
+ * This command returns the number of subdevices for the device.
+ *
+ *   numSubDevices
+ *     This parameter returns the number of subdevices within the device.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES (0x800280) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID (0x80U)
+
+typedef struct NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS {
+    NvU32 numSubDevices;
+} NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS;
+
+/*
+ * NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER
+ *
+ * This command returns the video link order of each subdevice id inside the
+ * device.  This call can only be made after SLI is enabled.  This call is
+ * intended for 3D clients to use to determine the vidlink order of the
+ * devices.  The Display Output Parent will always be the first subdevice
+ * mask listed in the array.  Note that this command should not be used in
+ * case of bridgeless SLI.  The order of the subdevices returned by this
+ * command will not be correct in case of bridgeless SLI.
+ *
+ *   ConnectionCount
+ *     Each HW can provide 1 or 2 links between all GPUs in a device.  This
+ *     number tells how many links are available between GPUs.  This data
+ *     also represents the number of concurrent SLI heads that can run at
+ *     the same time over this one device.
+ *
+ *   Order
+ *     This array returns the order of subdevices that are used through
+ *     the vidlink for display output.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER (0x800281) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID (0x81U)
+
+typedef struct NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS {
+    NvU32 ConnectionCount;
+    NvU32 Order[NV_MAX_SUBDEVICES];
+} NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS;
+
+/*
+ * NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER
+ *
+ * This command sets display ownership within the device to the specified
+ * subdevice instance.  The actual transfer of display ownership will take
+ * place at the next modeset.
+ *
+ *   subDeviceInstance
+ *     This member specifies the subdevice instance of the new display
+ *     owner.  The subdevice instance must be in the legal range
+ *     indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER (0x800282) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x82U)
+
+typedef struct NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS {
+    NvU32 subDeviceInstance;
+} NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS;
+
+/*
+ * NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER
+ *
+ * This command returns the subdevice instance of the current display owner
+ * within the device.
+ *
+ *   subDeviceInstance
+ *     This member returns the subdevice instance of the current display
+ *     owner.  The subdevice instance will be in the legal range
+ *     indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER (0x800283) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x83U)
+
+typedef struct NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS {
+    NvU32 subDeviceInstance;
+} NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS;
+
+/*
+ * NV0080_CTRL_CMD_GPU_SET_VIDLINK
+ *
+ * This command enables or disables the VIDLINK of all subdevices in the
+ * current SLI configuration.
+ *
+ *   enable
+ *     Enables or disables the vidlink
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0080_CTRL_CMD_GPU_SET_VIDLINK (0x800285) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID (0x85U)
+
+typedef struct NV0080_CTRL_GPU_SET_VIDLINK_PARAMS {
+    NvU32 enable;
+} NV0080_CTRL_GPU_SET_VIDLINK_PARAMS;
+
+#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE                 (0x00000000)
+#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE                  (0x00000001)
+
+/* commands */
+#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS           0
+#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN            1
+#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP              2
+
+/* status */
+#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON      0
+#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN 1
+#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED         2
+#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP   3
+
+/*
+ * NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE
+ *
+ * This command is used to enable or disable the persistence of a GPU's
+ * software state when no clients exist. With persistent software state enabled
+ * the GPU's software state is not torn down when the last client exits, but is
+ * retained until either the kernel module unloads or persistent software state
+ * is disabled.
+ *
+ *  newState
+ *    This input parameter is used to enable or disable the persistence of the
+ *    software state of all subdevices within the device.
+ *    Possible values are:
+ *      NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED
+ *      NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE          (0x800287) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */
+
+/* Possible values of persistentSwState */
+#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED             (0x00000000)
+#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED            (0x00000001)
+
+#define NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x87U)
+
+typedef struct NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS {
+    NvU32 newState;
+} NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS;
+
+/*
+ * NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE
+ *
+ *   swStatePersistence
+ *     This parameter returns a value indicating if persistent software
+ *     state is currently enabled or not for the specified GPU. See the
+ *     description of NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE.
+ *     Possible values are:
+ *       NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED
+ *       NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE (0x800288) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x88U)
+
+typedef struct NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS {
+    NvU32 swStatePersistence;
+} NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS;
+
+/**
+ * NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE
+ *
+ * This command returns a value indicating virtualization mode in
+ * which the GPU is running.
+ *
+ *   virtualizationMode
+ *     This parameter returns the virtualization mode of the device.
+ *     Possible values are:
+ *       NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE
+ *         This value indicates that there is no virtualization mode associated with the
+ *         device (i.e. it's a baremetal GPU).
+ *       NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS
+ *         This value indicates that the device is associated with the NMOS.
+ *       NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX
+ *         This value indicates that the device is associated with VGX(guest GPU).
+ *       NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST
+ *       NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU
+ *         This value indicates that the device is associated with vGPU(host GPU).
+ *       NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA
+ *         This value indicates that the device is associated with vSGA(host GPU).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE   (0x800289) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE      (0x00000000)
+#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS      (0x00000001)
+#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX       (0x00000002)
+#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST      (0x00000003)
+#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST
+#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA (0x00000004)
+
+#define NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID (0x89U)
+
+typedef struct NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS {
+    NvU32 virtualizationMode;
+} NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS;
+
+
+
+/*
+ * NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE
+ *
+ * This command returns the setting information for sparse texture compute
+ * mode optimization on the associated GPU. This setting indicates how the
+ * large page size should be selected by the RM for the GPU.
+ *
+ *   defaultSetting
+ *     This field specifies what the OS default setting is for the associated
+ *     GPU. See NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list
+ *     of possible values.
+ *   currentSetting
+ *     This field specifies which optimization mode was applied when the
+ *     driver was loaded. See
+ *     NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of
+ *     possible values.
+ *   pendingSetting
+ *     This field specifies which optimization mode will be applied on the
+ *     next driver reload. See
+ *     NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of
+ *     possible values.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8CU)
+
+typedef struct NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS {
+    NvU32 defaultSetting;
+    NvU32 currentSetting;
+    NvU32 pendingSetting;
+} NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS;
+
+/*
+ * NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE
+ *
+ * This command sets the pending setting for sparse texture compute mode. This
+ * setting indicates how the large page size should be selected by the RM for
+ * the GPU on the next driver reload.
+ *
+ *   setting
+ *     This field specifies which use case the RM should optimize the large
+ *     page size for on the next driver reload. Possible values for this
+ *     field are:
+ *       NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT
+ *         This value indicates that the RM should use the default setting for
+ *         the GPU's large page size. The default setting is reported by
+ *         NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE.
+ *       NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE
+ *         This value indicates that the RM should select the GPU's large page
+ *         size to optimize for compute use cases.
+ *       NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE
+ *         This value indicates that the RM should select the GPU's large page
+ *         size to optimize for sparse texture use cases.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ */
+#define NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8DU)
+
+typedef struct NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS {
+    NvU32 setting;
+} NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS;
+
+/* Possible sparse texture compute mode setting values */
+#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT                 0
+#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE        1
+#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE 2
+
+/*
+ * NV0080_CTRL_CMD_GPU_GET_VGX_CAPS
+ *
+ * This command gets the VGX capability of the GPU depending on the status of
+ * the VGX hardware fuse.
+ *
+ *   isVgx
+ *     This field is set to NV_TRUE is VGX fuse is enabled for the GPU otherwise
+ *     it is set to NV_FALSE.
+ *
+ * Possible status values returned are:
+ *   NVOS_STATUS_SUCCESS
+ *   NVOS_STATUS_ERROR_NOT_SUPPORTED
+ */
+#define NV0080_CTRL_CMD_GPU_GET_VGX_CAPS                                    (0x80028e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID (0x8EU)
+
+typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS {
+    NvBool isVgx;
+} NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS;
+
+
+
+/*
+ * NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS
+ *
+ * This command is used to query GPU SRIOV capabilities
+ *   totalVFs
+ *     Total number of virtual functions supported.
+ *
+ *   firstVfOffset
+ *     Offset of the first VF.
+ *
+ *   vfFeatureMask
+ *     Bitmask of features managed by the guest
+ *
+ *   FirstVFBar0Address
+ *     Address of BAR0 region of first VF.
+ *
+ *   FirstVFBar1Address
+ *     Address of BAR1 region of first VF.
+ *
+ *   FirstVFBar2Address
+ *     Address of BAR2 region of first VF.
+ *
+ *   bar0Size
+ *     Size of BAR0 region on VF.
+ *
+ *   bar1Size
+ *     Size of BAR1 region on VF.
+ *
+ *   bar2Size
+ *     Size of BAR2 region on VF.
+ *
+ *   b64bitBar0
+ *     If the VF BAR0 is 64-bit addressable.
+ *
+ *   b64bitBar1
+ *     If the VF BAR1 is 64-bit addressable.
+ *
+ *   b64bitBar2
+ *     If the VF BAR2 is 64-bit addressable.
+ *
+ *   bSriovEnabled
+ *     Flag for SR-IOV enabled or not.
+ *
+ *   bSriovHeavyEnabled
+ *     Flag for whether SR-IOV is enabled in standard or heavy mode.
+ *
+ *   bEmulateVFBar0TlbInvalidationRegister
+ *     Flag for whether VF's TLB Invalidate Register region needs emulation.
+ *
+ *   bClientRmAllocatedCtxBuffer
+ *     Flag for whether engine ctx buffer is managed by client RM.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS               (0x800291) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID (0x91U)
+
+typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
+    NvU32  totalVFs;
+    NvU32  firstVfOffset;
+    NvU32  vfFeatureMask;
+    NV_DECLARE_ALIGNED(NvU64 FirstVFBar0Address, 8);
+    NV_DECLARE_ALIGNED(NvU64 FirstVFBar1Address, 8);
+    NV_DECLARE_ALIGNED(NvU64 FirstVFBar2Address, 8);
+    NV_DECLARE_ALIGNED(NvU64 bar0Size, 8);
+    NV_DECLARE_ALIGNED(NvU64 bar1Size, 8);
+    NV_DECLARE_ALIGNED(NvU64 bar2Size, 8);
+    NvBool b64bitBar0;
+    NvBool b64bitBar1;
+    NvBool b64bitBar2;
+    NvBool bSriovEnabled;
+    NvBool bSriovHeavyEnabled;
+    NvBool bEmulateVFBar0TlbInvalidationRegister;
+    NvBool bClientRmAllocatedCtxBuffer;
+} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS;
+
+
+// Update this macro if new HW exceeds GPU Classlist MAX_SIZE
+#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE   160
+
+#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID (0x92U)
+
+typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS {
+    NvU32 numClasses;                                       // __OUT__
+    NvU32 classList[NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE];    // __OUT__
+} NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS;
+
+/*
+ * NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE
+ *
+ * Find a subdevice handle allocated under this device
+ */
+#define NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE (0x800293) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID (0x93U)
+
+typedef struct NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM {
+    NvU32    subDeviceInst;         // [in]
+    NvHandle hSubDevice;            // [out]
+} NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM;
+
+/*
+ * NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS
+ *
+ * This command gets branding information for the device.
+ *
+ *   brands
+ *     Mask containing branding information. A bit in this
+ *     mask is set if the GPU has particular branding.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO    NVBIT(0)
+#define NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS       NVBIT(1)
+#define NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN     NVBIT(2)
+
+#define NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS (0x800294) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID (0x94U)
+
+typedef struct NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS {
+    NvU32 brands;
+} NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS;
+
+/*
+ * These are the per-VF BAR1 sizes that we support in MB.
+ * They are used with the NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE control call and
+ * should match the NV_XVE_BAR1_CONFIG_SIZE register defines.
+ */
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M       64
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M      128
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M      256
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M      512
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G        1024
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G        2048
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G        4096
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G        8192
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G       16384
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G       32768
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G       65536
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G      131072
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN       NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M
+#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX       NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G
+
+#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID        NV_U32_MAX
+
+/*
+ * NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE
+ *
+ * @brief Resize BAR1 per-VF on the given GPU
+ *   vfBar1SizeMB[in]   size of per-VF BAR1 size in MB
+ *   numVfs[out]        number of VFs that can be created given the new BAR1 size
+ */
+#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE (0x800296) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID (0x96U)
+
+typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
+    NvU32 vfBar1SizeMB;
+    NvU32 numVfs;
+} NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS;
+
+/* _ctrl0080gpu_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
new file mode 100644
index 0000000..2592559
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
@@ -0,0 +1,275 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080gr.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+typedef struct NV0080_CTRL_GR_ROUTE_INFO {
+    NvU32 flags;
+    NV_DECLARE_ALIGNED(NvU64 route, 8);
+} NV0080_CTRL_GR_ROUTE_INFO;
+
+/* NV01_DEVICE_XX/NV03_DEVICE gr engine control commands and parameters */
+
+/**
+ * NV0080_CTRL_CMD_GR_GET_CAPS
+ *
+ * This command returns the set of graphics capabilities for the device
+ * in the form of an array of unsigned bytes.  Graphics capabilities
+ * include supported features and required workarounds for the graphics
+ * engine(s) within the device, each represented by a byte offset into the
+ * table and a bit position within that byte.
+ *
+ *   capsTblSize
+ *     This parameter specifies the size in bytes of the caps table.
+ *     This value should be set to NV0080_CTRL_GR_CAPS_TBL_SIZE.
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the graphics caps bits will be transferred by the RM.
+ *     The caps table is an array of unsigned bytes.
+ */
+#define NV0080_CTRL_CMD_GR_GET_CAPS (0x801102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS {
+    NvU32 capsTblSize;
+    NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
+} NV0080_CTRL_GR_GET_CAPS_PARAMS;
+
+/* extract cap bit setting from tbl */
+#define NV0080_CTRL_GR_GET_CAP(tbl,c)              (((NvU8)tbl[(1?c)]) & (0?c))
+
+
+
+/*
+ * Size in bytes of gr caps table.  This value should be one greater
+ * than the largest byte_index value above.
+ */
+#define NV0080_CTRL_GR_CAPS_TBL_SIZE            23
+
+
+
+/*
+ * NV0080_CTRL_CMD_GR_INFO
+ *
+ * This structure represents a single 32bit graphics engine value.  Clients
+ * request a particular graphics engine value by specifying a unique bus
+ * information index.
+ *
+ * Legal graphics information index values are:
+ *   NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
+ *     This index is used to request the number of clip IDs supported by
+ *     the device.
+ *   NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
+ *     This index is used to request the minimum number of attributes that
+ *     need to be enabled to avoid bug 261894.  A return value of 0
+ *     indicates that there is no minimum and the bug is not present on this
+ *     system.
+ */
+typedef struct NV0080_CTRL_GR_INFO {
+    NvU32 index;
+    NvU32 data;
+} NV0080_CTRL_GR_INFO;
+
+/* valid graphics info index values */
+#define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS                          (0x00000000)
+#define NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894              (0x00000001)
+#define NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK                 (0x00000002)
+#define NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT                  (0x00000003)
+#define NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT                 (0x00000004)
+#define NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE                 (0x00000005)
+#define NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT                         (0x00000006)
+#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT                 (0x00000007)
+#define NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR       (0x00000008)
+#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT             (0x00000009)
+#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT                 (0x0000000A)
+#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT             (0x0000000B)
+#define NV0080_CTRL_GR_INFO_INDEX_SM_VERSION                        (0x0000000C)
+#define NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM                  (0x0000000D)
+#define NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP              (0x0000000E)
+#define NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES              (0x0000000F)
+#define NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES                 (0x00000010)
+#define NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY     (0x00000011)
+#define NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY   (0x00000012)
+#define NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM                     (0x00000013)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS                   (0x00000014)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS                   (0x00000015)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS            (0x00000016)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC            (0x00000017)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS               (0x00000018)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS        (0x00000019)
+#define NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED                 (0x0000001A)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS                  (0x0000001B)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC            (0x0000001C)
+#define NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT                    (0x0000001D)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES           (0x0000001E)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS        (0x0000001F)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC             (0x00000020)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS        (0x00000021)
+#define NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT                     (0x00000022)
+#define NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT                 (0x00000023)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS                    (0x00000024)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS                   (0x00000025)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES             (0x00000026)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC         (0x00000027)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP            (0x00000028)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC            (0x00000029)
+#define NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC            (0x0000002A)
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP           (0x0000002B)
+#define NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT              (0x0000002C)
+#define NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT       (0x0000002D)
+#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT   (0x0000002E)
+
+
+#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC         (0x00000032)
+
+/* When adding a new INDEX, please update MAX_SIZE accordingly
+ * NOTE: 0080 functionality is merged with 2080 functionality, so this max size
+ * reflects that.
+ */
+#define NV0080_CTRL_GR_INFO_INDEX_MAX                               (0x00000032)
+#define NV0080_CTRL_GR_INFO_MAX_SIZE                                (0x33) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
+
+/*
+ * NV0080_CTRL_CMD_GR_GET_INFO
+ *
+ * This command returns graphics engine information for the associate GPU.
+ * Request to retrieve graphics information use a list of one or more
+ * NV0080_CTRL_GR_INFO structures.
+ *
+ *   grInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     grInfoList.
+ *   grInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the bus information is to be returned.
+ *     This buffer must be at least as big as grInfoListSize multiplied
+ *     by the size of the NV0080_CTRL_GR_INFO structure.
+ */
+#define NV0080_CTRL_CMD_GR_GET_INFO                                 (0x801104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV0080_CTRL_GR_GET_INFO_PARAMS {
+    NvU32 grInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 grInfoList, 8);
+} NV0080_CTRL_GR_GET_INFO_PARAMS;
+
+/*
+ * NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE
+ *     This command gets the current partition mode of a TSG context.
+ *
+ * NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE
+ *     This command sets the partition mode of a TSG context.
+ *
+ * NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
+ *     This structure defines the parameters used for TPC partitioning mode SET/GET commands
+ *
+ *     hChannelGroup [IN]
+ *         RM Handle to the TSG
+ *
+ *     mode [IN/OUT]
+ *         Partitioning mode enum value
+ *             For the SET cmd, this is an input parameter
+ *             For the GET cmd, this is an output parameter
+ *
+ *     bEnableAllTpcs [IN]
+ *         Flag to enable all TPCs by default
+ *
+ *     grRouteInfo[IN]
+ *         This parameter specifies the routing information used to
+ *         disambiguate the target GR engine.
+ *
+ */
+#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */
+
+#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */
+
+/* Enum for listing TPC partitioning modes */
+typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE {
+    NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0,
+    NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1,
+    NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2,
+} NV0080_CTRL_GR_TPC_PARTITION_MODE;
+
+typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS {
+    NvHandle                          hChannelGroup;   // [in]
+    NV0080_CTRL_GR_TPC_PARTITION_MODE mode;            // [in/out]
+    NvBool                            bEnableAllTpcs;  // [in/out]
+    NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);     // [in]
+} NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS;
+
+/**
+ * NV0080_CTRL_CMD_GR_GET_CAPS_V2
+ *
+ * This command returns the same set of graphics capabilities for the device
+ * as @ref NV0080_CTRL_CMD_GR_GET_CAPS. The difference is in the structure
+ * NV0080_CTRL_GR_GET_INFO_V2_PARAMS, which contains a statically sized array,
+ * rather than a caps table pointer and a caps table size in
+ * NV0080_CTRL_GR_GET_INFO_PARAMS. Additionally,
+ * NV0080_CTRL_GR_GET_INFO_V2_PARAMS contains a parameter for specifying routing
+ * information, used for MIG.
+ *
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the graphics caps bits will be written by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ *
+ *   bCapsPopulated
+ *     This parameter indicates that the capsTbl has been partially populated by
+ *     previous calls to NV0080_CTRL_CMD_GR_GET_CAPS_V2 on other subdevices.
+ */
+#define NV0080_CTRL_CMD_GR_GET_CAPS_V2 (0x801109) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV0080_CTRL_GR_GET_CAPS_V2_PARAMS {
+    NvU8   capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE];
+    NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvBool bCapsPopulated;
+} NV0080_CTRL_GR_GET_CAPS_V2_PARAMS;
+
+#define NV0080_CTRL_CMD_GR_GET_INFO_V2 (0x801110) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV0080_CTRL_GR_GET_INFO_V2_PARAMS {
+    NvU32               grInfoListSize;
+    NV0080_CTRL_GR_INFO grInfoList[NV0080_CTRL_GR_INFO_MAX_SIZE];
+    NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV0080_CTRL_GR_GET_INFO_V2_PARAMS;
+
+/* _ctrl0080gr_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h
new file mode 100644
index 0000000..096c451
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h
@@ -0,0 +1,112 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080host.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+/* NV01_DEVICE_XX/NV03_DEVICE host control commands and parameters */
+
+/*
+ * NV0080_CTRL_CMD_HOST_GET_CAPS
+ *
+ * This command returns the set of host capabilities for the device
+ * in the form of an array of unsigned bytes.  Host capabilities
+ * include supported features and required workarounds for the host-related
+ * engine(s) within the device, each represented by a byte offset into
+ * the table and a bit position within that byte.
+ *
+ *   capsTblSize
+ *     This parameter specifies the size in bytes of the caps table.
+ *     This value should be set to NV0080_CTRL_HOST_CAPS_TBL_SIZE.
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the host caps bits will be transferred by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_POINTER
+ */
+#define NV0080_CTRL_CMD_HOST_GET_CAPS (0x801401) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0080_CTRL_HOST_GET_CAPS_PARAMS {
+    NvU32 capsTblSize;
+    NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
+} NV0080_CTRL_HOST_GET_CAPS_PARAMS;
+
+/* extract cap bit setting from tbl */
+#define NV0080_CTRL_HOST_GET_CAP(tbl,c)            (((NvU8)tbl[(1?c)]) & (0?c))
+
+/* caps format is byte_index:bit_mask */
+#define NV0080_CTRL_HOST_CAPS_SEMA_ACQUIRE_BUG_105665               0:0x01
+#define NV0080_CTRL_HOST_CAPS_DUP_CMPLT_BUG_126020                  0:0x02
+/*
+ * This bit indicates whether CPU mappings obtained with NvRmMapMemory() are
+ * coherent with the GPU.  When this bit is _not_ set, all mappings are to the
+ * "raw" memory; i.e., they behave as it the NVOS33_FLAGS_MAPPING_DIRECT flag
+ * were used on a sysmem mapping.
+ */
+#define NV0080_CTRL_HOST_CAPS_GPU_COHERENT_MAPPING_SUPPORTED        0:0x04
+#define NV0080_CTRL_HOST_CAPS_SYS_SEMA_DEADLOCK_BUG_148216          0:0x08
+#define NV0080_CTRL_HOST_CAPS_SLOWSLI                               0:0x10
+#define NV0080_CTRL_HOST_CAPS_SEMA_READ_ONLY_BUG                    0:0x20
+#define NV0080_CTRL_HOST_CAPS_LARGE_NONCOH_UPSTR_WRITE_BUG_114871   0:0x40
+#define NV0080_CTRL_HOST_CAPS_LARGE_UPSTREAM_WRITE_BUG_115115       0:0x80
+#define NV0080_CTRL_HOST_CAPS_SEP_VIDMEM_PB_NOTIFIERS_BUG_83923     1:0x02
+#define NV0080_CTRL_HOST_CAPS_P2P_4_WAY                             1:0x08 // Deprecated
+#define NV0080_CTRL_HOST_CAPS_P2P_8_WAY                             1:0x10 // Deprecated
+#define NV0080_CTRL_HOST_CAPS_P2P_DEADLOCK_BUG_203825               1:0x20 // Deprecated
+#define NV0080_CTRL_HOST_CAPS_VIRTUAL_P2P                           1:0x40
+#define NV0080_CTRL_HOST_CAPS_BUG_254580                            1:0x80
+#define NV0080_CTRL_HOST_CAPS_COMPRESSED_BL_P2P_BUG_257072          2:0x02 // Deprecated
+#define NV0080_CTRL_HOST_CAPS_CROSS_BLITS_BUG_270260                2:0x04 // Deprecated
+/* unused                                                           2:0x08 */
+#define NV0080_CTRL_HOST_CAPS_MEM2MEM_BUG_365782                    2:0x10
+#define NV0080_CTRL_HOST_CAPS_CPU_WRITE_WAR_BUG_420495              2:0x20
+#define NV0080_CTRL_HOST_CAPS_EXPLICIT_CACHE_FLUSH_REQD             2:0x40
+#define NV0080_CTRL_HOST_CAPS_BAR1_READ_DEADLOCK_BUG_511418         2:0x80 // Deprecated
+
+/* size in bytes of host caps table */
+#define NV0080_CTRL_HOST_CAPS_TBL_SIZE   3
+
+#define NV0080_CTRL_CMD_HOST_GET_CAPS_V2 (0x801402) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS {
+    NvU8 capsTbl[NV0080_CTRL_HOST_CAPS_TBL_SIZE];
+} NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS;
+
+/* _ctrl0080host_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
new file mode 100644
index 0000000..8607cc2
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
@@ -0,0 +1,103 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080internal.finn
+//
+
+#include "nvlimits.h"
+#include "ctrl0080gr.h"
+#include "ctrl/ctrl0080/ctrl0080base.h"
+#include "ctrl/ctrl0080/ctrl0080perf.h"
+
+
+
+
+/*!
+ * @ref NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE
+ */
+#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE (0x802002) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */
+
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8);
+} NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS;
+
+
+/*!
+ * @ref NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE
+ */
+#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE (0x802003) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */
+
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8);
+} NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS;
+
+
+/*!
+ * @ref NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL
+ */
+#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL         (0x802009) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID" */
+
+
+/*!
+ *  This command disables cuda limit activation at teardown of the client.
+ */
+#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE             (0x802004) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4" */
+
+/*!
+ * @ref NV0080_CTRL_CMD_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL
+ */
+#define NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL (0x802007) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */
+
+
+
+/*!
+ * @ref NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT
+ */
+#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT     (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS {
+    NvU8 powerDisconnectedGpuBus[NV_MAX_DEVICES];
+    NvU8 powerDisconnectedGpuCount;
+} NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS;
+
+/* ctrl0080internal_h */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
new file mode 100644
index 0000000..60af5a6
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
@@ -0,0 +1,73 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080msenc.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+/* NV01_DEVICE_XX/NV03_DEVICE MSENC control commands and parameters */
+
+/*
+ * NV0080_CTRL_CMD_MSENC_GET_CAPS
+ *
+ * This command returns the set of MSENC capabilities for the device
+ * in the form of an array of unsigned bytes. MSENC capabilities
+ * include supported features and required workarounds for the MSENC-related
+ * engine(s) within the device, each represented by a byte offset into
+ * the table and a bit position within that byte.
+ *
+ *   capsTblSize
+ *     This parameter specifies the size in bytes of the caps table.
+ *     This value should be set to NV0080_CTRL_MSENC_CAPS_TBL_SIZE.
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the MSENC caps bits will be transferred by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0080_CTRL_CMD_MSENC_GET_CAPS (0x801b01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID << 8) | NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS {
+    NvU32 capsTblSize;
+    NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
+} NV0080_CTRL_MSENC_GET_CAPS_PARAMS;
+
+
+
+/* size in bytes of MSENC caps table */
+#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4
+
+/* _ctrl0080msenc_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h
new file mode 100644
index 0000000..689fe4b
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h
@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+/* NV01_DEVICE_XX/NV03_DEVICE NVJPG control commands and parameters */
+
+
+
+/*
+ * Size in bytes of NVJPG caps table.  This value should be one greater
+ * than the largest byte_index value above.
+ */
+#define NV0080_CTRL_NVJPG_CAPS_TBL_SIZE   9
+
+/*
+ * NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2
+ *
+ * This command returns the set of NVJPG capabilities for the device
+ * in the form of an array of unsigned bytes. NVJPG capabilities
+ * include supported features of the NVJPG engine(s) within the device,
+ * each represented by a byte offset into the table and a bit position within
+ * that byte.
+ *
+ *   [out] capsTbl
+ *     This caps table array is where the NVJPG caps bits will be transferred
+ *     by the RM. The caps table is an array of unsigned bytes.
+ *   instanceId
+ *     This parameter specifies the instance Id of NVDEC for which
+ *     cap bits are requested. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 (0x801f02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID << 8) | NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS {
+    NvU8  capsTbl[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE];
+    NvU32 instanceId;
+} NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS;
+
+/* _ctrl0080NVJPG_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h
new file mode 100644
index 0000000..3001076
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h
@@ -0,0 +1,48 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080perf.finn
+//
+
+#define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS {
+    NvBool bActivate;
+} NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS;
+
+#define NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS {
+    NvBool bCudaLimit;
+} NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS;
+
+
+
+/* _ctrl0080perf_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h
new file mode 100644
index 0000000..100a612
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h
@@ -0,0 +1,57 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080rc.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */
+
+/*
+ * NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK
+ *
+ * This command prevents RM from using callbacks when resetting a channel due
+ * to a page fault.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ */
+#define NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK (0x801d01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x1" */
+
+/*
+ * NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK
+ *
+ * This command permits RM to use callbacks when resetting a channel due
+ * to a page fault.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ */
+#define NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK  (0x801d02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x2" */
+
+/* _ctrl0080rc_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h
new file mode 100644
index 0000000..fbbdf73
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h
@@ -0,0 +1,93 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0080/ctrl0080unix.finn
+//
+
+#include "ctrl/ctrl0080/ctrl0080base.h"
+
+/* NV01_DEVICE_XX/NV03_DEVICE UNIX-specific control commands and parameters */
+
+/*
+ * NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH
+ *
+ * This command notifies RM to save or restore the current console state. It is
+ * intended to be called just before the display driver starts using the display
+ * engine, and after it has finished using it.
+ *
+ *   cmd
+ *    Indicates which operation should be performed.
+ *
+ *      SAVE_VT_STATE
+ *        Records the current state of the console, to be restored later.
+ *      RESTORE_VT_STATE
+ *        Restores the previously-saved console state.
+ *
+ *   fbInfo
+ *     Returns information about the system's framebuffer console, if one
+ *     exists. If no console is present, all fields will be zero.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH (0x801e01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS {
+    NvU32 cmd;                                    /* in */
+} NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS;
+
+/* Called when the display driver needs RM to save the console data,
+ * which will be used in RM based console restore */
+#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE    (0x00000001)
+
+/* Called when the display driver needs RM to restore the console */
+#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE (0x00000002)
+
+/* Called when the display driver has restored the console -- RM doesn't
+ * need to do anything further, but needs to be informed to avoid turning the
+ * GPU off and thus destroying the console state. */
+#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED (0x00000003)
+
+#define NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO             (0x801e02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS {
+    NvU32 subDeviceInstance; /* out */
+
+    NvU16 width; /* out */
+    NvU16 height; /* out */
+    NvU16 depth; /* out */
+    NvU16 pitch; /* out */
+} NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS;
+
+/* _ctrl0080unix_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0090.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0090.h
new file mode 100644
index 0000000..83af684
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0090.h
@@ -0,0 +1,130 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl0090.finn
+//
+
+
+
+// NV0080_CTRL_GR_TPC_PARTITION_MODE
+#include "ctrl/ctrl0080/ctrl0080gr.h"
+
+/*!
+ * This file defines control call interfaces for the KernelGraphicsContext
+ * objects Each channel running within a TSG contains a HW context represented
+ * by the above object(s). GR permits multiple channels to share a single
+ * context, and these APIs operate upon that context and may be issued from any
+ * TSG, channel, or context handle.
+ */
+
+/*
+ * NV0090_CTRL_CMD_NULL
+ *
+ * @brief This command does nothing.
+ *
+ * @return NV_OK
+ */
+#define NV0090_CTRL_CMD_NULL (0x900100) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x0" */
+
+/*!
+ * NV0090_CTRL_CMD_SET_TPC_PARTITION_MODE
+ * NV0090_CTRL_CMD_GET_TPC_PARTITION_MODE
+ *
+ * @brief sets or gets the TPC partition mode for this context
+ *
+ * @param[in/out] mode              Partitioning mode enum value
+ * @param[in/out] bEnableAllTpcs    Flag to enable all TPCs by default
+ *
+ * @return NV_OK on success
+ *         NV_ERR_OBJECT_NOT_FOUND if issued on non-GR ctx
+ */
+typedef struct NV0090_CTRL_TPC_PARTITION_MODE_PARAMS {
+    NV0080_CTRL_GR_TPC_PARTITION_MODE mode;
+    NvBool                            bEnableAllTpcs;
+} NV0090_CTRL_TPC_PARTITION_MODE_PARAMS;
+
+#define NV0090_CTRL_CMD_SET_TPC_PARTITION_MODE          (0x900101) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x1" */
+#define NV0090_CTRL_CMD_INTERNAL_SET_TPC_PARTITION_MODE (0x900102) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x2" */
+#define NV0090_CTRL_CMD_GET_TPC_PARTITION_MODE          (0x900103) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x3" */
+#define NV0090_CTRL_CMD_INTERNAL_GET_TPC_PARTITION_MODE (0x900104) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x4" */
+
+/**
+ * NV0090_CTRL_GET_MMU_DEBUG_MODE
+ *
+ * @brief retrieve the current MMU debug mode for the grctx according to the HW
+ *
+ * @param[out] bMode            current MMU debug mode
+ */
+typedef struct NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS {
+    NvBool bMode;
+} NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS;
+
+#define NV0090_CTRL_CMD_GET_MMU_DEBUG_MODE          (0x900105) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x5" */
+#define NV0090_CTRL_CMD_INTERNAL_GET_MMU_DEBUG_MODE (0x900106) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x6" */
+
+/**
+ * NV0090_CTRL_PROGRAM_VIDEMEM_PROMOTE
+ *
+ * @brief This control call is used to set the promotion policies to vidmem through
+ * per-TSG config
+ *
+ * If the request is for less bytes than the current PROMOTE setting, then
+ * the request is promoted. For example if the request size is for 32B and
+ * 64B promotion is turned on for that unit, then the request to FB will be
+ * for all the bytes to the 64B aligned address.
+ *
+ * @param[in] l1
+ *   An input parameter which represents VIDMEM_L1_PROMOTE[17:16].
+ * @param[in] t1
+ *   An input parameter which represents VIDMEM_T1_PROMOTE[19:18].
+ *
+ * @return NV_OK on success, or 
+ *         NV_ERR_INVALID_ARGUMENT or
+ *         NV_ERR_INVALID_STATE
+ */
+typedef enum NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE {
+    NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0,
+    NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1,
+    NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2,
+} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE;
+
+typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD {
+    NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE size;
+} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD;
+
+#define NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS {
+    NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD l1;
+    NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD t1;
+} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS;
+
+#define NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE          (0x900107) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x7" */
+#define NV0090_CTRL_CMD_INTERNAL_PROGRAM_VIDMEM_PROMOTE (0x900108) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x8" */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00f8.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00f8.h
new file mode 100644
index 0000000..595b021
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00f8.h
@@ -0,0 +1,218 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl00f8.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+
+#define NV00F8_CTRL_CMD(cat,idx)       NVXXXX_CTRL_CMD(0x00f8, NV00F8_CTRL_##cat, idx)
+
+/* NV00F8 command categories (6bits) */
+#define NV00F8_CTRL_RESERVED (0x00U)
+#define NV00F8_CTRL_FABRIC   (0x01U)
+
+/*
+ * NV00F8_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV00F8_CTRL_CMD_NULL (0xf80000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+/*
+ * NV00F8_CTRL_CMD_GET_INFO
+ *
+ * Queries memory allocation attributes.
+ *
+ *  size [OUT]
+ *    Size of the allocation.
+ *
+ *  pageSize [OUT]
+ *    Page size of the allocation.
+ *
+ *  allocFlags [OUT]
+ *    Flags passed during the allocation.
+ *
+ *  physAttrs [OUT]
+ *    Physical attributes associated with memory allocation.
+ *    For flexible mappings, it is not possible to retrieve this information,
+ *    behavior is undefined (returns all zeros).
+ */
+#define NV00F8_CTRL_CMD_GET_INFO (0xf80101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * addressSpace
+ *     Same as NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE.
+ *
+ * compressionCoverage
+ *     Same as NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE.
+ */
+typedef struct NV_PHYSICAL_MEMORY_ATTRS {
+    NvU32 addressSpace;
+    NvU32 compressionCoverage;
+} NV_PHYSICAL_MEMORY_ATTRS;
+
+#define NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV00F8_CTRL_GET_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32                    pageSize;
+    NvU32                    allocFlags;
+    NV_PHYSICAL_MEMORY_ATTRS physAttrs;
+} NV00F8_CTRL_GET_INFO_PARAMS;
+
+/*
+ * NV00F8_CTRL_CMD_DESCRIBE
+ *
+ * Queries the physical attributes of the fabric memory allocation.
+ *
+ *  offset [IN]
+ *    Offset into memory allocation to query physical addresses for.
+ *
+ *  totalPfns [OUT]
+ *    Number of PFNs in memory allocation.
+ *
+ *  pfnArray [OUT]
+ *    Array of PFNs in memory allocation (2MB page size shifted).
+ *
+ *  numPfns [OUT]
+ *    Number of valid entries in pfnArray.
+ *
+ * Note: This ctrl call is only available for kerenl mode client in vGPU platforms.
+ */
+
+#define NV00F8_CTRL_CMD_DESCRIBE            (0xf80102) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID" */
+
+#define NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE 512
+
+#define NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV00F8_CTRL_DESCRIBE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+    NV_DECLARE_ALIGNED(NvU64 totalPfns, 8);
+    NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE];
+    NvU32 numPfns;
+} NV00F8_CTRL_DESCRIBE_PARAMS;
+
+/*
+ *  hMemory [IN]
+ *    Physical memory handle to be attached.
+ *
+ *  offset [IN]
+ *    Offset into the fabric object.
+ *    Must be physical memory pagesize aligned (at least).
+ *
+ *  mapOffSet [IN]
+ *    Offset into the physical memory descriptor.
+ *    Must be physical memory pagesize aligned.
+ *
+ *  mapLength [IN]
+ *    Length of physical memory handle to be mapped.
+ *    Must be physical memory pagesize aligned and less than or equal to
+ *    fabric alloc size.
+ */
+typedef struct NV00F8_CTRL_ATTACH_MEM_INFO {
+    NvHandle hMemory;
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+    NV_DECLARE_ALIGNED(NvU64 mapOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 mapLength, 8);
+} NV00F8_CTRL_ATTACH_MEM_INFO;
+
+/*
+ * NV00F8_CTRL_CMD_ATTACH_MEM
+ *
+ * Attaches physical memory info to the fabric object.
+ *
+ *  memInfos [IN]
+ *    Memory infos to be attached.
+ *
+ *  numMemInfos [IN]
+ *    Number of memory infos to be attached.
+ *
+ *  flags [IN]
+ *    For future use only. Must be zero for now.
+ *
+ *  numAttached [OUT]
+ *    Successful attach count (returns a valid value on error too)
+ *
+ *  Restrictions:
+ *  a. Physical memory with 2MB pagesize is allowed
+ *  b. Only vidmem physical memory handle can be attached
+ *  c. Supported only for flexible fabric objects.
+ */
+#define NV00F8_CTRL_CMD_ATTACH_MEM      (0xf80103) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */
+
+#define NV00F8_MAX_ATTACHABLE_MEM_INFOS 64
+
+#define NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV00F8_CTRL_ATTACH_MEM_PARAMS {
+    NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHABLE_MEM_INFOS], 8);
+    NvU16 numMemInfos;
+    NvU32 flags;
+    NvU16 numAttached;
+} NV00F8_CTRL_ATTACH_MEM_PARAMS;
+
+/*
+ * NV00F8_CTRL_CMD_DETACH_MEM
+ *
+ * Detaches physical memory handle from the fabric object.
+ *
+ *  offsets [IN]
+ *    Offsets at which memory was attached.
+ *
+ *  numOffsets [IN]
+ *    Number of offsets to be detached.
+ *
+ *  flags [IN]
+ *    For future use only. Must be zero for now.
+ *
+ *  numDetached [OUT]
+ *    Successful detach count (returns a valid value on error too)
+ */
+#define NV00F8_CTRL_CMD_DETACH_MEM    (0xf80104) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID" */
+
+#define NV00F8_MAX_DETACHABLE_OFFSETS 64
+
+#define NV00F8_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV00F8_CTRL_DETACH_MEM_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 offsets[NV00F8_MAX_DETACHABLE_OFFSETS], 8);
+    NvU16 numOffsets;
+    NvU32 flags;
+    NvU16 numDetached;
+} NV00F8_CTRL_DETACH_MEM_PARAMS;
+
+/* _ctrl00f8_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fd.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fd.h
new file mode 100644
index 0000000..7ba86f8
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fd.h
@@ -0,0 +1,160 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl00fd.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+
+#define NV00FD_CTRL_CMD(cat,idx)       NVXXXX_CTRL_CMD(0x00fd, NV00FD_CTRL_##cat, idx)
+
+/* NV00FD command categories (6bits) */
+#define NV00FD_CTRL_RESERVED         (0x00)
+#define NV00FD_CTRL_MULTICAST_FABRIC (0x01)
+
+/*
+ * NV00FD_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV00FD_CTRL_CMD_NULL         (0xfd0000) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+/*
+ * NV00FD_CTRL_CMD_GET_INFO
+ *
+ * Queries multicast memory fabric allocation attributes.
+ *
+ *  alignment [OUT]
+ *    Alignment for the allocation.
+ *
+ *  allocSize [OUT]
+ *    Size of the allocation.
+ *
+ *  pageSize [OUT]
+ *    Page size of the allocation.
+ *
+ *  numMaxGpus [OUT]
+ *    Maximum number of attachable GPUs
+ *
+ *  numAttachedGpus [OUT]
+ *    Number of GPUs currently attached
+ *
+ */
+#define NV00FD_CTRL_CMD_GET_INFO (0xfd0101) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV00FD_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV00FD_CTRL_GET_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 alignment, 8);
+    NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
+    NvU32 pageSize;
+    NvU32 numMaxGpus;
+    NvU32 numAttachedGpus;
+} NV00FD_CTRL_GET_INFO_PARAMS;
+
+/*
+ * NV00FD_CTRL_CMD_ATTACH_MEM
+ *
+ * Attaches the physical memory handle and in turn the memory
+ * owner of the physical memory to the Multicast FLA object.
+ *
+ *  hSubdevice [IN]
+ *    Subdevice handle of the owner GPU
+ *
+ *  hMemory [IN]
+ *    Physical memory handle to be attached.
+ *
+ *  offset [IN]
+ *    Offset into the MCFLA object. (Must be zero for now, maybe used in future)
+ *    Must be MCFLA pagesize aligned.
+ *
+ *  mapOffSet [IN]
+ *    Offset into the physical memory descriptor.
+ *    Must be physical memory pagesize aligned.
+ *
+ *  mapLength [IN]
+ *    Length of physical memory handle to be mapped.
+ *    Must be physical memory pagesize aligned and less than or equal to
+ *    MCFLA alloc size
+ *
+ *  flags [IN]
+ *    For future use only. Must be zero for now.
+ *
+ *  devDescriptor [IN]
+ *    devDescriptor is a file descriptor for unix RM clients, but a void
+ *    pointer for windows RM clients. It is transparent to RM clients i.e. RM's
+ *    user-mode shim populates this field on behalf of clients.
+ *
+ *  Restrictions:
+ *  a. Memory belonging to only NVSwitch P2P supported GPUs
+ *     which can do multicast can be attached
+ *  b. Physical memory with 2MB pagesize is allowed
+ *  c. Memory of an already attached GPU should not be attached
+ *  d. Only vidmem physical memory handle can be attached
+ *
+ */
+#define NV00FD_CTRL_CMD_ATTACH_MEM (0xfd0102) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */
+
+#define NV00FD_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV00FD_CTRL_ATTACH_MEM_PARAMS {
+    NvHandle hSubdevice;
+    NvHandle hMemory;
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+    NV_DECLARE_ALIGNED(NvU64 mapOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 mapLength, 8);
+    NvU32    flags;
+    NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8);
+} NV00FD_CTRL_ATTACH_MEM_PARAMS;
+
+/*
+ * NV00FD_CTRL_CMD_REGISTER_EVENT
+ *
+ * Allows clients to optionally register for events after the Multicast
+ * FLA object is duped under another client.
+ *
+ *  pOsEvent [IN]
+ *    OS event handle created with NvRmAllocOsEvent().
+ *
+ */
+#define NV00FD_CTRL_CMD_REGISTER_EVENT (0xfd0103) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_REGISTER_EVENT_PARAMS_MESSAGE_ID" */
+
+#define NV00FD_CTRL_REGISTER_EVENT_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV00FD_CTRL_REGISTER_EVENT_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8);
+} NV00FD_CTRL_REGISTER_EVENT_PARAMS;
+
+/* _ctrl00fd_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fe.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fe.h
new file mode 100644
index 0000000..2be1a04
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fe.h
@@ -0,0 +1,64 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl00fe.finn
+//
+
+#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION 0:0
+#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_PHYSICAL (0x00000000U)
+#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_VIRTUAL  (0x00000001U)
+
+typedef struct NV00FE_CTRL_PAGING_OPERATION {
+    NvHandle hVirtualMemory;
+    NV_DECLARE_ALIGNED(NvU64 virtualOffset, 8);
+    NvHandle hPhysicalMemory;
+    NV_DECLARE_ALIGNED(NvU64 physicalOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32    flags;
+} NV00FE_CTRL_PAGING_OPERATION;
+
+/*
+ * NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS
+ *
+ * Execute a list of paging operations
+ * Page size is determined by the virtual allocation
+ * Offsets/sizes must respect the page size
+ *
+ */
+#define NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS       (0xfe0002U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID" */
+
+#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_MAX_COUNT (0x00010000U)
+
+#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS {
+    NvU32 pagingOpsCount;
+    NV_DECLARE_ALIGNED(NvP64 pagingOps, 8);
+} NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS;
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080.h
new file mode 100644
index 0000000..05f19cf
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080.h
@@ -0,0 +1,84 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080.finn
+//
+
+
+
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl2080/ctrl2080gpu.h"
+#include "ctrl2080/ctrl2080fuse.h"
+#include "ctrl2080/ctrl2080event.h"
+#include "ctrl2080/ctrl2080tmr.h"
+#include "ctrl2080/ctrl2080bios.h"
+#include "ctrl2080/ctrl2080mc.h"
+#include "ctrl2080/ctrl2080fifo.h"
+#include "ctrl2080/ctrl2080fb.h"
+
+
+#include "ctrl2080/ctrl2080gr.h"
+#include "ctrl2080/ctrl2080bus.h"
+#include "ctrl2080/ctrl2080thermal.h"
+#include "ctrl2080/ctrl2080fan.h"
+#include "ctrl2080/ctrl2080i2c.h"
+#include "ctrl2080/ctrl2080internal.h"
+#include "ctrl2080/ctrl2080spi.h"
+#include "ctrl2080/ctrl2080gpio.h"
+#include "ctrl2080/ctrl2080clk.h"
+#include "ctrl2080/ctrl2080perf.h"
+#include "ctrl2080/ctrl2080perf_cf.h"
+
+
+#include "ctrl2080/ctrl2080rc.h"
+#include "ctrl2080/ctrl2080dma.h"
+#include "ctrl2080/ctrl2080dmabuf.h"
+#include "ctrl2080/ctrl2080nvd.h"
+#include "ctrl2080/ctrl2080boardobj.h"
+#include "ctrl2080/ctrl2080pmgr.h"
+#include "ctrl2080/ctrl2080power.h"
+#include "ctrl2080/ctrl2080lpwr.h"
+#include "ctrl2080/ctrl2080acr.h"
+#include "ctrl2080/ctrl2080ce.h"
+#include "ctrl2080/ctrl2080nvlink.h"
+#include "ctrl2080/ctrl2080flcn.h"
+#include "ctrl2080/ctrl2080volt.h"
+#include "ctrl2080/ctrl2080ecc.h"
+#include "ctrl2080/ctrl2080cipher.h"
+#include "ctrl2080/ctrl2080fla.h"
+#include "ctrl2080/ctrl2080gsp.h"
+
+
+#include "ctrl2080/ctrl2080grmgr.h"
+#include "ctrl2080/ctrl2080ucodefuzzer.h"
+#include "ctrl2080/ctrl2080vgpumgrinternal.h"
+#include "ctrl2080/ctrl2080hshub.h"
+/* include appropriate os-specific command header */
+
+
+#include "ctrl2080/ctrl2080unix.h"
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h
new file mode 100644
index 0000000..322e119
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080acr.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h
new file mode 100644
index 0000000..7df6a6d
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h
@@ -0,0 +1,112 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080base.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV20_SUBDEVICE_XX control commands and parameters */
+
+#define NV2080_CTRL_CMD(cat,idx)                NVXXXX_CTRL_CMD(0x2080, NV2080_CTRL_##cat, idx)
+
+/* Subdevice command categories (6bits) */
+#define NV2080_CTRL_RESERVED                      (0x00)
+#define NV2080_CTRL_GPU                           (0x01)
+#define NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED     (0x81) /* finn: Evaluated from "(NV2080_CTRL_GPU | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_FUSE                          (0x02)
+#define NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED    (0x82) /* finn: Evaluated from "(NV2080_CTRL_FUSE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_EVENT                         (0x03)
+#define NV2080_CTRL_TIMER                         (0x04)
+#define NV2080_CTRL_THERMAL                       (0x05)
+#define NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED     (0xc5) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED (0x85) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_I2C                           (0x06)
+#define NV2080_CTRL_EXTI2C                        (0x07)
+#define NV2080_CTRL_BIOS                          (0x08)
+#define NV2080_CTRL_CIPHER                        (0x09)
+#define NV2080_CTRL_INTERNAL                      (0x0A)
+#define NV2080_CTRL_CLK_LEGACY_PRIVILEGED         (0xd0) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED     (0x90) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_CLK                           (0x10)
+#define NV2080_CTRL_FIFO                          (0x11)
+#define NV2080_CTRL_GR                            (0x12)
+#define NV2080_CTRL_FB                            (0x13)
+#define NV2080_CTRL_MC                            (0x17)
+#define NV2080_CTRL_BUS                           (0x18)
+#define NV2080_CTRL_PERF_LEGACY_PRIVILEGED        (0xe0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED    (0xa0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_PERF                          (0x20)
+#define NV2080_CTRL_NVIF                          (0x21)
+#define NV2080_CTRL_RC                            (0x22)
+#define NV2080_CTRL_GPIO                          (0x23)
+#define NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED    (0xa3) /* finn: Evaluated from "(NV2080_CTRL_GPIO | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_NVD                           (0x24)
+#define NV2080_CTRL_DMA                           (0x25)
+#define NV2080_CTRL_PMGR                          (0x26)
+#define NV2080_CTRL_PMGR_LEGACY_PRIVILEGED        (0xe6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED    (0xa6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_POWER                         (0x27)
+#define NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED   (0xa7) /* finn: Evaluated from "(NV2080_CTRL_POWER | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_LPWR                          (0x28)
+#define NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED    (0xa8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_LPWR_LEGACY_PRIVILEGED        (0xe8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_ACR                           (0x29)
+#define NV2080_CTRL_CE                            (0x2A)
+#define NV2080_CTRL_SPI                           (0x2B)
+#define NV2080_CTRL_NVLINK                        (0x30)
+#define NV2080_CTRL_FLCN                          (0x31)
+#define NV2080_CTRL_VOLT                          (0x32)
+#define NV2080_CTRL_VOLT_LEGACY_PRIVILEGED        (0xf2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED    (0xb2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_FAS                           (0x33)
+#define NV2080_CTRL_ECC                           (0x34)
+#define NV2080_CTRL_ECC_NON_PRIVILEGED            (0xb4) /* finn: Evaluated from "(NV2080_CTRL_ECC | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_FLA                           (0x35)
+#define NV2080_CTRL_GSP                           (0x36)
+#define NV2080_CTRL_NNE                           (0x37)
+#define NV2080_CTRL_GRMGR                         (0x38)
+#define NV2080_CTRL_UCODE_FUZZER                  (0x39)
+#define NV2080_CTRL_DMABUF                        (0x3A)
+
+// per-OS categories start at highest category and work backwards
+#define NV2080_CTRL_OS_WINDOWS                    (0x3F)
+#define NV2080_CTRL_OS_MACOS                      (0x3E)
+#define NV2080_CTRL_OS_UNIX                       (0x3D)
+
+
+/*
+ * NV2080_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *     NV_OK
+ */
+#define NV2080_CTRL_CMD_NULL                      (0x20800000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* _ctrl2080base_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
new file mode 100644
index 0000000..cf58350
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
@@ -0,0 +1,477 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080bios.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX bios-related control commands and parameters */
+
+
+
+typedef struct NV2080_CTRL_BIOS_INFO {
+    NvU32 index;
+    NvU32 data;
+} NV2080_CTRL_BIOS_INFO;
+
+/* Maximum number of bios infos that can be queried at once */
+#define NV2080_CTRL_BIOS_INFO_MAX_SIZE                              (0x0000000F)
+
+#define NV2080_CTRL_BIOS_INFO_INDEX_REVISION                        (0x00000000)
+#define NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION                    (0x00000001)
+
+
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_INFO
+ *
+ * This command returns bios information for the associated GPU.
+ * Requests to retrieve bios information use a list of one or more
+ * NV2080_CTRL_BIOS_INFO structures.
+ *
+ *   biosInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     biosInfoList.
+ *   biosInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the bios information is to be returned.
+ *     This buffer must be at least as big as biosInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_BIOS_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_BIOS_GET_INFO                               (0x20800802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | 0x2" */
+
+typedef struct NV2080_CTRL_BIOS_GET_INFO_PARAMS {
+    NvU32 biosInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 biosInfoList, 8);
+} NV2080_CTRL_BIOS_GET_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_INFO_V2
+ *
+ * This command returns bios information for the associated GPU.
+ * Requests to retrieve bios information use a list of one or more
+ * NV2080_CTRL_BIOS_INFO structures.
+ *
+ *   biosInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     biosInfoList.
+ *   biosInfoList
+ *     Bios information to be returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_BIOS_GET_INFO_V2 (0x20800810) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS {
+    NvU32                 biosInfoListSize;
+    NV2080_CTRL_BIOS_INFO biosInfoList[NV2080_CTRL_BIOS_INFO_MAX_SIZE];
+} NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_BIOS_NBSI
+ *
+ * NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH
+ *   This is the maximum length of a given registry string input (in characters).
+ *
+ * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII
+ *   This is a value indicating the format of a registry string is ascii.
+ * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE
+ *   This is a value indicating the format of a registry string is unicode.
+ * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH
+ *   This is a value indicating a registry string is actually a pre-hashed value.
+ *
+ * NV2080_CTRL_BIOS_NBSI_REG_STRING
+ *   This is a structure used to store a registry string object.
+ *   The members are as follows:
+ *
+ *   size
+ *     This is the size (in bytes) of the data contained in the string. If this
+ *     is greater than the maximum registry string length, an error will be
+ *     returned.
+ *   type
+ *     This is the type of data contained in the registry string. It can be either
+ *     ascii, unicode or a pre-hashed value.
+ *   value
+ *     This is the value of the string. Depending on the type, a different object
+ *     will be used to access the data.
+ */
+#define NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH (0x00000100)
+
+#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII     (0x00000000)
+#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE   (0x00000001)
+#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH      (0x00000002)
+
+#define NV2080_CTRL_BIOS_NBSI_MODULE_ROOT           (0x00000000)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_RM             (0x00000001)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER  (0x00000002)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO          (0x00000003)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_CPL            (0x00000004)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_D3D            (0x00000005)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_OGL            (0x00000006)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_PMU            (0x00000007)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_MODE           (0x00000008)
+// this should equal the last NBSI_MODULE plus 1.
+#define NV2080_CTRL_BIOS_NBSI_NUM_MODULES           (0x00000009)
+
+//
+// Never use this value! It's needed for DD/Video modules, but does not correspond
+// to a valid NBSI hive!
+//
+#define NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN        (0x80000000)
+
+typedef struct NV2080_CTRL_BIOS_NBSI_REG_STRING {
+    NvU32 size;
+    NvU32 type;
+
+    union {
+        NvU8  ascii[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH];
+        NvU16 unicode[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH];
+        NvU16 hash;
+    } value;
+} NV2080_CTRL_BIOS_NBSI_REG_STRING;
+
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_NBSI
+ *
+ * module
+ *   This field specifies the given module per the MODULE_TYPES enum.
+ * path
+ *   This field specifies the full path and registry node name for a
+ *   given NBSI object. This is a maximum of 255 unicode characters,
+ *   but may be provided as ascii or a pre-formed hash per the type
+ *   member. The size (in bytes) of the given string/hash should be
+ *   provided in the size member.
+ *
+ *   NOTE: In the case of an incomplete path such as HKR, one may pass
+ *   in simply the root node. E.g.:
+ *   1.) Normal case: HKLM\Path\Subpath
+ *   2.) Unknown case: HKR
+ *   It is expected that all unknown/incomplete paths will be determined
+ *   prior to NBSI programming! There is otherwise NO WAY to match
+ *   the hash given by an incomplete path to that stored in NBSI!
+ *
+ * valueName
+ *   This field specifies the registry name for a given NBSI object.
+ *   This is a maximum of 255 unicode characters, but may be provided
+ *   in ascii or a pre-formed hash per the type member. The size (in bytes)
+ *   of the given string/hash should be provided in the size member.
+ * retBuf
+ *   This field provides a pointer to a buffer into which the value
+ *   retrieved from NBSI may be returned
+ * retSize
+ *   This field is an input/output. It specifies the maximum size of the
+ *   return buffer as an input, and the size of the returned data as an
+ *   output.
+ * errorCode
+ *   This field is a return value. It gives an error code representing
+ *   failure to return a value (as opposed to failure of the call).
+ *   This obeys the following:
+ *
+ *   NV2080_CTRL_BIOS_GET_NBSI_SUCCESS
+ *     The call has returned complete and valid data.
+ *   NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE
+ *     The call returned complete and valid data which is expected to override
+ *     any stored registry settings.
+ *   NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE
+ *     The call returned data, but the size of the return buffer was
+ *     insufficient to contain it. The value returned in retSize represents
+ *     the total size necessary (in bytes) to contain the data.
+ *     if the size was non-0, the buffer is filled with the object contents up
+ *     to that size. Can be used with retBufOffset to use multiple calls to get
+ *     tables of very large size.
+ *   NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND
+ *     The call did not find a valid NBSI object for this key. This indicates
+ *     NBSI has no opinion and, more importantly, any data returned is identical
+ *     to data passed in.
+ *
+ * Possible return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_BIOS_GET_NBSI_SUCCESS         (0x00000000)
+#define NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE        (0x00000001)
+#define NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH        (0xFFFFFFFA)
+#define NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS (0xFFFFFFFB)
+#define NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE       (0xFFFFFFFC)
+#define NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE        (0xFFFFFFFD)
+#define NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE      (0xFFFFFFFE)
+#define NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND       (0xFFFFFFFF)
+
+#define NV2080_CTRL_CMD_BIOS_GET_NBSI             (0x20800803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_BIOS_GET_NBSI_PARAMS {
+    NvU32                            module;
+    NV2080_CTRL_BIOS_NBSI_REG_STRING path;
+    NV2080_CTRL_BIOS_NBSI_REG_STRING valueName;
+    NV_DECLARE_ALIGNED(NvP64 retBuf, 8);
+    NvU32                            retSize;
+    NvU32                            errorCode;
+} NV2080_CTRL_BIOS_GET_NBSI_PARAMS;
+
+#define NV2080_CTRL_CMD_BIOS_GET_NBSI_V2  (0x2080080e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_BIOS_GET_NBSI_MAX_RET_SIZE (0x100)
+
+#define NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS {
+    NvU32                            module;
+    NV2080_CTRL_BIOS_NBSI_REG_STRING path;
+    NV2080_CTRL_BIOS_NBSI_REG_STRING valueName;
+    NvU8                             retBuf[NV2080_BIOS_GET_NBSI_MAX_RET_SIZE];
+    NvU32                            retSize;
+    NvU32                            errorCode;
+} NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ
+ *
+ * globType
+ *   This field specifies the glob type wanted
+ *   0xffff: APItest... returns NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS
+ * globIndex
+ *   Index for globType desired
+ *      0 = best fit
+ *      1..255 = actual index
+ * globSource
+ *   Index to nbsi directory sources used when getting entire directory
+ *      0 = registry
+ *      1 = VBIOS
+ *      2 = SBIOS
+ *      3 = ACPI
+ * retBufOffset
+ *   When making multiple calls to get the object (if retSize is too small)
+ *   offset into real object (0=start of object)
+ * retBuf
+ *   This field provides a pointer to a buffer into which the object
+ *   retrieved from NBSI may be returned
+ * retSize
+ *   This field is an input/output. It specifies the maximum size of the
+ *   return buffer as an input, and the size of the returned data as an
+ *   output.
+ * totalObjSize
+ *   This field is an output, where the total size of the object being
+ *   retrieved is returned.
+ * errorCode
+ *   This field is a return value. It gives an error code representing
+ *   failure to return a value (as opposed to failure of the call).
+ *   This obeys the following:
+ *
+ *   NV2080_CTRL_BIOS_GET_NBSI_SUCCESS
+ *     The call has returned complete and valid data.
+ *   NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE
+ *     The call returned complete and valid data which is expected to override
+ *     any stored registry settings.
+ *   NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE
+ *     The call returned data, but the size of the return buffer was
+ *     insufficient to contain it. The value returned in retSize represents
+ *     the total size necessary (in bytes) to contain the data.
+ *   NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND
+ *     The call did not find a valid NBSI object for this key. This indicates
+ *     NBSI has no opinion and, more importantly, any data returned is identical
+ *     to data passed in.
+ *
+ * Possible return values are:
+ *   NV2080_CTRL_BIOS_GET_NBSI_SUCCESS
+ *   NV2080_CTRL_BIOS_GET_NBSI_APITEST_NODIRACCESS
+ *   NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS
+ *   NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE
+ *   NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE
+ *   NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE
+ *   NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ (0x20800806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS {
+    NvU16 globType;
+    NvU8  globIndex;
+    NvU16 globSource;
+    NvU32 retBufOffset;
+    NV_DECLARE_ALIGNED(NvP64 retBuf, 8);
+    NvU32 retSize;
+    NvU32 totalObjSize;
+    NvU32 errorCode;
+} NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS;
+
+#define GLOB_TYPE_GET_NBSI_DIR                       0xfffe
+#define GLOB_TYPE_APITEST                            0xffff
+#define GLOB_TYPE_GET_NBSI_ACPI_RAW                  0xfffd
+
+
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_SKU_INFO
+ *
+ * This command returns information about the current board SKU.
+ * NV_ERR_INVALID_OWNER will be returned if the call
+ * isn't made with the OS as the administrator.
+ *
+ *  chipSKU
+ *    This field returns the sku for the current chip.
+ *  chipSKUMod
+ *    This field returns the SKU modifier.
+ *  project
+ *    This field returns the Project (Board) number.
+ *  projectSKU
+ *    This field returns the Project (Board) SKU number.
+ *  CDP
+ *    This field returns the Collaborative Design Project Number.
+ *  projectSKUMod
+ *    This field returns the Project (Board) SKU Modifier.
+ *  businessCycle
+ *    This field returns the business cycle the board is associated with.
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_OWNER
+ */
+#define NV2080_CTRL_CMD_BIOS_GET_SKU_INFO (0x20800808) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum length of parameter strings */
+
+
+#define NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS {
+    NvU32 BoardID;
+    char  chipSKU[4];
+    char  chipSKUMod[2];
+    char  project[5];
+    char  projectSKU[5];
+    char  CDP[6];
+    char  projectSKUMod[2];
+    NvU32 businessCycle;
+} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_POST_TIME
+
+ * This command is used to get the GPU POST time (in milliseconds).
+ * If the associated GPU is the master GPU this value will be recorded
+ * by the VBIOS and retrieved from the KDA buffer.  If the associated
+ * GPU is a secondaryGPU then this value will reflect the devinit
+ * processing time.
+ *
+ * vbiosPostTime
+ *   This parameter returns the vbios post time in msec.
+ *
+ * Possible return status values are
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME (0x20800809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 vbiosPostTime, 8);
+} NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT
+ *
+ * This function is used to give out the UEFI version, UEFI image presence and
+ * Graphics Firmware Mode i.e. whether system is running in UEFI or not.
+ *
+ *   version
+ *     This parameter returns the UEFI version.
+ *
+ *   flags
+ *     This parameter indicates UEFI image presence and Graphics Firmware mode.
+ *       NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE
+ *         This field returns UEFI presence value. Legal values for this
+ *         field include:
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO
+ *             This value indicates that UEFI image is not present.
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES
+ *             This value indicates that UEFI image is present.
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER
+ *             This value indicates that there is a dummy UEFI placeholder,
+ *             which can later be updated with a valid UEFI image.
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN
+ *             This value indicates that UEFI image is hidden.
+ *       NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING
+ *         This field indicates the UEFI running value. Legal values for
+ *         this parameter include:
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE
+ *             This value indicates that UEFI is not running.
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE
+ *             This value indicates that UEFI is running.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_READY
+ *   NV_ERR_INVALID_STATE
+ */
+
+#define NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT (0x2080080b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS {
+    NvU32 version;
+    NvU32 flags;
+} NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS;
+
+/* Legal values for flags parameter */
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE               1:0
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO          (0x00000000)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES         (0x00000001)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER (0x00000002)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN      (0x00000003)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING                2:2
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE        (0x00000000)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE         (0x00000001)
+
+
+
+/* _ctrl2080bios_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h
new file mode 100644
index 0000000..6f69c5c
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h
@@ -0,0 +1,35 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn
+//
+
+
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h"
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h
new file mode 100644
index 0000000..caafd74
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn
+//
+
+
+
+#include "nvtypes.h"
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
new file mode 100644
index 0000000..eb8d979
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
@@ -0,0 +1,1588 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080bus.finn
+//
+
+#include "nvcfg_sdk.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX bus control commands and parameters */
+
+/**
+ * NV2080_CTRL_CMD_BUS_GET_PCI_INFO
+ *
+ * This command returns PCI bus identifier information for the specified GPU.
+ *
+ *   pciDeviceId
+ *       This parameter specifies the internal PCI device and vendor
+ *       identifiers for the GPU.
+ *   pciSubSystemId
+ *       This parameter specifies the internal PCI subsystem identifier for
+ *       the GPU.
+ *   pciRevisionId
+ *       This parameter specifies the internal PCI device-specific revision
+ *       identifier for the GPU.
+ *   pciExtDeviceId
+ *       This parameter specifies the external PCI device identifier for
+ *       the GPU.  It contains only the 16-bit device identifier.  This
+ *       value is identical to the device identifier portion of
+ *       pciDeviceId since non-transparent bridges are no longer supported.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_BUS_GET_PCI_INFO (0x20801801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS {
+    NvU32 pciDeviceId;
+    NvU32 pciSubSystemId;
+    NvU32 pciRevisionId;
+    NvU32 pciExtDeviceId;
+} NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_BUS_INFO
+ *
+ * This structure represents a single 32bit bus engine value.  Clients
+ * request a particular bus engine value by specifying a unique bus
+ * information index.
+ *
+ * Legal bus information index values are:
+ *   NV2080_CTRL_BUS_INFO_INDEX_TYPE
+ *     This index is used to request the bus type of the GPU.
+ *     Legal return values for this index are:
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS
+ *       NV2080_CTRL_BUS_INFO_TYPE_FPCI
+ *   NV2080_CTRL_BUS_INFO_INDEX_INTLINE
+ *     This index is used to request the interrupt line (or irq) assignment
+ *     for the GPU.  The return value is system-dependent.
+ *   NV2080_CTRL_BUS_INFO_INDEX_CAPS
+ *     This index is used to request the bus engine capabilities for the GPU.
+ *     The return value is specified as a mask of capabilities.
+ *     Legal return values for this index are:
+ *       NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH
+ *       NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS
+ *     These indices are used to request PCI Express link-specific
+ *     capabilities values.  A value of zero is returned for non-PCIE GPUs.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS
+ *     These indices are used to request PCI Express link-specific
+ *     control status values.  A value of zero is returned for non-PCIE GPUs.
+ *   NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS
+ *     This index is used to request coherent dma transfer flags.
+ *     Valid coherent dma transfer flags include:
+ *       NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA
+ *       NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART
+ *   NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS
+ *     This index is used to request noncoherent dma transfer flags.
+ *     Valid noncoherent dma transfer flags include:
+ *       NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA
+ *       NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART
+ *       NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE
+ *   NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE
+ *     This index is used to request the size of the GPU GART in MBytes.
+ *   NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS
+ *     This index is used to request GPU GART flags.
+ *     Valid gart flags include:
+ *       NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH
+ *         This flag indicates that GPU GART clients need to do an explicit
+ *         flush via an appropriate SetContextDma method.
+ *       NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED
+ *         This flag indicates that the GART address range includes both
+ *         system and video memory.
+ *   NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER
+ *     This index is used to request the PCI-based bus number of the GPU.
+ *     Support for this index is platform-dependent.
+ *   NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER
+ *     This index is used to request the PCI-based device number of the GPU.
+ *     Support for this index is platform-dependent.
+ *   NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER
+ *     This index is used to request the PCI-based domain number of the GPU.
+ *     Support for this index is platform-dependent.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS
+ *     These indices are used to request PCI Express error status.
+ *     The current status is cleared as part of these requests.
+ *     Valid PCI Express error status values include:
+ *       NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR
+ *       NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR
+ *       NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR
+ *       NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST
+ *   NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE
+ *     This index is used to request the bus interface type of the GPU.
+ *     Legal return values for this index are:
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS
+ *       NV2080_CTRL_BUS_INFO_TYPE_FPCI
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO // DEPRECATED
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO  // REPLACES "GEN2" variant
+ *     This index is used to retrieve PCI Express Gen configuration support
+ *     This index is used to retrieve PCI Express Gen2 configuration support 
+ *     for the GPU.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1
+ *          The GPU is PCI Express Gen1 capable.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2
+ *          The GPU is PCI Express Gen2 capable.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3
+ *          The GPU is PCI Express Gen3 capable.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4
+ *          The GPU is PCI Express Gen4 capable.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5
+ *          The GPU is PCI Express Gen5 capable.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1
+ *          The GPU is configured in PCI Express Gen1 mode.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2
+ *          The GPU is configured in PCI Express Gen2 mode.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3
+ *          The GPU is configured in PCI Express Gen3 mode.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4
+ *          The GPU is configured in PCI Express Gen4 mode.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5
+ *          The GPU is configured in PCI Express Gen5 mode.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER
+ *     This index retrieves PCI Express Advanced Error Reporting (AER) errors 
+ *     for the GPU.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS
+ *     This index retrieves the PCI Express link capabilities for the
+ *     board.  For example, a Quadro FX4700X2 has two GPUs and PCIe
+ *     switch.  With this board, this index returns the link
+ *     capabilities of the PCIe switch.  In a single GPU board, this
+ *     index returns the link capabilities of the GPU.  A value of
+ *     zero is returned for non-PCIE GPUs.
+ *     UPSTREAM_LINK_CAPS is kept for backwards compatibility.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS
+ *     This index retrieves the PCI Express link status for the board.
+ *     For example, a Quadro FX4700X2 has two GPUs and PCIe switch.
+ *     With this board, this index returns the link capabilities of
+ *     the PCIe switch.  In a single GPU board, this index returns the
+ *     link status of the GPU.  A value of zero is returned for
+ *     non-PCIE GPUs.
+ *     UPSTREAM_LINK_CTRL_STATUS is kept for backwards compatibility.
+ *   NV2080_CTRL_BUS_INFO_INDEX_ASLM_STATUS
+ *     This index is used to request the PCI Express ASLM settings.
+ *     This index is only valid when NV2080_CTRL_BUS_INFO_TYPE indicates PCIE.
+ *     A value of zero is returned for non-PCI Express bus type.
+ *     _ASLM_STATUS_PCIE is always _PRESENT if PCI Express bus type.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT
+ *     This index is used to get the ASLM switching error count.
+ *     A value of zero will be returned if no errors occurs while
+ *     ASLM switching
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_SWITCH_ERROR_COUNT
+ *     This index is used to get the Gen1<-->Gen2 switching error count
+ *     A value of zero will be returned in case speed change from Gen1 to
+ *     Gen2 is clean or if chipset is not gen2 capable or if gen1<-->gen2 
+ *     switching is disabled.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM
+ *     This index is used to get the ASPM CYA L0s\L1 enable\disable status.
+ *     Legal return value is specified as a mask of valid and data field
+ *     possible return values are:
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS
+ *     These indices are used to request detailed PCI Express error counters.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR
+ *     These indices are used to clear detailed PCI Express error counters.
+ *   NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE
+ *     This index is used to request the internal interface type of the GPU.
+ *     Legal return values for this index are:
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS
+ *       NV2080_CTRL_BUS_INFO_TYPE_FPCI
+ *   NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE
+ *     This index queries the type of sysmem connection to CPU
+ *     NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE
+ *     NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK
+ *     NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C
+ *
+ */
+
+typedef struct NV2080_CTRL_BUS_INFO {
+    NvU32 index;
+    NvU32 data;
+} NV2080_CTRL_BUS_INFO;
+
+/* valid bus info index values */
+
+/**
+ *  This index is used to request the bus type of the GPU.
+ *  Legal return values for this index are:
+ *    NV2080_CTRL_BUS_INFO_TYPE_PCI
+ *    NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS
+ *    NV2080_CTRL_BUS_INFO_TYPE_FPCI
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_TYPE                                     (0x00000000)
+#define NV2080_CTRL_BUS_INFO_INDEX_INTLINE                                  (0x00000001)
+#define NV2080_CTRL_BUS_INFO_INDEX_CAPS                                     (0x00000002)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS                       (0x00000003)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS                      (0x00000004)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS                  (0x00000005)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS                (0x00000006)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS                (0x00000007)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS               (0x00000008)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS           (0x00000009)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS         (0x0000000A)
+/**
+ * This index is used to request coherent dma transfer flags.
+ * Valid coherent dma transfer flags include:
+ *   NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA
+ *   NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS                       (0x0000000B)
+/**
+ * This index is used to request noncoherent dma transfer flags.
+ * Valid noncoherent dma transfer flags include:
+ *   NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA
+ *   NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART
+ *   NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS                    (0x0000000C)
+/**
+ * This index is used to request the size of the GPU GART in MBytes.
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE                            (0x0000000D)
+/**
+ * This index is used to request GPU GART flags.
+ * Valid gart flags include:
+ *   NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH
+ *     This flag indicates that GPU GART clients need to do an explicit
+ *     flush via an appropriate SetContextDma method.
+ *   NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED
+ *     This flag indicates that the GART address range includes both
+ *     system and video memory.
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS                           (0x0000000E)
+#define NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER                               (0x0000000F)
+#define NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER                            (0x00000010)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS                     (0x00000011)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS                    (0x00000012)
+#define NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE                           (0x00000013)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO                           (0x00000014)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER                        (0x00000015)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS                     (0x00000016)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS              (0x00000017)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS                         (0x00000018)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT       (0x00000019)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT       (0x0000001A)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM                        (0x0000001B)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS            (0x0000001C)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS                 (0x0000001D)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED              (0x0000001E)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS           (0x0000001F)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR      (0x00000020)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR           (0x00000021)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR        (0x00000022)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR     (0x00000023)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS         (0x00000024)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS            (0x00000025)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS               (0x00000026)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS       (0x00000027)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR   (0x00000028)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR      (0x00000029)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR         (0x0000002A)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR (0x0000002B)
+#define NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER                            (0x0000002C)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO                            (0x0000002D)
+#define NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE                       (0x0000002E)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO                   (0x0000002F)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO                      (0x00000030)
+#define NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO                                 (0x00000031)
+/**
+ * This index is used to request the top 32 bits of the size of the GPU
+ * GART in MBytes.
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI                         (0x00000032)
+#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE                   (0x00000033)
+#define NV2080_CTRL_BUS_INFO_INDEX_MAX                                      NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE
+#define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE                                  (0x00000034)
+
+/* valid bus info type return values */
+#define NV2080_CTRL_BUS_INFO_TYPE_PCI                                       (0x00000001)
+#define NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS                               (0x00000003)
+#define NV2080_CTRL_BUS_INFO_TYPE_FPCI                                      (0x00000004)
+#define NV2080_CTRL_BUS_INFO_TYPE_AXI                                       (0x00000008)
+
+/* valid bus capability flags */
+#define NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH                             (0x00000001)
+#define NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED                           (0x00000002)
+
+/* 
+ * Format of PCIE link caps return values
+ * Note that Link Capabilities register format is followed only for bits 11:0
+ */
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED               3:0
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS               (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS               (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS               (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS              (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS              (0x00000005)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS              (0x00000006)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH               9:4
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM                    11:10
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE                        (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S                         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1                      (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN                     15:12
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1                         (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2                         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3                         (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4                         (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5                         (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6                         (0x00000005)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL              19:16
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1                  (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2                  (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3                  (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4                  (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5                  (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6                  (0x00000005)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN                 23:20
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1                     (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2                     (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3                     (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4                     (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5                     (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6                     (0x00000005)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES           24:24
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED            (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED           (0x00000001)
+
+/* format of PCIE control status return values */
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM                 1:0
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED            (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S                 (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1                  (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1              (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED           19:16
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS      (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS      (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS      (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS     (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS     (0x00000005)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS     (0x00000006)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH           25:20
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED     (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1            (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2            (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4            (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8            (0x00000008)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12           (0x0000000C)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16           (0x00000010)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32           (0x00000020)
+
+/* coherent dma transfer flags */
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA             0:0
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE                (0x00000000)
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE                 (0x00000001)
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART            2:2
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE               (0x00000000)
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE                (0x00000001)
+
+/* noncoherent dma transfer flags */
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA          0:0
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE             (0x00000000)
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE              (0x00000001)
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART         2:2
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE            (0x00000000)
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE             (0x00000001)
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE        3:3
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE           (0x00000000)
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE            (0x00000001)
+
+/* GPU GART flags */
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH               0:0
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE                  (0x00000000)
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE                   (0x00000001)
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED                1:1
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE                   (0x00000000)
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE                    (0x00000001)
+
+/* format of PCIE errors return values */
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR                    (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR               (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR                   (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST                (0x00000008)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY              (0x00000010)
+
+/* PCIE Gen2 capability and current level */
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP                    0:0
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE                       (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE                        (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL             1:1
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1                 (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2                 (0x00000001)
+
+/* format of PCIE AER return values */
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR              (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR           (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP              (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR              (0x00000008)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT               (0x00000010)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT                 (0x00000020)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL                 (0x00000040)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW             (0x00000080)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP             (0x00000100)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR                (0x00000200)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ           (0x00000400)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR                     (0x00010000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP                     (0x00020000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP                    (0x00040000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER               (0x00080000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT                (0x00100000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL           (0x00200000)
+
+/* format of PCIE ASLM status return value */
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE                  0:0
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR                    (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT                  (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED             1:1
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO                  (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES                 (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE            2:2
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO                 (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES                (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED          3:3
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO               (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES              (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04                  4:4
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING                  (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT                  (0x00000001)
+
+/* format of GPU CYA CAPS return value */
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID               0:0
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO                     (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES                    (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM                     2:1
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED                     (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S                          (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1                           (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1                       (0x00000003)
+
+/* format of MSI INFO return value */
+#define NV2080_CTRL_BUS_INFO_MSI_STATUS                            0:0
+#define NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED                            (0x00000000)
+#define NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED                             (0x00000001)
+
+/*format of L1PM Substates capabilities information */
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED         0:0
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES        (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO         (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED         1:1
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES        (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO         (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED          2:2
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO          (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED          3:3
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO          (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED               4:4
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES              (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO               (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_RESERVED                     7:5
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PORT_RESTORE_TIME            15:8
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_SCALE             17:16
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_VALUE             23:19
+
+/*format of L1 PM Substates Control 1 Register */
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED         0:0
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES        (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO         (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED         1:1
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES        (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO         (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED          2:2
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO          (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED          3:3
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO          (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_COMMON_MODE_RESTORE_TIME   15:8
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_VALUE   25:16
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_SCALE   31:29
+
+/*format of L1 PM Substates Control 2 Register */
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_SCALE           1:0
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_VALUE           7:3
+
+/* valid sysmem connection type values */
+#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE              (0x00000000)
+#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK            (0x00000001)
+#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C               (0x00000002)
+
+/**
+ * NV2080_CTRL_CMD_BUS_GET_INFO
+ *
+ * This command returns bus engine information for the associated GPU.
+ * Requests to retrieve bus information use a list of one or more
+ * NV2080_CTRL_BUS_INFO structures.
+ *
+ *   busInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     busInfoList.
+ *   busInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the bus information is to be returned.
+ *     This buffer must be at least as big as busInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_BUS_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_BUS_GET_INFO                                        (0x20801802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_BUS_GET_INFO_PARAMS {
+    NvU32 busInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 busInfoList, 8);
+} NV2080_CTRL_BUS_GET_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_BUS_GET_INFO_V2 (0x20801823) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV2080_CTRL_BUS_GET_INFO_V2_PARAMS {
+    NvU32                busInfoListSize;
+    NV2080_CTRL_BUS_INFO busInfoList[NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE];
+} NV2080_CTRL_BUS_GET_INFO_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_BUS_PCI_BAR_INFO
+ *
+ * This structure describes PCI bus BAR information.
+ *
+ *   flags
+ *     This field contains any flags for the associated BAR.
+ *   barSize
+ *     This field contains the size in megabytes of the associated BAR.
+ *     DEPRECATED, please use barSizeBytes.
+ *   barSizeBytes
+ *     This field contains the size in bytes of the associated BAR.
+ *   barOffset
+ *     This field contains the PCI bus offset in bytes of the associated BAR.
+ */
+typedef struct NV2080_CTRL_BUS_PCI_BAR_INFO {
+    NvU32 flags;
+    NvU32 barSize;
+    NV_DECLARE_ALIGNED(NvU64 barSizeBytes, 8);
+    NV_DECLARE_ALIGNED(NvU64 barOffset, 8);
+} NV2080_CTRL_BUS_PCI_BAR_INFO;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO
+ *
+ * This command returns PCI bus BAR information.
+ *
+ *   barCount
+ *     This field returns the number of BARs for the associated subdevice.
+ *     Legal values for this parameter will be between one to
+ *      NV2080_CTRL_BUS_MAX_BARS.
+ *   barInfo
+ *     This field returns per-BAR information in the form of an array of
+ *     NV2080_CTRL_BUS_PCI_BAR_INFO structures.  Information for as many as
+ *     NV2080_CTRL_BUS_MAX_PCI_BARS will be returned.  Any unused entries will
+ *     be initialized to zero.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO (0x20801803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum number of BARs per subdevice */
+#define NV2080_CTRL_BUS_MAX_PCI_BARS         (8)
+
+#define NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS {
+    NvU32 pciBarCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_BUS_PCI_BAR_INFO pciBarInfo[NV2080_CTRL_BUS_MAX_PCI_BARS], 8);
+} NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH
+ *
+ * This command sets PCI-E link width to the specified new value.
+ *
+ *   pcieLinkWidth
+ *      This field specifies the new PCI-E link width.
+ *
+ *   failingReason
+ *      This field specifies the reason why the change of link width fails.
+ *      It is valid only when this routine returns NV_ERR_GENERIC.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_GENERIC
+ */
+#define NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH (0x20801804) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS {
+    NvU32 pcieLinkWidth;
+    NvU32 failingReason;
+} NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS;
+
+#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE          (0x00000001)
+#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS (0x00000002)
+#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING        (0x00000004)
+
+/*
+ * NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED
+ *
+ * This command Initiates a change in PCIE Bus Speed
+ *
+ *   busSpeed
+ *     This field is the target speed to train to.
+ *     Legal values for this parameter are:
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED                        (0x20801805) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS {
+    NvU32 busSpeed;
+} NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS;
+
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS          (0x00000001)
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS          (0x00000002)
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS          (0x00000003)
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS         (0x00000004)
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS         (0x00000005)
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS         (0x00000006)
+
+/*
+ * NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED
+ *
+ * This command Initiates a change in PCIE Bus Speed for a HWBC device's upstream
+ * link.
+ *
+ *   busSpeed
+ *     This field specifies the target speed to which to train.
+ *     Legal values for this parameter are:
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS
+ *   primaryBus
+ *     This field is the PCI Express Primary Bus number that uniquely identifies
+ *     a HWBC device's upstream port, i.e. the BR04 Upstream Port.
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED (0x20801806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS {
+    NvU32 busSpeed;
+    NvU8  primaryBus;
+} NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS;
+
+#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_2500MBPS (0x00000001)
+#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_5000MBPS (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED
+ *
+ * This command gets the current PCIE Bus Speed for a HWBC device's upstream
+ * link.
+ *
+ *   primaryBus
+ *     This field is the PCI Express Primary Bus number that uniquely identifies
+ *     a HWBC device's upstream port, i.e. the BR04 Upstream Port.
+ *   busSpeed
+ *     This field specifies a pointer in the caller's address space
+ *     to the NvU32 variable into which the bus speed is to be returned.
+ *     On success, this parameter will contain one of the following values:
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED      (0x20801807) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS {
+    NvU32 busSpeed;
+    NvU8  primaryBus;
+} NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS;
+
+#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_2500MBPS (0x00000001)
+#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_5000MBPS (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_BUS_MAP_BAR2
+ *
+ * This command sets up BAR2 page tables for passed-in memory handle.
+ * This command MUST be executed before NV2080_CTRL_CMD_BUS_UNMAP_BAR2
+ * or NV2080_CTRL_CMD_BUS_VERIFY_BAR2. Not supported on SLI.
+ *
+ * hMemory
+ *    This field is a handle to physical memory.
+ *
+ * Possible status values returned are
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_BUS_MAP_BAR2                          (0x20801809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_BUS_MAP_BAR2_PARAMS {
+    NvHandle hMemory;
+} NV2080_CTRL_BUS_MAP_BAR2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_UNMAP_BAR2
+ *
+ * This command unmaps any pending BAR2 page tables created with
+ * NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed in must
+ * match the handle used to map the page tables. Not supported on SLI.
+ *
+ * hMemory
+ *    This field is a handle to physical memory.
+ *
+ * Possible status values returned are
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_BUS_UNMAP_BAR2 (0x2080180a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS {
+    NvHandle hMemory;
+} NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_VERIFY_BAR2
+ *
+ * This command tests BAR2 against BAR0 if there are BAR2 page tables
+ * set up with NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed
+ * in must match the handle used to map the page tables. Not supported on SLI.
+ *
+ * hMemory
+ *    This field is a handle to physical memory.
+ * offset
+ *    Base offset of the surface where the test will make its first dword write.
+ * size
+ *    Test will write '(size/4)*4' bytes starting at surface offset `offset'.
+ *
+ * Possible status values returned are
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_BUS_VERIFY_BAR2 (0x2080180b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS {
+    NvHandle hMemory;
+    NvU32    offset;
+    NvU32    size;
+} NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_HWBC_GET_UPSTREAM_BAR0
+ *
+ * This command gets the BAR0 for a HWBC device's upstream port.
+ *
+ *   primaryBus
+ *     This field is the PCI Express Primary Bus number that uniquely identifies
+ *     a HWBC device's upstream port, i.e. the BR04 Upstream Port.
+ *   physBAR0
+ *     This field returns the BAR0 physical address of the HWBC device's
+ *     upstream port.
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_BUS_HWBC_GET_UPSTREAM_BAR0 (0x2080180e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 physBAR0, 8);
+    NvU8 primaryBus;
+} NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE
+ *  This command would reports the current Audio device power state or Sets new power state.
+ *
+ * command
+ *  This parametrer specifies the target GPU multifunction state.
+ *      NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE      Enables the multi function state
+ *      NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE     Disables the multi function state.
+ *      NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE         Get the Current device power state.
+ *
+ * Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_GENERIC
+ */
+
+#define NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE (0x20801812) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS {
+    NvU8  command;
+    NvU32 deviceState;
+} NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS;
+
+#define NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE  (0x00000000)
+#define NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE (0x00000001)
+#define NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE     (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * pexCounterMask
+ *  This parameter specifies the input mask for desired counter types.
+ *
+ * pexTotalCorrectableErrors
+ *  This parameter gives the total correctable errors which includes
+ *  NV_XVE_ERROR_COUNTER1 plus LCRC Errors, 8B10B Errors, NAKS and Failed L0s
+ *
+ * pexCorrectableErrors
+ *  This parameter only includes NV_XVE_ERROR_COUNTER1 value.
+ *
+ * pexTotalNonFatalErrors
+ *  This parameter returns total Non-Fatal Errors which may or may not
+ *  include Correctable Errors.
+ *
+ * pexTotalFatalErrors
+ *  This parameter returns Total Fatal Errors
+ *
+ * pexTotalUnsupportedReqs
+ *  This parameter returns Total Unsupported Requests
+ *
+ * pexErrors
+ *  This array contains the error counts for each error type as requested from
+ *  the pexCounterMask. The array indexes correspond to the mask bits one-to-one.
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS        (0x20801813) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PEX_MAX_COUNTER_TYPES           31
+#define NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS {
+    NvU32 pexCounterMask;
+    NvU32 pexTotalCorrectableErrors;
+    NvU16 pexCorrectableErrors;
+    NvU8  pexTotalNonFatalErrors;
+    NvU8  pexTotalFatalErrors;
+    NvU8  pexTotalUnsupportedReqs;
+    NvU16 pexCounters[NV2080_CTRL_PEX_MAX_COUNTER_TYPES];
+} NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS;
+
+/*
+ * Note that MAX_COUNTER_TYPES will need to be updated each time
+ * a new counter type gets added to the list below. The value
+ * depends on the bits set for the last valid define. Look
+ * at pexCounters[] comments above for details.
+ *
+ */
+#define NV2080_CTRL_BUS_PEX_COUNTER_TYPE                          0x00000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS               0x00000001
+#define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT                  0x00000002
+#define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT         0x00000004
+#define NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT                0x00000008
+#define NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT                 0x00000010
+#define NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT            0x00000020
+#define NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT      0x00000040
+#define NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT             0x00000080
+#define NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT        0x00000100
+#define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT               0x00000200
+#define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT               0x00000400
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS                   0x00000800
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT          0x00001000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT          0x00002000
+#define NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT                0x00004000
+#define NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT  0x00008000
+#define NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT      0x00010000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT                0x00020000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT               0x00040000
+#define NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT           0x00080000
+#define NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT                    0x00100000
+#define NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT        0x00200000
+#define NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT              0x00400000
+#define NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT         0x00800000
+#define NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT             0x01000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT              0x02000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT              0x04000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT              0x08000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT              0x10000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT 0x20000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT       0x40000000
+
+/*
+ * NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTER_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * pexCounterMask
+ *  This parameter specifies the input mask for desired counters to be
+ *  cleared. Note that all counters cannot be cleared.
+ */
+
+#define NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS                    (0x20801814) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS {
+    NvU32 pexCounterMask;
+} NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * pexCounterMask
+ *  This parameter specifies the input mask for desired counters to be
+ *  freezed. Note that all counters cannot be frozen.
+ * 
+ * bFreezeRmCounter
+ *  This parameter decides whether API will freeze it or unfreeze it.
+ *  NV_TRUE for freeze and NV_FALSE for unfreeze.
+ */
+
+#define NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS (0x20801815) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS {
+    NvU32  pexCounterMask;
+    NvBool bFreezeRmCounter;
+} NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS
+ *  This command gets the per Lane Counters and the type of errors.
+ *
+ * pexLaneErrorStatus
+ *  This mask specifies the type of error detected on any of the Lanes.
+ *
+ * pexLaneCounter
+ *  This array gives the counters per Lane. Each index corresponds to Lane
+ *  index + 1
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS (0x20801816) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PEX_MAX_LANES                 16
+#define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS {
+    NvU16 pexLaneErrorStatus;
+    NvU8  pexLaneCounter[NV2080_CTRL_PEX_MAX_LANES];
+} NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE                  0x00000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR   0x00000001
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR    0x00000002
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR       0x00000004
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR      0x00000008
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR        0x00000010
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW  0x00000020
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW 0x00000040
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR     0x00000080
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR     0x00000100
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY               (0x20801817) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x17U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS {
+    NvBool bPexLtrRegkeyOverride;
+    NvBool bPexRootPortLtrSupported;
+    NvBool bPexGpuLtrSupported;
+    NvU16  pexLtrSnoopLatencyValue;
+    NvU8   pexLtrSnoopLatencyScale;
+    NvU16  pexLtrNoSnoopLatencyValue;
+    NvU8   pexLtrNoSnoopLatencyScale;
+} NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS;
+
+#define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY (0x20801818) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS {
+    NvU16 pexLtrSnoopLatencyValue;
+    NvU8  pexLtrSnoopLatencyScale;
+    NvU16 pexLtrNoSnoopLatencyValue;
+    NvU8  pexLtrNoSnoopLatencyScale;
+} NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * pexCounterMask
+ *  This parameter specifies the input mask for desired counter types.
+ *
+ */
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES   0x00000001
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES   0x00000002
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0      0x00000004
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0      0x00000008
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S     0x00000010
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S     0x00000020
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S 0x00000040
+#define NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES      7
+
+#define NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS   (0x20801819) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS {
+    NvU32 pexCounterMask;
+    NvU32 pexCounters[NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES];
+} NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTER_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * pexCounterMask
+ *  This parameter specifies the input mask for desired counters to be
+ *  cleared. Note that all counters cannot be cleared.
+ * 
+ * NOTE: EX_UTIL_COUNTER_UPSTREAM & NV2080_CTRL_BUS_PEX_UTIL_COUNTER_DOWNSTREAM
+ *       belongs to PMU. The ctrl function will not reset nor disable/enable them.
+ */
+#define NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS (0x20801820) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS {
+    NvU32 pexCounterMask;
+} NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_BUS_GET_BFD (0x20801821) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_BUS_GET_BFD_PARAMS {
+    NvBool valid;
+    NvU16  deviceID;
+    NvU16  vendorID;
+    NvU32  domain;
+    NvU16  bus;
+    NvU16  device;
+    NvU8   function;
+} NV2080_CTRL_BUS_GET_BFD_PARAMS;
+
+#define NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID (0x21U)
+
+typedef struct NV2080_CTRL_BUS_GET_BFD_PARAMSARR {
+    NV2080_CTRL_BUS_GET_BFD_PARAMS params[32];
+} NV2080_CTRL_BUS_GET_BFD_PARAMSARR;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS
+ *  This command gets the following mentioned PDB Properties
+ * 
+ * aspmDisableFlags[] 
+ *  NvBool array stores each of the properties' state. the array size can
+ *  be increased as per requirement.
+ *
+ * NOTE: When adding more properties, increment NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS.
+ */
+
+#define NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE                0x00000000
+#define NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS           0x00000001
+#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE                      0x00000002
+#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED       0x00000003
+#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED     0x00000004
+#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY   0x00000005
+#define NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED            0x00000006
+#define NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY 0x00000007
+#define NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1                  0x00000008
+//append properties here
+
+#define NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS                              9
+
+#define NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS                            (0x20801822) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS {
+    NvBool aspmDisableFlags[NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS];
+} NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS;
+
+#define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS (0x20801824) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS {
+    NvBool bEnable;
+} NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK
+ *
+ * This command returns cached(SW only) NVLINK peer id mask. Currently, this control
+ * call is only needed inside a SR-IOV enabled guest where page table management is
+ * being done by the guest. Guest needs this mask to derive the peer id corresponding
+ * to the peer GPU. This peer id will then be programmed inside the PTEs by guest RM.
+ *
+ *   nvlinkPeerIdMask[OUT]
+ *      - The peer id mask is returned in this array.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK (0x20801825) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_MAX_NUM_GPUS                32
+
+#define NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS {
+    NvU32 nvlinkPeerIdMask[NV2080_CTRL_BUS_MAX_NUM_GPUS];
+} NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS;
+
+/* 
+ * NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS
+ * This command takes parameters eomMode, eomNblks and eomNerrs from the client
+ * and then sends it out to PMU.
+ */
+#define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS (0x20801826) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID (0x26U)
+
+typedef struct NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS {
+    NvU8 eomMode;
+    NvU8 eomNblks;
+    NvU8 eomNerrs;
+} NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS;
+
+/* 
+ * NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE
+ * This command takes parameters UPHY register's address and lane from the client
+ * and then sends it out to PMU.
+ */
+#define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE (0x20801827) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID (0x27U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS {
+    NvU32 regAddress;
+    NvU32 laneSelectMask;
+    NvU16 regValue;
+} NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_EOM_STATUS
+ *
+ */
+#define NV2080_CTRL_CMD_BUS_GET_EOM_STATUS (0x20801828) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_MAX_NUM_LANES      32
+
+#define NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID (0x28U)
+
+typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS {
+    NvU8  eomMode;
+    NvU8  eomNblks;
+    NvU8  eomNerrs;
+    NvU8  eomBerEyeSel;
+    NvU8  eomPamEyeSel;
+    NvU32 laneMask;
+    NvU16 eomStatus[NV2080_CTRL_BUS_MAX_NUM_LANES];
+} NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS
+ *
+ * This command returns the PCIe requester atomics operation capabilities
+ * from GPU to coherent SYSMEM.
+ *
+ * atomicsCaps[OUT]
+ *  Mask of supported PCIe atomic operations in the form of
+ *  NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_*
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS (0x20801829) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x29U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS {
+    NvU32 atomicsCaps;
+} NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS;
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32      0:0
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO  (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64      1:1
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO  (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32          2:2
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES     (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO      (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64          3:3
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES     (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO      (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32           4:4
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES      (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO       (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64           5:5
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES      (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO       (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128          6:6
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES     (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO      (0x00000000)
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS
+ *
+ * This command returns the supported GPU atomic operations
+ * that map to the capable PCIe atomic operations from GPU to
+ * coherent SYSMEM.
+ *
+ * atomicOp[OUT]
+ *  Array of structure that contains the atomic operation
+ *  supported status and its attributes. The array can be
+ *  indexed using one of NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_*
+ *  
+ *  bSupported[OUT]
+ *   Is the GPU atomic operation natively supported by the PCIe?
+ *  
+ *  attributes[OUT]
+ *   Provides the attributes mask of the GPU atomic operation when supported
+ *   in the form of
+ *   NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_*
+ *
+ */
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS            (0x2080182a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD           0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN           1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX           2
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC            3
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC            4
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND           5
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR            6
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR           7
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH           8
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS            9
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD           10
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN           11
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX           12
+
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT          13
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID (0x2AU)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
+    struct {
+        NvBool bSupported;
+        NvU32  attributes;
+    } atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT];
+} NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS;
+
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR         0:0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES    1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO     0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR         1:1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES    1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO     0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION      2:2
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES 1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO  0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32        3:3
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES   1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO    0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64        4:4
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES   1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO    0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128       5:5
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES  1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO   0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED         6:6
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES    1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO     0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED       7:7
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES  1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO   0
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_C2C_INFO
+ *
+ * This command returns the C2C links information.
+ *
+ *   bIsLinkUp[OUT]
+ *       NV_TRUE if the C2C links are present and the links are up.
+ *       The below remaining fields are valid only if return value is
+ *       NV_OK and bIsLinkUp is NV_TRUE.
+ *   nrLinks[OUT]
+ *       Total number of C2C links that are up.
+ *   linkMask[OUT]
+ *       Bitmask of the C2C links present and up.
+ *   perLinkBwMBps[OUT]
+ *       Theoretical per link bandwidth in MBps.
+ *   remoteType[OUT]
+ *       Type of the device connected to the remote end of the C2C link.
+ *       Valid values are :
+ *       NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU
+ *       NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU - connected to another GPU
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *
+ * Please also review the information below for additional information on
+ * select fields:
+ *
+ *   remoteType[OUT]
+ *       NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU
+ */
+
+
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO                            (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID (0x2BU)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
+    NvBool bIsLinkUp;
+    NvU32  nrLinks;
+    NvU32  linkMask;
+    NvU32  perLinkBwMBps;
+    NvU32  remoteType;
+} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS;
+
+#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1
+#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2
+
+/*
+ * NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS
+ *
+ * This command disables the GPU system memory access after quiescing the GPU,
+ * or re-enables sysmem access.
+ *
+ *   bDisable
+ *     If NV_TRUE the GPU is quiesced and system memory access is disabled .
+ *     If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS            (0x2080182c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID (0x2CU)
+
+typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS {
+    NvBool bDisable;
+} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO
+ *
+ * This command returns the C2C error info for a C2C links.
+ *
+ * errCnts[OUT]
+ *  Array of structure that contains the error counts for
+ *  number of times one of C2C fatal error interrupt has happened.
+ *  The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES
+ *  * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE.
+ *
+ *  nrCrcErrIntr[OUT]
+ *   Number of times CRC error interrupt triggered.
+ *  nrReplayErrIntr[OUT]
+ *   Number of times REPLAY error interrupt triggered.
+ *  nrReplayB2bErrIntr[OUT]
+ *   Number of times REPLAY_B2B error interrupt triggered.
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_INVALID_STATE
+ *  NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO                        (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES      2
+#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 5
+
+#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU)
+
+typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
+    struct {
+        NvU32 nrCrcErrIntr;
+        NvU32 nrReplayErrIntr;
+        NvU32 nrReplayB2bErrIntr;
+    } errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE];
+} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING
+ *
+ * This command sets P2P mapping.
+ *
+ * connectionType[IN]
+ *   Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION
+ * peerId[IN]
+ *   peerId of remote GPU from local GPU on which call is made.
+ * bSpaAccessOnly[IN]
+ *   SPA access only. SPA addressing mode is supported when we support ATS.
+ * bUseUuid [in]
+ *   Option only available for Guest RPCs and is not avaliable for external clients.
+ *   Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU.
+ * remoteGpuId[IN]
+ *   GPU ID of remote GPU.
+ * remoteGpuUuid [in]
+ *   Alternative to gpuId; used to identify target GPU for which caps are being queried.
+ *   Option only available for Guest RPCs.
+ *   If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU.
+ *   If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default.
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_INVALID_ARGUMENT
+ *  NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING                           (0x2080182e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID   0
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK    1
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE      2
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 3
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C       4
+
+#define NV2080_SET_P2P_MAPPING_UUID_LEN                               16U
+
+#define NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2EU)
+
+typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS {
+    NvU32  connectionType;
+    NvU32  peerId;
+    NvBool bSpaAccessOnly;
+    NvBool bUseUuid;
+    NvU32  remoteGpuId;
+    NvU8   remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN];
+} NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING
+ *
+ * This command unsets P2P mapping.
+ *
+ * connectionType[IN]
+ *   Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION
+ * peerId[IN]
+ *   peerId of remote GPU from local GPU on which call is mad.
+ * bUseUuid [in]
+ *   Option only available for Guest RPCs and is not avaliable for external clients.
+ *   Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU.
+ * remoteGpuId[IN]
+ *   GPU ID of remote GPU.
+ * remoteGpuUuid [in]
+ *   Alternative to gpuId; used to identify target GPU for which caps are being queried.
+ *   Option only available for Guest RPCs.
+ *   If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU.
+ *   If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default.
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_INVALID_ARGUMENT
+ *  NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING (0x2080182f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2FU)
+
+typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS {
+    NvU32  connectionType;
+    NvU32  peerId;
+    NvBool bUseUuid;
+    NvU32  remoteGpuId;
+    NvU8   remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN];
+} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS;
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
new file mode 100644
index 0000000..d2f5424
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
@@ -0,0 +1,329 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080ce.finn
+//
+
+
+
+#include "nvcfg_sdk.h"
+
+
+/* NV20_SUBDEVICE_XX ce control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_CAPS
+ *
+ * This command returns the set of CE capabilities for the device
+ * in the form of an array of unsigned bytes.
+ *
+ *   ceEngineType
+ *     This parameter specifies the copy engine type
+ *   capsTblSize
+ *     This parameter specifies the size in bytes of the caps table per CE.
+ *     This value should be set to NV2080_CTRL_CE_CAPS_TBL_SIZE.
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the CE caps bits will be transferred by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_CAPS  (0x20802a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+/*
+ * Size in bytes of CE caps table.  This value should be one greater
+ * than the largest byte_index value below.
+ */
+#define NV2080_CTRL_CE_CAPS_TBL_SIZE 2
+
+#define NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_CE_GET_CAPS_PARAMS {
+    NvU32 ceEngineType;
+    NvU32 capsTblSize;
+    NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
+} NV2080_CTRL_CE_GET_CAPS_PARAMS;
+
+#define NV2080_CTRL_CMD_CE_GET_CAPS_V2 (0x20802a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
+    NvU32 ceEngineType;
+    NvU8  capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE];
+} NV2080_CTRL_CE_GET_CAPS_V2_PARAMS;
+
+/* extract cap bit setting from tbl */
+#define NV2080_CTRL_CE_GET_CAP(tbl,c)               (((NvU8)tbl[(1?c)]) & (0?c))
+
+/* caps format is byte_index:bit_mask */
+#define NV2080_CTRL_CE_CAPS_CE_GRCE                          0:0x01
+#define NV2080_CTRL_CE_CAPS_CE_SHARED                        0:0x02
+#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ                   0:0x04
+#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE                  0:0x08
+#define NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P                    0:0x10
+#define NV2080_CTRL_CE_CAPS_CE_SYSMEM                        0:0x20
+#define NV2080_CTRL_CE_CAPS_CE_P2P                           0:0x40
+#define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED      0:0x80
+#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL      1:0x01
+#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL         1:0x02
+
+
+
+/*
+ *   NV2080_CTRL_CE_CAPS_CE_GRCE
+ *     Set if the CE is synchronous with GR
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SHARED
+ *     Set if the CE shares physical CEs with any other CE
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ
+ *     Set if the CE can give enhanced performance for SYSMEM reads over other CEs
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE
+ *     Set if the CE can give enhanced performance for SYSMEM writes over other CEs
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P
+ *     Set if the CE can be used for P2P transactions using NVLINK
+ *     Once a CE is exposed for P2P over NVLINK, it will remain available for the life of RM
+ *     PCE2LCE mapping may change based on the number of GPUs registered in RM however
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SYSMEM
+ *     Set if the CE can be used for SYSMEM transactions
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_P2P
+ *     Set if the CE can be used for P2P transactions
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED
+ *     Set if the CE supports BL copy size greater than 64K
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL
+ *     Set if the CE supports non-pipelined Block linear
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL
+ *     Set if the CE supports pipelined Block Linear
+ */
+
+
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK
+ *
+ * This command returns the mapping of PCE's for the given LCE.
+ *
+ *   ceEngineType
+ *     This parameter specifies the copy engine type
+ *   pceMask
+ *     This parameter specifies a mask of PCEs that correspond
+ *     to the LCE specified in ceEngineType
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+
+
+#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS {
+    NvU32 ceEngineType;
+    NvU32 pceMask;
+} NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG
+ *
+ * This command sets the PCE2LCE configuration
+ *
+ *   pceLceConfig[NV2080_CTRL_MAX_PCES]
+ *     This parameter specifies the PCE-LCE mapping requested
+ *   grceLceConfig[NV2080_CTRL_MAX_GRCES]
+ *     This parameter specifies which LCE is the GRCE sharing with
+ *     0xF -> Does not share with any LCE
+ *     0-MAX_LCE -> Shares with the given LCE
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MAX_PCES                  32
+#define NV2080_CTRL_MAX_GRCES                 2
+
+#define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
+    NvU32 ceEngineType;
+    NvU32 pceLceMap[NV2080_CTRL_MAX_PCES];
+    NvU32 grceSharedLceMap[NV2080_CTRL_MAX_GRCES];
+} NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS
+ *
+ * This command updates the PCE-LCE mappings
+ *
+ *   pceLceMap [IN]
+ *     This parameter contains the array of PCE to LCE mappings.
+ *     The array is indexed by the PCE index, and contains the
+ *     LCE index that the PCE is assigned to.  A unused PCE is
+ *     tagged with NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE.
+ *
+ *   grceConfig [IN]
+ *     This parameter contains the array of GRCE configs.
+ *     0xF -> GRCE does not share with any LCE
+ *     0-MAX_LCE -> GRCE shares with the given LCE
+ *
+ *   exposeCeMask [IN]
+ *     This parameter specifies the mask of LCEs to export to the
+ *     clients after the update.
+ *
+ *   bUpdateNvlinkPceLce [IN]
+ *     Whether PCE-LCE mappings need to be updated for nvlink topology.
+ *     If this is NV_FALSE, RM would ignore the above values.  However,
+ *     PCE-LCE mappings will still be updated if there were any regkey
+ *     overrides.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_GENERIC
+ */
+
+#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS {
+    NvU32  pceLceMap[NV2080_CTRL_MAX_PCES];
+    NvU32  grceConfig[NV2080_CTRL_MAX_GRCES];
+    NvU32  exposeCeMask;
+    NvBool bUpdateNvlinkPceLce;
+} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS;
+
+#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE      0xf
+
+/*
+ * NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB
+ *
+ * This function triggers an update of the exported CE classes.  CEs with
+ * no physical resources will not be exported.  A record of these
+ * will be return in in the stubbedCeMask.
+ *
+ * An example if NV2080_ENGINE_TYPE_COPY4 is stubbed (1<<4) will be
+ * set in stubbedCeMask.
+ */
+
+
+#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS {
+    NvU32 stubbedCeMask;
+} NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS
+ *
+ * Query _CE_GRCE, _CE_SHARED, _CE_SUPPORTS_PIPELINED_BL, _CE_SUPPORTS_NONPIPELINED_BL bits of CE
+ * capabilities.
+ *
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0x7" */
+
+#define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS {
+    NvU32 size;
+} NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS;
+
+#define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASKS
+ *
+ * Get HSHUB and FBHUB PCE masks.
+ *
+ *   [out] hshubPceMasks
+ *     PCE mask for each HSHUB
+ *   [out] fbhubPceMask
+ *     FBHUB PCE mask
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK             (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_MAX_HSHUBS                       5
+
+#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS {
+    NvU32 hshubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS];
+    NvU32 fbhubPceMask;
+} NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_ALL_CAPS
+ *
+ * Query caps of all CEs.
+ *
+ *   [out] capsTbl
+ *     Array of CE caps in the order of CEs. The caps bits interpretation is the same as in
+ *     NV2080_CTRL_CMD_CE_GET_CAPS.
+ *   [out] present
+ *     Bit mask indicating which CEs are usable by the client and have their caps indicated in capsTbl.
+ *     If a CE is not marked present, its caps bits should be ignored.
+ *     If client is subscribed to a MIG instance, only the CEs present in the instance are tagged as such.
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU)
+
+typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
+    NvU8  capsTbl[NV2080_CTRL_MAX_PCES][NV2080_CTRL_CE_CAPS_TBL_SIZE];
+    NvU32 present;
+} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS;
+
+#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0xb" */
+
+/* _ctrl2080ce_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h
new file mode 100644
index 0000000..55b9964
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080cipher.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h
new file mode 100644
index 0000000..20b8f4f
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h
@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080clk.finn
+//
+
+
+
+/* _ctrl2080clk_h_ */
+#include "nvfixedtypes.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080boardobj.h"
+#include "ctrl/ctrl2080/ctrl2080gpumon.h"
+#include "ctrl/ctrl2080/ctrl2080clkavfs.h"
+#include "ctrl/ctrl2080/ctrl2080volt.h"
+#include "ctrl/ctrl2080/ctrl2080pmumon.h"
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h
new file mode 100644
index 0000000..570987b
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h
@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn
+//
+
+
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080boardobj.h"
+#include "ctrl/ctrl2080/ctrl2080volt.h"
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h
new file mode 100644
index 0000000..e72e63c
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h
@@ -0,0 +1,183 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080dma.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX dma control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_DMA_INVALIDATE_TLB
+ *
+ * This command invalidates the GPU TLB. This is intended to be used
+ * by RM clients that manage their own TLB consistency when updating
+ * page tables on their own, or with DEFER_TLB_INVALIDATION options
+ * to other RM APIs.
+ *
+ *    hVASpace
+ *       This parameter specifies the VASpace object whose MMU TLB entries needs to be invalidated.
+ *       Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace.
+ *       Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC.
+ *
+ * This call can be used with the NV50_DEFERRED_API_CLASS (class 0x5080).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_TIMEOUT_RETRY
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_DMA_INVALIDATE_TLB (0x20802502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS {
+    NvHandle hClient; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
+    NvHandle hDevice; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
+    NvU32    engine;  // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
+    NvHandle hVASpace;
+} NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS;
+
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS             0:0
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE    (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE     (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO                1:1
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE       (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE        (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY              2:2
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE     (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE      (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE              3:3
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE     (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE      (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB                  4:4
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE         (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE          (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV                   5:5
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE          (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE           (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG                 6:6
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE        (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE         (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD                  7:7
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE         (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE          (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION           8:8
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE  (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE   (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON              9:9
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE     (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE      (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS          10:10
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE  (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR                  11:11
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE         (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE          (0x00000001)
+
+/*
+ * NV2080_CTRL_DMA_INFO
+ *
+ * This structure represents a single 32bit dma engine value.  Clients
+ * request a particular DMA engine value by specifying a unique dma
+ * information index.
+ *
+ * Legal dma information index values are:
+ *   NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
+ *     This index can be used to request the system address size in bits.
+ */
+typedef struct NV2080_CTRL_DMA_INFO {
+    NvU32 index;
+    NvU32 data;
+} NV2080_CTRL_DMA_INFO;
+
+/* valid dma info index values */
+#define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000)
+
+/* set INDEX_MAX to greatest possible index value */
+#define NV2080_CTRL_DMA_INFO_INDEX_MAX                 NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
+
+/*
+ * NV2080_CTRL_CMD_DMA_GET_INFO
+ *
+ * This command returns dma engine information for the associated GPU.
+ * Requests to retrieve dma information use an array of one or more
+ * NV2080_CTRL_DMA_INFO structures.
+ *
+ *   dmaInfoTblSize
+ *     This field specifies the number of valid entries in the dmaInfoList
+ *     array.  This value cannot exceed NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES.
+ *   dmaInfoTbl
+ *     This parameter contains the client's dma info table into
+ *     which the dma info values will be transferred by the RM.
+ *     The dma info table is an array of NV2080_CTRL_DMA_INFO structures.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_DMA_GET_INFO                   (0x20802503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum number of NV2080_CTRL_DMA_INFO entries per request */
+#define NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES           (256)
+
+#define NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_DMA_GET_INFO_PARAMS {
+    NvU32                dmaInfoTblSize;
+    /*
+     * C form:
+     * NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES];
+     */
+    NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES];
+} NV2080_CTRL_DMA_GET_INFO_PARAMS;
+
+typedef struct NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO {
+    /*! 
+     * 64KB aligned address of source 64KB tile for comptag reswizzle.
+     */
+    NvU32 srcAddr;
+
+    /*! 
+     * 64KB aligned address of destination 64KB tile for comptag reswizzle.
+     */
+    NvU32 dstAddr;
+
+    /*!
+     * Comptag index assigned to the 64K sized tile relative to
+     * the compcacheline. Absolute comptag index would be:
+     * startComptagIndex + relComptagIndex.
+     */
+    NvU16 relComptagIndex;
+} NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO;
+
+// _ctrl2080dma_h_
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h
new file mode 100644
index 0000000..982381f
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h
@@ -0,0 +1,105 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn
+//
+
+
+
+/*
+ * NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD
+ *
+ * Exports RM vidmem handles to a dma-buf fd.
+ *
+ * The objects in the 'handles' array are exported to the fd as range:
+ * [index, index + numObjects).
+ *
+ * A dma-buf fd is created the first time this control call is called.
+ * The fd is an input parameter for subsequent calls to attach additional handles
+ * over NV2080_CTRL_DMABUF_MAX_HANDLES.
+ *
+ * fd
+ *   A dma-buf file descriptor. If -1, a new FD will be created.
+ *
+ * totalObjects
+ *   The total number of objects that the client wishes to export to the FD.
+ *   This parameter will be honored only when the FD is getting created.
+ *
+ * numObjects
+ *   The number of handles the user wishes to export in this call.
+ *
+ * index
+ *   The index into the export fd at which to start exporting the handles in
+ *   'handles'. This index cannot overlap a previously used index.
+ *
+ * totalSize
+ *   The total size of memory being exported in bytes, needed to create the dma-buf.
+ *   This size includes the memory that will be exported in future export calls
+ *   for this dma-buf.
+ *
+ * handles
+ *   An array of {handle, offset, size} that describes the dma-buf.
+ *   The offsets and sizes must be OS page-size aligned.
+ *
+ * Limitations:
+ *   1. This call only supports vidmem objects for now.
+ *   2. All memory handles should belong to the same GPU or the same GPU MIG instance.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ *    NV_ERR_NO_MEMORY
+ *    NV_ERR_OPERATING_SYSTEM
+ *    NV_ERR_IN_USE
+ *    NV_ERR_INVALID_OBJECT
+ *    NV_ERR_INVALID_OBJECT_PARENT
+ */
+#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_DMABUF_MAX_HANDLES              128
+
+typedef struct NV2080_CTRL_DMABUF_MEM_HANDLE_INFO {
+    NvHandle hMemory;
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+} NV2080_CTRL_DMABUF_MEM_HANDLE_INFO;
+
+#define NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS {
+    NvS32 fd;
+    NvU32 totalObjects;
+    NvU32 numObjects;
+    NvU32 index;
+    NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_DMABUF_MEM_HANDLE_INFO handles[NV2080_CTRL_DMABUF_MAX_HANDLES], 8);
+} NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS;
+
+// _ctrl2080dmabuf_h_
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
new file mode 100644
index 0000000..7d0fabe
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
@@ -0,0 +1,63 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080ecc.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+
+
+#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS
+ *
+ * sramLastClearedTimestamp [out]
+ * dramLastClearedTimestamp [out]
+ *      unix-epoch based timestamp. These fields indicate when the error counters
+ *      were last cleared by the user.
+ *
+ * sramErrorCounts [out]
+ * dramErrorCounts [out]
+ *      Aggregate error counts for SRAM and DRAM
+ */
+
+#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U)
+
+typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
+    NvU32 sramLastClearedTimestamp;
+    NvU32 dramLastClearedTimestamp;
+
+    NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotalCounts, 8);
+    NV_DECLARE_ALIGNED(NvU64 sramUncorrectedTotalCounts, 8);
+    NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8);
+    NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8);
+} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS;
+/* _ctrl2080ecc_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
new file mode 100644
index 0000000..e71eb81
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
@@ -0,0 +1,372 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080event.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+#include "nv_vgpu_types.h"
+/* NV20_SUBDEVICE_XX event-related control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * This command sets event notification state for the associated subdevice.
+ * This command requires that an instance of NV01_EVENT has been previously
+ * bound to the associated subdevice object.
+ *
+ *   event
+ *     This parameter specifies the type of event to which the specified
+ *     action is to be applied.  This parameter must specify a valid
+ *     NV2080_NOTIFIERS value (see cl2080.h for more details) and should
+ *     not exceed one less NV2080_NOTIFIERS_MAXCOUNT.
+ *   action
+ *     This parameter specifies the desired event notification action.
+ *     Valid notification actions include:
+ *       NV2080_CTRL_SET_EVENT_NOTIFICATION_DISABLE
+ *         This action disables event notification for the specified
+ *         event for the associated subdevice object.
+ *       NV2080_CTRL_SET_EVENT_NOTIFICATION_SINGLE
+ *         This action enables single-shot event notification for the
+ *         specified event for the associated subdevice object.
+ *       NV2080_CTRL_SET_EVENT_NOTIFICATION_REPEAT
+ *         This action enables repeated event notification for the specified
+ *         event for the associated system controller object.
+ *    bNotifyState
+ *      This boolean is used to indicate the current state of the notifier
+ *      at the time of event registration. This is optional and its semantics
+ *      needs to be agreed upon by the notifier and client using the notifier
+ *    info32
+ *      This is used to send 32-bit initial state info with the notifier at
+ *      time of event registration
+ *    info16
+ *      This is used to send 16-bit initial state info with the notifier at
+ *      time of event registration
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION (0x20800301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
+    NvU32  event;
+    NvU32  action;
+    NvBool bNotifyState;
+    NvU32  info32;
+    NvU16  info16;
+} NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
+#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  (0x00000001)
+#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  (0x00000002)
+
+/* XUSB/PPC D-state defines */
+#define NV2080_EVENT_DSTATE_XUSB_D0                       (0x00000000)
+#define NV2080_EVENT_DSTATE_XUSB_D3                       (0x00000003)
+#define NV2080_EVENT_DSTATE_XUSB_INVALID                  (0xFFFFFFFF)
+#define NV2080_EVENT_DSTATE_PPC_D0                        (0x00000000)
+#define NV2080_EVENT_DSTATE_PPC_D3                        (0x00000003)
+#define NV2080_EVENT_DSTATE_PPC_INVALID                   (0xFFFFFFFF)
+
+// HDACODEC Decice DState, D3_COLD is only for verbose mapping, it cannot be logged
+typedef enum NV2080_EVENT_HDACODEC_DSTATE {
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = 0,
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = 1,
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = 2,
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = 3,
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = 4,
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = 5,
+} NV2080_EVENT_HDACODEC_DSTATE;
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * This command triggers a software event for the associated subdevice.
+ * This command accepts no parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER         (0x20800302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | 0x2" */
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
+ *
+ *     hMemory
+ *       This parameter specifies the handle of the memory object
+ *       that identifies the memory address translation for this
+ *       subdevice instance's notification(s).  The beginning of the
+ *       translation points to an array of notification data structures.
+ *       The size of the translation must be at least large enough to hold the
+ *       maximum number of notification data structures identified by
+ *       the NV2080_MAX_NOTIFIERS value.
+ *       Legal argument values must be instances of the following classes:
+ *         NV01_NULL
+ *         NV04_MEMORY
+ *       When hMemory specifies the NV01_NULL_OBJECT value then any existing
+ *       memory translation connection is cleared.  There must not be any
+ *       pending notifications when this command is issued.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x20800303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
+    NvHandle hMemory;
+} NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
+
+#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0
+#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING  1
+#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR    2
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY
+ *
+ *     hSemMemory
+ *       This parameter specifies the handle of the memory object that
+ *       identifies the semaphore memory associated with this subdevice
+ *       event notification.  Once this is set RM will generate an event
+ *       only when there is a change in the semaphore value.  It is
+ *       expected that the semaphore memory value will be updated by
+ *       the GPU indicating that there is an event pending. This
+ *       command is used by VGX plugin to determine which virtual
+ *       machine has generated a particular event.
+ *
+ *     semOffset
+ *       This parameter indicates the memory offset of the semaphore.
+ *
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_PARAM_STRUCT
+ *      NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY   (0x20800304) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS {
+    NvHandle hSemMemory;
+    NvU32    semOffset;
+} NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI
+ *
+ *     hSemMemory
+ *       This parameter specifies the handle of the memory object that
+ *       identifies the semaphore memory associated with this subdevice
+ *       event notification.  Once this is set RM will generate an event
+ *       only when there is a change in the semaphore value.  It is
+ *       expected that the semaphore memory value will be updated by
+ *       the GPU indicating that there is an event pending. This
+ *       command is used by VGX plugin to determine which virtual
+ *       machine has generated a particular event.
+ *
+ *     guestMSIAddr
+ *       This parameter indicates the guest allocated MSI address.
+ *
+ *     guestMSIData
+ *       This parameter indicates the MSI data set by the guest OS.
+ *
+ *     vmIdType
+ *       This parameter specifies the type of guest virtual machine identifier
+ *
+ *     guestVmId
+ *       This parameter specifies the guest virtual machine identifier
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_PARAM_STRUCT
+ *      NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI (0x20800305) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 guestMSIAddr, 8);
+    NvU32      guestMSIData;
+    NvHandle   hSemMemory;
+    NvBool     isReset;
+    VM_ID_TYPE vmIdType;
+    NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
+} NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION
+ *
+ *     hSemMemory
+ *       This parameter specifies the handle of the memory object that
+ *       identifies the semaphore memory associated with this subdevice
+ *       event notification.  Once this is set RM will generate an event
+ *       only when there is a change in the semaphore value.  It is
+ *       expected that the semaphore memory value will be updated by
+ *       the GPU indicating that there is an event pending. This
+ *       command is used by VGX plugin to determine which virtual
+ *       machine has generated a particular event.
+ *
+ *     isSemaMemValidationEnabled
+ *       This parameter used to enable/disable change in sema value check
+ *       while generating an event.
+ *
+ * Possible status values returned are:
+ *      NVOS_STATUS_SUCCESS
+ *      NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE
+ *      NVOS_STATUS_ERROR_INVALID_ARGUMENT
+ */
+
+
+#define NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION (0x20800306) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS {
+    NvHandle hSemMemory;
+    NvBool   isSemaMemValidationEnabled;
+} NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL
+ *
+ *     hSemMemory
+ *       This parameter specifies the handle of the memory object that
+ *       identifies the semaphore memory associated with this subdevice
+ *       event notification.  Once this is set RM will generate an event
+ *       only when there is a change in the semaphore value.  It is
+ *       expected that the semaphore memory value will be updated by
+ *       the GPU indicating that there is an event pending. This
+ *       command is used by VGX plugin to determine which virtual
+ *       machine has generated a particular event.
+ *
+ *     vmIdType
+ *       This parameter specifies the type of guest virtual machine identifier
+ *
+ *     guestVmId
+ *       This parameter specifies the guest virtual machine identifier
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL (0x20800307) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS {
+    NvHandle   hSemMemory;
+    VM_ID_TYPE vmIdType;
+    NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
+} NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO
+ *
+ * This command triggers a FIFO event for the associated subdevice.
+ *
+ *  hEvent
+ *    Handle of the event that should be notified. If zero, all
+ *    non-stall interrupt events for this subdevice will be notified.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO (0x20800308) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS {
+    NvHandle hEvent;
+} NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF_FOR_UID
+ *
+ * This command is used to create a video bind-point to an event buffer that
+ * is filtered by UID.
+ *
+ *  hEventBuffer[IN]
+ *      The event buffer to bind to
+ *
+ *  recordSize[IN]
+ *      The size of the FECS record in bytes
+ *
+ *  levelOfDetail[IN]
+ *      One of NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_:
+ *          FULL: Report all CtxSw events
+ *          SIMPLE: Report engine start and engine end events only
+ *          CUSTOM: Report events in the eventFilter field
+ *      NOTE: RM may override the level-of-detail depending on the caller
+ *
+ *  eventFilter[IN]
+ *      Bitmask of events to report if levelOfDetail is CUSTOM
+ *
+ *  bAllUsers[IN]
+ *     Only report video data for the current user if false, for all users if true
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF (0x20800309) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD {
+    NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = 0,
+    NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = 1,
+    NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = 2,
+} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD;
+
+#define NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS {
+    NvHandle                                hEventBuffer;
+    NvU32                                   recordSize;
+    NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD levelOfDetail;
+    NvU32                                   eventFilter;
+    NvBool                                  bAllUsers;
+} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS;
+
+/* _ctrl2080event_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h
new file mode 100644
index 0000000..a338bab
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080fan.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
new file mode 100644
index 0000000..a883326
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
@@ -0,0 +1,2906 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080fb.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX fb control commands and parameters */
+
+#include "nvlimits.h"
+
+/*
+ * NV2080_CTRL_FB_INFO
+ *
+ * This structure represents a single 32bit fb engine value.  Clients
+ * request a particular fb engine value by specifying a unique fb
+ * information index.
+ *
+ * Legal fb information index values are:
+ *   NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT
+ *     This index is used to request the number of tiled regions supported
+ *     by the associated subdevice.  The return value is GPU
+ *     implementation-dependent.  A return value of 0 indicates the GPU
+ *     does not support tiling.
+ *   NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE
+ *     This index is used to request the amount of compression (in bytes)
+ *     supported by the associated subdevice.  The return value is GPU
+ *     implementation-dependent.  A return value of 0 indicates the GPU
+ *     does not support compression.
+ *   Nv2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE
+ *     This index is used to request the DRAM page stride (in bytes)
+ *     supported by the associated subdevice.  The return value is GPU
+ *     implementation-dependent.
+ *   NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT
+ *     This index is used to request the number of free tiled regions on
+ *     the associated subdevice.  The return value represents the current
+ *     number of free tiled regions at the time the command is processed and
+ *     is not guaranteed to remain unchanged.  A return value of 0 indicates
+ *     that there are no available tiled regions on the associated subdevice.
+ *   NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT
+ *     This index is used to request the number of frame buffer partitions
+ *     on the associated subdevice. Starting with Fermi there are now two units
+ *     with the name framebuffer partitions. On those chips this index returns
+ *     the number of FBPAs. For number of FBPs use
+ *     NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE
+ *     This index is used to request the amount of framebuffer memory in
+ *     kilobytes physically present on the associated subdevice.  This
+ *     value will never exceed the value reported by
+ *     NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE.
+ *     This an SMC aware attribute, so the per-partition framebuffer memory
+ *     size will be returned when the client has a partition subscription.
+ *   NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE
+ *     This index is used to request the total amount of video memory in
+ *     kilobytes for use with the associated subdevice.  This value will
+ *     reflect both framebuffer memory as well as any system memory dedicated
+ *     for use with the subdevice.
+ *     This an SMC aware attribute, so the per-partition video memory size
+ *     will be returned when the client has a partition subscription.
+ *   NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE
+ *     This index is used to request the amount of total RAM in kilobytes
+ *     available for user allocations.  This value reflects the total ram
+ *     size less the amount of memory reserved for internal use.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_HEAP_START
+ *     This index is used to request the offset for start of heap in
+ *     kilobytes.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE
+ *     This index is used to request the available amount of video memory in
+ *     kilobytes for use with the associated subdevice or the SMC partition.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required to query per partition information, if the device is partitioned.
+ *     Alternatively, the SMC/MIG monitor capability can be acquired to query
+ *     aggregate available memory across all the valid partitions.
+ *   NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE
+ *     This index reflects the amount of heap memory in kilobytes that
+ *     is accessible by the CPU.  On subdevices with video memory sizes that
+ *     exceed the amount that can be bus mappable this value will be less
+ *     than that reported by NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH
+ *     This index is used to request the FB bus bandwidth on the associated
+ *     subdevice.
+ *   NV2080_CTRL_FB_INFO_INDEX_RAM_CFG
+ *     This index is used to request the implementation-dependent RAM
+ *     configuration value of the associated subdevice.
+ *   NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE
+ *     This index is used to request the type of RAM used for the framebuffer
+ *     on the associated subdevice.  Legal RAM types include:
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5
+ *   NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT
+ *     This index is used to request the number of FB banks on the associated
+ *     subdevice.
+ *   NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT
+ *     This index is used to request the offset relative to the start of the
+ *     overlay surface(s), in bytes, at which scanout should happen if the
+ *     primary and the overlay surfaces are all aligned on large page
+ *     boundaries.
+ *   NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB
+ *     This index is used to request the size of the GPU's virtual address
+ *     space in kilobytes.
+ *   NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB
+ *     This index is used to request the size of the GPU's virtual address
+ *     space heap (minus RM-reserved space) in kilobytes.
+ *   NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB
+ *     This index is used to request the size of the GPU's BAR1 mappable
+ *     virtual address space in kilobytes.
+ *   NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW
+ *     This index is deprecated, and returns zero value.
+ *   NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK
+ *     This index is used to request the mask of currently active partitions.
+ *     Each  active partition has an ID that's equivalent to the corresponding
+ *     bit position in the mask.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE
+ *     This index is used to request the amount of total RAM in kilobytes
+ *     reserved for internal RM allocations on Vista.  This will need to
+ *     be subtracted from the total heap size to get the amount available to
+ *     KMD.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION
+ *     This index is used to distinguish between different memory
+ *     configurations.
+ *   NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN
+ *     This index is used to check if the FB is functional
+ *   NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT
+ *     This index is used to get the number of FBPs on the subdevice. This
+ *     field is not to be confused with
+ *     NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (returns number of FBPAs).
+ *     Starting with Fermi the term partition is an ambiguous term, both FBP
+ *     and FBPA mean FB partitions. The FBPA is the low level DRAM controller,
+ *     while a FBP is the aggregation of one or more FBPAs, L2, ROP, and some
+ *     other units.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE
+ *     This index is used to get the size of the L2 cache in Bytes.
+ *     A value of zero indicates that the L2 cache isn't supported on the
+ *     associated subdevice.
+ *   NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID
+ *     This index is used to get the memory vendor ID information from
+ *     the Memory Information Table in the VBIOS.  Legal memory Vendor ID
+ *     values include:
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_RESERVED
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON
+ *   NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE
+ *     This index is used to request the amount of unused bar1 space. The
+ *     data returned is a value in KB. It is not guaranteed to be entirely
+ *     accurate since it is a snapshot at a particular time and can
+ *     change quickly.
+ *   NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE
+ *     This index is used to request the amount of largest unused contiguous
+ *     block in bar1 space.  The data returned is a value in KB. It is not
+ *     guaranteed to be entirely accurate since it is a snapshot at a particular
+ *     time and can change quickly.
+ *   NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE
+ *     This index is used to request the amount of usable framebuffer memory in
+ *     kilobytes physically present on the associated subdevice.  This
+ *     value will never exceed the value reported by
+ *     NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT
+ *     Returns the active LTC count across all active FBPs.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT
+ *     Returns the active LTS count across all active LTCs.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE
+ *     This is used to identify if pseudo-channel mode is enabled for HBM
+ *   NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE
+ *     This is used by WDDM-KMD to determine whether and how much RM reserved BAR1 for smooth transition
+ *   NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE
+ *     Returns the total size of the all dynamically offlined pages in KiB
+ *   NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED
+ *     Returns true if 1to1 comptag is enabled
+ *   NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE
+ *     Returns the total size of the memory(FB) that will saved/restored during save/restore cycle
+ *   NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT
+ *     Returns true if page retirement is allowed
+ *   NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED
+ *     Returns true if poison fuse is enabled
+ *   NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED
+ *     Returns true if ECC is enabled for FBPA
+ *   NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED
+ *     Returns true if dynamic page blacklisting is enabled
+ *   NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED
+ *     Returns true if 64KB mapping on BAR1 is force-enabled
+ *   NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE
+ *     Returns the P2P mailbox size to be allocated by the client. 
+ *     Returns 0 if the P2P mailbox is allocated by RM.
+ *   NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT_SIZE
+ *     Returns the P2P mailbox alignment requirement.
+ *     Returns 0 if the P2P mailbox is allocated by RM.
+ *   NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB
+ *     Returns the P2P mailbox max offset requirement.
+ *     Returns 0 if the P2P mailbox is allocated by RM.
+ *   NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB
+ *     Returns total protected memory when memory protection is enabled
+ *     Returns 0 when memory protection is not enabled.
+ *   NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB
+ *     Returns protected memory available for allocation when memory
+ *     protection is enabled.
+ *     Returns 0 when memory protection is not enabled.
+ *   NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE
+ *     Returns the ECC status size (corresponds to subpartitions or channels
+ *     depending on architecture/memory type).
+ */
+typedef struct NV2080_CTRL_FB_INFO {
+    NvU32 index;
+    NvU32 data;
+} NV2080_CTRL_FB_INFO;
+
+/* valid fb info index values */
+#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT                (0x00000000U) // Deprecated
+#define NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE                 (0x00000001U)
+#define NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE                 (0x00000002U)
+#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT           (0x00000003U)
+#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT                  (0x00000004U)
+#define NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE                        (0x00000005U)
+#define NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT           (0x00000006U)
+#define NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE                         (0x00000007U)
+#define NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE                   (0x00000008U)
+#define NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE                        (0x00000009U)
+#define NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE               (0x0000000AU)
+#define NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH                        (0x0000000BU)
+#define NV2080_CTRL_FB_INFO_INDEX_RAM_CFG                          (0x0000000CU)
+#define NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE                         (0x0000000DU)
+#define NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT                       (0x0000000EU)
+#define NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT        (0x0000000FU) // Deprecated (index reused to return 0)
+#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB          (0x0000000FU) // Deprecated (index reused to return 0)
+#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB           (0x0000000FU) // Deprecated (index reused to return 0)
+#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB        (0x0000000FU) // Deprecated (index reused to return 0)
+#define NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW                     (0x0000000FU) // Deprecated (index reused to return 0)
+#define NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB                   (0x00000010U)
+#define NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB                     (0x00000011U)
+#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB      (0x00000012U)
+#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB      (0x00000013U)
+#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK                   (0x00000014U)
+#define NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE         (0x00000015U)
+#define NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE                        (0x00000016U)
+#define NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION                     (0x00000017U)
+#define NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN                     (0x00000018U)
+#define NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT                        (0x00000019U)
+#define NV2080_CTRL_FB_INFO_INDEX_FBP_MASK                         (0x0000001AU)
+#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE                     (0x0000001BU)
+#define NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID             (0x0000001CU)
+#define NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE                  (0x0000001DU)
+#define NV2080_CTRL_FB_INFO_INDEX_HEAP_START                       (0x0000001EU)
+#define NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE   (0x0000001FU)
+#define NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE                  (0x00000020U)
+#define NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T                       (0x00000021U)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT                        (0x00000022U)
+#define NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT                        (0x00000023U)
+#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE                (0x00000024U)
+#define NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE              (0x00000025U)
+#define NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE        (0x00000026U)
+#define NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE                (0x00000027U)
+#define NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED             (0x00000028U)
+#define NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE         (0x00000029U)
+#define NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT            (0x0000002AU)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK                         (0x0000002BU)
+#define NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED                    (0x0000002CU)
+#define NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED                       (0x0000002DU)
+#define NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED         (0x0000002EU)
+#define NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED (0x0000002FU)
+#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE                 (0x00000030U)
+#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT            (0x00000031U)
+#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB (0x00000032U)
+#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB      (0x00000033U)
+#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB       (0x00000034U)
+#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE                  (0x00000035U)
+#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE                          (0x00000036U)
+
+#define NV2080_CTRL_FB_INFO_INDEX_MAX                              (0x35U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */
+
+/* valid fb RAM type values */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN                       (0x00000000U)
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM                         (0x00000001U)
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1                          (0x00000002U) /* SDDR and GDDR (aka DDR1 and GDDR1) */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2                         (0x00000003U) /* SDDR2 Used on NV43 and later */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2                          NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 /* Deprecated alias */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2                         (0x00000004U) /* GDDR2 Used on NV30 and some NV36 */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3                         (0x00000005U) /* GDDR3 Used on NV40 and later */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4                         (0x00000006U) /* GDDR4 Used on G80 and later (deprecated) */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3                         (0x00000007U) /* SDDR3 Used on G9x and later */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3                          NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 /* Deprecated alias */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5                         (0x00000008U) /* GDDR5 Used on GT21x and later */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2                        (0x00000009U) /* LPDDR (Low Power SDDR) used on T2x and later. */
+
+
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4                         (0x0000000CU) /* SDDR4 Used on Maxwell and later */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4                        (0x0000000DU) /* LPDDR (Low Power SDDR) used on T21x and later.*/
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1                          (0x0000000EU) /* HBM1 (High Bandwidth Memory) used on GP100 */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2                          (0x0000000FU) /* HBM2 (High Bandwidth Memory-pseudo channel) */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X                        (0x00000010U) /* GDDR5X Used on GP10x */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6                         (0x00000011U) /* GDDR6 Used on TU10x */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X                        (0x00000012U) /* GDDR6X Used on GA10x */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5                        (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3                          (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */
+
+/* valid RAM LOCATION types */
+#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED             (0x00000000U)
+#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED                (0x00000001U)
+#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED             (0x00000002U)
+
+/* valid Memory Vendor ID values */
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG           (0x00000001U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA           (0x00000002U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA            (0x00000003U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON             (0x00000004U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA             (0x00000005U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX             (0x00000006U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL             (0x00000007U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND           (0x00000008U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT              (0x00000009U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON            (0x0000000FU)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN           (0xFFFFFFFFU)
+
+#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED        (0x00000000U)
+#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED           (0x00000001U)
+#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED            (0x00000002U)
+
+/**
+ * NV2080_CTRL_CMD_FB_GET_INFO
+ *
+ * This command returns fb engine information for the associated GPU.
+ * Requests to retrieve fb information use a list of one or more
+ * NV2080_CTRL_FB_INFO structures.
+ *
+ *   fbInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     fbInfoList.
+ *   fbInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the fb information is to be returned.
+ *     This buffer must be at least as big as fbInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_FB_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_FB_GET_INFO                                (0x20801301U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_FB_GET_INFO_PARAMS {
+    NvU32 fbInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 fbInfoList, 8);
+} NV2080_CTRL_FB_GET_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_FB_GET_INFO_V2 (0x20801303U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS {
+    NvU32               fbInfoListSize;
+    NV2080_CTRL_FB_INFO fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE];
+} NV2080_CTRL_FB_GET_INFO_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO
+ *
+ * This command returns tile addressing information.
+ *
+ *   StartAddr
+ *     This parameter returns BAR1 plus the size of the local FB.
+ *   SpaceSize
+ *     This parameter returns the BAR1 aperture size less the size of the
+ *     local FB.
+ *
+ * Note that both parameters will contain zero if there is no system tile
+ * address space.
+ */
+#define NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO (0x20801302U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2" */
+
+typedef struct NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO {
+    NV_DECLARE_ALIGNED(NvU64 StartAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8);
+} NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET
+ *
+ * This command returns the GPU virtual address of a bar1
+ * allocation, given the CPU virtual address.
+ *
+ *   cpuVirtAddress
+ *     This field specifies the associated CPU virtual address of the
+ *     memory allocation.
+ *   gpuVirtAddress
+ *     The GPU virtual address associated with the allocation
+ *     is returned in this field.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET (0x20801310U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 cpuVirtAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 gpuVirtAddress, 8);
+} NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS;
+
+/*
+ * Note: Returns Zeros if no System carveout address info
+ *
+ * NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO
+ *
+ * This command returns FB carveout address space information
+ *
+ *   StartAddr
+ *     Returns the system memory address of the start of carveout space.
+ *   SpaceSize
+ *     Returns the size of carveout space.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO (0x2080130bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO {
+    NV_DECLARE_ALIGNED(NvU64 StartAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8);
+} NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO;
+
+/*
+ * NV2080_CTRL_FB_CMD_GET_CALIBRATION_LOCK_FAILED
+ *
+ * This command returns the failure counts for calibration.
+ *
+ *   uFlags
+ *     Just one for now -- ehether to reset the counts.
+ *   driveStrengthRiseCount
+ *     This parameter specifies the failure count for drive strength rising.
+ *   driveStrengthFallCount
+ *     This parameter specifies the failure count for drive strength falling.
+ *   driveStrengthTermCount
+ *     This parameter specifies the failure count for drive strength
+ *     termination.
+ *   slewStrengthRiseCount
+ *     This parameter specifies the failure count for slew strength rising.
+ *   slewStrengthFallCount
+ *     This parameter specifies the failure count for slew strength falling.
+ *   slewStrengthTermCount
+ *     This parameter specifies the failure count for slew strength
+ *     termination.
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NVOS_STATUS_INVALID_PARAM_STRUCT
+ *     NVOS_STATUS_NOT_SUPPORTED
+ *     NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED (0x2080130cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS {
+    NvU32 flags;
+    NvU32 driveStrengthRiseCount;
+    NvU32 driveStrengthFallCount;
+    NvU32 driveStrengthTermCount;
+    NvU32 slewStrengthRiseCount;
+    NvU32 slewStrengthFallCount;
+} NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS;
+
+/* valid flags parameter values */
+#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE              (0x00000000U)
+#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET             (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED
+ *
+ * This command specifies to RM if scanout compaction feature is allowed or
+ * not in the current configuration. In hybrid mode when dGPU is rendering the
+ * image, the dGPU blit to the scanout surface happens without mGPU's
+ * knowledge (directly to system memory), which results in stale compacted
+ * data resulting in corruption.
+ *
+ * This control call can be used to disable the compaction whenever the KMD
+ * (client) is switching to the pref mode in Hybrid i.e., whenever there is a
+ * possibility of dGPU doing a blit to mGpu scanout surface. Compaction can
+ * be enabled when system is back in hybrid power mode as mGpu will be
+ * rendering the image.
+ *
+ *   allowCompaction
+ *     This parameter specifies if the display compaction feature is allowed
+ *     or not allowed.
+ *   immediate
+ *     This parameter specifies whether compaction has to be enabled or
+ *     disabled immediately (based on the value of allowCompaction field) or
+ *     during the next modeset.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_INVALID_PARAM_STRUCT
+ *   NVOS_STATUS_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xD" */ // Deprecated, removed form RM
+
+typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS {
+    NvU32 allowCompaction;
+    NvU32 immediate;
+} NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS;
+
+/* valid allowCompaction values */
+#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOW         (0x00000001U)
+#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_DISALLOW      (0x00000000U)
+
+/* valid immediate values */
+#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_IMMEDIATE     (000000001U)
+#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_NOT_IMMEDIATE (000000000U)
+
+/*
+ * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
+ *
+ * This command flushes a cache on the GPU which all memory accesses go
+ * through.  The types of flushes supported by this API may not be supported by
+ * all hardware.  Attempting an unsupported flush type will result in an error.
+ *
+ *   addressArray
+ *     An array of physical addresses in the aperture defined by
+ *     NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE.  Each entry points to a
+ *     contiguous block of memory of size memBlockSizeBytes.  The addresses are
+ *     aligned down to addressAlign before coalescing adjacent addresses and
+ *     sending flushes to hardware.
+ *   addressAlign
+ *     Used to align-down addresses held in addressArray.  A value of 0 will be
+ *     forced to 1 to avoid a divide by zero.  Value is treated as minimum
+ *     alignment and any hardware alignment requirements above this value will
+ *     be honored.
+ *   addressArraySize
+ *     The number of entries in addressArray.
+ *   memBlockSizeBytes
+ *     The size in bytes of each memory block pointed to by addressArray.
+ *   flags
+ *     Contains flags to control various aspects of the flush.  Valid values
+ *     are defined in NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS*.  Not all flags are
+ *     valid for all defined FLUSH_MODEs or all GPUs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ * See Also:
+ *   NV0080_CTRL_CMD_DMA_FLUSH
+ *     Performs flush operations in broadcast for the GPU cache and other hardware
+ *     engines.  Use this call if you want to flush all GPU caches in a
+ *     broadcast device.
+ *    NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
+ *     Flushes memory associated with a single allocation if the hardware
+ *     supports it.  Use this call if you want to flush a single allocation and
+ *     you have a memory object describing the physical memory.
+ */
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE                      (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES            500U
+
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 addressArray[NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES], 8);
+    NvU32 addressArraySize;
+    NvU32 addressAlign;
+    NV_DECLARE_ALIGNED(NvU64 memBlockSizeBytes, 8);
+    NvU32 flags;
+} NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS;
+
+/* valid fields and values for flags */
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE              1:0
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY    (0x00000000U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY   (0x00000001U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY     (0x00000002U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK            2:2
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO            (0x00000000U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES           (0x00000001U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE            3:3
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO            (0x00000000U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES           (0x00000001U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE            4:4
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY (0x00000000U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE    (0x00000001U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH              5:5
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO              (0x00000000U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES             (0x00000001U)
+
+/*
+ * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2 instead)
+ *
+ * These commands access the cache allocation policy on a specific
+ * engine, if supported.
+ *
+ *   engine
+ *     Specifies the target engine.  Possible values are defined in
+ *     NV2080_ENGINE_TYPE.
+ *   allocPolicy
+ *     Specifies the read/write allocation policy of the cache on the specified
+ *     engine. Possible values are defined in
+ *     NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS and
+ *     NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES.
+ *
+ */
+typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS {
+    NvU32 engine;
+    NvU32 allocPolicy;
+} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS;
+
+/* valid values for allocPolicy */
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS                0:0
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO      (0x00000000U)
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES     (0x00000001U)
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES               1:1
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO     (0x00000000U)
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES    (0x00000001U)
+
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY
+ *
+ * This command is deprecated.
+ * Use NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 instead.
+ *
+ * This command sets the state of the cache allocation policy on a specific
+ * engine, if supported.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY       (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xF" */
+
+/*
+ * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAM
+ *
+ * These commands access the cache allocation policy on a specific
+ * client, if supported.
+ *
+ *   count
+ *     Specifies the number of entries in entry.
+ *   entry
+ *     Specifies an array of allocation policy entries.
+ *
+ * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY
+ *
+ *   clients
+ *     Specifies the target client.  Possible values are defined in
+ *     NV2080_CLIENT_TYPE_*.
+ *   allocPolicy
+ *     Specifies the read/write allocation policy of the cache on the specified
+ *     engine. Possible values are defined in
+ *     NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS and
+ *     NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES.
+ *
+ * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE
+ *
+ *     Specifies the maximum number of allocation policy entries allowed
+ */
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE 11U
+
+typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY {
+    NvU32 client;
+    NvU32 allocPolicy;
+} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY;
+
+typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
+    NvU32                                          count;
+    NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY entry[NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE];
+} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
+
+/* valid values for allocPolicy */
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS             0:0
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_DISABLE    (0x00000000U)
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ENABLE     (0x00000001U)
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW       1:1
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_NO   (0x00000000U)
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_YES  (0x00000001U)
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES            2:2
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_DISABLE   (0x00000000U)
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ENABLE    (0x00000001U)
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW      3:3
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_NO  (0x00000000U)
+#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_YES (0x00000001U)
+
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2
+ *
+ * This command sets the state of the cache allocation policy on a specific
+ * engine, if supported.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2          (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x18" */
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 instead)
+ *
+ * This command gets the state of the cache allocation policy on a specific
+ * engine, if supported.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY             (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x12" */
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2
+ *
+ * This command gets the state of the cache allocation policy on a specific
+ * engine, if supported.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2          (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x19" */
+
+
+/*
+ * NV2080_CTRL_CMD_FB_IS_KIND
+ *
+ * This command is used to perform various operations like 'IS_KIND_VALID',
+ * 'IS_KIND_COMPRESSIBLE'on the kind passed by the caller. The operation to be
+ * performed should be passed in the 'operation' parameter of
+ * NV2080_CTRL_FB_IS_KIND_PARAMS, the kind on which the operation is to be
+ * performed should be passed in the 'kind' parameter. The result of the
+ * operation (true/false) will be returned in the 'result' parameter.
+ *
+ *   operation
+ *     Specifies what operation is to be performed on the kind passed by the
+ *     caller. The supported operations are
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure is
+ *         supported for this GPU. Returns nonzero value in 'result' parameter
+ *         if the input kind is supported, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure is
+ *         compressible. Returns nonzero value in 'result' parameter if the
+ *         input kind is compressible, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports
+ *         1 bit compression. Returns nonzero value in 'result' parameter if
+ *         kind supports 1 bit compression, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports
+ *         2 bit compression. Returns nonzero value in 'result' parameter if
+ *         kind supports 1 bit compression, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports
+ *         4 bit compression. Returns nonzero value in 'result' parameter if
+ *         kind supports 4 bit compression, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure
+ *         supports ZBC. Returns nonzero value in 'result' parameter if the
+ *         input kind supports ZBC, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure
+ *         supports 1 bit ZBC. Returns nonzero value in 'result' parameter if
+ *         the input kind supports 1 bit ZBC, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure
+ *         supports 2 bit ZBC. Returns nonzero value in 'result' parameter if
+ *         the input kind supports 2 bit ZBC, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure
+ *         supports 4 bit ZBC. Returns nonzero value in 'result' parameter if
+ *         the input kind supports 4 bit ZBC, else returns zero in the result.
+ *   kind
+ *     Specifies the kind on which the operation is to be carried out. The
+ *     legal range of values for the kind parameter is different on different
+ *     GPUs. For e.g. on Fermi, valid range is 0x00 to 0xfe. Still, some values
+ *     inside this legal range can be invalid i.e. not defined.
+ *     So its always better to first check if a particular kind is supported on
+ *     the current GPU with 'NV2080_CTRL_FB_IS_KIND_SUPPORTED' operation.
+ *   result
+ *     Upon return, this parameter will hold the result (true/false) of the
+ *     operation performed on the kind.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_IS_KIND                                (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_FB_IS_KIND_PARAMS {
+    NvU32  operation;
+    NvU32  kind;
+    NvBool result;
+} NV2080_CTRL_FB_IS_KIND_PARAMS;
+
+/* valid values for operation */
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED      (0x00000000U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE   (0x00000001U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 (0x00000002U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 (0x00000003U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 (0x00000004U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC            (0x00000005U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1   (0x00000006U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2   (0x00000007U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4   (0x00000008U)
+
+/**
+ * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO
+ *
+ * This command returns the state of a cache which all GPU memory accesess go
+ * through.
+ *
+ *   powerState
+ *     Returns the power state of the cache.  Possible values are defined in
+ *     NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE.
+ *
+ *   writeMode
+ *     Returns the write mode of the cache.  Possible values are defined in
+ *     NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE.
+ *
+ *   bypassMode
+ *     Returns the bypass mode of the L2 cache.  Possible values are defined in
+ *     NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE.
+ *
+ *   rcmState
+ *     Returns the RCM state of the cache.  Possible values are defined in
+ *     NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE.
+ *
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO           (0x20801315U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS {
+    NvU32 powerState;
+    NvU32 writeMode;
+    NvU32 bypassMode;
+    NvU32 rcmState;
+} NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS;
+
+/* valid values for powerState */
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED     (0x00000000U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED    (0x00000001U)
+/* valid values for writeMode */
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH (0x00000000U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK    (0x00000001U)
+/* valid values for bypassMode */
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED    (0x00000000U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED     (0x00000001U)
+/* valid values for rcmState */
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL          (0x00000000U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING (0x00000001U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED       (0x00000002U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE    (0x00000003U)
+
+/*
+ * NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY
+ *
+ * These commands access the cache promotion policy on a specific
+ * engine, if supported by the hardware.
+ *
+ * Cache promotion refers to the GPU promoting a memory read to a larger
+ * size to preemptively fill the cache so future reads to nearby memory
+ * addresses will hit in the cache.
+ *
+ *   engine
+ *     Specifies the target engine.  Possible values are defined in
+ *     NV2080_ENGINE_TYPE.
+ *   promotionPolicy
+ *     Specifies the promotion policy of the cache on the specified
+ *     engine. Possible values are defined by
+ *     NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_*.  These values are in terms
+ *     of the hardware cache line size.
+ *
+ */
+typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS {
+    NvU32 engine;
+    NvU32 promotionPolicy;
+} NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS;
+
+/* valid values for promotionPolicy */
+#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_NONE    (0x00000000U)
+#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_QUARTER (0x00000001U)
+#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_HALF    (0x00000002U)
+#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_FULL    (0x00000003U)
+
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY
+ *
+ * This command sets the cache promotion policy on a specific engine, if
+ * supported by the hardware.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY (0x20801316U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x16" */ // Deprecated, removed form RM
+
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY
+ *
+ * This command gets the cache promotion policy on a specific engine, if
+ * supported by the hardware.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY (0x20801317U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x17" */ // Deprecated, removed form RM
+
+/*
+ * NV2080_CTRL_FB_CMD_GET_FB_REGION_INFO
+ *
+ * This command returns the FB memory region characteristics.
+ *
+ *   numFBRegions
+ *     Number of valid regions returned in fbRegion[]
+ *   fbRegion[].base
+ *     Base address of region.  The first valid address in the range
+ *     [base..limit].
+ *   fbRegion[].limit
+ *     Last/end address of region.  The last valid address in the range
+ *     [base..limit].
+ *     (limit - base + 1) = size of the region
+ *   fbRegion[].reserved
+ *     Amount of memory that RM speculatively needs within the region.  A
+ *     client doing its own memory management should leave at least this much
+ *     memory available for RM use.  This particularly applies to a driver
+ *     model like LDDM.
+ *   fbRegion[].performance
+ *     Relative performance of this region compared to other regions.
+ *     The definition is vague, and only connotes relative bandwidth or
+ *     performance.  The higher the value, the higher the performance.
+ *   fbRegion[].supportCompressed
+ *     TRUE if compressed surfaces/kinds are supported
+ *     FALSE if compressed surfaces/kinds are not allowed to be allocated in
+ *     this region
+ *   fbRegion[].supportISO
+ *     TRUE if ISO surfaces/kinds are supported (Display, cursor, video)
+ *     FALSE if ISO surfaces/kinds are not allowed to be allocated in this
+ *     region
+ *   fbRegion[].bProtected
+ *     TRUE if this region is a protected memory region.  If true only
+ *     allocations marked as protected (NVOS32_ALLOC_FLAGS_PROTECTED) can be
+ *     allocated in this region.
+ *   fbRegion[].blackList[] - DEPRECATED: Use supportISO
+ *     TRUE for each NVOS32_TYPE_IMAGE* that is NOT allowed in this region.
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO             (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES   17U
+
+typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES];
+
+typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 limit, 8);
+    NV_DECLARE_ALIGNED(NvU64 reserved, 8);
+    NvU32                                                  performance;
+    NvBool                                                 supportCompressed;
+    NvBool                                                 supportISO;
+    NvBool                                                 bProtected;
+    NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG blackList;
+} NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO;
+
+#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES 16U
+
+#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS {
+    NvU32 numFBRegions;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO fbRegion[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES], 8);
+} NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_OFFLINE_PAGES
+ *
+ * This command adds video memory page addresses to the list of offlined
+ * addresses so that they're not allocated to any client. The newly offlined
+ * addresses take effect after a reboot.
+ *
+ *   offlined
+ *     This input parameter is an array of NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO
+ *     structures, containing the video memory physical page numbers that
+ *     are to be blacklisted. This array can hold a maximum of NV2080_CTRL_FB_
+ *     BLACKLIST_PAGES_MAX_PAGES address pairs. Valid entries are adjacent.
+ *   pageSize
+ *     This input parameter contains the size of the page that is to be
+ *     blacklisted.
+ *   validEntries
+ *     This input parameter specifies the number of valid entries in the
+ *     offlined array.
+ *   numPagesAdded
+ *     This output parameter specifies how many of the validEntries were
+ *     actually offlined. If numPagesAdded < validEntries, it
+ *     means that only addresses from offlined[0] to offlined[numPagesAdded - 1]
+ *     were added to the list of offlined addresses.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_OFFLINE_PAGES              (0x20801321U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES       (0x00000040U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS (0xffffffffffffffffULL)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K    (0x00000000U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K   (0x00000001U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K  (0x00000002U)
+
+/*
+ * NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO
+ *
+ *   pageAddressWithEccOn
+ *     Address of the memory page retired when ECC is enabled on the board.
+ *   pageAddressWithEccOff
+ *     Address of the memory page retired when ECC is disabled on the board.
+ *   rbcAddress
+ *     Row/Bank/Column Address of the faulty memory which caused the page to
+ *     be retired
+ *   source
+ *     The reason for the page to be retired
+ *   status
+ *      Non-exceptional reasons for a page retirement failure
+ *         NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK
+ *            No error
+ *         NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT
+ *            The given address is already pending retirement or has
+ *            been retired during the current driver run. The page
+ *            will be offlined during the next driver run.
+ *         NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED
+ *            The given page was retired on a previous driver run,
+ *            so it should not be accessible unless offlining failed.
+ *            Failing to offline a page is strongly indicative of a
+ *            driver offlining bug.
+ *         NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL
+ *            The PBL is full and no more pages can be retired
+ *         NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR
+ *            Internal driver error
+ *
+ */
+
+
+
+typedef struct NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO {
+    NV_DECLARE_ALIGNED(NvU64 pageAddressWithEccOn, 8);
+    NV_DECLARE_ALIGNED(NvU64 pageAddressWithEccOff, 8);
+    NvU32 rbcAddress;
+    NvU32 source;
+    NvU32 status;
+    NvU32 timestamp;
+} NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO;
+
+/* valid values for source */
+#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE    (0x00000002U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE             (0x00000004U)
+
+
+
+/* valid values for status */
+#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK                  (0x00000000U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT  (0x00000001U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED (0x00000002U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL          (0x00000003U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR      (0x00000004U)
+
+/* deprecated */
+#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE        NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE
+#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE                 NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE
+
+
+#define NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8);
+    NvU32 pageSize;
+    NvU32 validEntries;
+    NvU32 numPagesAdded;
+} NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES
+ *
+ * This command returns the list of video memory page addresses in the
+ * Inforom's blacklist.
+ *
+ *   offlined
+ *     This output parameter is an array of NV2080_CTRL_FB_BLACKLIST_ADDRESS_
+ *     INFO structures, containing the video memory physical page numbers that
+ *     are blacklisted. This array can hold a maximum of NV2080_CTRL_FB_
+ *     BLACKLIST_PAGES_MAX_PAGES address pairs. Valid entries are adjacent.
+ *     The array also contains the Row/Bank/Column Address and source.
+ *   validEntries
+ *     This output parameter specifies the number of valid entries in the
+ *     offlined array.
+ *   bRetirementPending (DEPRECATED, use retirementPending instead)
+ *     This output parameter returns if any pages on the list are pending
+ *     retirement.
+ *   retirementPending
+ *     Communicates to the caller whether retirement updates are pending and the
+ *     reason for the updates. Possible fields are:
+ *     NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_*:
+ *       NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE:
+ *         Indicates whether pages are pending retirement due to SBE.
+ *       NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE:
+ *         Indicates whether pages are pending retirement due to DBE. Driver
+ *         reload needed to retire bad memory pages and allow compute app runs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+
+
+#define NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES                            (0x20801322U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE          0:0
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE   0U
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE    1U
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE          1:1
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE   0U
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE    1U
+
+
+
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8);
+    NvU32  validEntries;
+    NvBool bRetirementPending;
+    NvU8   retirementPending;
+} NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_QUERY_ACR_REGION
+ *
+ * This control command is used to query the secured region allocated
+ *
+ * queryType
+ *          NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_STATUS: Provides the alloc
+ *          status and ACR region ID.
+ *          NV2080_CTRL_CMD_FB_QUERY_MAP_REGION : Maps the region on BAR1
+ *           it returns the "pCpuAddr" and pPriv to user.
+ *          NV2080_CTRL_CMD_FB_QUERY_UNMAP_REGION: Unmaps the mapped region.
+ *          it takes the pPriv as input
+ *
+ * clientReq : struct ACR_REQUEST_PARAMS
+ *          It is used to find the allocated ACR region for that client
+ *          clientId     : ACR Client ID
+ *          reqReadMask  : read mask of ACR region
+ *          reqWriteMask : Write mask of ACR region
+ *          regionSize   : ACR region Size
+ *
+ * clientReqStatus : struct ACR_STATUS_PARAMS
+ *          This struct is stores the output of requested ACR region.
+ *          allocStatus     : Allocated Status of ACR region
+ *          regionId        : ACR region ID
+ *          physicalAddress : Physical address on FB
+ *
+ *
+ * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE
+ *          NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE : Control command executed successfully
+ *          NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST : Please check the parameter
+ *                      for ACR client request
+ *          NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_FAILED_TO_MAP_ON_BAR1 : RM Fails to map ACR region
+ *                      on BAR1
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+*/
+#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION (0x20801325U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID" */
+
+//
+// We can create an ACR region by using RMCreateAcrRegion[1|2] regkey or mods -acr[1|2]_size
+// Client ID for such region is 2 in RM.
+//
+#define NV2080_CTRL_CMD_FB_ACR_CLIENT_ID    2U
+
+typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE {
+    NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = 0,
+    NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY = 1,
+    NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS = 2,
+} NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE;
+
+typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE {
+    NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE = 0,
+    NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST = 1,
+} NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE;
+
+typedef struct ACR_REQUEST_PARAMS {
+    NvU32 clientId;
+    NvU32 reqReadMask;
+    NvU32 reqWriteMask;
+    NvU32 regionSize;
+} ACR_REQUEST_PARAMS;
+
+typedef struct ACR_REGION_ID_PROP {
+    NvU32 regionId;
+    NvU32 readMask;
+    NvU32 writeMask;
+    NvU32 regionSize;
+    NvU32 clientMask;
+    NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8);
+} ACR_REGION_ID_PROP;
+
+typedef struct ACR_STATUS_PARAMS {
+    NvU32 allocStatus;
+    NvU32 regionId;
+    NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8);
+} ACR_STATUS_PARAMS;
+
+typedef struct ACR_REGION_HANDLE {
+    NvHandle hClient;
+    NvHandle hParent;
+    NvHandle hMemory;
+    NvU32    hClass;
+    NvHandle hDevice;
+} ACR_REGION_HANDLE;
+
+typedef struct ACR_FALCON_LS_STATUS {
+    NvU16  falconId;
+    NvBool bIsInLs;
+} ACR_FALCON_LS_STATUS;
+
+#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS {
+    NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE       queryType;
+    NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE errorCode;
+    NV_DECLARE_ALIGNED(ACR_REGION_ID_PROP acrRegionIdProp, 8);
+    ACR_REQUEST_PARAMS                      clientReq;
+    NV_DECLARE_ALIGNED(ACR_STATUS_PARAMS clientReqStatus, 8);
+    ACR_REGION_HANDLE                       handle;
+    ACR_FALCON_LS_STATUS                    falconStatus;
+} NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES
+ *
+ * This command clears offlined video memory page addresses from the Inforom.
+ *
+ *   sourceMask
+ *     This is a bit mask of NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE. Pages
+ *     offlined from the specified sources will be cleared/removed from the
+ *     Inforom PBL object denylist.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES (0x20801326U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x26U)
+
+typedef struct NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS {
+    NvU32 sourceMask;
+} NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO
+ *
+ * Gets pointer to then object of class CompBitCopy, which is used for swizzling
+ * compression bits in the compression backing store. The caller is expected to
+ * have the appropriate headers for class CompBitCopy. Also retrieves values of some
+ * parameters needed to call the compbit swizzling method.
+ *
+ * @params[out] void *pCompBitCopyObj
+ *     Opaque pointer to object of class CompBitCopy
+ * @params[out] void *pSwizzleParams
+ *     Opaque pointer to values needed to call the compbit
+ *     swizzle method.
+ *
+ * Possible status values returned are:
+ *   NV_OK NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO (0x20801327U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID (0x27U)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pCompBitCopyObj, 8);
+    NV_DECLARE_ALIGNED(NvP64 pSwizzleParams, 8);
+} NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP
+ *
+ * Gets the count and mask of LTCs for a given FBP.
+ *
+ *   fbpIndex
+ *     The physical index of the FBP to get LTC info for.
+ *   ltcMask
+ *     The mask of active LTCs for the given FBP.
+ *   ltcCount
+ *     The count of active LTCs for the given FBP.
+ *   ltsMask
+ *      The mask of active LTSs for the given FBP
+ *   ltsCount
+ *      The count of active LTSs for the given FBP
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP (0x20801328U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID (0x28U)
+
+typedef struct NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS {
+    NvU8  fbpIndex;
+    NvU32 ltcMask;
+    NvU32 ltcCount;
+    NvU32 ltsMask;
+    NvU32 ltsCount;
+} NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS;
+
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT               < Deprecated >
+ *
+ * "set the context" for following CompBitCopy member functions.
+ * These are the CompBitCopy member variables that remain connstant
+ * over multiple CompBitCopy member function calls, yet stay the same
+ * throughout a single surface eviction.
+ *
+ * @params[in] UINT64  backingStorePA;
+ *     Physical Address of the Backing Store
+ * @params[in] UINT08 *backingStoreVA;
+ *     Virtual Address of the Backing Store
+ * @params[in] UINT64  backingStoreChunkPA;
+ *     Physical Address of the "Chunk Buffer"
+ * @params[in] UINT08 *backingStoreChunkVA;
+ *     Virtual Address of the "Chunk Buffer"
+ * @params[in] UINT32  backingStoreChunkSize;
+ *     Size of the "Chunk Buffer"
+ * @params[in] UINT08 *cacheWriteBitMap;
+ *     Pointer to the bitmap which parts of the
+ *     "Chunk" was updated.
+ * @params[in] bool    backingStoreChunkOverfetch;
+ *     Overfetch factor.
+ * @params[in] UINT32  PageSizeSrc;
+ *     Page size of Source Surface.
+ * @params[in] UINT32  PageSizeDest;
+ *     page size of Destination Surface.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT (0x20801329U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x29" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS {
+    NvU32  CBCBaseAddress;
+    NV_DECLARE_ALIGNED(NvU64 backingStorePA, 8);
+    NV_DECLARE_ALIGNED(NvU8 *backingStoreVA, 8);
+    NV_DECLARE_ALIGNED(NvU64 backingStoreChunkPA, 8);
+    NV_DECLARE_ALIGNED(NvU8 *backingStoreChunkVA, 8);
+    NvU32  backingStoreChunkSize;
+    NV_DECLARE_ALIGNED(NvU8 *cacheWriteBitMap, 8);
+    NvBool backingStoreChunkOverfetch;
+    NvU32  PageSizeSrc;
+    NvU32  PageSizeDest;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS              < Deprecated >
+ *
+ * Retrieves the Compression and Fast Clear bits for the surface+offset given.
+ *
+ * @params[out] NvU32  *fcbits;
+ *     Fast Clear Bits returned
+ * @params[out] NvU32  *compbits;
+ *     Compression Bits returned
+ * @params[in] NvU64  dataPhysicalStart;
+ *     Start Address of Data
+ * @params[in] NvU64  surfaceOffset;
+ *     Offset in the surface
+ * @params[in] NvU32  comptagLine;
+ *     Compression Tag Number
+ * @params[in] NvBool upper64KBCompbitSel;
+ *     Selects Upper or Lower 64K
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTEDD
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS (0x2080132aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2A" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU32 *fcbits, 8);
+    NV_DECLARE_ALIGNED(NvU32 *compbits, 8);
+    NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
+    NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
+    NvU32  comptagLine;
+    NvBool upper64KBCompbitSel;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS              < Deprecated >
+ *
+ * Sets the Compression and Fast Clear bits for the surface+offset given.
+ *
+ * @params[in] NvU32  fcbits;
+ *     Fast Clear Bits to write.
+ * @params[in] NvU32  compbits;
+ *     Compression Bits to write
+ * @params[in] NvBool writeFc;
+ *     Indicates if Fast Clear Bits should be written
+ * @params[in] NvU64  dataPhysicalStart;
+ *     Start Address of Data
+ * @params[in] NvU64  surfaceOffset;
+ *     Offset in the surface
+ * @params[in] NvU32  comptagLine;
+ *     Compression Tag Number
+ * @params[in] NvBool upper64KBCompbitSel;
+ *     Selects Upper or Lower 64K
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS (0x2080132bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2B" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS {
+    NvU32  fcbits;
+    NvU32  compbits;
+    NvBool writeFc;
+    NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
+    NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
+    NvU32  comptagLine;
+    NvBool upper64KBCompbitSel;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB         < Deprecated >
+ *
+ * Read 64KB chunk of CompBits
+ *
+ * @params[in] NvU64  SrcDataPhysicalStart;
+ *     Start Address of Data
+ * @params[in] NvU32  SrcComptagLine;
+ *     Compression Tag Number
+ * @params[in] NvU32  page64KB;
+ *     Which 64K block to read from.
+ * @params[out] NvU32  *compbitBuffer;
+ *     Buffer for CompBits read,
+ * @params[in] NvBool upper64KBCompbitSel;
+ *     Selects Upper or Lower 64K
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB (0x2080132cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2C" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 SrcDataPhysicalStart, 8);
+    NvU32  SrcComptagLine;
+    NvU32  page64KB;
+    NV_DECLARE_ALIGNED(NvU32 *compbitBuffer, 8);
+    NvBool upper64KBCompbitSel;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB        < Deprecated >
+ *
+ * Write 64K chunk of COmpBits.
+ *
+ * @params[in] NvU64  SrcDataPhysicalStart;
+ *     Start Address of Data
+ * @params[in] NvU32  SrcComptagLine;
+ *     Compression Tag Number
+ * @params[in] NvU32  page64KB;
+ *     Which 64K block to read from.
+ * @params[in] NvU32  *compbitBuffer;
+ *     Buffer for CompBits to write.
+ * @params[in] NvBool upper64KBCompbitSel
+ *     Selects Upper or Lower 64K
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB (0x2080132dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2D" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 DstDataPhysicalStart, 8);
+    NvU32  DstComptagLine;
+    NvU32  page64KB;
+    NV_DECLARE_ALIGNED(NvU32 *compbitBuffer, 8);
+    NvBool upper64KBCompbitSel;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS        < Deprecated >
+ *
+ * The PS (Performance Path, or Optimized path, or Per Slice version)
+ * of PutCompBits.
+ *
+ * @params[out] NvU32  *fcbits;
+ *     Buffer to receive Fast Clear Bits.
+ * @params[out] NvU32  *compbits;
+ *     Buffer to receive Compression Bits.
+ * @params[out] NvU32  *compCacheLine;
+ *     Buffer to receive Comp Cache Line data.
+ * @params[in] NvU64  dataPhysicalStart;
+ *     Start Address of Data
+ * @params[in] NvU64  surfaceOffset;
+ *     Offset in the surface
+ * @params[in] NvU32  comptagLine;
+ *     Compression Tag Line Number
+ * @params[in] NvU32  ROPTile_offset;
+ *     Offset in the surface of the ROP tile.
+ * @params[in] NvBool upper64KBCompbitSel;
+ *     Selects Upper or Lower 64K
+ * @params[in] NvBool getFcBits;
+ *   Indicates if fast clear bits should be returned.
+ * @params[in] NvP64  derivedParams
+ *   Actually a CompBitDerivedParams structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS (0x2080132eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2E" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU32 *fcbits, 8);
+    NV_DECLARE_ALIGNED(NvU32 *compbits, 8);
+    NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
+    NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
+    NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
+    NvU32  comptagLine;
+    NvU32  ROPTile_offset;
+    NvBool upper64KBCompbitSel;
+    NvBool getFcBits;
+    NV_DECLARE_ALIGNED(NvP64 derivedParams, 8);
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS        < Deprecated >
+ *
+ * The PS (Performance Path, or Optimized path, or Per Slice version)
+ * of GetCompBits.
+ *
+ * @params[in] NvU32  fcbits;
+ *     Buffer with Fast Clear Bits to write.
+ * @params[in] NvU32  compbits;
+ *     Buffer to receive Compression Bits.
+ * @params[in] NvBool writeFc
+ *     Indicates of Fast Clear Bits should be written.
+ * @params[in] NvU32  *compCacheLine;
+ *     Buffer to receive Comp Cache Line data.
+ * @params[in] NvU64  dataPhysicalStart;
+ *     Start Address of Data
+ * @params[in] NvU64  surfaceOffset;
+ *     Offset in the surface
+ * @params[in] NvU32  comptagLine;
+ *     Compression Tag Line Number
+ * @params[in] NvU32  ROPTile_offset;
+ *     Offset in the surface of the ROP tile.
+ * @params[in] NvBool upper64KBCompbitSel;
+ *     Selects Upper or Lower 64K
+ * @params[in] NvP64  derivedParams
+ *   Actually a CompBitDerivedParams structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS (0x2080132fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2F" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS {
+    NvU32  fcbits;
+    NvU32  compbits;
+    NvBool writeFc;
+    NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
+    NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
+    NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
+    NvU32  comptagLine;
+    NvU32  ROPTile_offset;
+    NvBool upper64KBCompbitSel;
+    NV_DECLARE_ALIGNED(NvP64 derivedParams, 8);
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS              < Deprecated >
+ *
+ * The PS (Performance Path, or Optimized path, or Per Slice version)
+ * of ReadCompCacheLine.
+ *
+ * @paramsNvU32  *compCacheLine;
+ *    Buffer for Comp Cache Line Read
+ * @paramsNvU32  comptagLine;
+ *    Comp Tag Line Number to read
+ * @paramsNvU32  partition;
+ *    FB Partition of the desired Comp Cache Line
+ * @paramsNvU32  slice;
+ *    Slice of the desired Comp Cache Line
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS (0x20801330U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x30" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
+    NvU32 comptagLine;
+    NvU32 partition;
+    NvU32 slice;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS             < Deprecated >
+ *
+ * The PS (Performance Path, or Optimized path, or Per Slice version)
+ * of WriteCompCacheLine.
+ *
+ * @params[in] NvU32  *compCacheLine;
+ *    Buffer for Comp Cache Line to Write
+ * @params[in] NvU32  comptagLine;
+ *    Comp Tag Line Number to Write
+ * @params[in] NvU32  partition;
+ *    FB Partition of the desired Comp Cache Line
+ * @params[in] NvU32  slice;
+ *    Slice of the desired Comp Cache Line
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS (0x20801331U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x31" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
+    NvU32 comptagLine;
+    NvU32 partition;
+    NvU32 slice;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS          < Deprecated >
+ *
+ * Used by PS (Performance Path, or Optimized path, or Per Slice version)
+ * to retrieve upper and lower Address of the CompCacheLine.
+ *
+ * @params[out] NvU64  *minCPUAddress;
+ *    Minimum (lower bound) of the ComCacheLine.
+ * @params[out] NvU64  *minCPUAddress;
+ *    Minimum (lower bound) of the ComCacheLine.
+ * @params[in] NvU32  comptagLine;
+ *    CompTagLine to fetch the bounds of.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS (0x20801332U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x32" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 *minCPUAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 *maxCPUAddress, 8);
+    NvU32 comptagLine;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET             < Deprecated >
+ *
+ * Used by PS (Performance Path, or Optimized path, or Per Slice version)
+ * to retrieve partition, slice and ROP Tile Offset  of the passed in
+ * surface location.
+ *
+ * @params[out] NvU64  *part;
+ *    Partition in which the target part of the surface resides.
+ * @params[out] NvU64  *slice;
+ *    Slice in which the target part of the surface resides.
+ * @params[out] NvU64  *ropTileoffset;
+ *    Offset to the start of the ROP Tile in which the target part of
+ * the surface resides.
+ * @params[in] NvU64  *dataPhysicalStart;
+ *    Start address of data for which part/slice/offset is desired.
+ * @params[in] NvU64  surfaceOffset;
+ *    Byte offset of data for which part/slice/offset is desired.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET (0x20801333U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x33" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 *part, 8);
+    NV_DECLARE_ALIGNED(NvU64 *slice, 8);
+    NV_DECLARE_ALIGNED(NvU64 *ropTileoffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
+    NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS      < Deprecated >
+ *
+ * Used by PS (Performance Path, or Optimized path, or Per Slice version)
+ * to create a CompBitCopy::CompBitDerivedParams object
+ *
+ * @params[out] NvP64  derivedParams
+ *   Actually a CompBitDerivedParams structure.
+  * @params[in] NvU32  comptagLine;
+ *     Compression Tag Line Number
+ * @params[in] NvU32  ROPTile_offset;
+ *     Offset in the surface of the ROP tile.
+ * @params[in] NvBool upper64KBCompbitSel;
+ *     Selects Upper or Lower 64K
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS (0x20801334U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x34" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 derivedParams, 8);
+    NvU32  comptagLine;
+    NvBool upper64KBCompbitSel;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1                    < Deprecated >
+ *
+ * Used by MODS (and possibly other clients) to have compbit code write
+ * write directly to BAR1, rather than a intermediate buffer.
+ *
+ * @params[in] NvBool bForceBar1;
+ *     Enables or disables direct writes to BAR1.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 (0x20801335U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x35" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS {
+    NvBool bForceBar1;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_AMAP_CONF
+ *
+ * Fills in fields of a structure of class ConfParamsV1, which is used for
+ * swizzling compression bits in the compression backing store.
+ * The caller is expected to have the appropriate headers for class ConfParamsV1.
+ *
+ * @params[in|out] void *pAmapConfParms
+ *     Opaque pointer to structure of values for ConfParamsV1
+ * @params[in|out] void *pCbcSwizzleParms
+ *     Opaque pointer to structure of values for CbcSwizzleParamsV1
+ *
+ * Possible status values returned are:
+ *   NV_OK NV_ERR_NOT_SUPPORTED
+ *
+ * pCbcSwizzleParams will be filled in with certain parameters from
+ * @CbcSwizzleParamsV1.  However, the caller is responsible for making sure
+ * all parameters are filled in before using it.
+ */
+#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF (0x20801336U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID (0x36U)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pAmapConfParams, 8);
+    NV_DECLARE_ALIGNED(NvP64 pCbcSwizzleParams, 8);
+} NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_CBC_OP
+ *
+ * Provides a way for clients to request a CBC Operation
+ *
+ * @params[in] CTRL_CMD_FB_CBC_OP fbCBCOp
+ *      CBC Operation requested.
+ *      Valid Values:
+ *          CTRL_CMD_FB_CBC_OP_CLEAN
+ *          CTRL_CMD_FB_CBC_OP_INVALIDATE
+ *
+ * Possible status values returned are:
+ *   NV_OK NV_ERR_NOT_SUPPORTED NV_ERR_INVALID_ARGUMENT NV_ERR_TIMEOUT
+ */
+#define NV2080_CTRL_CMD_FB_CBC_OP (0x20801337U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Permitted CBC Operations
+ */
+typedef enum CTRL_CMD_FB_CBC_OP {
+    CTRL_CMD_FB_CBC_OP_CLEAN = 0,
+    CTRL_CMD_FB_CBC_OP_INVALIDATE = 1,
+} CTRL_CMD_FB_CBC_OP;
+
+#define NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID (0x37U)
+
+typedef struct NV2080_CTRL_CMD_FB_CBC_OP_PARAMS {
+    CTRL_CMD_FB_CBC_OP fbCBCOp;
+} NV2080_CTRL_CMD_FB_CBC_OP_PARAMS;
+
+/*!
+ *  NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION
+ *
+ *  The call will fetch the compression tags reserved for CBC eviction.
+ *
+ *  Each comptag will correspond to a unique compression cacheline. The usage of
+ *  these comptags is to evict the CBC by making accesses to a dummy compressed page,
+ *  thereby evicting each CBC line.
+ *
+ *  @param [in][out] NvU32 pCompTags
+ *     Array of reserved compression tags of size @ref NV2080_MAX_CTAGS_FOR_CBC_EVICTION
+ *  @param [out] numCompTags
+ *     Number of entries returned in @ref pCompTags
+ *
+ *  @returns
+ *      NV_OK
+ *      NV_ERR_INVALID_STATE
+ *      NV_ERR_OUT_OF_RANGE
+ *      NV_ERR_INVALID_PARAMETER
+ */
+#define NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION (0x20801338U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Max size of @ref NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS::pCompTags
+ * Arbitrary, but sufficiently large number. Should be checked against CBC size.
+ */
+#define NV2080_MAX_CTAGS_FOR_CBC_EVICTION             0x7FU
+
+
+#define NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID (0x38U)
+
+typedef struct NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS {
+    NvU32 pCompTags[NV2080_MAX_CTAGS_FOR_CBC_EVICTION];
+    NvU32 numCompTags;
+} NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE
+ *
+ * This Call will allocate compression tag
+ *
+ * @params[in] NvU32 attr
+ *      Stores the information:
+ *          1. NVOS32_ATTR_COMPR_REQUIRED or not
+ *          2. NVOS32_ATTR_PAGE_SIZE
+ * @params[in] NvU32 attr2
+ *      Determine whether to allocate
+ *      an entire cache line or allocate by size
+ * @params[in] NvU32 size
+ *      Specify the size of allocation, in pages not bytes
+ * @params[in] NvU32 ctagOffset
+ *      Determine the offset usage of the allocation
+ * @params[out] NvU32 hwResId
+ *      Stores the result of the allocation
+ * @params[out] NvU32 RetcompTagLineMin
+ *      The resulting min Ctag Number from the allocation
+ * @params[out] NvU32 RetcompTagLineMax
+ *      The resulting max Ctag Number from the allocation
+ * @returns
+ *      NV_OK
+ *      NV_ERR_INSUFFICIENT_RESOURCES
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_INVALID_STATE
+ */
+
+#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE (0x20801339U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID (0x39U)
+
+typedef struct NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS {
+    NvU32 attr;
+    NvU32 attr2;
+    NvU32 size;
+    NvU32 ctagOffset;
+    NvU32 hwResId;
+    NvU32 retCompTagLineMin;
+    NvU32 retCompTagLineMax;
+} NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_FREE_TILE
+ *
+ * This control call is used to release tile back to the free pool
+ *
+ * @params[in] NvU32 hwResId
+ *      Stores the information of a previous allocation
+ * @returns
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_INVALID_STATE
+ */
+
+#define NV2080_CTRL_CMD_FB_FREE_TILE (0x2080133aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID (0x3AU)
+
+typedef struct NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS {
+    NvU32 hwResId;
+} NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_FB_SETUP_VPR_REGION
+ *
+ * This control command is used to request vpr region setup
+ *
+ * requestType
+ *          NV2080_CTRL_CMD_FB_SET_VPR: Request to setup VPR
+ *
+ * requestParams : struct VPR_REQUEST_PARAMS
+ *          It contains the VPR region request details like,
+ *          startAddr : FB offset from which we need to setup VPR
+ *          size      : required size of the region
+ *
+ * statusParams  : struct VPR_STATUS_PARAMS
+ *          This struct stores the output of requested VPR region
+ *          status    : Whether the request was successful
+ *
+ * NV2080_CTRL_CMD_FB_VPR_ERROR_CODE :
+ *          NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC : Some unknown error occurred
+ *          NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST : Request was invalid
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION (0x2080133bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE {
+    NV2080_CTRL_CMD_FB_SET_VPR = 0,
+} NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE;
+
+typedef enum NV2080_CTRL_CMD_FB_VPR_ERROR_CODE {
+    NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC = 0,
+    NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST = 1,
+} NV2080_CTRL_CMD_FB_VPR_ERROR_CODE;
+
+typedef struct VPR_REQUEST_PARAMS {
+    NvU32 startAddr;
+    NvU32 size;
+} VPR_REQUEST_PARAMS;
+
+typedef struct VPR_STATUS_PARAMS {
+    NvU32 status;
+} VPR_STATUS_PARAMS;
+
+#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID (0x3BU)
+
+typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS {
+    NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE requestType;
+    VPR_REQUEST_PARAMS                  requestParams;
+    VPR_STATUS_PARAMS                   statusParams;
+} NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS;
+typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS *PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES
+ *
+ * This command returns the list of offlined video memory page addresses in the
+ * region managed by Client
+ *
+ *   offlinedPages
+ *     This output parameter is an array of video memory physical page numbers that
+ *     are offlined. This array can hold a maximum of NV2080_CTRL_FB_
+ *     OFFLINED_PAGES_MAX_PAGES addresses.
+ *   pageSize
+ *     This output parameter contains the size of the page that is offlined.
+ *   validEntries
+ *     This output parameter specifies the number of valid entries in the
+ *     offlined array.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES (0x2080133cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x3CU)
+
+typedef struct NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS {
+    NvU32 offlinedPages[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES];    // A 32B can hold enough.
+    NvU32 pageSize;
+    NvU32 validEntries;
+} NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO
+ *
+ * This command returns parameters required to initialize compbit copy object
+ * used by address mapping library
+ *
+ *   defaultPageSize
+ *     Page size used by @ref CompBitCopy methods
+ *   comptagsPerCacheLine
+ *     Number of compression tags in a single compression cache line.
+ *   unpackedComptagLinesPerCacheLine;
+ *     From hw (not adjusted for CompBits code)  Number of compression tags
+ *     in a single compression cache line.
+ *   compCacheLineSizePerLTC;
+ *     Size of compression cache line per L2 slice. Size in Bytes.
+ *   unpackedCompCacheLineSizePerLTC;
+ *     From hw (not adjusted for CompBits code) size of compression
+ *     cache line per L2 slice. Size in Bytes
+ *   slicesPerLTC;
+ *     Number of L2 slices per L2 cache.
+ *   numActiveLTCs;
+ *     Number of active L2 caches. (Not floorswept)
+ *   familyName;
+ *     Family name for the GPU.
+ *   chipName;
+ *     Chip name for the GPU.
+ *   bitsPerRAMEntry;
+ *     Bits per RAM entry. (Need better doc)
+ *   ramBankWidth;
+ *     Width of RAM bank. (Need better doc)
+ *   bitsPerComptagLine;
+ *     Number of bits per compression tag line.
+ *   ramEntriesPerCompCacheLine;
+ *     Number of RAM entries spanned by 1 compression cache line.
+ *   comptagLineSize;
+ *     Size of compression tag line, in Bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO (0x2080133dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID (0x3DU)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS {
+    NvU32 defaultPageSize;
+    NvU32 comptagsPerCacheLine;
+    NvU32 unpackedComptagLinesPerCacheLine;
+    NvU32 compCacheLineSizePerLTC;
+    NvU32 unpackedCompCacheLineSizePerLTC;
+    NvU32 slicesPerLTC;
+    NvU32 numActiveLTCs;
+    NvU32 familyName;
+    NvU32 chipName;
+    NvU32 bitsPerRAMEntry;
+    NvU32 ramBankWidth;
+    NvU32 bitsPerComptagLine;
+    NvU32 ramEntriesPerCompCacheLine;
+    NvU32 comptagLineSize;
+} NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_RRD
+ *
+ * Sets the row-to-row delay on the GPU's FB
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  Any error code
+ */
+#define NV2080_CTRL_CMD_FB_SET_RRD (0x2080133eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_SET_RRD_RESET_VALUE (~((NvU32)0))
+#define NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID (0x3EU)
+
+typedef struct NV2080_CTRL_FB_SET_RRD_PARAMS {
+    NvU32 rrd;
+} NV2080_CTRL_FB_SET_RRD_PARAMS;
+
+/*
+ * NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
+ *
+ * This is not a control call of it's own, but there are common definitions for
+ * the two NV2080_CTRL_CMD_FB_SET_READ/WRITE_LIMIT control calls.
+ */
+typedef struct NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS {
+    NvU8 limit;
+} NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS;
+#define NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE (0xffU)
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_READ_LIMIT
+ *
+ * Sets the READ_LIMIT to be used in the NV_PFB_FBPA_DIR_ARB_CFG0 register
+ *
+ *  limit
+ *      The limit value to use
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  Any error code
+ */
+#define NV2080_CTRL_CMD_FB_SET_READ_LIMIT               (0x2080133fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE       NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE
+#define NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID (0x3FU)
+
+typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT
+ *
+ * Sets the WRITE_LIMIT to be used in the NV_PFB_FBPA_DIR_ARB_CFG0 register
+ *
+ *  limit
+ *      The limit value to us
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  Any error code
+ */
+#define NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT         (0x20801340U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE
+#define NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID (0x40U)
+
+typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING
+ *
+ * Patches some VBIOS values related to PBR to better suit mining applications
+ *
+ *  bEnable
+ *      Set the mining-specific values or reset to the original values
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  Any error code
+ */
+#define NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING (0x20801341U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID (0x41U)
+
+typedef struct NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS {
+    NvBool bEnable;
+} NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT
+ *
+ * Get memory alignment. Replacement for NVOS32_FUNCTION_GET_MEM_ALIGNMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT       (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS (4U)
+#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID (0x42U)
+
+typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS {
+    NvU32 alignType;                                 // Input
+    NvU32 alignAttr;
+    NvU32 alignInputFlags;
+    NvU32 alignHead;
+    NV_DECLARE_ALIGNED(NvU64 alignSize, 8);
+    NvU32 alignHeight;
+    NvU32 alignWidth;
+    NvU32 alignPitch;
+    NvU32 alignPad;
+    NvU32 alignMask;
+    NvU32 alignOutputFlags[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS];
+    NvU32 alignBank[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS];
+    NvU32 alignKind;
+    NvU32 alignAdjust;                                // Output -- If non-zero the amount we need to adjust the offset
+    NvU32 alignAttr2;
+} NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_CBC_BASEADDR
+ *
+ * Get the CBC Base physical address
+ * This control call is required by error containment tests
+ * NV2080_CTRL_CMD_FB_GET_AMAP_CONF can also return CBC base address
+ * but it requires kernel privilege, and it not callalble from SRT test
+ *
+ * @params[out] NvU64 cbcBaseAddr
+ *     Base physical address for CBC data.
+ *
+ * Possible status values returned are:
+ *   NV_OK NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR (0x20801343U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID (0x43U)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS {
+    NvU32 cbcBaseAddress;
+    NvU32 compCacheLineSize;
+    NV_DECLARE_ALIGNED(NvU64 backingStoreStartPA, 8);
+    NV_DECLARE_ALIGNED(NvU64 backingStoreAllocPA, 8);
+    NvU32 backingStoreChunkOverfetch;
+} NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS;
+
+#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING                             0:0
+#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE 0U
+#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE  1U
+
+
+
+typedef struct NV2080_CTRL_FB_REMAP_ENTRY {
+    NvU32 remapRegVal;
+    NvU32 timestamp;
+    NvU8  fbpa;
+    NvU8  sublocation;
+    NvU8  source;
+    NvU8  flags;
+} NV2080_CTRL_FB_REMAP_ENTRY;
+
+/* valid values for source */
+
+
+#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD         (0x00000002U)
+#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD         (0x00000003U)
+
+#define NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS                (0x00000200U)
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS
+ *
+ * This command returns the list of remapped rows stored in the Inforom.
+ *
+ *   entryCount
+ *     This output parameter specifies the number of remapped rows
+ *   flags
+ *     This output parameter contains info on whether or not there are pending
+ *     remappings and whether or not a remapping failed
+ *   entries
+ *     This output parameter is an array of NV2080_CTRL_FB_REMAP_ENTRY
+ *     containing inforomation on the remapping that occurred. This array can
+ *     hold a maximum of NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_INVALID_POINTER
+ *    NV_ERR_OBJECT_NOT_FOUND
+ *    NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS                 (0x20801344U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING                       \
+    NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE  NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE                       1:1
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE 0U
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE  1U
+
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x44U)
+
+typedef struct NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS {
+    NvU32                      entryCount;
+    NvU8                       flags;
+    NV2080_CTRL_FB_REMAP_ENTRY entries[NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS];
+} NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS;
+
+// Max size of the queryParams in Bytes, so that the NV2080_CTRL_FB_FS_INFO_QUERY struct is still 32B
+#define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE 24U
+
+/*!
+ * Structure holding the out params for NV2080_CTRL_FB_FS_INFO_INVALID_QUERY.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS {
+    // Unused param, will ensure the size of NV2080_CTRL_FB_FS_INFO_QUERY struct to be 32B
+    NvU8 data[NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE];
+} NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBP_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS {
+    /*!
+     * [IN]: swizzId
+     * PartitionID associated with a created smc partition. Currently used only for a
+     * device monitoring client to get the physical values of the FB. The client needs to pass
+     * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId.
+     * RM will consider this request similar to a legacy case.
+     * The client's subscription is used only as a capability check and not as an input swizzId.
+     */
+    NvU32 swizzId;
+    /*!
+     * [OUT]: physical/local fbp mask.
+     */
+    NV_DECLARE_ALIGNED(NvU64 fbpEnMask, 8);
+} NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LTC_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS {
+    /*!
+     * [IN]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [OUT]: physical/local ltc mask.
+     */
+    NvU32 ltcEnMask;
+} NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LTS_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS {
+    /*!
+     * [IN]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [OUT]: physical/local lts mask.
+     * Note that lts bits are flattened out for all ltc with in a fbp.
+     */
+    NvU32 ltsEnMask;
+} NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBPA_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS {
+    /*!
+     * [IN]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [OUT]: physical/local FBPA mask.
+     */
+    NvU32 fbpaEnMask;
+} NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS {
+    /*!
+     * [IN]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [OUT]: physical/local FBPA-SubPartition mask.
+     */
+    NvU32 fbpaSubpEnMask;
+} NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS {
+    /*!
+     * [IN]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [OUT]: Logical/local FBP index
+     */
+    NvU32 fbpLogicalIndex;
+} NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_ROP_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS {
+    /*!
+     * [IN]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [OUT]: physical/local ROP mask.
+     */
+    NvU32 ropEnMask;
+} NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS {
+    /*!
+     * [IN]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [IN]: swizzId
+     * PartitionID associated with a created smc partition.
+     */
+    NvU32 swizzId;
+    /*!
+     * [OUT]: physical ltc mask.
+     */
+    NvU32 ltcEnMask;
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS {
+    /*!
+     * [IN]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [IN]: swizzId
+     * PartitionID associated with a created smc partition.
+     */
+    NvU32 swizzId;
+    /*!
+     * [OUT]: physical lts mask.
+     */
+    NvU32 ltsEnMask;
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS {
+    /*!
+     * [IN]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [IN]: swizzId
+     * PartitionID associated with a created smc partition.
+     */
+    NvU32 swizzId;
+    /*!
+     * [OUT]: physical fbpa mask.
+     */
+    NvU32 fbpaEnMask;
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS {
+    /*!
+     * [IN]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [IN]: swizzId
+     * PartitionID associated with a created smc partition.
+     */
+    NvU32 swizzId;
+    /*!
+     * [OUT]: physical rop mask.
+     */
+    NvU32 ropEnMask;
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS {
+    /*!
+     * [IN]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [IN]: swizzId
+     * PartitionID associated with a created smc partition. Currently used only for a
+     * device monitoring client to get the physical values of the FB. The client needs to pass
+     * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId.
+     * RM will consider this request similar to a legacy case.
+     * The client's subscription is used only as a capability check and not as an input swizzId.
+     */
+    NvU32 swizzId;
+    /*!
+     * [OUT]: physical FBPA_SubPartition mask associated with requested partition.
+     */
+    NV_DECLARE_ALIGNED(NvU64 fbpaSubpEnMask, 8);
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS;
+
+// Possible values for queryType
+#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY               0x0U
+#define NV2080_CTRL_FB_FS_INFO_FBP_MASK                    0x1U
+#define NV2080_CTRL_FB_FS_INFO_LTC_MASK                    0x2U
+#define NV2080_CTRL_FB_FS_INFO_LTS_MASK                    0x3U
+#define NV2080_CTRL_FB_FS_INFO_FBPA_MASK                   0x4U
+#define NV2080_CTRL_FB_FS_INFO_ROP_MASK                    0x5U
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK       0x6U
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK       0x7U
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK      0x8U
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK       0x9U
+#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK              0xAU
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xBU
+#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP             0xCU
+
+typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
+    NvU16 queryType;
+    NvU8  reserved[2];
+    NvU32 status;
+    union {
+        NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS          inv;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS fbp, 8);
+        NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS               ltc;
+        NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS               lts;
+        NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS              fbpa;
+        NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS               rop;
+        NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS  dmLtc;
+        NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS  dmLts;
+        NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS dmFbpa;
+        NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS  dmRop;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS dmFbpaSubp, 8);
+        NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS         fbpaSubp;
+        NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS        fbpLogicalMap;
+    } queryParams;
+} NV2080_CTRL_FB_FS_INFO_QUERY;
+
+// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_FB_GET_FS_INFO
+#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 96U
+
+#define NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID (0x46U)
+
+typedef struct NV2080_CTRL_FB_GET_FS_INFO_PARAMS {
+    NvU16 numQueries;
+    NvU8  reserved[6];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_QUERY queries[NV2080_CTRL_FB_FS_INFO_MAX_QUERIES], 8);
+} NV2080_CTRL_FB_GET_FS_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_FS_INFO
+ *
+ * This control call returns the fb engine information for a partition/GPU.
+ * Supports an interface so that the caller can issue multiple queries by batching them
+ * in a single call. Returns the first error it encounters.
+ *
+ * numQueries[IN]
+ *     - Specifies the number of valid queries.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_FS_INFO                             (0x20801346U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS              (0x0U)
+#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW           (0x1U)
+#define NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS (0x2U)
+#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW          (0x3U)
+#define NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS             (0x4U)
+
+#define NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID (0x47U)
+
+typedef struct NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS {
+    NvU32 histogram[5];
+} NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM
+ *
+ * This control call returns stats on the number of banks that have a certain
+ * number of rows remapped in the bank. Specifically the number of banks that
+ * have 0, 1, 2 through (max-2), max-1 and max number of rows remapped in the
+ * bank. Values will be returned in an array.
+ *
+ * Index values are:
+ *
+ *   NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS
+ *     Number of banks with zero rows remapped
+     NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW
+ *     Number of banks with one row remapped
+     NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS
+ *     Number of banks with 2 through (max-2) rows remapped
+     NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW
+ *     Number of banks with (max-1) rows remapped
+     NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS
+ *     Number of banks with max rows remapped
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM (0x20801347U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_DYNAMICALLY_BLACKLISTED_PAGES
+ *
+ * This command returns the list of dynamically blacklisted video memory page addresses
+ * after last driver load.
+ *
+ *   blackList
+ *     This output parameter is an array of NV2080_CTRL_FB_DYNAMIC_BLACKLIST_ADDRESS_INFO
+ *     This array can hold a maximum of NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES.
+ *   validEntries
+ *     This output parameter specifies the number of valid entries in the
+ *     blackList array.
+ *   baseIndex
+ *     With the limit of up to 512 blacklisted pages, the size of this array
+ *     exceeds the rpc buffer limit. This control call will collect the data
+ *     in multiple passes. This parameter indicates the start index of the
+ *     data to be passed back to the caller
+ *     This cannot be greater than NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES
+ *   bMore
+ *     This parameter indicates whether there are more valid elements to be
+ *     fetched.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES (0x20801348U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */
+
+/* Maximum pages that can be dynamically blacklisted */
+#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES    512U
+
+/*
+ * Maximum entries that can be sent in a single pass of 
+ * NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES
+ */
+#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES  64U
+
+/**
+ * NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO
+ *   pageNumber
+ *     This output parameter specifies the dynamically blacklisted page number.
+ *   source
+ *     The reason for the page to be retired. Valid values for
+ *     this parameter include:
+ *        NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_INVALID
+ *           Invalid source.
+ *        NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE
+ *           Page retired by dynamic page retirement due to a double bit
+ *           error seen.
+ */
+typedef struct NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO {
+    NV_DECLARE_ALIGNED(NvU64 pageNumber, 8);
+    NvU8 source;
+} NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO;
+
+#define NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x48U)
+
+typedef struct NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES], 8);
+    NvU32  validEntries;
+    NvU32  baseIndex;
+    NvBool bMore;
+} NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS;
+
+/* valid values for source */
+
+#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID (0x00000000U)
+#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO
+ *
+ * This control command is used by clients to query information pertaining to client allocations.
+ *
+ *
+ * @params [IN/OUT] NvU64 allocCount:
+ *        Client specifies the allocation count that it received using the
+ *        previous NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO control call.
+ *        RM will get the total number of allocations known by RM and fill
+ *        allocCount with it.
+ *
+ * @params [IN] NvP64 pAllocInfo:
+ *        Pointer to the buffer allocated by client of size NV2080_CTRL_CMD_FB_ALLOCATION_INFO *
+ *        allocCount. RM returns the info pertaining to each  of the contiguous client
+ *        allocation chunks in pAllocInfo. The format of the allocation information is given by
+ *        NV2080_CTRL_CMD_FB_ALLOCATION_INFO. The client has to sort the returned information if
+ *        it wants to retain the legacy behavior of SORTED BY OFFSET. Information is only returned
+ *        if and only if allocCount[IN]>=allocCount[OUT] and clientCount[IN]>=clientCount[OUT].
+ *
+ * @params [IN/OUT] NvP64 clientCount:
+ *        Client specifies the client count that it received using the
+ *        previous NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO control call.
+ *        RM will get the total number of clients that have allocations with RM
+ *        and fill clientCount with it.
+ *
+ * @params [IN] NvP64 pClientInfo:
+ *        Pointer to the buffer allocated by client of size NV2080_CTRL_CMD_FB_CLIENT_INFO *
+ *        clientCount. RM returns the info pertaining to each of the clients that have allocations
+ *        known about by RM in pClientInfo. The format of the allocation information is given by
+ *        NV2080_CTRL_CMD_FB_CLIENT_INFO. Information is only returned if and only if
+ *        allocCount[IN]>=allocCount[OUT] and clientCount[IN]>=clientCount[OUT].
+ *
+ * @returns Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_POINTER
+ *   NV_ERR_NO_MEMORY
+ *
+ * @Usage: All privileged RM clients for debugging only. Initially, call this with allocCount =
+ *         clientCount = 0 to get client count, and then call again with allocated memory and sizes.
+ *         Client can repeat with the new count-sized allocations until a maximum try count is
+ *         reached or client is out of memory.
+ */
+
+#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO           (0x20801349U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * These work with the FLD_SET_REF_NUM and FLD_TEST_REF macros and describe the 'flags' member
+ * of the NV2080_CTRL_CMD_FB_ALLOCATION_INFO struct.
+ */
+
+// Address space of the allocation
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE 4:0
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM         0U
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM         1U
+
+// Whether the allocation is shared
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED 5:5
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE        0U
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE         1U
+
+// Whether this client owns this allocation
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER 6:6
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE         0U
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE          1U
+
+typedef struct NV2080_CTRL_CMD_FB_ALLOCATION_INFO {
+    NvU32 client;                        /* [OUT] Identifies the client that made or shares the allocation (index into pClientInfo)*/
+    NvU32 flags;                         /* [OUT] Flags associated with the allocation (see previous defines) */
+    NV_DECLARE_ALIGNED(NvU64 beginAddr, 8);   /* [OUT] Starting physical address of the chunk */
+    NV_DECLARE_ALIGNED(NvU64 size, 8);   /* [OUT] Size of the allocated contiguous chunk in bytes */
+} NV2080_CTRL_CMD_FB_ALLOCATION_INFO;
+
+typedef struct NV2080_CTRL_CMD_FB_CLIENT_INFO {
+    NvHandle handle;                                    /* [OUT] Handle of the client that made or shares the allocation */
+    NvU32    pid;                                       /* [OUT] PID of the client that made or shares the allocation */
+
+    /* For the definition of the subprocessID and subprocessName params, see NV0000_CTRL_CMD_SET_SUB_PROCESS_ID */
+    NvU32    subProcessID;                              /* [OUT] Subprocess ID of the client that made or shares the allocation */
+    char     subProcessName[NV_PROC_NAME_MAX_LENGTH];   /* [OUT] Subprocess Name of the client that made or shares the allocation */
+} NV2080_CTRL_CMD_FB_CLIENT_INFO;
+
+#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID (0x49U)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 allocCount, 8);
+    NV_DECLARE_ALIGNED(NvP64 pAllocInfo, 8);
+    NV_DECLARE_ALIGNED(NvU64 clientCount, 8);
+    NV_DECLARE_ALIGNED(NvP64 pClientInfo, 8);
+} NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS
+ *
+ * This control command is used by clients to update the NUMA status.
+ *
+ * @params [IN] NvBool bOnline:
+ *
+ * @returns Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *
+ */
+#define NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS (0x20801350U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID (0x50U)
+
+typedef struct NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS {
+    NvBool bOnline;
+} NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_NUMA_INFO
+ *
+ * This control command is used by clients to get per-subdevice NUMA memory
+ * information as assigned by the system.
+ *
+ * numaNodeId[OUT]
+ *     - Specifies the NUMA node ID.
+ *
+ * numaMemAddr[OUT]
+ *     - Specifies the NUMA memory address.
+ *
+ * numaMemSize[OUT]
+ *     - Specifies the NUMA memory size.
+ *
+ * numaOfflineAddressesCount[IN/OUT]
+ *     - If non-zero, then it specifies the maximum number of entries in
+ *       numaOfflineAddresses[] for which the information is required.
+ *       It will be updated with the actual number of entries present in
+ *       the numaOfflineAddresses[].
+ *
+ * numaOfflineAddresses[OUT]
+ *      - If numaOfflineAddressesCount is non-zero, it contains the addresses
+ *        of offline pages in the NUMA region.
+ *
+ * @returns Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_NUMA_INFO               (0x20801351U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64U
+
+#define NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID (0x51U)
+
+typedef struct NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS {
+    NvS32 numaNodeId;
+    NV_DECLARE_ALIGNED(NvU64 numaMemAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 numaMemSize, 8);
+    NvU32 numaOfflineAddressesCount;
+    NV_DECLARE_ALIGNED(NvU64 numaOfflineAddresses[NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES], 8);
+} NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS;
+
+/* _ctrl2080fb_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
new file mode 100644
index 0000000..b8341aa
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
@@ -0,0 +1,791 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080fifo.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/*
+ * NV2080_CTRL_CMD_SET_GPFIFO
+ *
+ * This command set the GPFIFO offset and number of entries for a channel
+ * after it has been allocated. The channel must be idle and not pending,
+ * otherwise ERROR_IN_USE will be returned.
+ *
+ *   hChannel
+ *     The handle to the channel.
+ *   base
+ *     The base of the GPFIFO in the channel ctxdma.
+ *   numEntries
+ *     The number of entries in the GPFIFO.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_CHANNEL
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV2080_CTRL_CMD_SET_GPFIFO (0x20801102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_CMD_SET_GPFIFO_PARAMS {
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NvU32    numEntries;
+} NV2080_CTRL_CMD_SET_GPFIFO_PARAMS;
+
+/*
+ * NV2080_CTRL_FIFO_BIND_CHANNEL
+ *
+ * This structure is used to describe a channel that is to have
+ * it's bindable engines bound to those of other channels.
+ *
+ * hClient
+ *  This structure member contains the handle of the client object
+ *  that owns the channel object specified by hChannel.
+ *
+ * hChannel
+ *  This structure member contains the channel handle of the channel
+ *  object.
+ */
+
+typedef struct NV2080_CTRL_FIFO_BIND_CHANNEL {
+    NvHandle hClient;
+    NvHandle hChannel;
+} NV2080_CTRL_FIFO_BIND_CHANNEL;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_BIND_ENGINES
+ *
+ * This control call is now deprecated.
+ * This command can be used to bind different video engines on G8X from separate
+ * channels together for operations such as idling.  The set of bindable engines
+ * includes the NV2080_ENGINE_TYPE_BSP, NV2080_ENGINE_TYPE_VP and
+ * NV2080_ENGINE_TYPE_PPP engines.
+ *
+ * bindChannelCount
+ *  This parameter specifies the number of channels to bind together.  This
+ *  parameter cannot exceed NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS.
+ *
+ * bindChannels
+ *  The parameter specifies the array of channels to bind together.  The first
+ *  bindChannelCount entries are used in the bind channel operation.
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_INVALID_DEVICE
+ *  NV_ERR_INVALID_CHANNEL
+ *  NV_ERR_INVALID_ARGUMENT
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS (16)
+
+#define NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS {
+    NvU32                         bindChannelCount;
+    NV2080_CTRL_FIFO_BIND_CHANNEL bindChannels[NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS];
+} NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS;
+
+#define NV2080_CTRL_CMD_FIFO_BIND_ENGINES          (0x20801103) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES
+ *
+ * This command is used for a client to setup specialized custom operational
+ * properties that may be specific to an environment, or properties that
+ * should be set generally but are not for reasons of backward compatibility
+ * with previous chip generations
+ *
+ *  flags
+ *   This field specifies the operational properties to be applied
+ *
+ * Possible return status values returned are
+ *   NV_OK
+ *   NV_ERR_INVALID_CHANNEL
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES (0x20801104) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS {
+    NvU32 flags;
+} NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS;
+
+#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE                 0:0
+#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE (0x00000000)
+#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE  (0x00000001)
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT
+ *
+ * This command returns the maximum number of physical channels available for
+ * allocation on the current GPU.  This may be less than or equal to the total
+ * number of channels supported by the current hardware.
+ *
+ * physChannelCount
+ *   This output parameter contains the maximum physical channel count.
+ *
+ *   physChannelCountInUse
+ *     This output parameter contains the number of physical channels in use
+ *
+ * Possible return status values returned are
+ *   NV_OK
+ *
+ */
+#define NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT                                 (0x20801108) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS {
+    NvU32 physChannelCount;
+    NvU32 physChannelCountInUse;
+} NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS;
+
+/*
+ * NV2080_CTRL_FIFO_INFO
+ *
+ * This structure represents a single 32bit fifo engine value.  Clients
+ * request a particular FIFO engine value by specifying a unique fifo
+ * information index.
+ *
+ * Legal fifo information index values are:
+ *   NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL
+ *     This index can be used to request the amount of instance space
+ *     in kilobytes reserved by the fifo engine.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS
+ *     This index can be used to query the maximum number of channel groups
+ *     that can be allocated on the GPU.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP
+ *     This index can be used to query the maximum number of channels that can
+ *    be allocated in a single channel group.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP
+ *     This index can be used to query the maximum number of subcontext that can
+ *     be allocated in a single channel group.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET
+ *     This index can be used to query the starting offset of the RM
+ *     pre-allocated USERD range in BAR1. This index query is honored only
+ *     on Legacy-vGPU host RM.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE
+ *     This index can be used to query the default timeslice value
+ *     (microseconds) used for a channel or channel group.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE
+ *     This index can be used to query the number of channel groups that are
+ *     already allocated on the GPU.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED
+ *     This index can be used to check if per runlist channel ram is supported, and
+ *     to query the supported number of channels per runlist.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE
+ *     This index can be used to get max channel groups supported per engine/runlist.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE
+ *     This index can be used too get channel groups currently in use per engine/runlist.
+ *
+ */
+typedef struct NV2080_CTRL_FIFO_INFO {
+    NvU32 index;
+    NvU32 data;
+} NV2080_CTRL_FIFO_INFO;
+
+/* valid fifo info index values */
+#define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL                       (0x000000000)
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS                   (0x000000001)
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP               (0x000000002)
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP             (0x000000003)
+#define NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET              (0x000000004)
+#define NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE            (0x000000005)
+#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE                (0x000000006)
+#define NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED (0x000000007)
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE        (0x000000008)
+#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE     (0x000000009)
+
+
+/* set INDEX_MAX to greatest possible index value */
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX                                  NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE
+
+#define NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT                     (12)
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_INFO
+ *
+ * This command returns fifo engine information for the associated GPU.
+ * Requests to retrieve fifo information use an array of one or more
+ * NV2080_CTRL_FIFO_INFO structures.
+ *
+ *   fifoInfoTblSize
+ *     This field specifies the number of valid entries in the fifoInfoList
+ *     array.  This value cannot exceed NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES.
+ *   fifoInfoTbl
+ *     This parameter contains the client's fifo info table into
+ *     which the fifo info values will be transferred by the RM.
+ *     The fifo info table is an array of NV2080_CTRL_FIFO_INFO structures.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FIFO_GET_INFO                                    (0x20801109) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum number of NV2080_CTRL_FIFO_INFO entries per request */
+#define NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES                            (256)
+
+#define NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_FIFO_GET_INFO_PARAMS {
+    NvU32                 fifoInfoTblSize;
+    /*
+     * C form:
+     * NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES];
+     */
+    NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES];
+    NvU32                 engineType;
+} NV2080_CTRL_FIFO_GET_INFO_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL
+ *
+ * This command removes the specified channel from the associated GPU's runlist
+ * and then initiates RC recovery.  If the channel is active it will first be preempted.
+ *   hChannel
+ *     The handle to the channel to be preempted.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_CHANNEL
+ */
+#define NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL (0x2080110a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS {
+    NvHandle hChannel;
+} NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS
+ *
+ * This command will disable or enable scheduling of channels described in the
+ * list provided. Whether or not the channels are also preempted off the GPU
+ * can be controlled by bOnlyDisableScheduling. By default channels are preempted
+ * off the GPU.
+ *
+ *  bDisable
+ *      This value determines whether to disable or
+ *      enable the set of channels.
+ *  numChannels
+ *      The number of channels to be stopped.
+ *  bOnlyDisableScheduling
+ *      When false and bDisable=NV_TRUE,the call will ensure none of the listed
+ *      channels are running in hardware and will not run until a call with
+ *      bDisable=NV_FALSE is made. When true and bDisable=NV_TRUE, the control
+ *      call will ensure that none of the listed channels can be scheduled on the
+ *      GPU until a call with bDisable=NV_FALSE is made, but will not remove any
+ *      of the listed channels from hardware if they are currently running. When
+ *      bDisable=NV_FALSE this field is ignored.
+ *  bRewindGpPut
+ *      If a channel is being disabled and bRewindGpPut=NV_TRUE, the channel's RAMFC
+ *      will be updated so that GP_PUT is reset to the value of GP_GET.
+ *  hClientList
+ *      An array of NvU32 listing the client handles
+ *  hChannelList
+ *      An array of NvU32 listing the channel handles
+ *      to be stopped.
+ *  pRunlistPreemptEvent
+ *      KEVENT handle for Async HW runlist preemption (unused on preMaxwell)
+ *      When NULL, will revert to synchronous preemption with spinloop
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NVOS_INVALID_STATE
+ */
+
+#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS         (0x2080110b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES (64)
+
+#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS {
+    NvBool   bDisable;
+    NvU32    numChannels;
+    NvBool   bOnlyDisableScheduling;
+    NvBool   bRewindGpPut;
+    NV_DECLARE_ALIGNED(NvP64 pRunlistPreemptEvent, 8);
+    // C form:  NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]
+    NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES];
+    // C form:  NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]
+    NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES];
+} NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS;
+
+#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE         (0x00000000)
+#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE          (0x00000001)
+#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE (0x00000000)
+#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE  (0x00000001)
+
+/*
+ * NV2080_CTRL_FIFO_MEM_INFO
+ *
+ * This structure describes the details of a block of memory. It consists
+ * of the following fields
+ *
+ * aperture
+ *   One of the NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_* values
+ * base
+ *   Physical base address of the memory
+ * size
+ *   Size in bytes of the memory
+*/
+typedef struct NV2080_CTRL_FIFO_MEM_INFO {
+    NvU32 aperture;
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+} NV2080_CTRL_FIFO_MEM_INFO;
+
+/*
+ * NV2080_CTRL_FIFO_CHANNEL_MEM_INFO
+ *
+ * This structure describes the details of the instance memory, ramfc
+ * and method buffers a channel. It consists of the following fields
+ *
+ *   inst
+ *     Structure describing the details of instance memory
+ *   ramfc
+ *     Structure describing the details of ramfc
+ *   methodBuf
+ *     Array of structures describing the details of method buffers
+ *   methodBufCount
+ *     Number of method buffers(one per runqueue)
+ */
+
+// max runqueues
+#define NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT 0x2
+
+typedef struct NV2080_CTRL_FIFO_CHANNEL_MEM_INFO {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO inst, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO ramfc, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO methodBuf[NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT], 8);
+    NvU32 methodBufCount;
+} NV2080_CTRL_FIFO_CHANNEL_MEM_INFO;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM
+ *
+ * This command returns the memory aperture, physical base address and the
+ * size of each of the instance memory, cache1 and ramfc of a channel.
+ *
+ *   hChannel
+ *     The handle to the channel for which the memory information is desired.
+ *   chMemInfo
+ *     A NV2080_CTRL_FIFO_CHANNEL_MEM_INFO structure
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_CHANNEL
+*/
+
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO (0x2080110c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS {
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_CHANNEL_MEM_INFO chMemInfo, 8);
+} NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID     0x00000000
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM      0x00000001
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH  0x00000002
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH 0x00000003
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION
+ *
+ *    This command determines the location (vidmem/sysmem)
+ *    and attribute (cached/uncached/write combined) of memory where USERD is located.
+ *
+ *   aperture
+ *     One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_* values.
+ *
+ *   attribute
+ *     One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_* values.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_POINTER
+*/
+
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION                   (0x2080110d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS {
+    NvU32 aperture;
+    NvU32 attribute;
+} NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS;
+
+// support for CPU coherent vidmem (VIDMEM_NVILINK_COH) is not yet available in RM
+
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM         0x00000000
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM         0x00000001
+
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED        0x00000000
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED      0X00000001
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002
+
+
+
+/*
+ *  NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE
+ *
+ *  This command retrieves entries from the SW encoded GPU device info table
+ *  from Host RM.
+ *
+ *  Parameters:
+ *
+ *    baseIndex [in]
+ *      The starting index to read from the devinfo table. Must be a multiple of
+ *      MAX_ENTRIES.
+ *
+ *    entries [out]
+ *      A buffer to store up to MAX_ENTRIES entries of the devinfo table.
+ *
+ *    numEntries [out]
+ *      Number of populated entries in the provided buffer.
+ *
+ *    bMore [out]
+ *      A boolean flag indicating whether more valid entries are available to be
+ *      read. A value of NV_TRUE indicates that a further call to this control
+ *      with baseIndex incremented by MAX_ENTRIES will yield further valid data.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ */
+#define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE                 (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES         256
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES         32
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES   16
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA    2
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16
+
+/*
+ * NV2080_CTRL_FIFO_DEVICE_ENTRY
+ *
+ * This structure contains the engine, engine name and
+ * push buffers information of FIFO device entry. It consists of the following fields
+ *
+ *   engineData
+ *     Type of the engine
+ *   pbdmaIds
+ *     List of pbdma ids associated with engine
+ *   pbdmaFaultIds
+ *     List of pbdma fault ids associated with engine
+ *   numPbdmas
+ *     Number of pbdmas
+ *   engineName
+ *     Name of the engine
+ */
+typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY {
+    NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES];
+    NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
+    NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
+    NvU32 numPbdmas;
+    char  engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN];
+} NV2080_CTRL_FIFO_DEVICE_ENTRY;
+
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS {
+    NvU32                         baseIndex;
+    NvU32                         numEntries;
+    NvBool                        bMore;
+    // C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
+    NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
+} NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT
+ *
+ *  This command clears the ENGINE or PBDMA FAULTED bit and reschedules the faulted channel
+ *  by ringing channel's doorbell
+ *
+ *  Parameters:
+ *
+ *    engineType [in]
+ *      The NV2080_ENGINE_TYPE of the engine to which the faulted
+ *      channel is bound. This may be a logical id for guest RM in
+ *      case of SMC.
+ *
+ *    vChid [in]
+ *      Virtual channel ID on which the fault occurred
+ *
+ *    faultType [in]
+ *      Whether fault was triggered by engine (_ENGINE_FAULTED) or PBDMA (_PBDMA_FAULTED)
+ *      The value specified must be one of the NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_* values
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_STATE
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT               (0x20801113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE 0x00000001
+#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA  0x00000002
+
+#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS {
+    NvU32 engineType;
+    NvU32 vChid;
+    NvU32 faultType;
+} NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY
+ *
+ * Allows clients to set the global scheduling policy for all runlists
+ * associated to the given subdevice.
+ *
+ * Currently, this is only supported for HW runlists.
+ *
+ * Since this is a global setting, only privileged clients will be allowed to
+ * set it. Regular clients will get NV_ERR_INSUFFICIENT_PERMISSIONS error.
+ *
+ * Once a certain scheduling policy is set, that policy cannot be changed to a
+ * different one unless all clients which set it have either restored the policy
+ * (using the corresponding restore flag) or died. Clients trying to set a
+ * policy while a different one is locked by another client will get a
+ * NV_ERR_INVALID_STATE error.
+ *
+ * The same client can set a scheduling policy and later change to another one
+ * only when no other clients have set the same policy. Such sequence will be
+ * equivalent to restoring the policy in between.
+ *
+ * For instance, the following sequence:
+ *
+ *      1. Set policy A
+ *      2. Set policy B
+ *
+ * is equivalent to:
+ *
+ *      1. Set policy A
+ *      2. Restore policy
+ *      3. Set policy B
+ *
+ * Parameters:
+ *
+ *   flags
+ *     This field specifies the operational properties to be applied:
+ *
+ *      - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE
+ *          Try to set the provided 'schedPolicy' scheduling policy. If the
+ *          operation succeeds, other clients will be prevented from setting a
+ *          different scheduling policy until all clients using it have either
+ *          restored it or died.
+ *
+ *      - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE
+ *          Let the scheduler know the client no longer requires the current
+ *          scheduling policy. This may or may not actually change the
+ *          scheduling policy, depending on how many other clients are also
+ *          using the current policy.
+ *
+ *          The 'schedPolicy' parameter is ignored when this flag is set.
+ *
+ *   schedPolicy
+ *     One of:
+ *
+ *      - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT
+ *          Set the default scheduling policy and prevent other clients from
+ *          changing it.
+ *
+ *      - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED
+ *          This scheduling policy will make channels to be scheduled according
+ *          to their interleave level. See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL
+ *          description for more details.
+ *      - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM
+ *          This scheduling policy will make channels to be scheduled according
+ *          to their interleave level per WDDM policy.
+ *          See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY                     (0x20801115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID" */
+
+/* schedPolicy values */
+#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT                     0x0
+#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED         0x1
+#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM    0x2
+
+/* SET_SCHED_POLICY flags */
+#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE        0:0
+#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE (0x00000000)
+#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE  (0x00000001)
+
+#define NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS {
+    NvU32 flags;
+    NvU32 schedPolicy;
+} NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO
+ *
+ *  This command updates the channel info params for an existing channel
+ *
+ *  Can be a deferred Api. The control call can be used for migrating a
+ *
+ *  channel to a new userd and gpfifo
+ *
+ *  Parameters:
+ *     [in] hClient  - Client handle
+ *     [in] hChannel - Channel handle
+ *     [in] hUserdMemory  - UserD handle
+ *     [in] gpFifoEntries - Number of Gpfifo Entries
+ *     [in] gpFifoOffset  - Gpfifo Virtual Offset
+ *     [in] userdOffset   - UserD offset
+ *
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_STATE
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO (0x20801116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS {
+    NvHandle hClient;
+    NvHandle hChannel;
+    NvHandle hUserdMemory;
+    NvU32    gpFifoEntries;
+    NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 userdOffset, 8);
+} NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS
+ *
+ * This command will disable or enable scheduling of all usermode channels.
+ *
+ *  bDisable
+ *      This value determines whether to disable or enable the usermode channels.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS (0x20801117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID (0x17U)
+
+typedef struct NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS {
+    NvBool bDisable;
+} NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB
+ *
+ * When a VF subcontext is marked as a zombie, host RM points its PDB to a dummy
+ * page allocated by guest RM in GPA space. This command provides the parameters
+ * of the guest RMs memory descriptor to be able to create a corresponding
+ * memory descriptor on the host RM. Host RM uses this to program the PDB of a
+ * zombie subcontext.
+ *
+ *  Parameters:
+ *  Input parameters to describe the memory descriptor
+ *     [in] base
+ *     [in] size
+ *     [in] addressSpace
+ *     [in] cacheAttrib
+ */
+#define NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB (0x20801118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32 addressSpace;
+    NvU32 cacheAttrib;
+} NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS
+ *
+ * Get's a bitmask of allocated channels. No guarantees are made about
+ * synchronization. A channel returned as allocated by this ctrl cmd might have
+ * already been destructed.
+ *
+ * Parameters:
+ * [in]     runlistId
+ * [in,out] bitMask   A 1 bit indicates that a channel with this index/id is
+ *                    allocated. This field is a multiple of 32 bits and each 32
+ *                    bit group must be accessed as a platform 32 bit int to
+ *                    correctly map channel IDs.
+ *
+ */
+#define NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS          (0x20801119) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID" */
+
+/*
+ * The maximum number than can be returned by
+ * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS
+ */
+#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS 4096
+
+#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS {
+    NvU32 runlistId;
+    NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32];
+} NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS;
+
+
+
+/* _ctrl2080fifo_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h
new file mode 100644
index 0000000..3fe89b9
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h
@@ -0,0 +1,208 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080fla.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX FLA control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_FLA_RANGE
+ *
+ * This command is used to initialize/destroy FLA VAS for a GPU.This is intended
+ * to be used by RM clients that manages the FLA VASpace range. The mode of the
+ * command is decided based on the parameter passed by the client.
+ *
+ *    base
+ *         This parameter specifies the base of the FLA VAS that needs to be allocated
+ *         for this GPU
+ *
+ *    size
+ *         This parameter specifies the size of the FLA VAS that needs to be allocated
+ *         for this GPU
+ *
+ *    mode
+ *         This parameter specifies the functionality of the command.
+ *           MODE_INITIALIZE
+ *             Setting this mode, will initialize the FLA VASpace for the gpu with
+ *             base and size passed as arguments. FLA VASpace will be owned by RM.
+ *             if the client calls the command more than once before destroying
+ *             the FLA VAS, then this command will verify the range exported before and
+ *             return success if it matches. If FLA is not supported for the platform,
+ *             will return NV_ERR_NOT_SUPPORTED.
+ *           MODE_DESTROY (deprecated)
+ *             This command is NOP.
+ *           MODE_HOST_MANAGED_VAS_INITIALIZE
+ *             This mode will initialize the FLA VASpace for the gpu with hVASpace
+ *             handle in addition to base and size arguments. FLA VASpace will be initiated 
+ *             and owned by guest RM. Used only in virtualization platforms by internal clients.
+ *           MODE_HOST_MANAGED_VAS_DESTROY
+ *              This mode will destroy the FLA VAS associated with the device. It will destruct
+ *              only the resources associated with host RM side. Used only in virtualization platforms
+ *              by internal clients.
+ *
+ *    hVASpace 
+ *         This paramete specifies the FLA VAspace that needs to be associated with 
+ *         device. This parameter takes effect only for internal client in virtualization
+ *         platforms. For any other platform and external clients, this parameter has no effect.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_IN_USE
+ *   NV_ERR_INVALID_OWNER
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_FLA_RANGE (0x20803501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_FLA_RANGE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32    mode;
+    NvHandle hVASpace;
+} NV2080_CTRL_FLA_RANGE_PARAMS;
+
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE 0x00000000
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE                         NVBIT(0)
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY                            NVBIT(1)
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE        NVBIT(2)
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY           NVBIT(3)
+
+
+/*
+ * NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK
+ *
+ * This command is used to (un)bind FLA Instance Memory Block(IMB) with MMU.
+ * This control call is created for vGPU platform, when a FLA VAS is created/destroyed
+ * by Guest RM. Guest RM doesn't have privilege to (un)bind the IMB with MMU, hence
+ * need to be RPC-ed to Host RM to (un)bind
+ * The mode of the command is decided based on the actionParam passed by the client.
+ *
+ *    imbPhysAddr
+ *         This parameter specifies the FLA Instance Memory Block PA to be programmed
+ *         to MMU. IMB address should be 4k aligned. This parameter is needed only
+ *         for ACTION_BIND.
+ *
+ *    addrSpace
+ *         This parameter specifies the address space of FLA Instance Memory Block. This
+ *         parmater is needed only for ACTION_BIND.
+ *         Available options are:
+ *           NV2080_CTRL_FLA_ADDRSPACE_SYSMEM
+ *               Clients need to use this address space if the IMB is located in sysmem
+ *           NV2080_CTRL_FLA_ADDRSPACE_FBMEM
+ *               Clients need to use this address space if the IMB is located in FB
+ *
+ *    actionParam
+ *         This parameter specifies the functionality of the command.
+ *           NV2080_CTRL_FLA_ACTION_BIND
+ *             Setting this type, will call busBindFla helper HAL
+ *           NV2080_CTRL_FLA_ACTION_UNBIND
+ *             Setting this type, will call busUnbindFla helper HAL
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ */
+typedef enum NV2080_CTRL_FLA_ADDRSPACE {
+    NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = 0,
+    NV2080_CTRL_FLA_ADDRSPACE_FBMEM = 1,
+} NV2080_CTRL_FLA_ADDRSPACE;
+
+typedef enum NV2080_CTRL_FLA_ACTION {
+    NV2080_CTRL_FLA_ACTION_BIND = 0,
+    NV2080_CTRL_FLA_ACTION_UNBIND = 1,
+} NV2080_CTRL_FLA_ACTION;
+
+#define NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK (0x20803502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 imbPhysAddr, 8);
+    NV2080_CTRL_FLA_ADDRSPACE addrSpace;
+    NV2080_CTRL_FLA_ACTION    flaAction;
+} NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_FLA_GET_RANGE
+ *
+ * This command is used to query the FLA base and size from plugin to return as static info to Guest RM. 
+ *
+ *    base
+ *         This parameter returns the base address of FLA range registered to the subdevice. 
+ *    size
+ *         This parameter returns the size of FLA range registered to the subdevice. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FLA_GET_RANGE (0x20803503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_FLA_GET_RANGE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+} NV2080_CTRL_FLA_GET_RANGE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS
+ *
+ * This command returns the total size and the free size of the fabric vaspace.
+ * Note: This returns the information for the FABRIC_VASPACE_A class.
+ *
+ *   totalSize[OUT]
+ *      - Total fabric vaspace.
+ *
+ *   freeSize [OUT]
+ *      - Available fabric vaspace.
+ *
+ * Possible status values returned are:
+ *
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS (0x20803504) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 freeSize, 8);
+} NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS;
+
+// _ctrl2080fla_h_
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
new file mode 100644
index 0000000..474f916
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
@@ -0,0 +1,444 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080flcn.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+
+//
+// XAPICHK/XAPI_TEST breaks on including "nvmisc.h". Workaround: don't include
+// the header in that case and just redefine the macros we need.
+//
+#include "nvmisc.h"
+/*
+ * Obsolete Falcon ID type. Use NV2080_ENGINE_TYPE_ instead
+ */
+#define FALCON_ID_PMU           (NV2080_ENGINE_TYPE_PMU)
+#define FALCON_ID_DPU           (NV2080_ENGINE_TYPE_DPU)
+#define FALCON_ID_SEC2          (NV2080_ENGINE_TYPE_SEC2)
+#define FALCON_ID_FBFLCN        (NV2080_ENGINE_TYPE_FBFLCN)
+
+/*
+ * NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE
+ *
+ * This command returns total heap size and free heap size of a falcon engine
+ *
+ *  flcnID
+ *    The falcon ID
+ *
+ *  heapSize
+ *    Total heap size in byte
+ *
+ *  heapFree
+ *    Total free heap size in byte
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_NOT_SUPPORTED
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_INVALID_OBJECT
+ */
+#define NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE (0x20803101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS {
+    NvU32 flcnID;
+    NvU32 heapSize;
+    NvU32 heapFree;
+} NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS;
+
+/*!
+ * @defgroup NVOS_INST_EVT Instrumentation event types.
+ * @{
+ */
+
+//! Reserved for uStreamer internal use.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE    0x00U
+
+//! RTOS CTXSW includes next taskID and number of ODP for previous task.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END          0x01U
+
+//! Begin of a HW IRQ.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN       0x02U
+
+//! End of a HW IRQ, before stack pinning etc is performed.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END         0x03U
+
+//! RTOS Timer tick slip. (Only for # tick processed > 1).
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK         0x04U
+
+//! Task start processing an event, includes taskId, eventType and unitId (optional).
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN   0x05U
+
+//! Task finished processing an event, incldues taskId.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END     0x06U
+
+//! Latency for inserting response into RM queue.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY   0x07U
+
+//! Special / multi-purpose event, see field definition below.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT 0x08U
+
+//! Unused, recycle
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0           0x09U
+
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END            0x0AU
+
+//! Begin/end for arbitrary block of code. The payload contains a sub-ID for each location profiled.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN      0x0BU
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END        0x0CU
+
+//! Queueing time for the most recent event.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY 0x0DU
+/*!@}*/
+
+#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID        0xFFU
+
+/*
+ * NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH
+ *
+ * Get the egine arch i.e FALCON, RISCV etc given the NV2080_ENGINE_TYPE_*.
+ *
+ */
+#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH              (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
+    //! The engine type, from NV2080_ENGINE_TYPE_*
+    NvU32 engine;
+
+    //! The engine architecture - FALCON or RISC-V
+    NvU32 engineArch;
+} NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS;
+
+/*!
+ * @defgroup Engine Arch types
+ * @{
+ */
+#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT                         0x0
+#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON                          0x1
+#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV                           0x2
+/*!@}*/
+
+
+/* ----------------------- uStreamer (INST v2) ------------------------------ */
+/*!
+ * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT uStreamer event fields.
+ *
+ * This is a binary-packed representation of uStreamer events. There are
+ * three main types of entry: Head, Payload, and Tail. COMM here is used
+ * when a field is shared among multiple event types.
+ *
+ * @{
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG                         31:31
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD                         30:30
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE                     29:29
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND                       28:28
+
+/*!
+ * Below DRF's need constants assigned to start and end so they can be represented in FINN properly
+ * This is because FINN v1 will not have the ability to represent DRF's and bit fields yet.
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT         (27)
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE           (20)
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID \
+    (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT) : \
+    (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE)
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT  (28)
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE    (24)
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT \
+    (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT) : \
+    (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE)
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH                        19:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD                        7:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT                23:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME                          29:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD                       30:0
+/*!@}*/
+
+
+/*!
+ * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_BREAKDOWN
+ *
+ * These DRFs define breakdown of the compact payload for various event IDs.
+ *
+ * @{
+ */
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID                               7:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON                               10:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD                          0x0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0                           0x1
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK                     0x2
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK                    0x3
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED                  0x4
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT                      23:11
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP                           23:0
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID                        7:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID                       15:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE                   23:16
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID                          7:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID                     15:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC                        15:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE          0xF0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID                       23:16
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT                          10U
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID                      7:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID                          23:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED             0x000000
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL      0x000001
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT                         6U
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID                                     11:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID                            0x000
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL                    0x001
+
+/*!@}*/
+
+
+/*!
+ * @defgroup NV2080_CTRL_FLCN_USTREAMER_FEATURE
+ *
+ * This defines all the features currently supported by uStreamer. For a new
+ * usecase of uStreamer, a feature should be defined here describing the usecase.
+ * This value should be unique for each queue.
+ *
+ * @{
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT                       0U
+#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON                        1U
+#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT                        2U
+/*!@}*/
+
+/*!
+ * @defgroup NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY
+ *
+ * This defines the DRF used for ustreamer queue policy
+ *
+ * @{
+ */
+
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH                   0:0
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED      0U
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED       1U
+
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH                   1:1
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED      0U
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED       1U
+
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH              2:2
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED 0U
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED  1U
+
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD              31:8
+
+/*!@}*/
+
+/*!
+ * The maximum number of compact event types, calculated from the number of bits
+ * in the event structure.
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT                 (0x20U) /* finn: Evaluated from "(1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE + 1))" */
+
+/*!
+ * The maximum number of event types, calculated from the number of bits in the
+ * event structure.
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES                         (0x120U) /* finn: Evaluated from "((1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE + 1)) + NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT)" */
+
+/*!
+ * The number of bytes required in the event mask to contain all event types.
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES                       (0x24U) /* finn: Evaluated from "((NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES + 7) / 8)" */
+
+/*!
+ * uStreamer Event Filter type, stored as a bitmask.
+ */
+typedef struct NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER {
+    NvU8 mask[NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES];
+} NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER;
+
+/*!
+ * NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO
+ * Get queue info for mapping / unmapping
+ */
+#define NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO (0x20803120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS {
+    //! The engine type, from NV2080_ENGINE_TYPE_*
+    NvU32 engine;
+
+    //!
+    // The page size of the requested queue in bytes.
+    //
+    NvU32 pageSize;
+
+    //! Offset of the queue buffer in FB.
+    NV_DECLARE_ALIGNED(NvUPtr offset, 8);
+
+    //!
+    // The size of the user-mapped instrumentation buffer. Measured in bytes.
+    //
+    NvU32 size;
+
+    //!
+    // The feature ID of the queue.
+    //
+    NvU8  queueFeatureId;
+} NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET/SET
+ *
+ * Get/set the event bitmask for the default queue.
+ */
+#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x22" */
+
+#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x23" */
+
+typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS {
+    //! The engine type, from NV2080_ENGINE_TYPE_*
+    NvU32                                   engine;
+
+    /*!
+     * The bitmask of which event types to log. An event type corresponding to
+     * a bit with a zero will be ignored at the log site, which prevents it
+     * from filling up the resident buffer in the PMU. In general, set this to
+     * only log the event types you actually want to use.
+     * Refer to NVOS_BM_* in nvos_utility.h for usage.
+     */
+    NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER eventFilter;
+
+    //! The queueId of the queue whose eventFilter we want to interact with
+    NvU8                                    queueId;
+} NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO
+ *
+ * This command provides the attributes of the falcon engine context buffer
+ *
+ *   hUserClient [IN]
+ *     This parameter specifies the client handle that owns this channel.
+ *   hChannel [IN]
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *   alignment
+ *     Specifies the alignment requirement for each context buffer
+ *   size
+ *     Aligned size of context buffer
+ *   bufferHandle
+ *     Opaque pointer to memdesc. Used by kernel clients for tracking purpose only.
+ *   pageCount
+ *     allocation size in the form of pageCount
+ *   physAddr
+ *     Physical address of the buffer first page
+ *   aperture
+ *     allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN
+ *   kind
+ *     PTE kind of this allocation.
+ *   pageSize
+ *     Page size of the buffer.
+ *   bIsContigous
+ *     States if physical allocation for this buffer is contiguous. PageSize will
+ *     have no meaning if this flag is set.
+ *   bDeviceDescendant
+ *     TRUE if the allocation is a constructed under a Device or Subdevice.
+ *   uuid
+ *     SHA1 UUID of the Device or Subdevice. Valid when bDeviceDescendant is TRUE.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO (0x20803124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS {
+    NvHandle hUserClient;
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 alignment, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8);
+    NV_DECLARE_ALIGNED(NvU64 pageCount, 8);
+    NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
+    NvU32    aperture;
+    NvU32    kind;
+    NvU32    pageSize;
+    NvBool   bIsContigous;
+    NvBool   bDeviceDescendant;
+    NvU8     uuid[16];
+} NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS;
+
+// Aperture flags
+#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN
+#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM
+#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM
+
+/*
+ * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE
+ *
+ * This command provides the size of the falcon engine context buffer
+ *
+ *   hChannel [IN]
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *   totalBufferSize [OUT]
+ *     This parameter returns the total context buffers size.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE (0x20803125) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS {
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8);
+} NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS;
+
+
+
+/* _ctrl2080flcn_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h
new file mode 100644
index 0000000..2af63e7
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080fuse.finn
+//
+
+
+
+/* _ctrl2080fuse_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h
new file mode 100644
index 0000000..41f9767
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h
@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080gpio.finn
+//
+
+
+
+/* _ctrl2080gpio_h_ */
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
new file mode 100644
index 0000000..0b97569
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
@@ -0,0 +1,4115 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080gpu.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080gr.h"
+#include "ctrl/ctrl0000/ctrl0000system.h"
+#include "nvcfg_sdk.h"
+#include "nvstatus.h"
+
+#define NV_GRID_LICENSE_INFO_MAX_LENGTH                     (128)
+
+/* License info strings for vGPU products */
+#define NV_GRID_LICENSE_FEATURE_VPC_EDITION                 "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
+#define NV_GRID_LICENSE_FEATURE_VAPPS_EDITION               "GRID-Virtual-Apps,3.0"
+#define NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
+#define NV_GRID_LICENSE_FEATURE_GAMING_EDITION              "GRID-vGaming,8.0"
+#define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION             "NVIDIA-vComputeServer,9.0;Quadro-Virtual-DWS,5.0"
+
+#define NV_GRID_LICENSED_PRODUCT_VWS     "NVIDIA RTX Virtual Workstation"
+#define NV_GRID_LICENSED_PRODUCT_GAMING  "NVIDIA Cloud Gaming"
+#define NV_GRID_LICENSED_PRODUCT_VPC     "NVIDIA Virtual PC"
+#define NV_GRID_LICENSED_PRODUCT_VAPPS   "NVIDIA Virtual Applications"
+#define NV_GRID_LICENSED_PRODUCT_COMPUTE "NVIDIA Virtual Compute Server"
+
+
+
+/* NV20_SUBDEVICE_XX gpu control commands and parameters */
+
+/* Valid feature values */
+#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS                     0:0
+#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_FALSE (0x00000000U)
+#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_TRUE  (0x00000001U)
+
+
+
+typedef struct NV2080_CTRL_GPU_INFO {
+    NvU32 index;
+    NvU32 data;
+} NV2080_CTRL_GPU_INFO;
+
+/* valid gpu info index values */
+
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT                  (0x00000004U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0                        (0x00000012U)
+#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1                        (0x00000013U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS                       (0x0000001fU)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD                        (0x00000022U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE           (0x00000025U)
+#define NV2080_CTRL_GPU_INFO_INDEX_IBMNPU_RELAXED_ORDERING             (0x00000026U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED          (0x00000027U)
+#define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED             (0x00000028U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT                      (0x00000029U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE                        (0x0000002aU)
+#define NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM     (0x0000002bU)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION                      (0x0000002cU)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY                  (0x0000002dU)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM             (0x0000002fU)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY                  (0x00000030U)
+#define NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE         (0x00000031U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED          (0x00000033U)
+#define NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED                     (0x00000034U)
+#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED               (0x00000035U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY            (0x00000036U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY            (0x00000037U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU                             (0x0000003cU)
+#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY                   (0x0000003dU)
+#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE                             (0x0000003eU)
+
+/* valid minor revision extended values */
+#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE                   (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P                      (0x00000001U)
+#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V                      (0x00000002U)
+#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV                     (0x00000003U)
+
+
+
+/* valid system memory access capability values */
+#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO                          (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES                         (0x00000001U)
+
+
+
+/* valid gemini board values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO                     (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES                    (0x00000001U)
+
+/* valid surprise removal values */
+#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO        (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES       (0x00000001U)
+
+/* valid relaxed ordering values */
+#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_DISABLED          (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_ENABLED           (0x00000001U)
+#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_UNSUPPORTED       (0xFFFFFFFFU)
+
+/* valid poison fuse capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO       (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES      (0x00000001U)
+
+/* valid nvswitch proxy detected values */
+#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO                (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES               (0x00000001U)
+
+/* valid NVSR GPU support info values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO                   (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES                  (0x00000001U)
+
+/* valid SMC mode values */
+#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED                  (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED                      (0x00000001U)
+#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED                     (0x00000002U)
+#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING               (0x00000003U)
+#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING              (0x00000004U)
+
+/* valid split VAS mode values */
+#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO        (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES       (0x00000001U)
+
+/* valid grid capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO               (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES              (0x00000001U)
+
+/* valid per runlist channel ram capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED    (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED     (0x00000001U)
+
+/* valid ATS capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO               (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES              (0x00000001U)
+
+/* valid Nvenc Session Stats reporting state values */
+#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED      (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED       (0x00000001U)
+#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED (0x00000002U)
+
+/* valid 4K PAGE isolation requirement values */
+#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO       (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES      (0x00000001U)
+
+/* valid display enabled values */
+#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO                        (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES                       (0x00000001U)
+
+/* valid mobile config enabled values */
+#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO            (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES           (0x00000001U)
+
+
+/* valid profiling capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED   (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED    (0x00000001U)
+
+/* valid debugging capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED   (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED    (0x00000001U)
+
+
+
+/* valid CMP (Crypto Mining Processor) SKU values */
+#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO                          (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES                         (0x00000001U)
+
+
+/* valid dma-buf suport values */
+#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO                (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES               (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_INFO
+ *
+ * This command returns gpu information for the associated GPU.  Requests
+ * to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO
+ * structures.
+ *
+ *   gpuInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     gpuInfoList.
+ *   gpuInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the gpu information is to be returned.
+ *     This buffer must be at least as big as gpuInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_GPU_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_GPU_GET_INFO                                   (0x20800101U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS {
+    NvU32 gpuInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8);
+} NV2080_CTRL_GPU_GET_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2" */
+
+typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS {
+    NvU32                gpuInfoListSize;
+    NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE];
+} NV2080_CTRL_GPU_GET_INFO_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_NAME_STRING
+ *
+ * This command returns the name of the GPU in string form in either ASCII
+ * or UNICODE format.
+ *
+ *   gpuNameStringFlags
+ *     This field specifies flags to use while creating the GPU name string.
+ *     Valid flags values:
+ *       NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII
+ *         The returned name string should be in standard ASCII format.
+ *       NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE
+ *         The returned name string should be in unicode format.
+ *   gpuNameString
+ *     This field contains the buffer into which the name string should be
+ *     returned.  The length of the returned string will be no more than
+ *     NV2080_CTRL_GPU_MAX_NAME_STRING_LENGTH bytes in size.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_GPU_GET_NAME_STRING                (0x20800110U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_GPU_MAX_NAME_STRING_LENGTH                  (0x0000040U)
+
+// This field is deprecated - 'gpuNameStringFlags' is now a simple scalar.
+// Field maintained (and extended from 0:0) for compile-time compatibility.
+#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE                    31:0
+
+/* valid gpu name string flags */
+#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII   (0x00000000U)
+#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE (0x00000001U)
+
+#define NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS {
+    NvU32 gpuNameStringFlags;
+    union {
+        NvU8  ascii[NV2080_GPU_MAX_NAME_STRING_LENGTH];
+        NvU16 unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
+    } gpuNameString;
+} NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING
+ *
+ * This command returns the short name of the GPU in ASCII string form.
+ *
+ *   gpuShortNameString
+ *     This field contains the buffer into which the short name string should
+ *     be returned.  The length of the returned string will be no more than
+ *     NV2080_MAX_NAME_STRING_LENGTH bytes in size.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING (0x20800111U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS {
+    NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
+} NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_POWER
+ *
+ * This command sets the power state for the GPU as a whole, various engines,
+ * or clocks.
+ *
+ *   target
+ *     One of NV2080_CTRL_GPU_SET_POWER_TARGET_*
+ *
+ *   newLevel
+ *     One of NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_*
+ *            NV2080_CTRL_GPU_SET_POWER_STATE_ENGINE_LEVEL_*
+ *            NV2080_CTRL_GPU_SET_POWER_STATE_CLOCK_LEVEL_*
+ *     depending on the target above.
+ *
+ *   oldLevel
+ *     Previous level as appropriate.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GPU_SET_POWER (0x20800112U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_GPU_SET_POWER_PARAMS {
+    NvU32 target;
+    NvU32 newLevel;
+    NvU32 oldLevel;
+} NV2080_CTRL_GPU_SET_POWER_PARAMS;
+
+
+
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0            (0x00000000U)
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1            (0x00000001U)
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2            (0x00000002U)
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3            (0x00000003U)
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4            (0x00000004U)
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7            (0x00000007U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_SDM
+ *
+ * This command returns the subdevice mask value for the associated subdevice.
+ * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction
+ * provided by the NV36_CHANNEL_DMA and newer channel dma classes.
+ *
+ *   subdeviceMask [out]
+ *     This field return the subdevice mask value.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_SDM                            (0x20800118U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_GPU_GET_SDM_PARAMS {
+    NvU32 subdeviceMask;
+} NV2080_CTRL_GPU_GET_SDM_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_SDM
+ *
+ * This command sets the subdevice instance and mask value for the associated subdevice.
+ * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction
+ * provided by the NV36_CHANNEL_DMA and newer channel dma classes.
+ * It must be called before the GPU HW is initialized otherwise
+ * NV_ERR_INVALID_STATE is being returned.
+ *
+ *   subdeviceMask [in]
+ *     This field configures the subdevice mask value for the GPU/Subdevice
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_DATA
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_SET_SDM (0x20800120U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_GPU_SET_SDM_PARAMS {
+    NvU32 subdeviceMask;
+} NV2080_CTRL_GPU_SET_SDM_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO
+ *
+ * This command returns the associated subdevices' simulation information.
+ *
+ *   type
+ *     This field returns the simulation type.
+ *     One of NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_*
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO (0x20800119U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS {
+    NvU32 type;
+} NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE          (0x00000000U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL   (0x00000001U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL   (0x00000002U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL        (0x00000003U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL           (0x00000004U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU           (0x00000005U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER (0x00000006U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA         (0x00000007U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL     (0x00000008U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL  (0x00000009U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN       (0xFFFFFFFFU)
+
+/*
+ * NV2080_CTRL_GPU_REG_OP
+ *
+ * This structure describes register operation information for use with
+ * the NV2080_CTRL_CMD_GPU_EXEC_REG_OPS command.  The structure describes
+ * a single register operation.  The operation can be a read or write and
+ * can involve either 32bits or 64bits of data.
+ *
+ * For 32bit read operations, the operation takes the following form:
+ *
+ *   regValueLo = read(bar0 + regOffset)
+ *   regValueHi = 0
+ *
+ * For 64bit read operations, the operation takes the following form:
+ *
+ *   regValueLo = read(bar0 + regOffset)
+ *   regValueHi = read(bar0 + regOffset + 4)
+ *
+ * For 32bit write operations, the operation takes the following form:
+ *
+ *   new = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo)
+ *   write(bar0 + regOffset, new)
+ *
+ * For 64bit write operations, the operation takes the following form:
+ *
+ *   new_lo = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo)
+ *   new_hi = ((read(bar0 + regOffset + 4) &  ~regAndNMaskHi) | regValueHi)
+ *   write(bar0 + regOffset, new_lo)
+ *   write(bar0 + regOffset + 4, new_hi)
+ *
+ * Details on the parameters follow:
+ *
+ *   regOp
+ *     This field specifies the operation to be applied to the register
+ *     specified by the regOffset parameter.  Valid values for this
+ *     parameter are:
+  *      NV2080_CTRL_GPU_REG_OP_READ_08
+ *         The register operation should be a 8bit global privileged register read.
+ *       NV2080_CTRL_GPU_REG_OP_WRITE_08
+ *         The register operation should be a 8bit global privileged register write.
+ *       NV2080_CTRL_GPU_REG_OP_READ_32
+ *         The register operation should be a 32bit register read.
+ *       NV2080_CTRL_GPU_REG_OP_WRITE_32
+ *         The register operation should be a 32bit register write.
+ *       NV2080_CTRL_GPU_REG_OP_READ_64
+ *         The register operation should be a 64bit register read.
+ *       NV2080_CTRL_GPU_REG_OP_WRITE_64
+ *         The register operation should be a 64bit register write.
+ *   regType
+ *     This field specifies the type of the register specified by the
+ *     regOffset parameter.  Valid values for this parameter are:
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL
+ *         The register is a global privileged register.  Read operations
+ *         return the current value from the associated global register.
+ *         Write operations for registers of this type take effect immediately.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX
+ *         The register is a graphics context register.  Read operations
+ *         return the current value from the associated global register.
+ *         Write operations are applied to all existing graphics engine
+ *         contexts.  Any newly created graphics engine contexts will also
+ *         be modified.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC
+ *         This is a graphics context TPC register group. Write operations are
+ *         applied to TPC group(s) specified by regGroupMask.
+ *         This field is ignored for read operations.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM
+ *         This is a graphics context SM register group that is inside TPC
+ *         group.  Write operations are applied to SM group(s) specified by
+ *         regGroupMask (TPC) and regSubGroupMask (SM). This field is ignored
+ *         for read operations.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP
+ *         This is a graphics context CROP register group. Write operations
+ *         are applied to registers specified by regGroupMask. This field is
+ *         ignored for read operations.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP
+ *         This is a graphics context ZROP register group. Write operations
+ *         are applied to registers specified by regGroupMask. This field is
+ *         ignored for read operations.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_FB
+ *         This is a fb register group. Write operations are applied to
+ *         registers specified by regGroupMask. This field is
+ *         ignored for read operations.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD
+ *         This is a graphics context QUAD register group. Operations
+ *         are applied to registers specified by regQuad value.
+ *   regQuad
+ *     This field specifies the quad to be accessed for register regOffsetwhen
+ *     the regType specified is NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD.
+ *   regGroupMask
+ *     This field specifies which registers inside an array should be updated.
+ *     This field is used when regType is one of below:
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_FB
+ *     When regGroupMask is used, the regOffset MUST be the first register in
+ *     an array.
+ *   regSubGroupMask
+ *     This field specifies which registers inside a group should be updated.
+ *     This field is used for updating SM registers when regType is:
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC
+ *     When regSubGroupMask is used, regOffset MUST be the first register in an
+ *     array AND also the first one in sub array.  regGroupMask specifies
+ *     TPC(X) and regSubGroupMask specifies SM_CTX_N(Y)
+ *   regStatus
+ *     This field returns the completion status for the associated register
+ *     operation in the form of a bitmask.  Possible status values for this
+ *     field are:
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS
+ *         This value indicates the operation completed successfully.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP
+ *         This bit value indicates that the regOp value is not valid.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE
+ *         This bit value indicates that the regType value is not valid.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET
+ *         This bit value indicates that the regOffset value is invalid.
+ *         The regOffset value must be within the legal BAR0 range for the
+ *         associated GPU and must target a supported register with a
+ *         supported operation.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OFFSET
+ *         This bit value indicates that the operation to the register
+ *         specified by the regOffset value is not supported for the
+ *         associated GPU.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK
+ *         This bit value indicates that the regTpcMask value is invalid.
+ *         The regTpcMask must be a subset of TPCs that are enabled on the
+ *         associated GPU.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS
+ *         The caller does not have access to the register at given offset
+ *   regOffset
+ *     This field specifies the register offset to access.  The specified
+ *     offset must be a valid BAR0 offset for the associated GPU.
+ *   regValueLo
+ *     This field contains the low 32bits of the register value.
+ *     For read operations, this value returns the current value of the
+ *     register specified by regOffset.  For write operations, this field
+ *     specifies the logical OR value applied to the current value
+ *     contained in the register specified by regOffset.
+ *   regValueHi
+ *     This field contains the high 32bits of the register value.
+ *     For read operations, this value returns the current value of the
+ *     register specified by regOffset + 4.  For write operations, this field
+ *     specifies the logical OR value applied to the current value
+ *     contained in the register specified by regOffset + 4.
+ *   regAndNMaskLo
+ *     This field contains the mask used to clear a desired field from
+ *     the current value contained in the register specified by regOffsetLo.
+ *     This field is negated and ANDed to this current register value.
+ *     This field is only used for write operations.  This field is ignored
+ *     for read operations.
+ *   regAndNMaskHi
+ *     This field contains the mask used to clear a desired field from
+ *     the current value contained in the register specified by regOffsetHi.
+ *     This field is negated and ANDed to this current register value.
+ *     This field is only used for write operations.  This field is ignored
+ *     for read operations.
+ */
+typedef struct NV2080_CTRL_GPU_REG_OP {
+    NvU8  regOp;
+    NvU8  regType;
+    NvU8  regStatus;
+    NvU8  regQuad;
+    NvU32 regGroupMask;
+    NvU32 regSubGroupMask;
+    NvU32 regOffset;
+    NvU32 regValueHi;
+    NvU32 regValueLo;
+    NvU32 regAndNMaskHi;
+    NvU32 regAndNMaskLo;
+} NV2080_CTRL_GPU_REG_OP;
+
+/* valid regOp values */
+#define NV2080_CTRL_GPU_REG_OP_READ_32               (0x00000000U)
+#define NV2080_CTRL_GPU_REG_OP_WRITE_32              (0x00000001U)
+#define NV2080_CTRL_GPU_REG_OP_READ_64               (0x00000002U)
+#define NV2080_CTRL_GPU_REG_OP_WRITE_64              (0x00000003U)
+#define NV2080_CTRL_GPU_REG_OP_READ_08               (0x00000004U)
+#define NV2080_CTRL_GPU_REG_OP_WRITE_08              (0x00000005U)
+
+/* valid regType values */
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL           (0x00000000U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX           (0x00000001U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC       (0x00000002U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM        (0x00000004U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP      (0x00000008U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP      (0x00000010U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_FB               (0x00000020U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD      (0x00000040U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE           (0x00000080U)
+
+/* valid regStatus values (note: NvU8 ie, 1 byte) */
+#define NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS        (0x00U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP     (0x01U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE   (0x02U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET (0x04U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x08U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK   (0x10U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS       (0x20U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS
+ *
+ * This command is used to submit a buffer containing one or more
+ * NV2080_CTRL_GPU_REG_OP structures for processing.  Each entry in the
+ * buffer specifies a single read or write operation.  Each entry is checked
+ * for validity in an initial pass over the buffer with the results for
+ * each operation stored in the corresponding regStatus field. Unless
+ * bNonTransactional flag is set to true, if any invalid entries are found
+ * during this initial pass then none of the operations are executed. Entries
+ * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL
+ * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries.
+ *
+ *   hClientTarget
+ *     This parameter specifies the handle of the client that owns the channel
+ *     specified by hChannelTarget. If this parameter is set to 0 then the set
+ *     of channel-specific register operations are applied to all current and
+ *     future channels.
+ *   hChannelTarget
+ *     This parameter specifies the handle of the target channel (or channel
+ *     group) object instance to which channel-specific register operations are
+ *     to be directed. If hClientTarget is set to 0 then this parameter must
+ *     also be set to 0.
+ *   bNonTransactional
+ *     This field specifies if command is non-transactional i.e. if set to
+ *     true, all the valid operations will be executed.
+ *   reserved00
+ *     This parameter is reserved for future use.  It should be initialized to
+ *     zero for correct operation.
+ *   regOpCount
+ *     This field specifies the number of entries on the caller's regOps
+ *     list.
+ *   regOps
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer from which the desired register information is to be
+ *     retrieved.  This buffer must be at least as big as regInfoCount
+ *     multiplied by the size of the NV2080_CTRL_GPU_REG_OP structure.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine. When SMC is enabled, this
+ *     is a mandatory parameter.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS             (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x22" */
+
+typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS {
+    NvHandle hClientTarget;
+    NvHandle hChannelTarget;
+    NvU32    bNonTransactional;
+    NvU32    reserved00[2];
+    NvU32    regOpCount;
+    NV_DECLARE_ALIGNED(NvP64 regOps, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINES
+ *
+ * Returns a list of supported engine types along with the number of instances
+ * of each type. Querying with engineList NULL returns engineCount.
+ *
+ *   engineCount
+ *     This field specifies the number of entries on the caller's engineList
+ *     field.
+ *   engineList
+ *     This field is a pointer to a buffer of NvU32 values representing the
+ *     set of engines supported by the associated subdevice.  Refer to cl2080.h
+ *     for the complete set of supported engine types.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ENGINES (0x20800123U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS {
+    NvU32 engineCount;
+    NV_DECLARE_ALIGNED(NvP64 engineList, 8);
+} NV2080_CTRL_GPU_GET_ENGINES_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */
+
+/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
+#define NV2080_GPU_MAX_ENGINES_LIST_SIZE   0x3EU
+
+#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS {
+    NvU32 engineCount;
+    NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+} NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST
+ *
+ * Returns a list of classes supported by a given engine type.
+ *
+ *   engineType
+ *     This field specifies the engine type being queried.
+ *     NV2080_CTRL_ENGINE_TYPE_ALLENGINES will return  classes
+ *     supported by all engines.
+ *
+ *   numClasses
+ *     This field specifies the number of classes supported by
+ *     engineType.
+ *
+ *   classList
+ *     This field is an array containing the list of supported
+ *     classes. Is of type (NvU32*)
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST (0x20800124U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS {
+    NvU32 engineType;
+    NvU32 numClasses;
+    NV_DECLARE_ALIGNED(NvP64 classList, 8);
+} NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO
+ *
+ * This command returns the fault properties of the specified engine type.
+ *
+ *   engineType
+ *     Input parameter.
+ *     This field specifies the engine type being queried.
+ *     Engine type is specified using the NV2080_ENGINE_TYPE_* defines in cl2080.h.
+ *     The list of engines supported by a chip can be got using the
+ *     NV2080_CTRL_CMD_GPU_GET_ENGINES ctrl call.
+ *
+ *   mmuFaultId
+ *     Output parameter.
+ *     This field returns the MMU fault ID for the specified engine.
+ *     If the engine supports subcontext, this field provides the base fault id.
+ *
+ *   bSubcontextSupported
+ *     Output parameter.
+ *     Returns TRUE if subcontext faulting is supported by the engine.
+ *     Engine that support subcontext use fault IDs in the range [mmuFaultId, mmuFaultId + maxSubCtx).
+ *     "maxSubctx" can be found using the NV2080_CTRL_FIFO_INFO ctrl call with
+ *     NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP as the index.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO (0x20800125U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS {
+    NvU32  engineType;
+    NvU32  mmuFaultId;
+    NvBool bSubcontextSupported;
+} NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_MODE
+ *
+ * This command is used to detect the mode of the GPU associated with the
+ * subdevice.
+ *
+ *   mode
+ *     This parameter returns the current mode of GPU.  Legal values for
+ *     this parameter include:
+ *       NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE
+ *         The GPU is currently operating in graphics mode.
+ *       NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE
+ *         The GPU is currently operating in compute mode.
+ *       NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE
+ *         The current mode of the GPU could not be determined.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_GPU_QUERY_MODE           (0x20800128U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID" */
+
+/* valid mode parameter values */
+#define NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE  (0x00000000U)
+#define NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE (0x00000001U)
+#define NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE  (0x00000002U)
+
+#define NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID (0x28U)
+
+typedef struct NV2080_CTRL_GPU_QUERY_MODE_PARAMS {
+    NvU32 mode;
+} NV2080_CTRL_GPU_QUERY_MODE_PARAMS;
+
+
+
+/*!
+ * NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY
+ * Data block describing a virtual context buffer to be promoted
+ *
+ *  gpuPhysAddr [IN]
+ *    GPU Physical Address for the buffer
+ *  gpuVirtAddr [IN]
+ *    GPU Virtual Address for the buffer
+ *   size[IN]
+ *    Size of this virtual context buffer
+ *  physAttr [IN]
+ *    Physical memory attributes (aperture, cacheable)
+ *  bufferId [IN]
+ *    Virtual context buffer type, data type NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_*
+ *  bInitialize [IN]
+ *   Flag indicating that this virtual context buffer should be initialized prior to promotion.
+ *   The client must clear (memset) the buffer to 0x0 prior to initialization.
+ *   Following buffers need initialization:
+ *    1. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN
+ *    2. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH
+ *    3. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP
+ *    4. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP
+ *  bNonmapped [IN]
+ *   Flag indicating that the virtual address is not to be promoted with this
+ *   call. It is illegal to set this flag and not set bInitialize.
+ */
+typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY {
+    NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32 physAttr;
+    NvU16 bufferId;
+    NvU8  bInitialize;
+    NvU8  bNonmapped;
+} NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY;
+
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN                         0U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM                           1U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH                        2U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB             3U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL                     4U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB                 5U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL                6U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL                    7U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK                8U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT                   9U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP              10U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP       12U
+
+#define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES                        16U
+
+/*
+ * NV2080_CTRL_CMD_GPU_PROMOTE_CTX
+ *
+ * This command is used to promote a Virtual Context
+ *
+ *   engineType
+ *     Engine Virtual Context is for
+ *   hClient
+ *     Client Handle for hVirtMemory
+ *   ChID
+ *     Hw Channel -- Actually hw index for channel (deprecated)
+ *   hChanClient
+ *     The client handle for hObject
+ *   hObject
+ *     Passed in object handle for either a single channel or a channel group
+ *   hVirtMemory
+ *     Virtual Address handle to map Virtual Context to
+ *   virtAddress
+ *     Virtual Address to map Virtual Context to
+ *   size
+ *     size of the Virtual Context
+ *   entryCount
+ *     Number of valid entries in the promotion entry list
+ *   promoteEntry
+ *     List of context buffer entries to issue promotions for.
+ *
+ *   When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be
+ *   specified, the code cases based on hVirtMemory(NULL vs non-NULL) so
+ *   if both are specified, hVirtMemory has precedence.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED    - The Class does not support version info retrieval
+ *   NV_ERR_INVALID_DEVICE   - The Class/Device is not yet ready to provide this info.
+ *   NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified.
+ */
+#define NV2080_CTRL_CMD_GPU_PROMOTE_CTX                                    (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID (0x2BU)
+
+typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS {
+    NvU32    engineType;
+    NvHandle hClient;
+    NvU32    ChID;
+    NvHandle hChanClient;
+    NvHandle hObject;
+    NvHandle hVirtMemory;
+    NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32    entryCount;
+    // C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8);
+} NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS;
+typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_EVICT_CTX
+ *
+ * This command is used to evict a Virtual Context
+ *
+ *   engineType
+ *     Engine Virtual Context is for
+ *   hClient
+ *     Client Handle
+ *   ChID
+ *     Hw Channel -- Actually hw index for channel (deprecated)
+ *   hChanClient
+ *     Client handle for hObject
+ *   hObject
+ *     Passed in object handle for either a single channel or a channel group
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED    - The Class does not support version info retrieval
+ *   NV_ERR_INVALID_DEVICE   - The Class/Device is not yet ready to provide this info.
+ *   NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified.
+ */
+#define NV2080_CTRL_CMD_GPU_EVICT_CTX (0x2080012cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID (0x2CU)
+
+typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS {
+    NvU32    engineType;
+    NvHandle hClient;
+    NvU32    ChID;
+    NvHandle hChanClient;
+    NvHandle hObject;
+} NV2080_CTRL_GPU_EVICT_CTX_PARAMS;
+typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS *PNV2080_CTRL_GPU_EVICT_CTX_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_INITIALIZE_CTX
+ *
+ * This command is used to initialize a Virtual Context. The ctx buffer must be
+ * cleared (zerod) by the caller prior to invoking this method.
+ *
+ *   engineType
+ *     Engine Virtual Context is for
+ *   hClient
+ *     Client Handle for the hVirtMemory
+ *   ChID
+ *      Hw channel -- Actually channel index (deprecated)
+ *   hChanClient
+ *     The client handle for hObject
+ *   hObject
+ *     Passed in object handle for either a single channel or a channel group
+ *   hVirtMemory
+ *     Virtual Address where to map Virtual Context to
+ *   physAddress
+ *     Physical offset in FB to use as Virtual Context
+ *   physAttr
+ *     Physical memory attributes
+ *   hDmaHandle
+ *     Dma Handle when using discontiguous context buffers
+ *   index
+ *     Start offset in Virtual DMA Context
+ *   size
+ *     Size of the Virtual Context
+ *
+ *   Only hVirtMemory or size should be specified, the code cases based on hVirtMemory
+ *   (NULL vs non-NULL) so if both are specified, hVirtMemory has precedence.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED    - The Class does not support version info retrieval
+ *   NV_ERR_INVALID_DEVICE   - The Class/Device is not yet ready to provide this info.
+ *   NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified.
+ */
+#define NV2080_CTRL_CMD_GPU_INITIALIZE_CTX (0x2080012dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID (0x2DU)
+
+typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS {
+    NvU32    engineType;
+    NvHandle hClient;
+    NvU32    ChID;
+    NvHandle hChanClient;
+    NvHandle hObject;
+    NvHandle hVirtMemory;
+    NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
+    NvU32    physAttr;
+    NvHandle hDmaHandle;
+    NvU32    index;
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+} NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS;
+typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS;
+
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE              1:0
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM   (0x00000000U)
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS  (0x00000001U)
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS (0x00000002U)
+
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE         2:2
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES (0x00000000U)
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO  (0x00000001U)
+
+/*
+ * NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX - Tells RM Whether this Ctx buffer needs to
+ * do a full initialization (Load the golden image). When a context is promoted on a different
+ * channel than it was originally inited, the client can use this flag to tell RM
+ * that this is an already inited Context. In such cases RM will update the internal state
+ * to update the context address and state variables.
+ */
+
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX              3:3
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO   (0x00000000U)
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES  (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_CPU_QUERY_ECC_INTR
+ * Queries the top level ECC PMC PRI register
+ * TODO remove these parameters, tracked in bug #1975721
+ */
+#define NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR               (0x2080012eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2E" */
+
+typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS {
+    NvU32 eccIntrStatus;
+} NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS
+ *
+ * This command is used to query the ECC status of a GPU by a subdevice
+ * handle.  Please see the NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS
+ * data structure description below for details on the data reported
+ * per hardware unit.
+ *
+ *   units
+ *     Array of structures used to describe per-unit state
+ *
+ *   flags
+ *     See interface flag definitions below.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+
+
+#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS                   (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */
+
+
+#define NV2080_CTRL_GPU_ECC_UNIT_COUNT                         (0x00000018U)
+
+
+
+// Deprecated do not use
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE             0:0
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED   (0x00000000U)
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW        (0x00000001U)
+
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE         0U
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE          1U
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE 2U
+
+/*
+ * NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS
+ *
+ * This structure represents the exception status of a class of per-unit
+ * exceptions
+ *
+ *   count
+ *     number of exceptions that have occurred since boot
+ */
+typedef struct NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS {
+    NV_DECLARE_ALIGNED(NvU64 count, 8);
+} NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS;
+
+/*
+ * NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS
+ *
+ * This structure represents the per-unit ECC exception status
+ *
+ *   enabled
+ *     ECC enabled yes/no for this unit
+ *   scrubComplete
+ *     Scrub has completed yes/no. A scrub is performed for some units to ensure
+ *     the checkbits are consistent with the protected data.
+ *   supported
+ *     Whether HW supports ECC in this unit for this GPU
+ *   dbe
+ *     Double bit error (DBE) status. The value returned reflects a counter
+ *     that is monotonic, but can be reset by clients.
+ *   dbeNonResettable (deprecated do not use)
+ *     Double bit error (DBE) status, not client resettable.
+ *   sbe
+ *     Single bit error (SBE) status. The value returned reflects a counter
+ *     that is monotonic, but can be reset by clients.
+ *   sbeNonResettable (deprecated do not use)
+ *     Single bit error (SBE) status, not client resettable.
+ *
+ */
+typedef struct NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS {
+    NvBool enabled;
+    NvBool scrubComplete;
+    NvBool supported;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbe, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbeNonResettable, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbe, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbeNonResettable, 8);
+} NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS;
+
+/*
+ * NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
+ *
+ * This structure returns ECC exception status and GPU Fatal Poison for all units
+ *
+ *   units
+ *     This structure represents ECC exception status for all Units.
+ *   bFatalPoisonError
+ *     Whether GPU Fatal poison error occurred in this GPU. This will be set for Ampere_and_later
+ *   uncorrectableError
+ *     Indicates whether any uncorrectable GR ECC errors have occurred. When
+ *     SMC is enabled, uncorrectableError is only valid when the client is
+ *     subscribed to a partition. Check QUERY_ECC_STATUS_UNC_ERR_*
+ *   flags
+ *     Flags passed by caller. Refer  NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_* for details.
+ *   grRouteInfo
+ *     SMC partition information. This input is only valid when SMC is
+ *     enabled on Ampere_and_later.
+ *
+ */
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID (0x2FU)
+
+typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS units[NV2080_CTRL_GPU_ECC_UNIT_COUNT], 8);
+    NvBool bFatalPoisonError;
+    NvU8   uncorrectableError;
+    NvU32  flags;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES
+ *
+ * This command sets the compute mode rules for the associated subdevice.  The
+ * default mode is equivalent to NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE.  This
+ * command is available to clients with administrator privileges only.  An
+ * attempt to use this command by a client without administrator privileged
+ * results in the return of an NV_ERR_INSUFFICIENT_PERMISSIONS status.
+ *
+ *   rules
+ *     This parameter is used to specify the rules that govern the GPU with
+ *     respect to NV50_COMPUTE objects. Legal values for this parameter include:
+ *
+ *       NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE
+ *         This mode indicate that no special restrictions apply to the
+ *         allocation of NV50_COMPUTE objects.
+ *
+ *       NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE
+ *         This mode means that only one instance of NV50_COMPUTE will be
+ *         allowed at a time. This restriction is enforced at each subsequent
+ *         NV50_COMPUTE allocation attempt. Setting this mode will not affect
+ *         any existing compute programs that may be running. For example,
+ *         if this mode is set while three compute programs are running, then
+ *         all of those programs will be allowed to continue running. However,
+ *         until they all finish running, no new NV50_COMPUTE objects may be
+ *         allocated. User-mode clients should treat this as restricting access
+ *         to a NV50_COMPUTE object to a single thread within a process.
+ *
+ *       NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED
+ *         This mode means that that GPU is not ever allowed to instantiate an
+ *         NV50_COMPUTE object, and thus cannot run any new compute programs.
+ *         This restriction is enforced at each subsequent NV50_COMPUTE object
+ *         allocation attempt. Setting this mode will not affect any existing
+ *         compute programs that may be running. For example, if this mode is
+ *         set while three compute programs are running, then all of those
+ *         programs will be allowed to continue running. However, no new
+ *         NV50_COMPUTE objects may be allocated.
+ *
+ *
+ *       NV2080_CTRL_GPU_COMPUTE_MODE_EXCLUSIVE_COMPUTE_PROCESS
+ *         This mode is identical to EXCLUSIVE_COMPUTE, where only one instance
+ *         of NV50_COMPUTE will be allowed at a time. It is separate from
+ *         EXCLUSIVE_COMPUTE to allow user-mode clients to differentiate
+ *         exclusive access to a compute object from a single thread of a
+ *         process from exclusive access to a compute object from all threads
+ *         of a process. User-mode clients should not limit access to a
+ *         NV50_COMPUTE object to a single thread when the GPU is set to
+ *         EXCLUSIVE_COMPUTE_PROCESS.
+ *
+ *     An invalid rules parameter value results in the return of an
+ *     NV_ERR_INVALID_ARGUMENT status.
+ *
+ *   flags
+ *     Reserved. Caller should set this field to zero.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT (if an invalid rule number is provided)
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS (if the user is not the Administrator or superuser)
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES                   (0x20800130U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */
+
+/* valid rules parameter values */
+#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE                      (0x00000000U)
+#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE         (0x00000001U)
+#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED        (0x00000002U)
+#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS (0x00000003U)
+
+#define NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x30U)
+
+typedef struct NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS {
+    NvU32 rules;
+    NvU32 flags;
+} NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES
+ *
+ * This command queries the compute mode rules for the associated subdevice.
+ * Please see the NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES command, above, for
+ * details as to what the rules mean.
+ *
+ *   rules
+ *     Specifies the rules that govern the GPU, with respect to NV50_COMPUTE
+ *     objects.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES (0x20800131U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x31U)
+
+typedef struct NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS {
+    NvU32 rules;
+} NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION
+ *
+ * This command returns the current ECC configuration setting for
+ * a GPU given its subdevice handle.  The value returned is
+ * the current ECC setting for the GPU stored in non-volatile
+ * memory on the board.
+ *
+ *   currentConfiguration
+ *      The current ECC configuration setting.
+ *
+ *   defaultConfiguration
+ *      The factory default ECC configuration setting.
+ *
+ * Please see the NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS command if
+ * you wish to determine if ECC is currently enabled.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION (0x20800133U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED  (0x00000000U)
+#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED   (0x00000001U)
+
+#define NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x33U)
+
+typedef struct NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS {
+    NvU32 currentConfiguration;
+    NvU32 defaultConfiguration;
+} NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION
+ *
+ * This command changes the ECC configuration setting for a GPU
+ * given its subdevice handle.  The value specified is
+ * stored in non-volatile memory on the board and will take
+ * effect with the next GPU reset
+ *
+ *   newConfiguration
+ *     The new configuration setting to take effect with
+ *     the next GPU reset.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION (0x20800134U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE (0x00000000U)
+#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE  (0x00000001U)
+
+#define NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x34U)
+
+typedef struct NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS {
+    NvU32 newConfiguration;
+} NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS
+ *
+ * This command resets volatile and/or persistent ECC error
+ * status information for a GPU given its subdevice
+ * handle.
+ *
+ *   statuses
+ *     The ECC error statuses (the current, volatile
+ *     and/or the persistent error counter(s)) to
+ *     be reset by the command.
+ *   flags
+ *     FORCE_PURGE
+ *          Forcibly clean all the ECC InfoROM state if this flag is set
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS                     (0x20800136U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE                          (0x00000000U)
+#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE                      (0x00000001U)
+#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE                     (0x00000002U)
+
+#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE           0:0
+#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE 0U
+#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE  1U
+
+#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID (0x36U)
+
+typedef struct NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS {
+    NvU32 statuses;
+    NvU8  flags;
+} NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO
+ *
+ * This command returns a mask of enabled GPCs for the associated GPU.
+ *
+ *    gpcMask
+ *      This parameter returns a mask of enabled GPCs. Each GPC has an ID
+ *      that's equivalent to the corresponding bit position in the mask.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO (0x20800137U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID (0x37U)
+
+typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS {
+    NvU32 gpcMask;
+} NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO
+ *
+ * This command returns a mask of enabled TPCs for a specified GPC.
+ *
+ *    gpcId
+ *      This parameter specifies the GPC for which TPC information is
+ *      to be retrieved. If the GPC with this ID is not enabled this command
+ *      will return an tpcMask value of zero.
+ *
+ *    tpcMask
+ *      This parameter returns a mask of enabled TPCs for the specified GPC.
+ *      Each TPC has an ID that's equivalent to the corresponding bit
+ *      position in the mask.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO (0x20800138U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID (0x38U)
+
+typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS {
+    NvU32 gpcId;
+    NvU32 tpcMask;
+} NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO
+ *
+ * This command returns a mask of enabled ZCULLs for a specified GPC.
+ *
+ *    gpcId
+ *      This parameter specifies the GPC for which ZCULL information is to be
+ *      retrieved. If the GPC with this ID is not enabled this command will
+ *      return an zcullMask value of zero.
+ *
+ *    zcullMask
+ *      This parameter returns a mask of enabled ZCULLs for the specified GPC.
+ *      Each ZCULL has an ID that's equivalent to the corresponding bit
+ *      position in the mask.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *
+ * Deprecated: Please use GR based control call
+ * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO (0x20800139U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID (0x39U)
+
+typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS {
+    NvU32 gpcId;
+    NvU32 zcullMask;
+} NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO
+ *
+ * If an InfoROM with a valid OEM Board Object is present, this
+ * command returns relevant information from the object to the
+ * caller.
+ *
+ * The following data are currently reported:
+ *
+ * buildDate
+ *   The board's build date (8 digit BCD in format YYYYMMDD).
+ *
+ * marketingName
+ *   The board's marketing name (24 ASCII letters e.g. "Quadro FX5800").
+ *
+ * boardSerialNumber
+ *   The board's serial number.
+ *
+ * memoryManufacturer
+ *   The board's memory manufacturer ('S'amsung/'H'ynix/'I'nfineon).
+ *
+ * memoryDateCode
+ *   The board's memory datecode (LSB justified ASCII field with 0x00
+ *   denoting empty space).
+ *
+ * productPartNumber
+ *   The board's 900 product part number (LSB justified ASCII field with 0x00
+ *   denoting empty space e.g. "900-21228-0208-200").
+ *
+ * boardRevision
+ *   The board's revision (for e.g. A02, B01)
+ *
+ * boardType
+ *   The board's type ('E'ngineering/'P'roduction)
+ *
+ * board699PartNumber
+ *   The board's 699 product part number (LSB justified ASCII field with 0x00
+ *   denoting empty space e.g. "699-21228-0208-200").
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO    (0x2080013fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_GPU_MAX_MARKETING_NAME_LENGTH      (0x00000018U)
+#define NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH       (0x00000010U)
+#define NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH      (0x00000014U)
+#define NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH    (0x00000006U)
+#define NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH (0x00000014U)
+
+#define NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID (0x3FU)
+
+typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS {
+    NvU32 buildDate;
+    NvU8  marketingName[NV2080_GPU_MAX_MARKETING_NAME_LENGTH];
+    NvU8  serialNumber[NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH];
+    NvU8  memoryManufacturer;
+    NvU8  memoryPartID[NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH];
+    NvU8  memoryDateCode[NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH];
+    NvU8  productPartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH];
+    NvU8  boardRevision[3];
+    NvU8  boardType;
+    NvU8  board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH];
+} NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ID
+ *
+ * This command returns the gpuId of the associated object.
+ *
+ *   gpuId
+ *     This field return the gpuId.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ID (0x20800142U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID (0x42U)
+
+typedef struct NV2080_CTRL_GPU_GET_ID_PARAMS {
+    NvU32 gpuId;
+} NV2080_CTRL_GPU_GET_ID_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE
+ *
+ * This command is used to enable or disable GPU debug mode. While this mode
+ * is enabled,  some client RM calls that can potentially timeout return
+ * NV_ERR_BUSY_RETRY, signalling the client to try again once GPU
+ * debug mode is disabled.
+ *
+ * mode
+ *   This parameter specifies whether GPU debug mode is to be enabled or
+ *   disabled. Possible values are:
+ *
+ *     NV2080_CTRL_GPU_DEBUG_MODE_ENABLED
+ *     NV2080_CTRL_GPU_DEBUG_MODE_DISABLED
+ *
+ * Possible return status values are
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE (0x20800143U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x43U)
+
+typedef struct NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS {
+    NvU32 mode;
+} NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS;
+
+#define NV2080_CTRL_GPU_DEBUG_MODE_ENABLED     (0x00000001U)
+#define NV2080_CTRL_GPU_DEBUG_MODE_DISABLED    (0x00000002U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE
+ *
+ * This command is used to query whether debug mode is enabled on the current
+ * GPU. Please see the description of NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE
+ * for more details on GPU debug mode.
+ *
+ * currentMode
+ *   This parameter returns the state of GPU debug mode for the current GPU.
+ *   Possible values are:
+ *
+ *     NV2080_CTRL_GPU_DEBUG_MODE_ENABLED
+ *     NV2080_CTRL_GPU_DEBUG_MODE_DISABLED
+ *
+ * Possible return status values are
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE (0x20800144U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x44U)
+
+typedef struct NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS {
+    NvU32 currentMode;
+} NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST
+ *
+ * Returns a list of engines that can partner or coexist
+ * when using the target channel or partnership class.
+ * This list may include all engines (pre-Kepler), or as few
+ * as 1 engine (Kepler and beyond).
+ *
+ *   engineType
+ *     This field specifies the target engine type.
+ *     See cl2080.h for a list of valid engines.
+ *
+ *   partnershipClassId
+ *     This field specifies the target channel
+ *     or partnership class ID.
+ *     An example of such a class is GF100_CHANNEL_GPFIFO.
+ *
+ *   runqueue
+ *     This field is an index which indicates the runqueue to
+ *     return the list of supported engines for. This is the
+ *     same field as what NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE
+ *     specifies. This is only valid for TSG.
+ *
+ *   numPartners;
+ *     This field returns the number of
+ *     valid entries in the partnersList array
+ *
+ *   partnerList
+ *     This field is an array containing the list of supported
+ *     partner engines types, in no particular order, and
+ *     may even be empty (numPartners = 0).
+ *     See cl2080.h for a list of possible engines.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST           (0x20800147U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID" */
+
+/* this macro specifies the maximum number of partner entries */
+#define NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS                  (0x00000020U)
+
+#define NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID (0x47U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS {
+    NvU32 engineType;
+    NvU32 partnershipClassId;
+    NvU32 runqueue;
+    NvU32 numPartners;
+    // C form: NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS];
+    NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS];
+} NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_GID_INFO
+ *
+ * This command returns the GPU ID (GID) string for the associated
+ * GPU.  This value can be useful for GPU identification and security
+ * system validation.
+ *
+ * The GPU ID is a SHA-1 based 16 byte ID, formatted as a 32 character
+ *      hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the
+ *      canonical format of a UUID)
+ *
+ * The GPU IDs are generated using the ECID, PMC_BOOT_0, and
+ * PMC_BOOT_42 of the GPU as the hash message.
+ *
+ *   index
+ *     (Input) "Select which GID set to get." Or so the original documentation
+ *     said. In reality, there is only one GID per GPU, and the implementation
+ *     completely ignores this parameter. You can too.
+ *
+ *   flags (Input) The _FORMAT* flags designate ascii or binary format. Binary
+ *     format returns the raw bytes of either the 16-byte SHA-1 ID or the
+ *     32-byte SHA-256 ID.
+ *
+ *     The _TYPE* flags needs to specify the _SHA1 type.
+ *
+ *   length
+ *     (Output) Actual GID length, in bytes.
+ *
+ *   data[NV2080_BUS_MAX_GID_LENGTH]
+ *     (Output) Result buffer: the GID itself, in a format that is determined by
+ *     the "flags" field (described above).
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_GPU_GET_GID_INFO      (0x2080014aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum possible number of bytes of GID information returned */
+#define NV2080_GPU_MAX_GID_LENGTH             (0x000000100ULL)
+
+/* maximum possible number of bytes of GID information returned if given the BINARY and SHA1 flags */
+#define NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH (0x000000010ULL)
+
+#define NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID (0x4AU)
+
+typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS {
+    NvU32 index;
+    NvU32 flags;
+    NvU32 length;
+    NvU8  data[NV2080_GPU_MAX_GID_LENGTH];
+} NV2080_CTRL_GPU_GET_GID_INFO_PARAMS;
+
+/* valid flags values */
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT                  1:0
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII  (0x00000000U)
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY (0x00000002U)
+
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE                    2:2
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1     (0x00000000U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION
+ *
+ * This command can be used by clients to retrieve the version of an
+ * InfoROM object.
+ *
+ *   objectType
+ *     This parameter specifies the name of the InfoROM object whose version
+ *     should be queried.
+ *
+ *   version
+ *     This parameter returns the version of the InfoROM object specified by
+ *     the objectType parameter.
+ *
+ *   subversion
+ *     This parameter returns the subversion of the InfoROM object specified
+ *     by the objectType parameter.
+ *
+ * Possible return status values:
+ *   NV_OK
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION (0x2080014bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN           3U
+
+#define NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID (0x4BU)
+
+typedef struct NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS {
+    char objectType[NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN];
+    NvU8 version;
+    NvU8 subversion;
+} NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO
+ *
+ * This command will specify that system is Optimus enabled.
+ *
+ * isOptimusEnabled
+ *     Set NV_TRUE if system is Optimus enabled.
+ *
+ * Possible status return values are:
+ *      NV_OK
+ */
+#define NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO (0x2080014cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID (0x4CU)
+
+typedef struct NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS {
+    NvBool isOptimusEnabled;
+} NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_IP_VERSION
+ *
+ * Will return the IP VERSION on the given engine for engines that support
+ * this capability.
+ *
+ *   targetEngine
+ *     This parameter specifies the target engine type to query for IP_VERSION.
+ *
+ *   ipVersion
+ *     This parameter returns the IP VERSION read from the unit's IP_VER
+ *     register.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_IP_VERSION (0x2080014dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4DU)
+
+typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS {
+    NvU32 targetEngine;
+    NvU32 ipVersion;
+} NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY     (0x00000001U)
+#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC    (0x00000002U)
+#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR        (0x00000003U)
+#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU    (0x00000004U)
+#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U)
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_ID_ILLUM_SUPPORT
+ *
+ * This command returns an indicator which reports if the specified Illumination control
+ * attribute is supported
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS 0U
+#define NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS  1U
+#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT      (0x20800153U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID (0x53U)
+
+typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS {
+    NvU32  attribute;
+    NvBool bSupported;
+} NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ID_ILLUM
+ *
+ * This command returns the current value of the specified Illumination control attribute.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x54" */
+
+typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS {
+    NvU32 attribute;
+    NvU32 value;
+} NV2080_CTRL_CMD_GPU_ILLUM_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_ID_ILLUM
+ *
+ * This command sets a new valuefor the specified Illumination control attribute.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_SET_ILLUM                 (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x55" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION
+ *
+ * This command can be used by clients to retrieve the version of the entire
+ * InfoROM image.
+ *
+ *   version
+ *      This parameter returns the version of the InfoROM image as a NULL-
+ *      terminated character string of the form "XXXX.XXXX.XX.XX" where each
+ *      'X' is an integer character.
+ *
+ * Possible status return values are:
+ *   NVOS_STATUS_SUCCES
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_DATA
+ */
+#define NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION (0x20800156U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN     16U
+
+#define NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID (0x56U)
+
+typedef struct NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS {
+    NvU8 version[NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN];
+} NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT
+ *
+ * This command returns whether or not ECC is supported via the InfoROM.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT (0x20800157U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x57" */
+
+/*
+ * NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION
+ *
+ * This structure contains information about a single physical bridge.
+ *
+ *   fwVersion
+ *     This field specifies Firmware Version of the bridge stored in
+ *     bridge EEPROM.
+ *   oemVersion
+ *     This field specifies Oem Version of the firmware stored in
+ *     bridge EEPROM.
+ *   siliconRevision
+ *     This field contains the silicon revision of the bridge hardware.
+ *     It is set by the chip manufacturer.
+ *   hwbcResourceType
+ *     This field specifies the hardware broadcast resource type.
+ *     Value denotes the kind of bridge - PLX or BR04
+ *
+ */
+
+typedef struct NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS {
+    NvU32 fwVersion;
+    NvU8  oemVersion;
+    NvU8  siliconRevision;
+    NvU8  hwbcResourceType;
+} NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO
+ *
+ * This command returns physical bridge information in the system.
+ * Information consists of bridgeCount and a list of bridgeId's.
+ * The bridge Id's are used by NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION
+ * to get firmware version, oem version and silicon revision info.
+ *
+ *   bridgeCount
+ *     This field specifies the number of physical brides present
+ *     in the system.
+ *   hPhysicalBridges
+ *     This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE.
+ *     In this array, the bridge Id's are stored.
+ *   bridgeList
+ *     This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE.
+ *     In this array, the bridge version details are stored.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO (0x2080015aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MAX_PHYSICAL_BRIDGE                      (100U)
+#define NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID (0x5AU)
+
+typedef struct NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS {
+    NvU8                                           bridgeCount;
+    NvHandle                                       hPhysicalBridges[NV2080_CTRL_MAX_PHYSICAL_BRIDGE];
+    NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE];
+} NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_GPU_BRIDGE_VERSION
+ *
+ * This structure contains information about a single physical bridge.
+ *
+ *   bus
+ *     This field specifies the bus id of the bridge.
+ *   device
+ *     This field specifies the device id of the bridge.
+ *   func
+ *     This field specifies the function id of the bridge.
+ *   oemVersion
+ *     This field specifies Oem Version of the firmware stored in
+ *     bridge EEPROM.
+ *   siliconRevision
+ *     This field contains the silicon revision of the bridge hardware.
+ *     It is set by the chip manufacturer.
+ *   hwbcResourceType
+ *     This field specifies the hardware broadcast resource type.
+ *     Value denotes the kind of bridge - PLX or BR04
+ *   domain
+ *     This field specifies the respective domain of the PCI device.
+ *   fwVersion
+ *     This field specifies Firmware Version of the bridge stored in
+ *     bridge EEPROM.
+ *
+ *   If (fwVersion, oemVersion, siliconRevision) == 0, it would mean that RM
+ *   was unable to fetch the value from the bridge device.
+ *
+ */
+
+typedef struct NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS {
+    NvU8  bus;
+    NvU8  device;
+    NvU8  func;
+    NvU8  oemVersion;
+    NvU8  siliconRevision;
+    NvU8  hwbcResourceType;
+    NvU32 domain;
+    NvU32 fwVersion;
+} NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU
+ *
+ * This command returns information about all the upstream bridges of the GPU.
+ * Information consists of bridge firmware version and its bus topology.
+ *
+ *   bridgeCount
+ *     This field specifies the number of physical brides present
+ *     in the system.
+ *   physicalBridgeIds
+ *     This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE.
+ *     In this array, the bridge Ids are stored.
+ *   bridgeList
+ *     This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE.
+ *     In this array, the bridge version details are stored.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU (0x2080015bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID (0x5BU)
+
+typedef struct NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS {
+    NvU8                                  bridgeCount;
+    NvU32                                 physicalBridgeIds[NV2080_CTRL_MAX_PHYSICAL_BRIDGE];
+    NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE];
+} NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS
+ *
+ * This command is used to query the status of the HW scrubber. If a scrub is
+ * in progress then the range which is being scrubbed is also reported back.
+ *
+ *   scrubberStatus
+ *     Reports the status of the scrubber unit - running/idle.
+ *
+ *   remainingtimeMs
+ *     If scrubbing is going on, reports the remaining time in milliseconds
+ *     required to finish the scrub.
+ *
+ *   scrubStartAddr
+ *     This parameter reports the start address of the ongoing scrub if scrub
+ *     is going on, otherwise reports the start addr of the last finished scrub
+ *
+ *   scrubEndAddr
+ *     This parameter reports the end address of the ongoing scrub if scrub
+ *     is going on, otherwise reports the end addr of the last finished scrub.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS (0x2080015fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID (0x5FU)
+
+typedef struct NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS {
+    NvU32 scrubberStatus;
+    NvU32 remainingTimeMs;
+    NV_DECLARE_ALIGNED(NvU64 scrubStartAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 scrubEndAddr, 8);
+} NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS;
+
+/* valid values for scrubber status */
+#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING (0x00000000U)
+#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE    (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_VPR_CAPS
+ *
+ * This command is used to query the VPR capability information for a
+ * GPU. If VPR is supported, the parameters are filled accordingly.
+ * The addresses returned are all physical addresses.
+ *
+ *   minStartAddr
+ *     Returns the minimum start address that can be possible for VPR.
+ *
+ *   maxEndAddr
+ *     Returns the maximum end   address that can be possible for VPR.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_VPR_CAPS                       (0x20800160U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID (0x60U)
+
+typedef struct NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 minStartAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 maxEndAddr, 8);
+} NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR
+ *
+ * Communicates to RM to handle GPU Surprise Removal
+ * Called from client when it receives SR IRP from OS
+ * Possible status values returned are:
+ *   NVOS_STATUS_SUCCESS
+ */
+#define NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR                      (0x20800167U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x67" */
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_PES_INFO
+ *
+ * This command provides the PES count and mask of enabled PES for a
+ * specified GPC. It also returns the TPC to PES mapping information
+ * for a given GPU.
+ *
+ *   gpcId[IN]
+ *     This parameter specifies the GPC for which PES information is to be
+ *     retrieved. If the GPC with this ID is not enabled this command will
+ *     return an activePesMask of zero
+ *
+ *   numPesInGpc[OUT]
+ *     This parameter returns the number of PES in this GPC.
+ *
+ *   activePesMask[OUT]
+ *     This parameter returns a mask of enabled PESs for the specified GPC.
+ *     Each PES has an ID that is equivalent to the corresponding bit position
+ *     in the mask.
+ *
+ *   maxTpcPerGpcCount[OUT]
+ *     This parameter returns the max number of TPCs in a GPC.
+ *
+ *   tpcToPesMap[OUT]
+ *     This array stores the TPC to PES mappings. The value at tpcToPesMap[tpcIndex]
+ *     is the index of the PES it belongs to.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_PES_INFO                       (0x20800168U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT 10U
+
+#define NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID (0x68U)
+
+typedef struct NV2080_CTRL_GPU_GET_PES_INFO_PARAMS {
+    NvU32 gpcId;
+    NvU32 numPesInGpc;
+    NvU32 activePesMask;
+    NvU32 maxTpcPerGpcCount;
+    NvU32 tpcToPesMap[NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT];
+} NV2080_CTRL_GPU_GET_PES_INFO_PARAMS;
+
+/* NV2080_CTRL_CMD_GPU_GET_OEM_INFO
+ *
+ * If an InfoROM with a valid OEM Object is present, this
+ * command returns relevant information from the object to the
+ * caller.
+ *
+ * oemInfo
+ *  This array stores information specifically for OEM use
+ *  (e.g. "their own serial number", "lot codes", etc)
+ *  "The byte definition is up to the OEM"
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_OEM_INFO (0x20800169U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_GPU_MAX_OEM_INFO_LENGTH   (0x000001F8U)
+
+#define NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID (0x69U)
+
+typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS {
+    NvU8 oemInfo[NV2080_GPU_MAX_OEM_INFO_LENGTH];
+} NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS;
+
+/* NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS
+ *
+ * Complete any pending tasks the need to be run after GC6 exit is complete at OS/KMD level
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_READY
+ */
+#define NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS (0x2080016aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x6A" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_VPR_INFO
+ *
+ * This command is used to query the VPR information for a GPU.
+ * The following VPR related information can be queried by selecting the queryType:
+ *   1. The current VPR range.
+ *   2. The max VPR range ever possible on this GPU.
+ *
+ *   queryType [in]
+ *     This input parameter is used to select the type of information to query.
+ *     Possible values for this parameter are:
+ *       1. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS: Use this to query the
+ *              max VPR range ever possible on this GPU.
+ *       2. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE: Use this to query
+ *              the current VPR range on this GPU.
+ *
+ *   bVprEnabled [out]
+ *     For query type "NV2080_CTRL_GPU_GET_VPR_INFO_CUR_RANGE", this parameter
+ *     returns if VPR is currently enabled or not.
+ *
+ *   vprStartAddress [out]
+ *     For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns minimum allowed VPR start address.
+ *     For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR start address.
+ *
+ *   vprEndAddress [out]
+ *     For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns maximum allowed VPR end address.
+ *     For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR end address.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO                (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */
+
+
+typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE {
+    NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = 0,
+    NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = 1,
+} NV2080_CTRL_VPR_INFO_QUERY_TYPE;
+
+#define NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID (0x6BU)
+
+typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS {
+    NV2080_CTRL_VPR_INFO_QUERY_TYPE queryType;
+    NvBool                          bIsVprEnabled;
+    NV_DECLARE_ALIGNED(NvU64 vprStartAddressInBytes, 8);
+    NV_DECLARE_ALIGNED(NvU64 vprEndAddressInBytes, 8);
+} NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY
+ *
+ * This command is used to query the encoder capacity of the GPU.
+ *
+ *   queryType [in]
+ *     This input parameter is used to select the type of information to query.
+ *     Possible values for this parameter are:
+ *       1. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264: Use this to query the
+ *              H.264 encoding capacity on this GPU.
+ *       2. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC: Use this to query the
+ *              H.265/HEVC encoding capacity on this GPU.
+ *
+ *   encoderCapacity [out]
+ *     Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance
+ *     may be minimal for this GPU and software should fall back to CPU-based encode.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY (0x2080016cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE {
+    NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0,
+    NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1,
+} NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE;
+
+#define NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x6CU)
+
+typedef struct NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS {
+    NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE queryType;
+    NvU32                                   encoderCapacity;
+} NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS;
+
+/*
+ * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS
+ *
+ * This command is used to retrieve the GPU's count of encoder sessions,
+ * trailing average FPS and encode latency over all active sessions.
+ *
+ *   encoderSessionCount
+ *     This field specifies count of all active encoder sessions on this GPU.
+ *
+ *   averageEncodeFps
+ *     This field specifies the average encode FPS for this GPU.
+ *
+ *   averageEncodeLatency
+ *     This field specifies the average encode latency in microseconds for this GPU.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS (0x2080016dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x6DU)
+
+typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS {
+    NvU32 encoderSessionCount;
+    NvU32 averageEncodeFps;
+    NvU32 averageEncodeLatency;
+} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS;
+
+#define NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES 0x200U  // 512 entries.
+
+/*
+ * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO
+ *
+ * This command returns NVENC software sessions information for the associate GPU.
+ * Request to retrieve session information use a list of one or more
+ * NV2080_CTRL_NVENC_SW_SESSION_INFO structures.
+ *
+ *   sessionInfoTblEntry
+ *     This field specifies the number of entries on the that are filled inside
+ *     sessionInfoTbl. Max value of this field once returned from RM would be
+ *     NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES,
+ *
+ *   sessionInfoTbl
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the NVENC session information is to be returned.
+ *     When buffer is NULL, RM assume that client is querying sessions count value
+ *     and return the current encoder session counts in sessionInfoTblEntry field.
+ *     To get actual buffer data, client should allocate sessionInfoTbl of size
+ *     NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES  multiplied by the
+ *     size of the NV2080_CTRL_NVENC_SW_SESSION_INFO structure. RM will fill the
+ *     current session data in sessionInfoTbl buffer and then update the
+ *     sessionInfoTblEntry to reflect current session count value.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NO_MEMORY
+ *   NV_ERR_INVALID_LOCK_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+typedef struct NV2080_CTRL_NVENC_SW_SESSION_INFO {
+    NvU32 processId;
+    NvU32 subProcessId;
+    NvU32 sessionId;
+    NvU32 codecType;
+    NvU32 hResolution;
+    NvU32 vResolution;
+    NvU32 averageEncodeFps;
+    NvU32 averageEncodeLatency;
+} NV2080_CTRL_NVENC_SW_SESSION_INFO;
+
+#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x6EU)
+
+typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS {
+    NvU32 sessionInfoTblEntry;
+    NV_DECLARE_ALIGNED(NvP64 sessionInfoTbl, 8);
+} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO (0x2080016eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR
+ *
+ * The command sets fabric base address which represents top N bits of a
+ * peer memory address. These N bits will be used to index NvSwitch routing
+ * tables to forward peer memory accesses to associated GPUs.
+ *
+ * The command is available to clients with administrator privileges only.
+ * An attempt to use this command by a client without administrator privileged
+ * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status.
+ *
+ * The command allows to set fabricAddr once in a lifetime of a GPU. A GPU must
+ * be destroyed in order to re-assign a different fabricAddr. An attempt to
+ * re-assign address without destroying a GPU would result in the return of
+ * NV_ERR_STATE_IN_USE status.
+ *
+ *   fabricBaseAddr[IN]
+ *      - An address with at least 32GB alignment.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_STATE_IN_USE
+ */
+
+#define NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x6FU)
+
+typedef struct NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 fabricBaseAddr, 8);
+} NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT
+ *
+ * The command will trigger the specified interrupt on the host from a guest.
+ *
+ *   handle[IN]
+ *      - An opaque handle that will be passed in along with the interrupt
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID (0x72U)
+
+typedef struct NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS {
+    NvU32 handle;
+} NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT                                      (0x20800172U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS
+ *
+ * This control call is to query the status of gpu function registers
+ *
+ *    statusMask[IN]
+ *        - Input mask of required status registers
+ *    xusbData[OUT]
+ *        - data from querying XUSB status register
+ *    ppcData[OUT]
+ *        - data from querying PPC status register
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+
+
+#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID (0x73U)
+
+typedef struct NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS {
+    NvU32 statusMask;
+    NvU32 xusbData;
+    NvU32 ppcData;
+} NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS (0x20800173U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_GPU_PARTITION_SPAN
+ *
+ * This struct represents the span of a memory partition, which represents the
+ * slices a given partition occupies (or may occupy) within a fixed range which
+ * is defined per-chip. A partition containing more resources will cover more
+ * GPU slices and therefore cover a larger span.
+ *
+ *   lo
+ *      - The starting unit of this span, inclusive
+ *
+ *   hi
+ *      - The ending unit of this span, inclusive
+ *
+ */
+typedef struct NV2080_CTRL_GPU_PARTITION_SPAN {
+    NV_DECLARE_ALIGNED(NvU64 lo, 8);
+    NV_DECLARE_ALIGNED(NvU64 hi, 8);
+} NV2080_CTRL_GPU_PARTITION_SPAN;
+
+/*
+ * NV2080_CTRL_GPU_SET_PARTITION_INFO
+ *
+ * This command partitions a GPU into different SMC-Memory partitions.
+ * The command will configure HW partition table to create work and memory
+ * isolation.
+ *
+ * The command is available to clients with administrator privileges only.
+ * An attempt to use this command by a client without administrator privileged
+ * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status.
+ *
+ * The command allows partitioning an invalid partition only. An attempt to
+ * re-partition a valid partition will resule in NV_ERR_STATE_IN_USE.
+ * Repartitioning can be done only if a partition has been destroyed/invalidated
+ * before re-partitioning.
+ *
+ *   swizzId[IN/OUT]
+ *      - PartitionID associated with a newly created partition. Input in case
+ *        of partition invalidation.
+ *
+ *   partitionFlag[IN]
+ *      - Flags to determine if GPU is requested to be partitioned in FULL,
+ *        HALF, QUARTER or ONE_EIGHTHED and whether the partition requires
+ *        any additional resources.
+ *        When flags include NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA
+ *        partition will be created with at least one video decode, jpeg and
+ *        optical flow engines. This flag is valid only for partitions with
+ *        a single GPC.
+ *
+ *   bValid[IN]
+ *      - NV_TRUE if creating a partition. NV_FALSE if destroying a partition.
+ *
+ *   placement[IN]
+ *      - Optional placement span to allocate the partition into. Valid
+ *        placements are returned from NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY.
+ *        The partition flag NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN must
+ *        be set for this parameter to be used. If the flag is set and the given
+ *        placement is not valid, an error will be returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_STATE_IN_USE
+ */
+typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
+    NvU32  swizzId;
+    NvU32  partitionFlag;
+    NvBool bValid;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8);
+} NV2080_CTRL_GPU_SET_PARTITION_INFO;
+
+#define PARTITIONID_INVALID                                      NV2080_CTRL_GPU_PARTITION_ID_INVALID
+#define NV2080_CTRL_GPU_PARTITION_ID_INVALID                     0xFFFFFFFFU
+#define NV2080_CTRL_GPU_MAX_PARTITIONS                           0x00000008U
+#define NV2080_CTRL_GPU_MAX_PARTITION_IDS                        0x00000009U
+#define NV2080_CTRL_GPU_MAX_SMC_IDS                              0x00000008U
+#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC                          0x0000000cU
+#define NV2080_CTRL_GPU_MAX_CE_PER_SMC                           0x00000008U
+
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE              1:0
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL          0x00000000U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF          0x00000001U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER       0x00000002U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH        0x00000003U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE         4U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE             4:2
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL         0x00000000U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF         0x00000001U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF    0x00000002U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER      0x00000003U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH       0x00000005U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE        6U
+
+
+#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES                      8U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA          30:30
+#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE   0U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE    1U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN            31:31
+#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE     0U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE      1U
+
+// TODO XXX Bug 2657907 Remove these once clients update
+#define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU                 (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL)    | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL))
+#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU             (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF)    | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF))
+#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU        (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF)    | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF))
+#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU          (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER))
+#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU         (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH)  | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH))
+
+#define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U)
+
+typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS {
+    NvU32 partitionCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_SET_PARTITION_INFO partitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
+} NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_SET_PARTITIONS (0x20800174U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_GPU_GET_PARTITION_INFO
+ *
+ * This command gets the partition information for requested partitions.
+ * If GPU is not partitioned, the control call will return NV_ERR_NOT_SUPPORTED.
+ *
+ * The command will can return global partition information as well as single
+ * partition information if global flag is not set.
+ * In bare-metal user-mode can request all partition info while in virtualization
+ * plugin should make an RPC with swizzId which is assigned to the requesting
+ * VM.
+ *
+ *   swizzId[IN]
+ *      - HW Partition ID associated with the requested partition.
+ *
+ *   partitionFlag[OUT]
+ *      - partitionFlag that was provided during partition creation.
+ *
+ *   grEngCount[OUT]
+ *      - Number of SMC engines/GR engines allocated in partition
+ *        GrIDs in a partition will always start from 0 and end at grEngCount-1
+ *
+ *   veidCount[OUT]
+ *      - VEID Count assigned to a partition. These will be divided across
+ *        SMC engines once CONFIGURE_PARTITION call has been made. The current
+ *        algorithm is to assign veidPerGpc * gpcCountPerSmc to a SMC engine.
+ *
+ *   smCount[OUT]
+ *      - SMs assigned to a partition.
+ *
+ *   ceCount[OUT]
+ *      - Copy Engines assigned to a partition.
+ *
+ *   nvEncCount[OUT]
+ *      - NvEnc Engines assigned to a partition.
+ *
+ *   nvDecCount[OUT]
+ *      - NvDec Engines assigned to a partition.
+ *
+ *   nvJpgCount[OUT]
+ *      - NvJpg Engines assigned to a partition.
+ *
+ *   gpcCount[OUT]
+ *      - Max GPCs assigned to a partition, including the GfxCapable ones.
+ *
+ *   virtualGpcCount[OUT]
+ *      - Virtualized GPC count assigned to partition
+ *
+ *   gfxGpcCount[OUT]
+ *      - Max GFX GPCs assigned to a partition. This is a subset of the GPCs incuded in gpcCount.
+ *
+ *   gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
+ *      - GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX
+ *
+ *   virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
+ *      - Virtualized GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX
+ *
+ *   gfxGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
+ *      - GFX GPC count associated with every valid SMC/Gr. This is a subset of the GPCs included in gfxGpcCount
+ *
+ *   veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
+ *      - VEID count associated with every valid SMC. VEIDs within this SMC
+ *        will start from 0 and go till veidCount[SMC_ID] - 1.
+ *
+ *   span[OUT]
+ *      - The span covered by this partition
+ *
+ *   bValid[OUT]
+ *      - NV_TRUE if partition is valid else NV_FALSE.
+ *
+ *   bPartitionError[OUT]
+ *      - NV_TRUE if partition had poison error which requires drain and reset
+ *        else NV_FALSE.
+ *
+ *   validCTSIdMask[OUT]
+ *      - Mask of CTS IDs usable by this partition, not reflecting current allocations
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_NOT_SUPPORTED
+ */
+typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO {
+    NvU32  swizzId;
+    NvU32  partitionFlag;
+    NvU32  grEngCount;
+    NvU32  veidCount;
+    NvU32  smCount;
+    NvU32  ceCount;
+    NvU32  nvEncCount;
+    NvU32  nvDecCount;
+    NvU32  nvJpgCount;
+    NvU32  nvOfaCount;
+    NvU32  gpcCount;
+    NvU32  virtualGpcCount;
+    NvU32  gfxGpcCount;
+    NvU32  gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
+    NvU32  virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
+    NvU32  gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
+    NvU32  veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
+    NV_DECLARE_ALIGNED(NvU64 memSize, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN span, 8);
+    NvBool bValid;
+    NvBool bPartitionError;
+    NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8);
+} NV2080_CTRL_GPU_GET_PARTITION_INFO;
+
+/*
+ * NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS
+ *
+ *   queryPartitionInfo[IN]
+ *      - Max sized array of NV2080_CTRL_GPU_GET_PARTITION_INFO to get partition
+ *       Info
+ *
+ *   bGetAllPartitionInfo[In]
+ *      - Flag to get all partitions info. Only root client will receive all
+ *        partition's info. Non-Root clients should not use this flag
+ *
+ *   validPartitionCount[Out]
+ *      - Valid partition count which has been filled by RM as part of the call
+ *
+ */
+#define NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID (0x75U)
+
+typedef struct NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_GET_PARTITION_INFO queryPartitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
+    NvU32  validPartitionCount;
+    NvBool bGetAllPartitionInfo;
+} NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_PARTITIONS      (0x20800175U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_GPU_CONFIGURE_PARTITION
+ *
+ * This command configures a partition by associating GPCs with SMC Engines
+ * available in that partition. Engines which are to have GPCs assigned to them
+ * shall not already have any GPCs assigned to them. It is not valid to both
+ * assign GPCs and remove GPCs as part of a single call to this function.
+ *
+ *   swizzId[IN]
+ *      - PartitionID for configuring partition. If partition has a valid
+ *        context created, then configuration is not allowed.
+ *
+ *   gpcCountPerSmcEng[IN]
+ *      - Number of GPCs expected to be configured per SMC. Supported
+ *        configurations are 0, 1, 2, 4 or 8. "0" means a particular SMC
+ *        engine will be disabled with no GPC connected to it.
+ *
+ *   updateSmcEngMask[IN]
+ *      - Mask tracking valid entries of gpcCountPerSmcEng. A value of
+ *        0 in bit index i indicates that engine i will keep its current
+ *        configuration.
+ *
+ *   bUseAllGPCs[IN]
+ *      - Flag specifying alternate configuration mode, indicating that in
+ *        swizzid 0 only, all non-floorswept GPCs should be connected to the
+ *        engine indicated by a raised bit in updateSmcEngMask. Only a single
+ *        engine may be targeted by this operation. The gpcCountPerSmcEng
+ *        parameter should not be used with this flag.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_STATE_IN_USE
+ */
+#define NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION (0x20800176U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID (0x76U)
+
+typedef struct NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS {
+    NvU32  swizzId;
+    NvU32  gpcCountPerSmcEng[NV2080_CTRL_GPU_MAX_SMC_IDS];
+    NvU32  updateSmcEngMask;
+    NvBool bUseAllGPCs;
+} NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS;
+
+
+/*
+ * NV2080_CTRL_GPU_FAULT_PACKET
+ *
+ * This struct represents a GMMU fault packet.
+ *
+ */
+#define NV2080_CTRL_GPU_FAULT_PACKET_SIZE 32U
+typedef struct NV2080_CTRL_GPU_FAULT_PACKET {
+    NvU8 data[NV2080_CTRL_GPU_FAULT_PACKET_SIZE];
+} NV2080_CTRL_GPU_FAULT_PACKET;
+
+/*
+ * NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT
+ *
+ * This command reports a nonreplayable fault packet to RM.
+ * It is only used by UVM.
+ *
+ *   pFaultPacket[IN]
+ *      - A fault packet that will be later cast to GMMU_FAULT_PACKET *.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT (0x20800177U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID (0x77U)
+
+typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS {
+    NV2080_CTRL_GPU_FAULT_PACKET faultPacket;
+} NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU
+ *
+ *  This command is similar to NV2080_CTRL_CMD_GPU_EXEC_REG_OPS, except it is used
+ *  by the VGPU plugin client only. This command provides access to the subset of
+ *  privileged registers.
+ *
+ *  See confluence page "vGPU UMED Security" for details.
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU           (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x78" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE
+ *
+ * This command returns the runlist pri base of the specified engine(s).
+ *
+ *   engineList
+ *     Input array.
+ *     This array specifies the engines being queried for information.
+ *     The list of engines supported by a chip can be fetched using the
+ *     NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call.
+ *
+ *   runlistPriBase
+ *     Output array.
+ *     Returns the runlist pri base for the specified engines
+ *     Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL
+ *     and will return _ERROR when the control call fails due to an invalid argument
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE (0x20800179U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID (0x79U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS {
+    NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+    NvU32 runlistPriBase[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+} NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL  (0xFFFFFFFFU)
+#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFBU)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID
+ *
+ * This command returns the host hardware defined engine ID of the specified engine(s).
+ *
+ *   engineList
+ *     Input array.
+ *     This array specifies the engines being queried for information.
+ *     The list of engines supported by a chip can be fetched using the
+ *     NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call.
+ *
+ *   hwEngineID
+ *     Output array.
+ *     Returns the host hardware engine ID(s) for the specified engines
+ *     Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL
+ *     and will return _ERROR when the control call fails due to an invalid argument
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID              (0x2080017aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID (0x7AU)
+
+typedef struct NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS {
+    NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+    NvU32 hwEngineID[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+} NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL      (0xFFFFFFFFU)
+#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR     (0xFFFFFFFBU)
+
+/*
+ * NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS
+ *
+ * This command is used to retrieve the GPU's count of FBC sessions,
+ * average FBC calls and FBC latency over all active sessions.
+ *
+ *   sessionCount
+ *     This field specifies count of all active fbc sessions on this GPU.
+ *
+ *   averageFPS
+ *     This field specifies the average frames captured.
+ *
+ *   averageLatency
+ *     This field specifies the average FBC latency in microseconds.
+ *
+ * Possible status values returned are :
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+*/
+#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS (0x2080017bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x7BU)
+
+typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS {
+    NvU32 sessionCount;
+    NvU32 averageFPS;
+    NvU32 averageLatency;
+} NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS;
+
+/*
+* NV2080_CTRL_NVFBC_SW_SESSION_INFO
+*
+*   processId[OUT]
+*           Process id of the process owning the NvFBC session.
+*           On VGX host, this will specify the vGPU plugin process id.
+*   subProcessId[OUT]
+*           Process id of the process owning the NvFBC session if the
+*           session is on VGX guest, else the value is zero.
+*   vgpuInstanceId[OUT]
+*           vGPU on which the process owning the NvFBC session
+*           is running if session is on VGX guest, else
+*           the value is zero.
+*   sessionId[OUT]
+*           Unique session id of the NvFBC session.
+*   sessionType[OUT]
+*           Type of NvFBC session.
+*   displayOrdinal[OUT]
+*           Display identifier associated with the NvFBC session.
+*   sessionFlags[OUT]
+*           One or more of NV2080_CTRL_NVFBC_SESSION_FLAG_xxx.
+*   hMaxResolution[OUT]
+*           Max horizontal resolution supported by the NvFBC session.
+*   vMaxResolution[OUT]
+*           Max vertical resolution supported by the NvFBC session.
+*   hResolution[OUT]
+*           Horizontal resolution requested by caller in grab call.
+*   vResolution[OUT]
+*           Vertical resolution requested by caller in grab call.
+*   averageFPS[OUT]
+*           Average no. of frames captured per second.
+*   averageLatency[OUT]
+*           Average frame capture latency in microseconds.
+*/
+
+#define NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED            0x00000001U
+#define NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED  0x00000002U
+#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT  0x00000004U
+#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008U
+#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT  0x00000010U
+
+typedef struct NV2080_CTRL_NVFBC_SW_SESSION_INFO {
+    NvU32 processId;
+    NvU32 subProcessId;
+    NvU32 vgpuInstanceId;
+    NvU32 sessionId;
+    NvU32 sessionType;
+    NvU32 displayOrdinal;
+    NvU32 sessionFlags;
+    NvU32 hMaxResolution;
+    NvU32 vMaxResolution;
+    NvU32 hResolution;
+    NvU32 vResolution;
+    NvU32 averageFPS;
+    NvU32 averageLatency;
+} NV2080_CTRL_NVFBC_SW_SESSION_INFO;
+
+/*
+* NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO
+*
+* This command returns NVFBC software sessions information for the associate GPU.
+*
+*   sessionInfoCount
+*     This field specifies the number of entries that are filled inside
+*     sessionInfoTbl. Max value of this field once returned from RM would be
+*     NV2080_GPU_NVFBC_MAX_COUNT.
+*
+*   sessionInfoTbl
+*     This field specifies the array in which the NVFBC session information is to
+*     be returned. RM will fill the current session data in sessionInfoTbl array
+*     and then update the sessionInfoCount to reflect current session count value.
+*
+* Possible status values returned are:
+*   NV_OK
+*   NV_ERR_NO_MEMORY
+*   NV_ERR_INVALID_LOCK_STATE
+*   NV_ERR_INVALID_ARGUMENT
+*/
+
+#define NV2080_GPU_NVFBC_MAX_SESSION_COUNT 256U
+
+#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x7CU)
+
+typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS {
+    NvU32                             sessionInfoCount;
+    NV2080_CTRL_NVFBC_SW_SESSION_INFO sessionInfoTbl[NV2080_GPU_NVFBC_MAX_SESSION_COUNT];
+} NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE
+ *
+ * This command returns the VMMU page size
+ *
+ *   vmmuSegmentSize
+ *     Output parameter.
+ *     Returns the VMMU segment size (in bytes)
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID (0x7EU)
+
+typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 vmmuSegmentSize, 8);
+} NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS;
+
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB     0x02000000U
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB     0x04000000U
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB    0x08000000U
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB    0x10000000U
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB    0x20000000U
+
+
+
+/*
+ * NV2080_CTRL_GPU_GET_PARTITION_CAPACITY
+ *
+ * This command returns the count of partitions of given size (represented by
+ * NV2080_CTRL_GPU_PARTITION_FLAG_*) which can be requested via
+ * NV2080_CTRL_GPU_SET_PARTITIONS ctrl call.
+ * Note that this API does not "reserve" any partitions, and there is no
+ * guarantee that the reported count of available partitions of a given size
+ * will remain consistent following creation of partitions of different size
+ * through NV2080_CTRL_GPU_SET_PARTITIONS.
+ * Note that this API is unsupported if SMC is feature-disabled.
+ *
+ *   partitionFlag[IN]
+ *      - Partition flag indicating size of requested partitions
+ *
+ *   partitionCount[OUT]
+ *      - Available number of partitions of the given size which can currently be created.
+ *
+ *   availableSpans[OUT]
+ *      - For each partition able to be created of the specified size, the span
+ *        it could occupy.
+ *
+ *   availableSpansCount[OUT]
+ *      - Number of valid entries in availableSpans.
+ *
+ *   totalPartitionCount[OUT]
+ *      - Total number of partitions of the given size which can be created.
+ *
+ *   totalSpans[OUT]
+ *      - List of spans which can possibly be occupied by partitions of the
+ *        given type.
+ *
+ *   totalSpansCount[OUT]
+ *      - Number of valid entries in totalSpans.
+ *
+ *   bStaticInfo[IN]
+ *      - Flag indicating that client requests only the information from
+ *        totalPartitionCount and totalSpans.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY (0x20800181U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID (0x81U)
+
+typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS {
+    NvU32  partitionFlag;
+    NvU32  partitionCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN availableSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
+    NvU32  availableSpansCount;
+    NvU32  totalPartitionCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
+    NvU32  totalSpansCount;
+    NvBool bStaticInfo;
+} NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_CACHED_INFO
+ *
+ * This command returns cached(SW only) gpu information for the associated GPU.
+ * Requests to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO
+ * structures.
+ * The gpuInfoList is aligned with NV2080_CTRL_GPU_GET_INFO_V2_PARAMS for security concern
+ *
+ *   gpuInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     gpuInfoList.
+ *   gpuInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the gpu information is to be returned.
+ *     This buffer must be at least as big as gpuInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_GPU_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x82" */
+
+typedef struct NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS {
+    NvU32                gpuInfoListSize;
+    NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE];
+} NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_GPU_SET_PARTITIONING_MODE
+ *
+ * This command configures this GPU to control global mode for partitioning.
+ * This command may not be sent to a GPU with any active partitions.
+ * This command may be used to set the following modes:
+ *
+ * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING
+ *  NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY
+ *      This is the default mode. While this GPU is in this mode, no partitions
+ *      will be allowed to be created via SET_PARTITIONS - a client must set one
+ *      of the below modes prior to partitioning the GPU. When a client sets a
+ *      GPU into this mode, any performance changes resulting from partitions
+ *      made while in either of the below modes will be cleared. A
+ *      physical-function-level reset is required after setting this mode.
+ *
+ *  NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF
+ *      In this mode, when the GPU is partitioned, each partition will have the
+ *      maximum possible performance which can be evenly distributed among all
+ *      partitions. The total performance of the GPU, taking into account all
+ *      partitions created in this mode, may be less than that of a GPU running
+ *      in legacy non-SMC mode. Partitions created while in this mode require a
+ *      physical-function-level reset before the partitioning may take full
+ *      effect.  Destroying all partitions while in this mode may be
+ *      insufficient to restore full performance to the GPU - only by setting
+ *      the mode to _LEGACY can this be achieved. A physical-function-level
+ *      reset is NOT required after setting this mode.
+ *
+ *  NV2080_CTRL_GPU_SET_PARTIITONING_MODE_REPARTITIONING_FAST_RECONFIG
+ *      By setting this mode, the performance of the GPU will be restricted such
+ *      that all partitions will have a consistent fraction of the total
+ *      available performance, which may be less than the maximum possible
+ *      performance available to each partition. Creating or destroying
+ *      partitions on this GPU while in this mode will not require a
+ *      physical-function-level reset, and will not affect other active
+ *      partitions. Destroying all partitions while in this mode may be
+ *      insufficient to restore full performance to the GPU - only by setting
+ *      the mode to _LEGACY can this be achieved. A physical-function-level
+ *      reset is required after setting this mode.
+ *
+ * Parameters:
+ *   partitioningMode[IN]
+ *      - Partitioning Mode to set for this GPU.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE                          (0x20800183U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING                1:0
+#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY        0U
+#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF      1U
+#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG 2U
+
+#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0x83U)
+
+typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS {
+    NvU32 partitioningMode;
+} NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS;
+
+
+
+/* NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO
+ *
+ * This structure describes resources available in a partition requested of a
+ * given type.
+ *
+ * [OUT] partitionFlag
+ *      - Flags to specify in NV2080_CTRL_CMD_GPU_SET_PARTITIONS to request this
+ *        partition
+ *
+ * [OUT] grCount
+ *      - Total Number of SMC engines/GR engines (including GFX capable ones in this parition)
+ *
+ * [OUT] gfxGrCount
+ *      - Number of SMC engines/GR engines capable of GFX. This is a subset of the engines included in grCount
+ *
+ * [OUT] gpcCount
+ *      - Number of GPCs in this partition, including the GFX Capable ones.
+ *
+ * [OUT] virtualGpcCount
+ *      - Number of virtualized GPCs in this partition, including the GFX Capable ones.
+ *
+ * [OUT] gfxGpcCount
+ *      - Number of GFX Capable GPCs in this partition. This is a subset of the GPCs included in gpcCount.
+ *
+ * [OUT] veidCount
+ *      - Number of VEIDS in this partition
+ *
+ * [OUT] smCount
+ *      - Number of SMs in this partition
+ *
+ * [OUT] ceCount
+ *      - Copy Engines in this partition
+ *
+ * [OUT] nvEncCount
+ *      - Encoder Engines in this partition
+ *
+ * [OUT] nvDecCount
+ *      - Decoder Engines in this partition
+ *
+ * [OUT] nvJpgCount
+ *      - Jpg Engines in this partition
+ *
+ * [OUT] nvOfaCount
+ *      - Ofa engines in this partition
+ * [OUT] memorySize
+ *      - Total available memory within this partition
+ */
+typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO {
+    NvU32 partitionFlag;
+    NvU32 grCount;
+    NvU32 gfxGrCount;
+    NvU32 gpcCount;
+    NvU32 virtualGpcCount;
+    NvU32 grGpcCount;
+    NvU32 veidCount;
+    NvU32 smCount;
+    NvU32 ceCount;
+    NvU32 nvEncCount;
+    NvU32 nvDecCount;
+    NvU32 nvJpgCount;
+    NvU32 nvOfaCount;
+    NV_DECLARE_ALIGNED(NvU64 memorySize, 8);
+} NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO;
+
+/*
+ * NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS
+ *
+ * This command returns information regarding GPU partitions which can be
+ * requested via NV2080_CTRL_CMD_GPU_SET_PARTITIONS.
+ *
+ * [OUT] descCount
+ *      - Number of valid partition types
+ *
+ * [OUT] partitionDescs
+ *      - Information describing available partitions
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID (0x85U)
+
+typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS {
+    NvU32 descCount;
+    // C form: NV2080_CTRL_GPU_DESCRIBE_PARTITION_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES], 8);
+} NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS (0x20800185U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID" */
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE
+ *
+ * This command returns information regarding maximum page size supported
+ * by GMMU on the platform on which RM is running.
+ *
+ * [OUT] maxSupportedPageSize
+ *      - Maximum local vidmem page size supported by GMMU of a given GPU (HW)
+ *        on a given platform (OS)
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE (0x20800188U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U)
+
+typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS {
+    NvU32 maxSupportedPageSize;
+} NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC
+ *
+ * This command returns the max number of MMUs per GPC
+ *
+ *   gpcId [IN]
+ *     Logical GPC id
+ *   count [OUT]
+ *     The number of MMUs per GPC
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine. When SMC is enabled, this
+ *     is a mandatory parameter.
+ */
+#define NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID (0x8AU)
+
+typedef struct NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS {
+    NvU32 gpcId;
+    NvU32 count;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC (0x2080018aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS
+ *
+ * This command returns the GPU partition IDs for all active partitions
+ * If GPU is not partitioned, the control call will return partition count as "0"
+ *
+ *   swizzId[OUT]
+ *      - HW Partition ID associated with the active partitions
+ *
+ *   partitionCount[OUT]
+ *      - Number of active partitions in system
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID (0x8BU)
+
+typedef struct NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS {
+    NvU32 swizzId[NV2080_CTRL_GPU_MAX_PARTITION_IDS];
+    NvU32 partitionCount;
+} NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS               (0x2080018bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID" */
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_PIDS
+ *
+ * Given a resource identifier and its type, this command returns a set of
+ * process identifiers (PIDs) of processes that have instantiated this resource.
+ * For example, given a class number, this command returns a list of all
+ * processes with clients that have matching object allocations.
+ * This is a SMC aware call and the scope of the information gets restricted
+ * based on partition subscription.
+ * The call enforces partition subscription if SMC is enabled, and client is not
+ * a monitoring client.
+ * Monitoring clients get global information without any scope based filtering.
+ * Monitoring clients are also not expected to subscribe to a partition when
+ * SMC is enabled.
+ *
+ *   idType
+ *     Type of the resource identifier. See below for a list of valid types.
+ *   id
+ *     Resource identifier.
+ *   pidTblCount
+ *      Number of entries in the PID table.
+ *   pidTbl
+ *     Table which will contain the PIDs. Each table entry is of type NvU32.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_PIDS       (0x2080018dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID" */
+
+/* max size of pidTable */
+#define NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT 950U
+
+#define NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID (0x8DU)
+
+typedef struct NV2080_CTRL_GPU_GET_PIDS_PARAMS {
+    NvU32 idType;
+    NvU32 id;
+    NvU32 pidTblCount;
+    NvU32 pidTbl[NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT];
+} NV2080_CTRL_GPU_GET_PIDS_PARAMS;
+
+/*
+ * Use class NV20_SUBDEVICE_0 with NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS to query
+ * PIDs with or without GPU contexts. For any other class id, PIDs only with GPU
+ * contexts are returned.
+ */
+#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS      (0x00000000U)
+#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST (0x00000001U)
+
+/*
+ * NV2080_CTRL_SMC_SUBSCRIPTION_INFO
+ *
+ * This structure contains information about the SMC subscription type.
+ * If MIG is enabled a valid ID is returned, it is set to PARTITIONID_INVALID otherwise.
+ *
+ *  computeInstanceId
+ *      This parameter returns a valid compute instance ID
+ *  gpuInstanceId
+ *      This parameter returns a valid GPU instance ID
+ */
+typedef struct NV2080_CTRL_SMC_SUBSCRIPTION_INFO {
+    NvU32 computeInstanceId;
+    NvU32 gpuInstanceId;
+} NV2080_CTRL_SMC_SUBSCRIPTION_INFO;
+
+/*
+ * NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA
+ *
+ * This structure contains the video memory usage information.
+ *
+ *   memPrivate
+ *     This parameter returns the amount of memory exclusively owned
+ *     (i.e. private) to the client
+ *   memSharedOwned
+ *     This parameter returns the amount of shared memory owned by the client
+ *   memSharedDuped
+ *     This parameter returns the amount of shared memory duped by the client
+ *   protectedMemPrivate
+ *     This parameter returns the amount of protected memory exclusively owned
+ *     (i.e. private) to the client whenever memory protection is enabled
+ *   protectedMemSharedOwned
+ *     This parameter returns the amount of shared protected memory owned by the
+ *     client whenever memory protection is enabled
+ *   protectedMemSharedDuped
+ *     This parameter returns the amount of shared protected memory duped by the
+ *     client whenever memory protection is enabled
+ */
+typedef struct NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA {
+    NV_DECLARE_ALIGNED(NvU64 memPrivate, 8);
+    NV_DECLARE_ALIGNED(NvU64 memSharedOwned, 8);
+    NV_DECLARE_ALIGNED(NvU64 memSharedDuped, 8);
+    NV_DECLARE_ALIGNED(NvU64 protectedMemPrivate, 8);
+    NV_DECLARE_ALIGNED(NvU64 protectedMemSharedOwned, 8);
+    NV_DECLARE_ALIGNED(NvU64 protectedMemSharedDuped, 8);
+} NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA;
+
+#define NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE (0x00000000U)
+
+#define NV2080_CTRL_GPU_PID_INFO_INDEX_MAX                NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE
+
+typedef union NV2080_CTRL_GPU_PID_INFO_DATA {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA vidMemUsage, 8);
+} NV2080_CTRL_GPU_PID_INFO_DATA;
+
+
+/*
+ * NV2080_CTRL_GPU_PID_INFO
+ *
+ * This structure contains the per pid information. Each type of information
+ * retrievable via NV2080_CTRL_CMD_GET_PID_INFO is assigned a unique index
+ * below. In addition the process for which the lookup is for is also defined.
+ * This is a SMC aware call and the scope of the information gets restricted
+ * based on partition subscription.
+ * The call enforces partition subscription if SMC is enabled, and client is not
+ * a monitoring client.
+ * Monitoring clients get global information without any scope based filtering.
+ * Monitoring clients are also not expected to subscribe to a partition when
+ * SMC is enabled.
+ *
+ *   pid
+ *     This parameter specifies the PID of the process for which information is
+ *     to be queried.
+ *   index
+ *     This parameter specifies the type of information being queried for the
+ *     process of interest.
+ *   result
+ *     This parameter returns the result of the instruction's execution.
+ *   data
+ *     This parameter returns the data corresponding to the information which is
+ *     being queried.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *
+ * Valid PID information indices are:
+ *
+ *   NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE
+ *     This index is used to request the amount of video memory on this GPU
+ *     allocated to the process.
+ */
+typedef struct NV2080_CTRL_GPU_PID_INFO {
+    NvU32                             pid;
+    NvU32                             index;
+    NvU32                             result;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_DATA data, 8);
+    NV2080_CTRL_SMC_SUBSCRIPTION_INFO smcSubscription;
+} NV2080_CTRL_GPU_PID_INFO;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_PID_INFO
+ *
+ * This command allows querying per-process information from the RM. Clients
+ * request information by specifying a unique informational index and the
+ * Process ID of the process in question. The result is set to indicate success
+ * and the information queried (if available) is returned in the data parameter.
+ *
+ *   pidInfoListCount
+ *     The number of valid entries in the pidInfoList array.
+ *   pidInfoList
+ *     An array of NV2080_CTRL_GPU_PID_INFO of maximum length
+ *     NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_PID_INFO       (0x2080018eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID" */
+
+/* max size of pidInfoList */
+#define NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT 200U
+
+#define NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID (0x8EU)
+
+typedef struct NV2080_CTRL_GPU_GET_PID_INFO_PARAMS {
+    NvU32 pidInfoListCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO pidInfoList[NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT], 8);
+} NV2080_CTRL_GPU_GET_PID_INFO_PARAMS;
+
+
+
+/*!
+ * NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT
+ *
+ * @brief Handle VF PRI faults
+ *
+ *   faultType
+ *     BAR1, BAR2, PHYSICAL or UNBOUND_INSTANCE
+ *
+ * Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_NOT_SUPPORTED
+ *
+ */
+
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT                       (0x20800192U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID          0U
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1             1U
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2             2U
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL         3U
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE 4U
+
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID (0x92U)
+
+typedef struct NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS {
+    NvU32 faultType;
+} NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS;
+
+
+/*!
+ * Compute policy types to be specified by callers to set a config.
+ *
+ * _TIMESLICE
+ *     Set the timeslice config for the requested GPU.
+ *     Check @ref NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE for
+ *     permissible timeslice values.
+ */
+#define NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE      0U
+#define NV2080_CTRL_GPU_COMPUTE_POLICY_MAX            1U
+
+/*!
+ * Enum consisting of permissible timeslice options that can configured
+ * for a GPU. These can be queried by compute clients and the exact
+ * timeslice values can be chosen appropriately as per GPU support
+ */
+typedef enum NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE {
+    NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = 0,
+    NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = 1,
+    NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = 2,
+    NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = 3,
+    NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = 4,
+} NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE;
+
+typedef struct NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG {
+    /*!
+     * NV2080_CTRL_GPU_COMPUTE_POLICY_<xyz>
+     */
+    NvU32 type;
+
+    /*!
+     * Union of type-specific data
+     */
+    union {
+        NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE timeslice;
+    } data;
+} NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG;
+
+#define NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x94U)
+
+typedef struct NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS {
+    NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG config;
+} NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG
+ *
+ * This command retrieves all compute policies configs for the associated gpu.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG  (0x20800195U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID" */
+
+/*!
+ * This define limits the max number of policy configs that can be handled by
+ * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG command.
+ *
+ * @note Needs to be in sync (greater or equal) to NV2080_CTRL_GPU_COMPUTE_POLICY_MAX.
+ */
+
+#define NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX 32U
+
+#define NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x95U)
+
+typedef struct NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS {
+    NvU32                                 numConfigs;
+
+    /*!
+     * C form:
+     * NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX];
+     */
+    NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX];
+} NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_GFID
+ *
+ * This command returns the GFID (GPU Function ID) for a given SR-IOV
+ * Virtual Function (VF) of the physical GPU.
+ *
+ *   domain [IN]
+ *     This field specifies the respective domain of the PCI device.
+ *   bus [IN]
+ *     This field specifies the bus id for a given VF.
+ *   device [IN]
+ *     This field specifies the device id for a given VF.
+ *   func [IN]
+ *     This field specifies the function id for a given VF.
+ *   gfid[OUT]
+ *      - This field returns GFID for a given VF BDF.
+ *   gfidMask[OUT]
+ *      - This field returns GFID mask value.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_GFID (0x20800196U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID (0x96U)
+
+typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS {
+    NvU32 domain;
+    NvU8  bus;
+    NvU8  device;
+    NvU8  func;
+    NvU32 gfid;
+    NvU32 gfidMask;
+} NV2080_CTRL_GPU_GET_GFID_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY
+ *
+ * This command informs the GPU driver that the GPU partition associated with
+ * a given GFID has been activated or will be deactivated.
+ *
+ *   gfid[IN]
+ *      - The GPU function identifier for a given VF BDF
+ *   bEnable [IN]
+ *      - Set to NV_TRUE if the GPU partition has been activated.
+ *      - Set to NV_FALSE if the GPU partition will be deactivated.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+
+#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY (0x20800197U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID (0x97U)
+
+typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS {
+    NvU32  gfid;
+    NvBool bEnable;
+} NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST
+ *
+ * @brief Validate the address range for memory map request by comparing the
+ *        user supplied address range with GPU BAR0/BAR1 range.
+ *
+ * @param[in]   addressStart    Start address for memory map request
+ * @param[in]   addressLength   Length for for memory map request
+ * @param[out]  protection      NV_PROTECT_READ_WRITE, if both read/write is allowed
+ *                              NV_PROTECT_READABLE, if only read is allowed
+ *
+ * Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_PROTECTION_FAULT
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST (0x20800198U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID (0x98U)
+
+typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 addressStart, 8);
+    NV_DECLARE_ALIGNED(NvU64 addressLength, 8);
+    NvU32 protection;
+} NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES
+ *
+ * This command is used to retrieve the load time (latency) of each engine.
+ *
+ *   engineCount
+ *     This field specifies the number of entries of the following
+ *     three arrays.
+ *
+ *   engineList[NV2080_GPU_MAX_ENGINE_OBJECTS]
+ *     An array of NvU32 which stores each engine's descriptor.
+ *
+ *   engineStateLoadTime[NV2080_GPU_MAX_ENGINE_OBJECTS]
+ *     A array of NvU64 which stores each engine's load time.
+ *
+ *   engineIsInit[NV2080_GPU_MAX_ENGINE_OBJECTS]
+ *     A array of NvBool which stores each engine's initialization status.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS        0xA0U
+
+#define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS {
+    NvU32  engineCount;
+    NvU32  engineList[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS];
+    NV_DECLARE_ALIGNED(NvU64 engineStateLoadTime[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS], 8);
+    NvBool engineIsInit[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS];
+} NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING
+ *
+ * This command is used to retrieve the mapping of engine ID and engine Name.
+ *
+ *   engineCount
+ *     This field specifies the size of the mapping.
+ *
+ *   engineID
+ *     An array of NvU32 which stores each engine's descriptor.
+ *
+ *   engineName
+ *     An array of char[100] which stores each engine's name.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING (0x2080019cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID (0x9CU)
+
+typedef struct NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS {
+    NvU32 engineCount;
+    NvU32 engineID[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS];
+    char  engineName[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS][100];
+} NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS
+ *
+ * Same as above NV2080_CTRL_CMD_GPU_EXEC_REG_OPS except that this CTRL CMD will
+ * not allow any embedded pointers. The regOps array is inlined as part of the
+ * struct.
+ * NOTE: This intended for gsp plugin only as it may override regOp access
+ *       restrictions
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS (0x2080019dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID" */
+
+/* setting this to 100 keeps it right below 4k in size */
+#define NV2080_CTRL_REG_OPS_ARRAY_MAX           100U
+#define NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID (0x9DU)
+
+typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS {
+    NvHandle               hClientTarget;
+    NvHandle               hChannelTarget;
+    NvU32                  bNonTransactional;
+    NvU32                  reserved00[2];
+    NvU32                  regOpCount;
+    NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_REG_OPS_ARRAY_MAX];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS;
+
+
+
+
+/*!
+ * NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO
+ *
+ * [in/out] gpuId
+ *   GPU ID for which the capabilities are queried.
+ *   For the NV2080_CTRL_CMD_GET_P2P_CAPS control:
+ *     If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to
+ *     the GPU ID of an attached GPU.
+ *     If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester
+ *     should set it to the ID of the GPU that needs to be queried from.
+ * [in] gpuUuid
+ *   Alternative to gpuId; used to identify target GPU for which caps are being queried.
+ *   Option only available for Guest RPCs.
+ *     If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU.
+ *     If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default.
+ *     If bAllCaps == NV_TRUE, gpuUuid is ignored.
+ * [out] p2pCaps
+ *   Peer to peer capabilities discovered between the GPUs.
+ *   See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values.
+ * [out] p2pOptimalReadCEs
+ *   Mask of CEs to use for p2p reads over Nvlink.
+ * [out] p2pOptimalWriteCEs
+ *   Mask of CEs to use for p2p writes over Nvlink.
+ * [out] p2pCapsStatus
+ *   Status of all supported p2p capabilities.
+ *   See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values.
+ * [out] busPeerId
+ *   Bus peer ID. For an invalid or a non-existent peer this field
+ *   has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
+ */
+#define NV2080_GET_P2P_CAPS_UUID_LEN         16U
+
+typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO {
+    NvU32 gpuId;
+    NvU8  gpuUuid[NV2080_GET_P2P_CAPS_UUID_LEN];
+    NvU32 p2pCaps;
+    NvU32 p2pOptimalReadCEs;
+    NvU32 p2pOptimalWriteCEs;
+    NvU8  p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
+    NvU32 busPeerId;
+} NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO;
+
+/*!
+ * NV2080_CTRL_CMD_GET_P2P_CAPS
+ *
+ * Returns peer to peer capabilities present between GPUs.
+ * The caller must either specify bAllCaps to query the capabilities for
+ * all the attached GPUs or they must pass a valid list of GPU IDs.
+ *
+ *   [in] bAllCaps
+ *     Set to NV_TRUE to query the capabilities for all the attached GPUs.
+ *     Set to NV_FALSE and specify peerGpuCount and peerGpuCaps[].gpuId
+ *     to retrieve the capabilities only for the specified GPUs.
+ *   [in] bUseUuid
+ *     Option only available for Guest RPCs.
+ *     Set to NV_TRUE to use gpuUuid in lieu of gpuId to identify target GPU.
+ *     If bAllCaps == NV_TRUE, bUseUuid is ignored.
+ *   [in/out] peerGpuCount
+ *     The number of the peerGpuCaps entries.
+ *     If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to
+ *     the total number of the attached GPUs.
+ *     If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester
+ *     should set it to the number of the peerGpuCaps entries.
+ *   [in/out] peerGpuCaps
+ *     The array of NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO entries, describing
+ *     the peer to peer capabilities of the GPUs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount
+ *   NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuCaps[].gpuId
+ */
+#define NV2080_CTRL_CMD_GET_P2P_CAPS (0x208001a0U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0xA0U)
+
+typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS {
+    NvBool                                  bAllCaps;
+    NvBool                                  bUseUuid;
+    NvU32                                   peerGpuCount;
+    NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
+} NV2080_CTRL_GET_P2P_CAPS_PARAMS;
+
+
+
+/*!
+ * NV2080_CTRL_GPU_COMPUTE_PROFILE
+ *
+ * This structure specifies resources in an execution partition
+ *
+ *  id[OUT]
+ *      - Total Number of GPCs in this partition
+ *
+ *  computeSize[OUT]
+ *      - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile
+ *
+ *  gpcCount[OUT]
+ *      - Total Number of GPCs in this partition (including GFX Supported GPCs)
+ *
+ *  veidCount[OUT]
+ *      - Number of VEIDs allocated to this profile
+ *
+ *  smCount[OUT]
+ *      - Number of SMs usable in this profile
+ */
+typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE {
+    NvU8  computeSize;
+    NvU32 gfxGpcCount;
+    NvU32 gpcCount;
+    NvU32 veidCount;
+    NvU32 smCount;
+} NV2080_CTRL_GPU_COMPUTE_PROFILE;
+
+/*!
+ * NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
+ *
+ * This structure specifies resources in an execution partition
+ *
+ *  profileCount[OUT]
+ *      - Total Number of profiles filled
+ *
+ *  profiles[OUT]
+ *      - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles 
+ */
+#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U)
+
+typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
+    NvU32                           profileCount;
+    NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
+} NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES       (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED 0U
+#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED 1U
+#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS 2U
+#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE    3U
+
+#define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN             16U
+
+#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0)
+
+/*!
+ * NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
+ *
+ * This structure provides the GPU<-->FM probe state info on NVSwitch based
+ * systems
+ *
+ *  state[OUT]
+ *      - Current state of GPU<-->FM probe req/rsp
+ *        Following values can be returned
+ *        _UNSUPPORTED - system does not support this feature
+ *        _NOT_STARTED - probe request is not yet sent to the FM
+ *        _IN_PROGRESS - probe response is not yet received
+ *        _COMPLETE    - probe response is received
+ *        When state is NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE
+ *        status has to be checked for probe response success/failure
+ *  status[OUT]
+ *      - Inband Probe response status
+ *        A GPU which returns NV_OK status upon receiving the probe response
+ *        can participate in P2P
+ *  clusterUuid[OUT]
+ *      - Uuid of the cluster to which this node belongs
+ *  fabricPartitionId[OUT]
+ *      - Fabric partition Id
+ *  fabricCaps[OUT]
+ *      - Summary of fabric capabilities received from probe resp
+ *        Possible values are
+ *            NV2080_CTRL_GPU_FABRIC_PROBE_CAP_*
+ */
+#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U)
+
+typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
+    NvU8      state;
+    NV_STATUS status;
+    NvU8      clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN];
+    NvU16     fabricPartitionId;
+    NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8);
+} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS
+ * 
+ * This command retrieves and constructs the GPU partnumber from the VBIOS.
+ * 
+ * The following data are currently supported:
+ * 
+ * pciDevId
+ *    The PCI device ID
+ *
+ * chipSku
+ *    The chip SKU information
+ *
+ * chipMajor
+ *    The chip major number
+ *
+ * chipMinor
+ *    The chip minor number
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS      (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */
+
+/* 
+ * The string format for a GPU part number 
+ * The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string,
+ * the chip major number, and then the chip minor number.
+ * Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS
+ * struct fields.
+ */
+#define GPU_PART_NUMBER_FMT "%04X-%s-%X%X"
+
+/* The maximum length for the chip sku */
+#define NV2080_MAX_CHIP_SKU_LENGTH                0x00000004U
+
+#define NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID (0xA4U)
+
+typedef struct NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS {
+    NvU32 pciDevId;
+    NvU8  chipSku[NV2080_MAX_CHIP_SKU_LENGTH];
+    NvU32 chipMajor;
+    NvU32 chipMinor;
+} NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP
+ *
+ * This command returns the host hardware defined engine ID of the specified engine(s).
+ *
+ *   swizzId[IN]
+ *       - HW Partition ID associated with the requested partition.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP (0x208001a5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID (0xA5U)
+
+typedef struct NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS {
+    NvU32 swizzId;
+} NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS      (0x208001a6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP  (0x208001a7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU (0x208001a8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID" */
+
+/* setting this to 100 keeps it right below 4k in size */
+#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX    50U
+typedef struct NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS {
+    NvHandle               hClientTarget;
+    NvHandle               hChannelTarget;
+    NvU32                  bNonTransactional;
+    NvU32                  regOpCount;
+    NvU32                  smIds[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX];
+    NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS;
+
+#define NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID (0xA6U)
+
+typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS;
+#define NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID (0xA7U)
+
+typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS;
+#define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U)
+
+typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS;
+/* _ctrl2080gpu_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h
new file mode 100644
index 0000000..742b21a
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h
@@ -0,0 +1,96 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn
+//
+
+
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/*!
+ *  This structure represents base class of GPU monitoring sample.
+ */
+typedef struct NV2080_CTRL_GPUMON_SAMPLE {
+    /*!
+    * Timestamps in nano-seconds. 
+    */
+    NV_DECLARE_ALIGNED(NvU64 timeStamp, 8);
+} NV2080_CTRL_GPUMON_SAMPLE;
+
+/*!
+ *  This structure represents base GPU monitoring sample.
+ */
+typedef struct NV2080_CTRL_GPUMON_SAMPLES {
+    /*!
+    * Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference. 
+    */
+    NvU8  type;
+    /*!
+    * Size of the buffer, this should be
+    * bufSize ==  NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_*
+    *    sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE).
+    */
+    NvU32 bufSize;
+    /*!
+    * Number of samples in ring buffer.
+    */
+    NvU32 count;
+    /*!
+    * tracks the offset of the tail in the circular queue array pSamples.
+    */
+    NvU32 tracker;
+    /*!
+    * Pointer to a circular queue based on array of NV2080_CTRL_GPUMON_SAMPLE
+    * or its derived types structs with size == bufSize.
+    *
+    * @note This circular queue wraps around after 10 seconds of sampling,
+    * and it is clients' responsibility to query within this time frame in
+    * order to avoid losing samples.
+    * @note With one exception, this queue contains last 10 seconds of samples
+    * with tracker poiniting to oldest entry and entry before tracker as the
+    * newest entry. Exception is when queue is not full (i.e. tracker is
+    * pointing to a zeroed out entry), in that case valid entries are between 0
+    * and tracker.
+    * @note Clients can store tracker from previous query in order to provide
+    * samples since last read.
+    */
+    NV_DECLARE_ALIGNED(NvP64 pSamples, 8);
+} NV2080_CTRL_GPUMON_SAMPLES;
+
+/*!
+ * Enumeration of GPU monitoring sample types.
+ */
+#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS 0x00000001
+#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL       0x00000002
+
+/*!
+ * Macro for invalid PID.
+ */
+#define NV2080_GPUMON_PID_INVALID         ((NvU32)(~0))
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
new file mode 100644
index 0000000..dde6eed
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
@@ -0,0 +1,1820 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080gr.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+#include "ctrl/ctrl0080/ctrl0080gr.h"        /* 2080 is partially derivative of 0080 */
+#include "nvcfg_sdk.h"
+
+/*
+ * NV2080_CTRL_GR_ROUTE_INFO
+ *
+ * This structure specifies the routing information used to
+ * disambiguate the target GR engine.
+ *
+ *   flags
+ *     This field decides how the route field is interpreted
+ *
+ *   route
+ *     This field has the data to identify target GR engine
+ *
+ */
+#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE                 1:0
+#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE    0x0U
+#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID   0x1U
+#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL 0x2U
+
+#define NV2080_CTRL_GR_ROUTE_INFO_DATA_CHANNEL_HANDLE      31:0
+#define NV2080_CTRL_GR_ROUTE_INFO_DATA_ENGID               31:0
+
+typedef NV0080_CTRL_GR_ROUTE_INFO NV2080_CTRL_GR_ROUTE_INFO;
+
+/* NV20_SUBDEVICE_XX gr control commands and parameters */
+
+/*
+ * NV2080_CTRL_GR_INFO
+ *
+ * This structure represents a single 32bit gr engine value.  Clients
+ * request a particular gr engine value by specifying a unique gr
+ * information index.
+ *
+ * Legal gr information index values are:
+ *   NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT
+ *     This index is used to request the surface buffer alignment (in bytes)
+ *     required by the associated subdevice.  The return value is GPU
+ *     implementation-dependent.
+ *   NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT
+ *     This index is used to request the required swizzled surface alignment
+ *     (in bytes) supported by the associated subdevice.  The return value
+ *     is GPU implementation-dependent.  A return value of 0 indicates the GPU
+ *     does not support swizzled surfaces.
+ *   NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE
+ *     This index is used to request the vertex cache size (in entries)
+ *     supported by the associated subdevice.  The return value is GPU
+ *     implementation-dependent.  A value of 0 indicates the GPU does
+ *     have a vertex cache.
+ *   NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT
+ *     This index is used to request the number of VPE units supported by the
+ *     associated subdevice.  The return value is GPU implementation-dependent.
+ *     A return value of 0 indicates the GPU does not contain VPE units.
+ *   NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT
+ *     This index is used to request the number of shader pipes supported by
+ *     the associated subdevice.  The return value is GPU
+ *     implementation-dependent.  A return value of 0 indicates the GPU does
+ *     not contain dedicated shader units.
+ *     For tesla: this value is the number of enabled TPCs
+ *   NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT
+ *     This index is used to request the number of sub units per
+ *     shader pipes supported by the associated subdevice.  The return
+ *     value is GPU implementation-dependent.  A return value of 0 indicates
+ *     the GPU does not contain dedicated shader units.
+ *     For tesla: this value is the number of enabled SMs (per TPC)
+ *   NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR
+ *     This index is used to request the scaling factor for thread stack
+ *     memory.
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT
+ *     This index is used to request the number of SM register banks supported.
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT
+ *     This index is used to request the number of registers per SM register
+ *     bank. A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_SM_VERSION
+ *     This index is used to determine the SM version.
+ *     A value of 0 indicates the GPU does not support this function.
+ *     Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*.
+ *   NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM
+ *     This index is used to determine the maximum number of warps
+ *     (thread groups) per SM.
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP
+ *     This index is used to determine the maximum number of threads
+ *     in each warp (thread group).
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY
+ *     This index is used to request the default fb memory read/write request
+ *     size in bytes (typically based on the memory configuration/controller).
+ *     Smaller memory requests are likely to take as long as a full one.
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY
+ *     This index is used to request the default host memory read/write request
+ *     size in bytes (typically based on the memory configuration/controller).
+ *     Smaller memory requests are likely to take as long as a full one.
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM
+ *     This index is used to request the maximum number of streaming processors
+ *     per SM.
+ *   NV2080_CTRL_GR_INFO_INDEX_LITTER_*
+ *     This index is used to query the various LITTER size information from
+ *     the chip.
+ *   NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED
+ *     This index is used to query whether the chip has timeslice mode enabled.
+ *   NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT
+ *     This index is used to return the number of "GPU Cores"
+ *     supported by the graphics pipeline
+ *   NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT
+ *     This index is used to return the number of "Ray Tracing Cores"
+ *     supported by the graphics pipeline
+ *    NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
+ *     This index is used to return the number of "Tensor Cores"
+ *     supported by the graphics pipeline
+ */
+typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
+
+/*
+ * Valid GR info index values
+ * These indices are offset from supporting the 0080 version of this call
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS                          NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
+#define NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894              NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
+#define NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK                 NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK
+/**
+ * This index is used to request the surface buffer alignment (in bytes)
+ * required by the associated subdevice.  The return value is GPU
+ * implementation-dependent.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT                  NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT
+#define NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT                 NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT
+#define NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE                 NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE
+/**
+ * This index is used to request the number of VPE units supported by the
+ * associated subdevice.  The return value is GPU implementation-dependent.
+ * A return value of 0 indicates the GPU does not contain VPE units.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT                         NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT
+/**
+ * This index is used to request the number of shader pipes supported by
+ * the associated subdevice.  The return value is GPU
+ * implementation-dependent.  A return value of 0 indicates the GPU does
+ * not contain dedicated shader units.
+ * For tesla: this value is the number of enabled TPCs
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT                 NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT
+/**
+ * This index is used to request the scaling factor for thread stack
+ * memory.
+ * A value of 0 indicates the GPU does not support this function.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR       NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR
+/**
+ * This index is used to request the number of sub units per
+ * shader pipes supported by the associated subdevice.  The return
+ * value is GPU implementation-dependent.  A return value of 0 indicates
+ * the GPU does not contain dedicated shader units.
+ * For tesla: this value is the number of enabled SMs (per TPC)
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT             NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT                 NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT             NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT
+/**
+ * This index is used to determine the SM version.
+ * A value of 0 indicates the GPU does not support this function.
+ * Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_SM_VERSION                        NV0080_CTRL_GR_INFO_INDEX_SM_VERSION
+/**
+ * This index is used to determine the maximum number of warps
+ * (thread groups) per SM.
+ * A value of 0 indicates the GPU does not support this function.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM                  NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM
+/**
+ * This index is used to determine the maximum number of threads
+ * in each warp (thread group).
+ * A value of 0 indicates the GPU does not support this function.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP              NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP
+#define NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES              NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES
+#define NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES                 NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES
+#define NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY     NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY
+#define NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY   NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM                     NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS                   NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS                   NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS            NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC            NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS               NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS        NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS
+#define NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED                 NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS                  NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC            NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT                    NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES           NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS        NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC             NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS        NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS
+/**
+ * This index is used to return the number of "Ray Tracing Cores"
+ * supported by the graphics pipeline
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT                     NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT                 NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS                    NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS                   NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES             NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC         NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP            NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC            NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC            NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP           NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT              NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT       NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT   NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS         NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS              NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC         NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
+
+/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly
+ * NOTE: 0080 functionality is merged with 2080 functionality, so this max size
+ * reflects that.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_MAX                               NV0080_CTRL_GR_INFO_INDEX_MAX
+#define NV2080_CTRL_GR_INFO_MAX_SIZE                                NV0080_CTRL_GR_INFO_MAX_SIZE
+
+/* valid SM version return values */
+
+#define NV2080_CTRL_GR_INFO_SM_VERSION_NONE                         (0x00000000U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_05                         (0x00000105U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_1                          (0x00000110U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_2                          (0x00000120U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_3                          (0x00000130U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_4                          (0x00000140U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_5                          (0x00000150U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_2_0                          (0x00000200U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_2_1                          (0x00000210U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_2_2                          (0x00000220U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_0                          (0x00000300U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_1                          (0x00000310U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_2                          (0x00000320U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_3                          (0x00000330U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_5                          (0x00000350U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_6                          (0x00000360U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_8                          (0x00000380U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_9                          (0x00000390U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_4_0                          (0x00000400U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_5_0                          (0x00000500U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_5_02                         (0x00000502U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_5_03                         (0x00000503U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_6_0                          (0x00000600U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_6_01                         (0x00000601U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_6_02                         (0x00000602U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_0                          (0x00000700U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_01                         (0x00000701U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_02                         (0x00000702U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_03                         (0x00000703U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_05                         (0x00000705U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_02                         (0x00000802U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_06                         (0x00000806U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_07                         (0x00000807U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08                         (0x00000808U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09                         (0x00000809U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00                         (0x00000900U)
+
+
+
+/* compatibility SM versions to match the official names in the ISA (e.g., SM5.2)  */
+#define NV2080_CTRL_GR_INFO_SM_VERSION_5_2                          (NV2080_CTRL_GR_INFO_SM_VERSION_5_02)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_5_3                          (NV2080_CTRL_GR_INFO_SM_VERSION_5_03)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_6_1                          (NV2080_CTRL_GR_INFO_SM_VERSION_6_01)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_6_2                          (NV2080_CTRL_GR_INFO_SM_VERSION_6_02)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_1                          (NV2080_CTRL_GR_INFO_SM_VERSION_7_01)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_2                          (NV2080_CTRL_GR_INFO_SM_VERSION_7_02)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_3                          (NV2080_CTRL_GR_INFO_SM_VERSION_7_03)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_5                          (NV2080_CTRL_GR_INFO_SM_VERSION_7_05)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_2                          (NV2080_CTRL_GR_INFO_SM_VERSION_8_02)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_6                          (NV2080_CTRL_GR_INFO_SM_VERSION_8_06)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_7                          (NV2080_CTRL_GR_INFO_SM_VERSION_8_07)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8                          (NV2080_CTRL_GR_INFO_SM_VERSION_8_08)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9                          (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0                          (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
+
+
+
+/**
+ * NV2080_CTRL_CMD_GR_GET_INFO
+ *
+ * This command returns gr engine information for the associated GPU.
+ * Requests to retrieve gr information use a list of one or more
+ * NV2080_CTRL_GR_INFO structures.
+ *
+ *   grInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     grInfoList.
+ *   grInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the gr information is to be returned.
+ *     This buffer must be at least as big as grInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_GR_INFO structure.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine. When MIG is enabled, this
+ *     is a mandatory parameter.
+ */
+#define NV2080_CTRL_CMD_GR_GET_INFO                                 (0x20801201U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_GR_GET_INFO_PARAMS {
+    NvU32 grInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 grInfoList, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_GET_INFO_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE
+ *
+ * This command is used to set the zcull context switch mode for the specified
+ * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the
+ * target channel does not support zcull context switch mode changes.
+ *
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have it's zcull context switch mode changed.
+ *   hShareClient
+ *     Support for sharing zcull buffers across RM clients is no longer
+ *     supported.  To maintain API compatibility, this field must match
+ *     the hClient used in the control call.
+ *   hShareChannel
+ *     This parameter specifies the channel handle of
+ *     the channel with which the zcull context buffer is to be shared.  This
+ *     parameter is valid when zcullMode is set to SEPARATE_BUFFER.  This
+ *     parameter should be set to the same value as hChannel if no
+ *     sharing is intended.
+ *   zcullMode
+ *     This parameter specifies the new zcull context switch mode.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_GLOBAL
+ *         This mode is the normal zcull operation where it is not
+ *         context switched and there is one set of globally shared
+ *         zcull memory and tables.  This mode is only supported as
+ *         long as all channels use this mode.
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_NO_CTXSW
+ *         This mode causes the zcull tables to be reset on a context
+ *         switch, but the zcull buffer will not be saved/restored.
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_SEPARATE_BUFFER
+ *         This mode will cause the zcull buffers and tables to be
+ *         saved/restored on context switches.  If a share channel
+ *         ID is given (shareChID), then the 2 channels will share
+ *         the zcull context buffers.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x5" */
+
+typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS {
+    NvHandle hChannel;
+    NvHandle hShareClient;
+    NvHandle hShareChannel;
+    NvU32    zcullMode;
+} NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS;
+/* valid zcullMode values */
+#define NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL          (0x00000000U)
+#define NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW        (0x00000001U)
+#define NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER (0x00000002U)
+
+/**
+ * NV2080_CTRL_CMD_GR_GET_ZCULL_INFO
+ *
+ * This command is used to query the RM for zcull information that the
+ * driver will need to allocate and manage the zcull regions.
+ *
+ *   widthAlignPixels
+ *     This parameter returns the width alignment restrictions in pixels
+ *     used to adjust a surface for proper aliquot coverage (typically
+ *     #TPC's * 16).
+ *
+ *   heightAlignPixels
+ *     This parameter returns the height alignment restrictions in pixels
+ *     used to adjust a surface for proper aliquot coverage (typically 32).
+ *
+ *   pixelSquaresByAliquots
+ *     This parameter returns the pixel area covered by an aliquot
+ *     (typically #Zcull_banks * 16 * 16).
+ *
+ *   aliquotTotal
+ *     This parameter returns the total aliquot pool available in HW.
+ *
+ *   zcullRegionByteMultiplier
+ *     This parameter returns multiplier used to convert aliquots in a region
+ *     to the number of bytes required to save/restore them.
+ *
+ *   zcullRegionHeaderSize
+ *     This parameter returns the region header size which is required to be
+ *     allocated and accounted for in any save/restore operation on a region.
+ *
+ *   zcullSubregionHeaderSize
+ *     This parameter returns the subregion header size which is required to be
+ *     allocated and accounted for in any save/restore operation on a region.
+ *
+ *   subregionCount
+ *     This parameter returns the subregion count.
+ *
+ *   subregionWidthAlignPixels
+ *     This parameter returns the subregion width alignment restrictions in
+ *     pixels used to adjust a surface for proper aliquot coverage
+ *     (typically #TPC's * 16).
+ *
+ *   subregionHeightAlignPixels
+ *     This parameter returns the subregion height alignment restrictions in
+ *     pixels used to adjust a surface for proper aliquot coverage
+ *     (typically 62).
+ *
+ *   The callee should compute the size of a zcull region as follows.
+ *     (numBytes = aliquots * zcullRegionByteMultiplier +
+ *                 zcullRegionHeaderSize + zcullSubregionHeaderSize)
+ */
+#define NV2080_CTRL_CMD_GR_GET_ZCULL_INFO            (0x20801206U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED
+#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS {
+    NvU32 widthAlignPixels;
+    NvU32 heightAlignPixels;
+    NvU32 pixelSquaresByAliquots;
+    NvU32 aliquotTotal;
+    NvU32 zcullRegionByteMultiplier;
+    NvU32 zcullRegionHeaderSize;
+    NvU32 zcullSubregionHeaderSize;
+    NvU32 subregionCount;
+    NvU32 subregionWidthAlignPixels;
+    NvU32 subregionHeightAlignPixels;
+} NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_PM_MODE
+ *
+ * This command is used to set the pm context switch mode for the specified
+ * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the
+ * target channel does not support pm context switch mode changes.
+ *
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have its pm context switch mode changed.
+ *   pmMode
+ *     This parameter specifies the new pm context switch mode.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW
+ *         This mode says that the pms are not to be context switched.
+ *       NV2080_CTRL_CTXSW_PM_MODE_CTXSW
+ *         This mode says that the pms in Mode-B are to be context switched.
+ *       NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW
+ *         This mode says that the pms in Mode-E (stream out) are to be context switched.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */
+
+typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS {
+    NvHandle hChannel;
+    NvU32    pmMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS;
+
+/* valid pmMode values */
+#define NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW         (0x00000000U)
+#define NV2080_CTRL_CTXSW_PM_MODE_CTXSW            (0x00000001U)
+#define NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW (0x00000002U)
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND
+ *
+ * This command is used to set the zcull context switch mode and virtual address
+ * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is
+ * returned if the target channel does not support zcull context switch mode
+ * changes.
+ *
+ *   hClient
+ *     This parameter specifies the client handle of
+ *     that owns the zcull context buffer. This field must match
+ *     the hClient used in the control call for non-kernel clients.
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have its zcull context switch mode changed.
+ *   vMemPtr
+ *     This parameter specifies the 64 bit virtual address
+ *     for the allocated zcull context buffer.
+ *   zcullMode
+ *     This parameter specifies the new zcull context switch mode.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_GLOBAL
+ *         This mode is the normal zcull operation where it is not
+ *         context switched and there is one set of globally shared
+ *         zcull memory and tables.  This mode is only supported as
+ *         long as all channels use this mode.
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_NO_CTXSW
+ *         This mode causes the zcull tables to be reset on a context
+ *         switch, but the zcull buffer will not be saved/restored.
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_SEPARATE_BUFFER
+ *         This mode will cause the zcull buffers and tables to be
+ *         saved/restored on context switches.  If a share channel
+ *         ID is given (shareChID), then the 2 channels will share
+ *         the zcull context buffers.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND        (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */
+
+typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS {
+    NvHandle hClient;
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8);
+    NvU32    zcullMode;
+} NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS;
+/* valid zcullMode values same as above NV2080_CTRL_CTXSW_ZCULL_MODE */
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_PM_BIND
+ *
+ * This command is used to set the PM context switch mode and virtual address
+ * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is
+ * returned if the target channel does not support PM context switch mode
+ * changes.
+ *
+ *   hClient
+ *     This parameter specifies the client handle of
+ *     that owns the PM context buffer.
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have its PM context switch mode changed.
+ *   vMemPtr
+ *     This parameter specifies the 64 bit virtual address
+ *     for the allocated PM context buffer.
+ *   pmMode
+ *     This parameter specifies the new PM context switch mode.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_GR_SET_CTXSW_PM_MODE_NO_CTXSW
+ *         This mode says that the pms are not to be context switched
+ *       NV2080_CTRL_GR_SET_CTXSW_PM_MODE_CTXSW
+ *         This mode says that the pms are to be context switched
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x9" */
+
+typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS {
+    NvHandle hClient;
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8);
+    NvU32    pmMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS;
+/* valid pmMode values same as above NV2080_CTRL_CTXSW_PM_MODE */
+
+/*
+ * NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP
+ *
+ * Send a list of values used to describe GPC/TPC tile mapping tables.
+ *
+ *   mapValueCount
+ *     This field specifies the number of actual map entries.  This count
+ *     should equal the number of TPCs in the system.
+ *   mapValues
+ *     This field is a pointer to a buffer of NvU08 values representing map
+ *     data.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES 128U
+#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP        (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xA" */
+
+typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS {
+    NvU32 mapValueCount;
+    NvU8  mapValues[NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE
+ *
+ * This command is used to set the SMPC context switch mode for the specified
+ * channel or channel group (TSG). A value of NV_ERR_NOT_SUPPORTED
+ * is returned if the target channel/TSG does not support SMPC context switch
+ * mode changes.  If a channel is part of a TSG, the user must send in the TSG
+ * handle and not an individual channel handle, an error will be returned if a
+ * channel handle is used in this case.
+ *
+ * SMPC = SM Performance Counters
+ *
+ *   hChannel
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *     that is to have its SMPC context switch mode changed.
+ *     If this parameter is set to 0, then the mode below applies to all current
+ *     and future channels (i.e. we will be enabling/disabling global mode)
+ *   smpcMode
+ *     This parameter specifies the new SMPC context switch mode.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_GR_SET_CTXSW_SMPC_MODE_NO_CTXSW
+ *         This mode says that the SMPC data is not to be context switched.
+ *       NV2080_CTRL_GR_SET_CTXSW_SMPC_MODE_CTXSW
+ *         This mode says that the SMPC data is to be context switched.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xE" */
+
+typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS {
+    NvHandle hChannel;
+    NvU32    smpcMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS;
+
+/* valid smpcMode values */
+#define NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW                   (0x00000000U)
+#define NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW                      (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
+ *
+ * This command returns an array of the mappings between SMs and GPC/TPCs.
+ *
+ *   smId
+ *     An array of the mappings between SMs and GPC/TPCs.
+ *   smCount
+ *     Returns the number of valid mappings in the array.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS          (0x2080120fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT 144U
+#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS {
+    struct {
+        NvU32 gpcId;
+        NvU32 tpcId;
+    } smId[NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT];
+    NvU32 smCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE
+ *
+ * This command is used to set the preemption context switch mode for the specified
+ * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the
+ * target channel does not support preemption context switch mode changes.
+ *
+ *   flags
+ *     This field specifies flags for the preemption mode changes.
+ *     These flags can tell callee which mode is valid in the call
+ *     since we handle graphics and/or compute
+ *   hChannel
+ *     This parameter specifies the channel handle of the channel
+ *     that is to have it's preemption context switch mode set.
+ *   gfxpPreemptMode
+ *     This parameter specifies the new Graphics preemption context switch
+ *     mode. Legal values for this parameter include:
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI
+ *         This mode is the normal wait-for-idle context switch mode.
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP
+ *         This mode causes the graphics engine to allow preempting the
+ *         channel mid-triangle.
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL
+ *         This mode causes the graphics engine to use a shared pool of buffers
+ *         to support GfxP with lower memory overhead
+ *   cilpPreemptMode
+ *     This parameter specifies the new Compute preemption context switch
+ *     mode. Legal values for this parameter include:
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI
+ *         This mode is the normal wait-for-idle context switch mode.
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA
+ *         This mode causes the compute engine to allow preempting the channel
+ *         at the instruction level.
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP
+ *         This mode causes the compute engine to allow preempting the channel
+ *         at the instruction level.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x10" */
+
+typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS {
+    NvU32    flags;
+    NvHandle hChannel;
+    NvU32    gfxpPreemptMode;
+    NvU32    cilpPreemptMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS;
+
+/* valid preemption flags */
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP                0:0
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE (0x00000000U)
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET    (0x00000001U)
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP                1:1
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE (0x00000000U)
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET    (0x00000001U)
+
+/* valid Graphics mode values */
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI              (0x00000000U)
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP             (0x00000001U)
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL        (0x00000002U)
+
+/* valid Compute mode values */
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI          (0x00000000U)
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA          (0x00000001U)
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP         (0x00000002U)
+
+/* valid preemption buffers */
+typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS {
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = 0,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = 1,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = 2,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = 3,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = 4,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 8,
+} NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS;
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND
+ *
+ * This command is used to set the preemption context switch mode and virtual
+ * addresses of the preemption buffers for the specified channel. A value of
+ * NV_ERR_NOT_SUPPORTED is returned if the target channel does not
+ * support preemption context switch mode changes.
+ *
+ *   flags
+ *     This field specifies flags for the preemption mode changes.
+ *     These flags can tell callee which mode is valid in the call
+ *     since we handle graphics and/or compute
+ *   hClient
+ *     This parameter specifies the client handle of
+ *     that owns the preemption context buffer.
+ *   hChannel
+ *     This parameter specifies the channel handle of the channel
+ *     that is to have its preemption context switch mode set.
+ *   vMemPtr
+ *     This parameter specifies the 64 bit virtual address
+ *     for the allocated preemption context buffer.
+ *   gfxpPreemptMode
+ *     This parameter specifies the new Graphics preemption context switch
+ *     mode. Legal values for this parameter include:
+ *       NV2080_CTRL_CTXSW_PREEMPTION_MODE_GFX_WFI
+ *         This mode is the normal wait-for-idle context switch mode.
+ *       NV2080_CTRL_CTXSW_PREEMPTION_MODE_GFX_GFXP
+ *         This mode causes the graphics engine to allow preempting the
+ *         channel mid-triangle.
+ *   cilpPreemptMode
+ *     This parameter specifies the new Compute preemption context switch
+ *     mode. Legal values for this parameter include:
+ *       NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_WFI
+ *         This mode is the normal wait-for-idle context switch mode.
+ *       NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_CTA
+ *         This mode causes the compute engine to allow preempting the channel
+ *         at the instruction level.
+ *       NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_CILP
+ *         This mode causes the compute engine to allow preempting the channel
+ *         at the instruction level.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x11" */
+
+typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS {
+    NvU32    flags;
+    NvHandle hClient;
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 vMemPtrs[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END], 8);
+    NvU32    gfxpPreemptMode;
+    NvU32    cilpPreemptMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS;
+/* valid mode and flag values same as above NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE */
+
+/*
+ * NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE
+ *
+ * This command is used to apply the WAR for PC sampling to avoid hang in
+ * multi-ctx scenario.
+ *
+ *   hChannel
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *     that is to have its PC Sampling mode changed.
+ *   samplingMode
+ *     This parameter specifies whether sampling is turned ON or OFF.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_GR_SET_PC_SAMPLING_MODE_DISABLED
+ *         This mode says that PC sampling is disabled for current context.
+ *       NV2080_CTRL_GR_SET_PC_SAMPLING_MODE_ENABLED
+ *         This mode says that PC sampling is disabled for current context.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x12" */
+
+typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS {
+    NvHandle hChannel;
+    NvU32    samplingMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS;
+
+/* valid samplingMode values */
+#define NV2080_CTRL_PC_SAMPLING_MODE_DISABLED (0x00000000U)
+#define NV2080_CTRL_PC_SAMPLING_MODE_ENABLED  (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_ROP_INFO
+ *
+ * Gets information about ROPs including the ROP unit count and information
+ * about ROP operations per clock.
+ *
+ *   ropUnitCount
+ *     The count of active ROP units.
+ *   ropOperationsFactor.
+ *     The number of ROP operations per clock for a single ROP unit.
+ *   ropOperationsCount
+ *     The number of ROP operations per clock across all active ROP units.
+ */
+#define NV2080_CTRL_CMD_GR_GET_ROP_INFO       (0x20801213U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_GR_GET_ROP_INFO_PARAMS {
+    NvU32 ropUnitCount;
+    NvU32 ropOperationsFactor;
+    NvU32 ropOperationsCount;
+} NV2080_CTRL_GR_GET_ROP_INFO_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_CTXSW_STATS
+ *
+ * This command is used to get the context switch statistics.  The user can
+ * also add a flag to tell RM to reset the stats counters back to 0.
+ *
+ *   hChannel
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *     that is to have the stats returned.  Note, must be the TSG handle if
+ *     channel is part of a TSG.
+ *   flags
+ *     This parameter specifies processing flags. See possible flags below.
+ *   saveCnt
+ *     This parameter returns the number of saves on the channel.
+ *   restoreCnt
+ *     This parameter returns the number of restores on the channel.
+ *   wfiSaveCnt
+ *     This parameter returns the number of WFI saves on the channel.
+ *   ctaSaveCnt
+ *     This parameter returns the number of CTA saves on the channel.
+ *   cilpSaveCnt
+ *     This parameter returns the number of CILP saves on the channel.
+ *   gfxpSaveCnt
+ *     This parameter returns the number of GfxP saves on the channel.
+ */
+#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x15" */
+
+typedef struct NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS {
+    NvHandle hChannel;
+    NvU32    flags;
+    NvU32    saveCnt;
+    NvU32    restoreCnt;
+    NvU32    wfiSaveCnt;
+    NvU32    ctaSaveCnt;
+    NvU32    cilpSaveCnt;
+    NvU32    gfxpSaveCnt;
+} NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS;
+/* valid GET_CTXSW_STATS flags settings */
+#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET                      0:0
+#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE (0x00000000U)
+#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE  (0x00000001U)
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE
+ *
+ * This command provides the size, alignment of all context buffers including global and
+ * local context buffers which has been created & will be mapped on a context
+ *
+ *   hChannel [IN]
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *   totalBufferSize [OUT]
+ *     This parameter returns the total context buffers size.
+ */
+#define NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE (0x20801218U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS {
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8);
+} NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS;
+
+/*
+ * NV2080_CTRL_GR_CTX_BUFFER_INFO
+ *   alignment
+ *     Specifies the alignment requirement for each context buffer
+ *   size
+ *     Aligned size of context buffer
+ *   bufferHandle [deprecated]
+ *     Opaque pointer to memdesc. Used by kernel clients for tracking purpose only.
+ *   pageCount
+ *     allocation size in the form of pageCount
+ *   physAddr
+ *     Physical address of the buffer first page
+ *   bufferType
+ *     NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID type of this buffer
+ *   aperture
+ *     allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN
+ *   kind
+ *     PTE kind of this allocation.
+ *   pageSize
+ *     Page size of the buffer.
+ *   bIsContigous
+ *     States if physical allocation for this buffer is contiguous. PageSize will
+ *     have no meaning if this flag is set.
+ *   bGlobalBuffer
+ *     States if a defined buffer is global as global buffers need to be mapped
+ *     only once in TSG.
+ *   bLocalBuffer
+ *     States if a buffer is local to a channel.
+ *   bDeviceDescendant
+ *     TRUE if the allocation is a constructed under a Device or Subdevice.
+ *   uuid
+ *     SHA1 UUID of the Device or Subdevice. Valid when deviceDescendant is TRUE.
+ */
+typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO {
+    NV_DECLARE_ALIGNED(NvU64 alignment, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8);
+    NV_DECLARE_ALIGNED(NvU64 pageCount, 8);
+    NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
+    NvU32  bufferType;
+    NvU32  aperture;
+    NvU32  kind;
+    NvU32  pageSize;
+    NvBool bIsContigous;
+    NvBool bGlobalBuffer;
+    NvBool bLocalBuffer;
+    NvBool bDeviceDescendant;
+    NvU8   uuid[16];
+} NV2080_CTRL_GR_CTX_BUFFER_INFO;
+typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO *PNV2080_CTRL_GR_CTX_BUFFER_INFO;
+
+#define NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT    64U
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO
+ *
+ * This command provides the size, alignment of all context buffers including global and
+ * local context buffers which has been created & will be mapped on a context.
+ * If the client invoking the command is a kernel client, the buffers are retained.
+ *
+ *   hUserClient [IN]
+ *     This parameter specifies the client handle that owns this channel.
+ *   hChannel [IN]
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *   bufferCount [OUT]
+ *     This parameter specifies the number of entries in ctxBufferInfo filled
+ *     by the command.
+ *   ctxBufferInfo [OUT]
+ *     Array of context buffer info containing alignment, size etc.
+ */
+#define NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO (0x20801219U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS {
+    NvHandle hUserClient;
+    NvHandle hChannel;
+    NvU32    bufferCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTX_BUFFER_INFO ctxBufferInfo[NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT], 8);
+} NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS;
+
+// Aperture flags
+#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN
+#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM
+#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
+ *     This command returns the global logical ordering of SM w.r.t GPCs/TPCs.
+ *
+ * NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS
+ *     This structure holds the TPC/SM ordering info.
+ *
+ *     gpcId
+ *         Logical GPC Id.
+ *         This is the ordering of enabled GPCs post floor sweeping.
+ *         The GPCs are numbered from 0 to N-1, where N is the enabled GPC count.
+ *
+ *     localTpcId
+ *         Local Logical TPC Id.
+ *         This is the ordering of enabled TPCs within a GPC post floor sweeping.
+ *         This ID is used in conjunction with the gpcId.
+ *         The TPCs are numbered from 0 to N-1, where N is the enabled TPC count for the given GPC.
+ *
+ *     localSmId
+ *         Local Logical SM Id.
+ *         This is the ordering of enabled SMs within a TPC post floor sweeping.
+ *         This ID is used in conjunction with the localTpcId.
+ *         The SMs are numbered from 0 to N-1, where N is the enabled SM count for the given TPC.
+ *
+ *     globalTpcId
+ *         Global Logical TPC Id.
+ *         This is the ordering of all enabled TPCs in the GPU post floor sweeping.
+ *         The TPCs are numbered from 0 to N-1, where N is the enabled TPC count across all GPCs
+ *
+ *     globalSmId
+ *         Global Logical SM Id array.
+ *         This is the global ordering of all enabled SMs in the GPU post floor sweeping.
+ *         The SMs are numbered from 0 to N-1, where N is the enabled SM count across all GPCs.
+ *
+ *     virtualGpcId
+ *         Virtual GPC Id.
+ *         This is the ordering of enabled GPCs post floor sweeping (ordered in increasing
+ *         number of TPC counts) The GPCs are numbered from 0 to N-1, where N is the
+ *         enabled GPC count and 8-23 for singleton TPC holders.
+ *
+ *     migratableTpcId
+ *         Migratable TPC Id.
+ *         This is the same as the Local Tpc Id for virtual GPC 0-8 (true physical gpcs) and 0 for
+ *         virtual gpcs 8-23 that represent singleton tpcs.
+ *
+ *     numSm
+ *         Enabled SM count across all GPCs.
+ *         This represent the valid entries in the globalSmId array
+ *
+ *     numTpc
+ *         Enabled TPC count across all GPCs.
+ *
+ *     grRouteInfo
+ *         This parameter specifies the routing information used to
+ *         disambiguate the target GR engine.
+ *
+ */
+#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER              (0x2080121bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT 512U
+
+#define NV2080_CTRL_GR_DISABLED_SM_VGPC_ID                  0xFFU
+
+#define NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x1BU)
+
+typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS {
+    struct {
+        NvU16 gpcId;
+        NvU16 localTpcId;
+        NvU16 localSmId;
+        NvU16 globalTpcId;
+        NvU16 virtualGpcId;
+        NvU16 migratableTpcId;
+    } globalSmId[NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT];
+
+    NvU16 numSm;
+    NvU16 numTpc;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS;
+
+/*
+* NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL
+*
+* This command gives current resident channel on GR engine
+*
+*   chID [OUT]
+*       RM returns current resident channel on GR engine
+*   grRouteInfo [IN]
+*       This parameter specifies the routing information used to
+*       disambiguate the target GR engine.
+*/
+#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1C" */
+
+typedef struct NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS {
+    NvU32 chID;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA
+ *
+ * This command provides the _VAT_ALARM data i.e. error and warning, counter and
+ * timestamps along with max GPC and TPC per GPC count.
+ *
+ *   smVatAlarm [OUT]
+ *     VAT Alarm data array per SM containing per GPC per TPC, counter and
+ *      timestamp values for error and warning alarms.
+ *   maxGpcCount [OUT]
+ *     This parameter returns max GPC count.
+ *   maxTpcPerGpcCount [OUT]
+ *     This parameter returns the max TPC per GPC count.
+ */
+#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT         10U
+#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT 10U
+
+#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA                  (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1D" */
+
+typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC {
+    NV_DECLARE_ALIGNED(NvU64 errorCounter, 8);
+    NV_DECLARE_ALIGNED(NvU64 errorTimestamp, 8);
+    NV_DECLARE_ALIGNED(NvU64 warningCounter, 8);
+    NV_DECLARE_ALIGNED(NvU64 warningTimestamp, 8);
+} NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC;
+
+typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC tpc[NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT], 8);
+} NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC;
+
+typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC gpc[NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT], 8);
+} NV2080_CTRL_GR_VAT_ALARM_DATA;
+
+typedef struct NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA smVatAlarm, 8);
+    NvU32 maxGpcCount;
+    NvU32 maxTpcPerGpcCount;
+} NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS;
+typedef struct NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS *PNV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE
+ *
+ * This command provides the size of GR attribute buffer.
+ *
+ *   attribBufferSize [OUT]
+ *     This parameter returns the attribute buffer size.
+ */
+#define NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE (0x2080121eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x1EU)
+
+typedef struct NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS {
+    NvU32 attribBufferSize;
+} NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE
+ *
+ * This API queries size parameters for a request maximum graphics preemption
+ * pool size.  It is only available to kernel callers
+ *
+ * NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS
+ *   struct to return the size parameters
+ *
+ *   maxSlots
+ *     Input specifying the maximum number of slots, RM will calculate the output
+ *     parameters based on this.  Must be non-zero
+ *   ctrlStructSize
+ *     Output indicating the required size in bytes of the control structure to
+ *     support a pool of maxSlots size.
+ *   ctrlStructAlign
+ *     Output indicating the required alignment of the control structure
+ *   poolSize
+ *     Output indicating the required size in bytes of the GfxP Pool.
+ *   poolAlign
+ *     Output indicating the required alignment of the GfxP Pool
+ *   slotStride
+ *     The number of bytes in each slot, i * slotStride gives the offset from the
+ *     base of the pool to a given slot
+ */
+#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1F" */
+
+typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS {
+    NvU32 maxSlots;
+    NvU32 slotStride;
+    NV_DECLARE_ALIGNED(NvU64 ctrlStructSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 ctrlStructAlign, 8);
+    NV_DECLARE_ALIGNED(NvU64 poolSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 poolAlign, 8);
+} NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE
+ *
+ * This API takes a CPU pointer to a GFxP Pool Control Structure and does the
+ * required onetime initialization.  It should be called once and only once
+ * before a pool is used.  It is only accessible to kernel callers.
+ *
+ * NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS
+ *   struct to hand in the required info to RM
+ *
+ *   pControlStructure
+ *     This input is the kernel CPU pointer to the control structure.
+ */
+#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x20" */
+
+typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
+    NvU32 maxSlots;
+} NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS;
+
+#define NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS     64U
+
+/*
+ * NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS
+ *
+ * This API adds a list of buffer slots to a given control structure.  It can
+ * only be called when no channel using the given pool is running or may become
+ * running for the duration of this call.  If more slots are added than there
+ * is room for in the control structure the behavior is undefined. It is only
+ * accessible to kernel callers.
+ *
+ * NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS
+ *
+ *   pControlStructure
+ *     This input is the kernel CPU pointer to the control structure
+ *   numSlots
+ *     This input indicates how many slots are being added and are contained in the slots parameter
+ *   slots
+ *     This input contains an array of the slots to be added to the control structure
+ */
+#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x21" */
+
+typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
+    NvU32 numSlots;
+    NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
+} NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS
+ *
+ * This API removes buffer slots from a given control structure.  It can
+ * only be called when no channel using the given pool is running or may become
+ * running for the duration of this call. It can operate in two modes, either
+ * it will a specified number of slots, or a specified list of slots.
+ *
+ * It is only accessible to kernel callers.
+ *
+ * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS_PARAMS
+ *
+ *   pControlStructure
+ *     This input is the kernel CPU pointer to the control structure
+ *   numSlots
+ *     This input indicates how many slots are being removed.  if
+ *     bRemoveSpecificSlots is true, then it also indicates how many entries in
+ *     the slots array are populated.
+ *   slots
+ *     This array is either an input or output.  If bRemoveSpecificSlots is true,
+ *     then this will contain the list of slots to remove.  If it is false, then
+ *     it will be populated by RM with the indexes of the slots that were
+ *     removed.
+ *   bRemoveSpecificSlots
+ *     This input determines which mode the call will run in.  If true the caller
+ *     will specify the list of slots they want removed, if any of those slots
+ *     are not on the freelist, the call will fail.  If false they only specify
+ *     the number of slots they want removed and RM will pick up to that
+ *     many.  If there are not enough slots on the freelist to remove the
+ *     requested amount, RM will return the number it was able to remove.
+ */
+#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x22" */
+
+typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
+    NvU32  numSlots;
+    NvU32  slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
+    NvBool bRemoveSpecificSlots;
+} NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS;
+
+
+
+#define NV2080_CTRL_CMD_GR_GET_CAPS_V2 (0x20801227U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x27U)
+
+typedef NV0080_CTRL_GR_GET_CAPS_V2_PARAMS NV2080_CTRL_GR_GET_CAPS_V2_PARAMS;
+
+#define NV2080_CTRL_CMD_GR_GET_INFO_V2 (0x20801228U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x28U)
+
+typedef NV0080_CTRL_GR_GET_INFO_V2_PARAMS NV2080_CTRL_GR_GET_INFO_V2_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_GPC_MASK
+ *
+ * This command returns a mask of enabled GPCs for the associated subdevice.
+ *
+ *    grRouteInfo[IN]
+ *      This parameter specifies the routing information used to
+ *      disambiguate the target GR engine.
+ *
+ *    gpcMask[OUT]
+ *      This parameter returns a mask of enabled GPCs. Each GPC has an ID
+ *      that's equivalent to the corresponding bit position in the mask.
+ */
+#define NV2080_CTRL_CMD_GR_GET_GPC_MASK (0x2080122aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID (0x2AU)
+
+typedef struct NV2080_CTRL_GR_GET_GPC_MASK_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32 gpcMask;
+} NV2080_CTRL_GR_GET_GPC_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_TPC_MASK
+ *
+ * This command returns a mask of enabled TPCs for a specified GPC.
+ *
+ *    grRouteInfo[IN]
+ *      This parameter specifies the routing information used to
+ *      disambiguate the target GR engine.
+ *
+ *    gpcId[IN]
+ *      This parameter specifies the GPC for which TPC information is
+ *      to be retrieved. If the GPC with this ID is not enabled this command
+ *      will return an tpcMask value of zero.
+ *
+ *    tpcMask[OUT]
+ *      This parameter returns a mask of enabled TPCs for the specified GPC.
+ *      Each TPC has an ID that's equivalent to the corresponding bit
+ *      position in the mask.
+ */
+#define NV2080_CTRL_CMD_GR_GET_TPC_MASK (0x2080122bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID (0x2BU)
+
+typedef struct NV2080_CTRL_GR_GET_TPC_MASK_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32 gpcId;
+    NvU32 tpcMask;
+} NV2080_CTRL_GR_GET_TPC_MASK_PARAMS;
+
+#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x2C" */
+
+typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2CU)
+
+typedef struct NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS params, 8);
+} NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES
+ *
+ * This command is used to provide the caller with the alignment and size
+ * of the context save region for an engine
+ *
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ *   engineId
+ *     This parameter is an input parameter specifying the engineId for which
+ *     the alignment/size is requested.
+ *   alignment
+ *     This parameter is an output parameter which will be filled in with the
+ *     minimum alignment requirement.
+ *   size
+ *     This parameter is an output parameter which will be filled in with the
+ *     minimum size of the context save region for the engine.
+ *   bInfoPopulated
+ *     This parameter will be set if alignment and size are already set with
+ *     valid values from a previous call.
+ */
+
+#define NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES (0x2080122dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x2DU)
+
+typedef struct NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32  engineId;
+    NvU32  alignment;
+    NvU32  size;
+    NvBool bInfoPopulated;
+} NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER
+ *
+ * This command provides an interface to retrieve the speed select values of
+ * various instruction types.
+ *
+ *    grRouteInfo[IN]
+ *      This parameter specifies the routing information used to
+ *      disambiguate the target GR engine.
+ *
+ *    imla0[OUT]
+ *       The current speed select for IMLA0.
+ *
+ *    fmla16[OUT]
+ *       The current speed select for FMLA16.
+ *
+ *    dp[OUT]
+ *       The current speed select for DP.
+ *
+ *    fmla32[OUT]
+ *       The current speed select for FMLA32.
+ *
+ *    ffma[OUT]
+ *       The current speed select for FFMA.
+ *
+ *    imla1[OUT]
+ *       The current speed select for IMLA1.
+ *
+ *    imla2[OUT]
+ *       The current speed select for IMLA2.
+ *
+ *    imla3[OUT]
+ *       The current speed select for IMLA3.
+ *
+ *    imla4[OUT]
+ *       The current speed select for IMLA4.
+ */
+#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER                       (0x20801230U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED          (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2   (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4   (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8   (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16  (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32  (0x5U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64  (0x6U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED         (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2  (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4  (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8  (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 (0x5U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED             (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED          (0x1U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED         (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2  (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4  (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8  (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 (0x5U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED           (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2    (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4    (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8    (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16   (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32   (0x5U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED          (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2   (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4   (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8   (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16  (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32  (0x5U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64  (0x6U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED          (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2   (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4   (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8   (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16  (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32  (0x5U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64  (0x6U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED          (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2   (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4   (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8   (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16  (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32  (0x5U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64  (0x6U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED          (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2   (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4   (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8   (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16  (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32  (0x5U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64  (0x6U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x30U)
+
+typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU8 imla0;
+    NvU8 fmla16;
+    NvU8 dp;
+    NvU8 fmla32;
+    NvU8 ffma;
+    NvU8 imla1;
+    NvU8 imla2;
+    NvU8 imla3;
+    NvU8 imla4;
+} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID
+ *
+ * *DEPRECATED* Use NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 instead
+ *
+ * This command is used to create a FECS bind-point to an event buffer that
+ * is filtered by UID.
+ *
+ *  hEventBuffer[IN]
+ *      The event buffer to bind to
+ *
+ *  recordSize[IN]
+ *      The size of the FECS record in bytes
+ *
+ *  levelOfDetail[IN]
+ *      One of NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_:
+ *          FULL: Report all CtxSw events
+ *          SIMPLE: Report ACTIVE_REGION_START and ACTIVE_REGION_END only
+ *          COMPAT: Events that KMD is interested in (for backwards compatibility)
+ *          CUSTOM: Report events in the eventFilter field
+ *      NOTE: RM may override the level-of-detail depending on the caller
+ *
+ *  eventFilter[IN]
+ *      Bitmask of events to report if levelOfDetail is CUSTOM
+ *
+ *  bAllUsers[IN]
+ *     Only report FECS CtxSw data for the current user if false, for all users if true
+ */
+
+#define NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID (0x20801231U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD {
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL = 0,
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE = 1,
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT = 2,
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM = 3,
+} NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD;
+
+#define NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID (0x31U)
+
+typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS {
+    NvHandle                            hEventBuffer;
+    NvU32                               recordSize;
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail;
+    NvU32                               eventFilter;
+    NvBool                              bAllUsers;
+} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK
+ *
+ * This command returns a mask of physical GPC Ids for the associated syspipe
+ *
+ *    physSyspipeId[IN]
+ *      This parameter specifies syspipe for which phys GPC mask is requested
+ *
+ *    gpcMask[OUT]
+ *      This parameter returns a mask of mapped GPCs to provided syspipe.
+ *      Each GPC-ID has a corresponding bit position in the mask.
+ */
+#define NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK (0x20801232U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID (0x32U)
+
+typedef struct NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS {
+    NvU32 physSyspipeId;
+    NvU32 gpcMask;
+} NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_PPC_MASK
+ *
+ * This command returns a mask of enabled PPCs for a specified GPC.
+ *
+ *    grRouteInfo[IN]
+ *      This parameter specifies the routing information used to
+ *      disambiguate the target GR engine.
+ *
+ *    gpcId[IN]
+ *      This parameter specifies the GPC for which TPC information is
+ *      to be retrieved. If the GPC with this ID is not enabled this command
+ *      will return an ppcMask value of zero.
+ *
+ *    ppcMask[OUT]
+ *      This parameter returns a mask of enabled PPCs for the specified GPC.
+ *      Each PPC has an ID that's equivalent to the corresponding bit
+ *      position in the mask.
+ */
+#define NV2080_CTRL_CMD_GR_GET_PPC_MASK (0x20801233U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID (0x33U)
+
+typedef struct NV2080_CTRL_GR_GET_PPC_MASK_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32 gpcId;
+    NvU32 ppcMask;
+} NV2080_CTRL_GR_GET_PPC_MASK_PARAMS;
+
+#define NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC (0x20801234U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID (0x34U)
+
+typedef struct NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS {
+    NvU32 gpcId;
+    NvU32 numTpcs;
+} NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_CTXSW_MODES
+ *
+ * This command is used to get context switch modes for the specified
+ * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the
+ * target channel does not support context switch mode changes.
+ *
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have its context switch modes retrieved.
+ *   zcullMode
+ *     See NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE for possible return values
+ *   pmMode
+ *     See NV2080_CTRL_CMD_GR_CTXSW_PM_MODE for possible return values
+ *   smpcMode
+ *     See NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE for possible return values
+ *   cilpPreemptMode
+ *     See NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE for possible return values
+ *   gfxpPreemptMode
+ *     See NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE for possible return values
+ */
+#define NV2080_CTRL_CMD_GR_GET_CTXSW_MODES (0x20801235U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x35U)
+
+typedef struct NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS {
+    NvHandle hChannel;
+    NvU32    zcullMode;
+    NvU32    pmMode;
+    NvU32    smpcMode;
+    NvU32    cilpPreemptMode;
+    NvU32    gfxpPreemptMode;
+} NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP
+ *
+ * Get a list of values used to describe GPC/TPC tile mapping tables.
+ *
+ *   mapValueCount
+ *     This field specifies the number of actual map entries.  This count
+ *     should equal the number of TPCs in the system.
+ *   mapValues
+ *     This field is a pointer to a buffer of NvU08 values representing map
+ *     data.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x36" */
+
+typedef NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS_MESSAGE_ID (0x36U)
+
+typedef struct NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS params, 8);
+} NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK
+ *
+ * This command returns a mask of enabled ZCULLs for a specified GPC.
+ *
+ *    gpcId[IN]
+ *      This parameter, physical GPC index, specifies the GPC for which ZCULL
+ *      information is to be retrieved. If the GPC with this ID is not enabled
+ *      this command will return a zcullMask value of zero.
+ *
+ *    zcullMask[OUT]
+ *      This parameter returns a mask of enabled ZCULLs for the specified GPC.
+ *      Each ZCULL has an ID that's equivalent to the corresponding bit
+ *      position in the mask.
+ */
+
+#define NV2080_CTRL_CMD_GR_GET_ZCULL_MASK (0x20801237U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID (0x37U)
+
+typedef struct NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS {
+    NvU32 gpcId;
+    NvU32 zcullMask;
+} NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2
+ *
+ * This command is used to create a FECS bind-point to an event buffer that
+ * is filtered by UID.
+ *
+ *  hEventBuffer[IN]
+ *      The event buffer to bind to
+ *
+ *  recordSize[IN]
+ *      The size of the FECS record in bytes
+ *
+ *  levelOfDetail[IN]
+ *      One of NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_:
+ *          FULL: Report all CtxSw events
+ *          SIMPLE: Report ACTIVE_REGION_START and ACTIVE_REGION_END only
+ *          COMPAT: Events that KMD is interested in (for backwards compatibility)
+ *          CUSTOM: Report events in the eventFilter field
+ *      NOTE: RM may override the level-of-detail depending on the caller
+ *
+ *  eventFilter[IN]
+ *      Bitmask of events to report if levelOfDetail is CUSTOM
+ *
+ *  bAllUsers[IN]
+ *     Only report FECS CtxSw data for the current user if false, for all users if true
+ *
+ *  reasonCode [OUT]
+ *     Reason for failure
+ */
+#define NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 (0x20801238U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE {
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE = 0,
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD = 1,
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU = 2,
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED = 3,
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN = 4,
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY = 5,
+} NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE;
+
+#define NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID (0x38U)
+
+typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS {
+    NvHandle                            hEventBuffer;
+    NvU32                               recordSize;
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail;
+    NvU32                               eventFilter;
+    NvBool                              bAllUsers;
+    NvU32                               reasonCode;
+} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO
+ *
+ * This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine
+ *
+ *  grRouteInfo[IN]
+ *      This parameter specifies the routing information used to
+ *      disambiguate the target GR engine.
+ *
+ *  physGfxGpcMask [OUT]
+ *     Physical mask of Gfx capable GPC's
+ *
+ *  numGfxTpc [OUT]
+ *     Total number of Gfx capable TPC's
+ */
+#define NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO (0x20801239U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID (0x39U)
+
+typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32 physGfxGpcMask;
+    NvU32 numGfxTpc;
+} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS;
+
+/* _ctrl2080gr_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h
new file mode 100644
index 0000000..481b59a
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h
@@ -0,0 +1,263 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX grmgr control commands and parameters */
+
+//
+// NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO
+//
+// This control call works as a batched query interface where we
+// have multiple different queries that can be passed in
+// and RM will return the associated data and status type
+// If there is any error in NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS,
+// we will immediately fail the call.
+// However, if there is an error in the query-specific calls, we will
+// log the error and march on.
+//
+// NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS
+//  numQueries[IN]
+//      - Specifies the number of valid queries that the caller will be passing in
+//
+// Possible status values returned are:
+//   NV_OK
+//   NV_ERR_INVALID_ARGUMENT
+//   NV_ERR_INVALID_STATE
+//
+#define NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO        (0x20803801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID << 8) | NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID" */
+
+// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES    96
+
+//
+// Preference is to keep max.size of union at 24 bytes (i.e. 6 32-bit members)
+// so that the size of entire query struct is maintained at 32 bytes, to ensure
+// that overall params struct does not exceed 4kB
+//
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE 32
+#define NV2080_CTRL_GRMGR_MAX_SMC_IDS               8
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS
+ *  gpcCount[OUT]
+ *      - No. of logical/local GPCs which client can use to create the
+ *        logical/local mask respectively
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS {
+    NvU32 gpcCount;         // param[out] - logical/local GPC mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS
+ *  gpcId[IN]
+ *      - Logical/local GPC ID
+ *  chipletGpcMap[OUT]
+ *      - Returns chiplet GPC ID for legacy case and device monitoring client
+ *      - Returns local GPC ID (== input gpcId) for SMC client
+ *      - Does not support DM attribution case
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS {
+    NvU32 gpcId;            // param[in] - logical/local GPC ID
+    NvU32 chipletGpcMap;    // param[out] - chiplet GPC ID
+} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS
+ *  gpcId[IN]
+ *      - Logical/local GPC ID
+ *  tpcMask[OUT]
+ *      - Returns physical TPC mask for legacy, DM client and SMC cases
+ *      - Does not support DM attribution case
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS {
+    NvU32 gpcId;            // param[in] - logical/local GPC ID
+    NvU32 tpcMask;          // param[out] - physical TPC mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS
+ *  gpcId[IN]
+ *      - Logical/local GPC ID
+ *  ppcMask[OUT]
+ *      - Returns physical PPC mask for legacy, DM client and SMC cases
+ *      - Does not support DM attribution case
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS {
+    NvU32 gpcId;            // param[in] - logical/local GPC ID
+    NvU32 ppcMask;          // param[out] - physical PPC mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS;
+
+/*!
+ *  !!! DEPRECATED - This query will return NV_ERR_NOT_SUPPORTED since deleting
+ *               it would break driver compatibility !!!
+ *
+ *  NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS
+ *  swizzId[IN]
+ *      - Swizz ID of partition
+ *      - A DM client with an invalid swizz ID, will fail this call
+ *      - This parameter is not compulsory for an SMC client; the subscription
+ *        itself will do the necessary validation.
+ *  gpcId[IN]
+ *      - Logical/local GPC ID
+ *  chipletGpcMap[OUT]
+ *      - Returns chiplet GPC ID for legacy case and device monitoring client
+ *      - Returns local GPC ID (== input gpcId) for SMC client
+ *      - Does not support non-attribution case for DM client
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS {
+    NvU32 swizzId;          // param[in]  - swizz ID of partition
+    NvU32 gpcId;            // param[in]  - logical/local GPC ID
+    NvU32 chipletGpcMap;    // param[out] - chiplet GPC ID
+} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS
+ *  gpcId[IN]
+ *      - Logical/local GPC ID
+ *  ropMask[OUT]
+ *      - Returns physical ROP mask for legacy, DM client
+ *      - Returns logical ROP mask for SMC
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS {
+    NvU32 gpcId;            // param[in] - logical/local GPC ID
+    NvU32 ropMask;          // param[out] - physical ROP mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS;
+
+/*!
+ *  NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS
+ *  chipletSyspipeMask [OUT]
+ *      - Mask of chiplet SMC-IDs for DM client attribution case
+ *      - Mask of local SMC-IDs for SMC client
+ *      - Legacy case returns 1 GR
+ *      - Does not support attribution case for DM client
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS {
+    NvU32 chipletSyspipeMask;   // param[out] - Mask of chiplet SMC IDs
+} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS;
+
+/*!
+ *  NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS
+ *  swizzId[IN]
+ *      - Swizz ID of partition
+ *      - A DM client with an invalid swizz ID, will fail this call
+ *  physSyspipeId[GRMGR_MAX_SMC_IDS] [OUT]
+ *      - Physical SMC-IDs mapped to partition local idx for DM client attribution case
+ *      - Does not support non-attribution case for DM client, SMC clients, legacy case
+ *  physSyspipeIdCount[OUT]
+ *      - Valid count of physSmcIds which has been populated in above array.
+ *      - Failure case will return 0
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS {
+    NvU16 swizzId;                                          // param[in]  - swizz ID of partition
+    NvU16 physSyspipeIdCount;                               // param[out] - Count of physSmcIds in above array
+    NvU8  physSyspipeId[NV2080_CTRL_GRMGR_MAX_SMC_IDS];      // param[out] - physical/local SMC IDs
+} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS
+ * swizzId[IN]
+ *      - Swizz ID of partition
+ *      - Mandatory parameter
+ *      - A DM client with an invalid swizz ID, will fail this call
+ * grIdx[IN]
+ *      - Local grIdx for a partition
+ *      - Mandatory parameter
+ * gpcEnMask[OUT]
+ *      - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask
+ *      - These Ids should be used as input further
+ *      - Does not support non-attribution case for DM client, SMC clients, legacy case
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS {
+    NvU32 swizzId;      // param[in]  - swizz ID of partition
+    NvU32 grIdx;        // param[in]  - partition local GR ID
+    NvU32 gpcEnMask;    // param[out] - logical enabled GPC mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID
+ * syspipeId[OUT]
+ *      - Partition-local GR idx for client subscribed to exec partition
+ *      - Does not support legacy case, DM client, or SMC client subscribed only to partition
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS {
+    NvU32 syspipeId;    // param[out] - partition-local Gr idx
+} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS;
+
+/*!
+ * queryType[IN]
+ *  - Use queryType defines to specify what information is being requested
+ * status[OUT]
+ *  - Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_INVALID_STATE
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS {
+    NvU16 queryType;
+    NvU8  reserved[2]; // To keep the struct aligned for now and available for future use (if needed)
+    NvU32 status;
+    union {
+        NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS                     gpcCountData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS               chipletGpcMapData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS                      tpcMaskData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS                      ppcMaskData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS     partitionGpcMapData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS          syspipeMaskData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS partitionChipletSyspipeData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS         dmGpcMaskData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS          partitionSyspipeIdData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS                      ropMaskData;
+    } queryData;
+} NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS;
+
+#define NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS {
+    NvU16                                     numQueries;
+    NvU8                                      reserved[6]; // To keep the struct aligned for now and available for future use (if needed)
+    NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS queries[NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES];
+} NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS;
+
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID                       0
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT                     1
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP               2
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK                      3
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK                      4
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP     5   /* deprecated */
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK          6
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS 7
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK         8
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID          9
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK                      10
+
+/* _ctrl2080grmgr_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
new file mode 100644
index 0000000..ee04d61
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
@@ -0,0 +1,82 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080gsp.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX GSP control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_GSP_GET_FEATURES
+ *
+ * This command is used to determine which GSP features are
+ * supported on this GPU.
+ *
+ *   gspFeatures
+ *     Bit mask that specifies GSP features supported.
+ *   bValid
+ *     If this field is set to NV_TRUE, then above bit mask is
+ *     considered valid. Otherwise, bit mask should be ignored
+ *     as invalid. bValid will be set to NV_TRUE when RM is a
+ *     GSP client with GPU support offloaded to GSP firmware.
+ *   bDefaultGspRmGpu
+ *     If this field is set to NV_TRUE, it indicates that the
+ *     underlying GPU has GSP-RM enabled by default. If set to NV_FALSE,
+ *     it indicates that the GPU has GSP-RM disabled by default.
+ *   firmwareVersion
+ *     This field contains the buffer into which the firmware build version
+ *     should be returned, if GPU is offloaded. Otherwise, the buffer
+ *     will remain untouched.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GSP_GET_FEATURES    (0x20803601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_GSP_MAX_BUILD_VERSION_LENGTH (0x0000040)
+
+#define NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
+    NvU32  gspFeatures;
+    NvBool bValid;
+    NvBool bDefaultGspRmGpu;
+    NvU8   firmwareVersion[NV2080_GSP_MAX_BUILD_VERSION_LENGTH];
+} NV2080_CTRL_GSP_GET_FEATURES_PARAMS;
+
+/* Valid feature values */
+#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED                    0:0
+#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000)
+#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE  (0x00000001)
+
+// _ctrl2080gsp_h_
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h
new file mode 100644
index 0000000..f0df6c5
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h
@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080hshub.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/*
+ * NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK
+ *
+ * This command get active HSHUB masks.
+ *
+ *   hshubNcisocMask
+ *     NCISOC enabled active HSHUBs
+ *   hshubNvlMask
+ *     NVLINK capable active HSHUBs.
+ */
+
+#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS {
+    NvU32 hshubNcisocMask;
+    NvU32 hshubNvlMask;
+} NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS;
+
+#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK (0x20804101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID" */
+
+/* _ctrl2080hshub_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h
new file mode 100644
index 0000000..b3314d9
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h
@@ -0,0 +1,365 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080i2c.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX i2c-related control commands and parameters */
+
+/*
+ * NV2080_CTRL_I2C_VERSION
+ *   
+ *   NV2080_CTRL_I2C_VERSION_0_0: 
+ *       This return state specifies that support is only available 
+ *       for single subAddr reads.
+ *
+ */
+#define NV2080_CTRL_I2C_VERSION_0                         0x00
+
+/* maximum number of i2c entries support */
+#define NV2080_CTRL_I2C_MAX_ENTRIES                       256
+#define NV2080_CTRL_I2C_MAX_REG_LEN                       8
+#define NV2080_CTRL_I2C_MAX_ADDR_ENTRIES                  20
+
+/*
+ * NV2080_CTRL_I2C_FLAGS
+ *
+ *   NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: 
+ *       This option specified that non-compliant i2c for SI1930UC is required
+ *
+ *   NV2080_CTRL_I2C_FLAGS_PRIVILEGE
+ *       This option specified that the i2c access is privileged
+ *
+ *   NV2080_CTRL_I2C_FLAGS_PX3540
+ *       This option specified that the i2c device -PX3540/3544- is accessed
+ */
+#define NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC             (0x00000001)
+#define NV2080_CTRL_I2C_FLAGS_PRIVILEGE                   (0x00000002)
+#define NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED              (0x00000004)
+#define NV2080_CTRL_I2C_FLAGS_PX3540                      (0x00000010)
+#define NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED (0x00000008)
+
+/*
+ * NV2080_CTRL_CMD_I2C_READ_BUFFER
+ *
+ * This command allocates video memory for a particular subset of microcode.
+ *
+ *   version
+ *       This field is returned to the client and indicates the current
+ *       supported I2C controls available.  
+ *
+ *   port
+ *       This field must be specified by the client to indicate which port/bus
+ *       in which i2c access is desired.
+ *
+ *   flags
+ *       This field is specified by the client to request additional options
+ *       as provided by NV2080_CTRL_I2C_FLAGS.
+ *
+ *   inputCount
+ *       This field specifies the total # of elements contained in inputBuffer
+ *
+ *   inputBuffer
+ *       This should contain the chipaddr as the first element, followed by
+ *       the each subAddress in which to access the first element of data
+ *       Eg. <chipAddr> <subAddr1> ... <subAddrX> 
+ *       In general, client will only have 2 elements <chipAddr> <subAddr>
+ *
+ *   outputCount
+ *       This field specifies how many registers from the start register index.
+ *       The maximum values allow are NV2080_CTRL_I2C_MAX_ENTRIES.
+ *
+ *   outputBuffer
+ *       This buffer is returned to the client with the data read from
+ *       the start register index.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_I2C_READ_BUFFER_PARAMS {
+    NvU32 version;
+    NvU32 port;
+    NvU32 flags;
+    NvU32 inputCount;
+    // C form: NvU8    inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+    NvU8  inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+    NvU32 outputCount;
+    // C form: NvU8    outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+    NvU8  outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+} NV2080_CTRL_I2C_READ_BUFFER_PARAMS;
+
+#define NV2080_CTRL_CMD_I2C_READ_BUFFER (0x20800601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_I2C_WRITE_BUFFER
+ *
+ * This command allocates video memory for a particular subset of microcode.
+ *
+ *   version
+ *       This field is returned to the client and indicates the current
+ *       supported I2C controls available.  
+ *
+ *   port
+ *       This field must be specified by the client to indicate which port/bus
+ *       in which i2c access is desired.
+ *
+ *   flags
+ *       This field is specified by the client to request additional options.
+ *       NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: 
+ *       - Specifies that non-compliant i2c access for SI1930UC is required
+ *
+ *   inputCount
+ *       This field specifies the total # of elements contained in inputBuffer
+ *
+ *   inputBuffer
+ *       This should contain the chipaddr as the first element, followed by
+ *       the each subAddress in which to access the first element of data,
+ *       and finally the data to be programmed.
+ *       Eg. <chipAddr> <subAddr1> ... <subAddrX> <data1> ... <dataX>
+ *       In general, client will have 2 elements + data to be programmed.
+ *       <chipAddr> <subAddr> <data1> ... <dataX>
+ *
+ *   encrClientID
+ *      This field is specified by client, which is used to uniquely access
+ *      the client's encryption context
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_STATE
+ *
+ */
+
+#define NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS {
+    NvU32 version;
+    NvU32 port;
+    NvU32 flags;
+    NvU32 inputCount;
+    // C form: NvU8    inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+    NvU8  inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+    NvU32 encrClientID;
+} NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS;
+
+#define NV2080_CTRL_CMD_I2C_WRITE_BUFFER (0x20800602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID" */
+
+
+/*
+ * NV2080_CTRL_CMD_I2C_READ_REG
+ *
+ * This command allocates video memory for a particular subset of microcode.
+ *
+ *   version
+ *       This field is returned to the client and indicates the current
+ *       supported I2C controls available.  
+ *
+ *   port
+ *       This field must be specified by the client to indicate which port/bus
+ *       in which i2c access is desired.
+ *
+ *   flags
+ *       This field is specified by the client to request additional options.
+ *       NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: 
+ *       - Specifies that non-compliant i2c access for SI1930UC is required
+ *   addr
+ *       This field is specified by the client to target address.
+ *   reg
+ *       This field is specified by the client to target register address.
+ *
+ *   bufsize
+ *       This field specifies the total bytes # of register size
+ *
+ *   buffer
+ *       when used for read, it used as buffer that store returned register content
+ *       when used for write, It include data that will be written.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_STATE
+ *
+ */
+typedef struct NV2080_CTRL_I2C_RW_REG_PARAMS {
+    NvU32 version;
+    NvU32 port;
+    NvU32 flags;
+    NvU32 addr;
+    NvU8  reg;
+    NvU8  bufsize;
+    // C form: NvU8    buffer[NV2080_CTRL_I2C_MAX_ENTRIES - 1];
+    NvU8  buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)];
+} NV2080_CTRL_I2C_RW_REG_PARAMS;
+
+// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name
+typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS;
+#define NV2080_CTRL_CMD_I2C_READ_REG  (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x3" */
+
+#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x4" */
+
+/*
+ * NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS
+ *
+ * This command allows Clients to read and write data using the I2C ports
+ * 
+ *   token [IN]
+ *      This used in i2cAcquirePort
+ *
+ *   cmd [IN]
+ *      The I2CAccess command
+ *     
+ *   port [IN]
+ *       The port ID of the concerned display
+ *     
+ *   flags [IN]
+ *      The I2CAccess Flags such ack,start,stop
+ *   
+ *   data  [OUT/IN]
+ *      Data that needs to be pass or read out
+ *
+ *   dataBuffSize [IN]
+ *       Size of the data buffer.
+ *   
+ *   speed [IN]
+ *      Speed of transaction.
+ *
+ *   status [OUT]
+ *      The I2CAccess Status returned
+ *
+ *   encrClientID [IN]
+ *      This field is specified by client, which is used to uniquely access
+ *      the client's encryption context
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_I2C_ACCESS    (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_I2C_ACCESS_PARAMS {
+    NvU32 token;
+    NvU32 cmd;
+    NvU32 port;
+    NvU32 flags;
+    NV_DECLARE_ALIGNED(NvP64 data, 8);
+    NvU32 status;
+    NvU32 dataBuffSize;
+    NvU32 speed;
+    NvU32 encrClientID;
+} NV2080_CTRL_I2C_ACCESS_PARAMS;
+
+// commands
+#define NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE                   0x1
+#define NV2080_CTRL_I2C_ACCESS_CMD_RELEASE                   0x2
+#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE                0x3
+#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE                 0x4
+#define NV2080_CTRL_I2C_ACCESS_CMD_NULL                      0x5
+#define NV2080_CTRL_I2C_ACCESS_CMD_RESET                     0x6
+#define NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT                 0x11
+#define NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE             0x12
+#define NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE           0x13
+#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER              0x14
+#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER               0x15
+#define NV2080_CTRL_I2C_ACCESS_CMD_START                     0x17
+#define NV2080_CTRL_I2C_ACCESS_CMD_STOP                      0x18
+#define NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE             0x20
+
+// flags
+#define NV2080_CTRL_I2C_ACCESS_FLAG_START                    0x1
+#define NV2080_CTRL_I2C_ACCESS_FLAG_STOP                     0x2
+#define NV2080_CTRL_I2C_ACCESS_FLAG_ACK                      0x4
+#define NV2080_CTRL_I2C_ACCESS_FLAG_RAB                      0x8
+#define NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS              0x10
+#define NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE                0x20
+#define NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED           0x40
+#define NV2080_CTRL_I2C_ACCESS_FLAG_RESTART                  0x80
+#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT       0x100
+#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT          0x200
+#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT          0x400
+#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT        0x800
+#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT           0x1000
+
+// port
+#define NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC                  0x0
+#define NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY                  0x1
+#define NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY                0x2
+#define NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY                 0x3
+#define NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY                0x4
+
+// Alternate numeric port designators
+#define NV2080_CTRL_I2C_ACCESS_PORT_1                        0x1
+#define NV2080_CTRL_I2C_ACCESS_PORT_2                        0x2
+#define NV2080_CTRL_I2C_ACCESS_PORT_3                        0x3
+#define NV2080_CTRL_I2C_ACCESS_PORT_4                        0x4
+#define NV2080_CTRL_I2C_ACCESS_PORT_5                        0x5
+#define NV2080_CTRL_I2C_ACCESS_PORT_6                        0x6
+#define NV2080_CTRL_I2C_ACCESS_PORT_7                        0x7
+#define NV2080_CTRL_I2C_ACCESS_PORT_8                        0x8
+#define NV2080_CTRL_I2C_ACCESS_PORT_9                        0x9
+#define NV2080_CTRL_I2C_ACCESS_PORT_10                       0x10
+
+// Total ports count
+#define NV2080_CTRL_I2C_ACCESS_NUM_PORTS                     NV2080_CTRL_I2C_ACCESS_PORT_10
+
+// status
+#define NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS                0x0
+#define NV2080_CTRL_I2C_ACCESS_STATUS_ERROR                  0x1
+#define NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR         0x2
+#define NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY            0x3
+#define NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND        0x4
+#define NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING 0x5
+
+#define NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE           (0x20800620) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS {
+    NvU32 head;
+    NvU32 authType;
+    NvU32 status;
+} NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS;
+
+/* _ctrl2080i2c_h_ */
+
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h
new file mode 100644
index 0000000..54a762a
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h
@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080illum.finn
+//
+
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
new file mode 100644
index 0000000..5307f5d
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
@@ -0,0 +1,3176 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080internal.finn
+//
+
+#include "nvimpshared.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+#include "ctrl/ctrl2080/ctrl2080gpu.h"
+#include "ctrl/ctrl2080/ctrl2080gr.h"        /* Some controls derivative of 2080gr */
+#include "ctrl/ctrl0080/ctrl0080msenc.h"     /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE    */
+#include "ctrl/ctrl0080/ctrl0080bsp.h"       /* NV0080_CTRL_BSP_CAPS_TBL_SIZE      */
+#include "ctrl/ctrl2080/ctrl2080fifo.h"      /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */
+#include "ctrl/ctrl0000/ctrl0000system.h"
+#include "ctrl/ctrl90f1.h"
+#include "ctrl/ctrl30f1.h"
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO
+ *
+ *    This command obtains information from physical RM for use by CPU-RM.
+ *
+ *   feHwSysCap
+ *     Display IP v03_00 and later.
+ *     Contents of capability register.
+ *
+ *   windowPresentMask
+ *     Display IP v03_00 and later.
+ *     Mask for the present WINDOWs actually on the current chip.
+ *   bFbRemapperEnabled
+ *     Display IP v02_01 and later.
+ *     Indicates that the display remapper HW exists and is enabled.
+ *   numHeads
+ *     Display IP v02_01 and later.
+ *     Provides the number of heads HW support.
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
+    NvU32  feHwSysCap;
+    NvU32  windowPresentMask;
+    NvBool bFbRemapperEnabled;
+    NvU32  numHeads;
+    NvBool bPrimaryVga;
+    NvU32  i2cPort;
+    NvU32  internalDispActiveMask;
+} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS;
+
+
+
+//
+// MemorySystem settings that are static after GPU state init/load is finished.
+//
+// Fields are shared between the VGPU guest/GSP Client as well as the VGPU
+// host/GSP-RM.
+//
+#define NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID (0x1CU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
+    /*! Determines if RM should use 1 to 1 Comptagline allocation policy */
+    NvBool bOneToOneComptagLineAllocation;
+
+    /*! Determines if RM should use 1 to 4 Comptagline allocation policy */
+    NvBool bUseOneToFourComptagLineAllocation;
+
+    /*! Determines if RM should use raw Comptagline allocation policy */
+    NvBool bUseRawModeComptaglineAllocation;
+
+    /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */
+    NvBool bDisableCompbitBacking;
+
+    /*! Determine if we need to disable post L2 compression */
+    NvBool bDisablePostL2Compression;
+
+    /*! Is ECC DRAM feature supported? */
+    NvBool bEnabledEccFBPA;
+
+    NvBool bL2PreFill;
+
+    /*! L2 cache size */
+    NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8);
+
+    NvBool bReservedMemAtBottom;
+
+    /*! Indicate whether fpba is present or not */
+    NvBool bFbpaPresent;
+
+    /*! Size covered by one comptag */
+    NvU32  comprPageSize;
+
+    /*! log32(comprPageSize) */
+    NvU32  comprPageShift;
+
+    /*! Maximum number of pages that can be dynamaically blacklisted */
+    NvU16  maximumBlacklistPages;
+
+    /*! RAM type */
+    NvU32  ramType;
+
+    /*! LTC count */
+    NvU32  ltcCount;
+
+    /*! LTS per LTC count */
+    NvU32  ltsPerLtcCount;
+
+    /*! Ampere PLC bug */
+    NvBool bDisablePlcForCertainOffsetsBug3046774;
+} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS;
+
+/*!
+ * Retrieve Memory System Static data.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG        (0x20800a1c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_REGISTER_UVM_ACCESS_CNTR_BUFFER
+ *
+ * This command sends access counter buffer pages allocated by CPU-RM
+ * to be setup and enabled in physical RM.
+ *
+ * bufferSize
+ *   Size of the access counter buffer to register.
+ *
+ * bufferPteArray
+ *   Pages of access counter buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER (0x20800a1d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES    64
+#define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU)
+
+typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS {
+    NvU32 bufferSize;
+    NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8);
+} NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER
+ *
+ * This command requests physical RM to disable the access counter buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1E" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER
+ *
+ * This command requests physical RM to service the access counter buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER    (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x21" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE
+ *
+ * This command retrieves the access counter buffer size from physical RM.
+ *
+ * bufferSize[OUT]
+ *   Size of the access counter buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE   (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x29U)
+
+typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS {
+    NvU32 bufferSize;
+} NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES          8
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1F" */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS {
+    NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE];
+} NV2080_CTRL_INTERNAL_STATIC_GR_CAPS;
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
+ * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x22" */
+
+
+
+#define NV2080_CTRL_INTERNAL_GR_MAX_SM                          240
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
+    struct {
+        NvU16 gpcId;
+        NvU16 localTpcId;
+        NvU16 localSmId;
+        NvU16 globalTpcId;
+        NvU16 virtualGpcId;
+        NvU16 migratableTpcId;
+    } globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM];
+
+    NvU16 numSm;
+    NvU16 numTpc;
+} NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS;
+
+
+/*!
+ * Retrieve BSP Static data.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BSP_GET_CAPS (0x20800a24) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS     8
+
+typedef struct NV2080_CTRL_INTERNAL_BSP_CAPS {
+    NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE];
+} NV2080_CTRL_INTERNAL_BSP_CAPS;
+
+#define NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS {
+    NV2080_CTRL_INTERNAL_BSP_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS];
+    NvBool                        valid[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS];
+} NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS;
+
+/*!
+ * Retrieve MSENC Static data.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS (0x20800a25) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS     3
+
+typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS {
+    NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE];
+} NV2080_CTRL_INTERNAL_MSENC_CAPS;
+
+#define NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS {
+    NV2080_CTRL_INTERNAL_MSENC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS];
+    NvBool                          valid[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS];
+} NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS;
+
+
+#define NV2080_CTRL_INTERNAL_GR_MAX_GPC                             12
+#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT                  10
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK
+ * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK
+ * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x26" */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS {
+    NvU32 gpcMask;
+
+    /*!
+     * tpcMask is indexed by logical GPC ID for MIG case
+     * and indexed by physical GPC ID for non-MIG case
+     */
+    NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+
+    /*!
+     * tpcCount is always indexed by logical GPC ID
+     */
+    NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+    NvU32 physGpcMask;
+    NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+
+    NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT];
+    NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+
+    /*!
+     * zcullMask is always indexed by physical GPC ID
+     */
+    NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+
+    NvU32 physGfxGpcMask;
+    NvU32 numGfxTpc;
+} NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS {
+    /*!
+     * floorsweeping masks which are indexed via local GR index
+     */
+    NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES
+ *
+ * This command returns physical addresses of specified context buffer.
+ * To obtain addresses of whole buffer firstPage has to be advanced on
+ * subsequent invocations of the control until whole buffer is probed.
+ * If the buffer is contiguous, only single address will be returned by
+ * this control.
+ *
+ *    bufferType[IN]
+ *      Buffer type as returned by GET_CTX_BUFFER_INFO.
+ *
+ *    firstPage[IN]
+ *      Index of the first page to return in 'physAddrs' array.
+ *
+ *    numPages[OUT]
+ *      Number of entries filled in 'physAddrs' array. This will be 0
+ *      if firstPage is greater or equal to number of pages managed by 'hBuffer'.
+ *
+ *    physAddrs[OUT]
+ *      Physical addresses of pages comprising specified buffer.
+ *
+ *    bNoMorePages[OUT]
+ *      End of buffer reached. Either 'physAddrs' contains last page of the
+ *      buffer or 'firstPage' specifies index past the buffer.
+ */
+#define NV2080_CTRL_KGR_MAX_BUFFER_PTES         128
+#define NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES (0x20800a28) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID (0x28U)
+
+typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS {
+    NvHandle hUserClient;
+    NvHandle hChannel;
+    NvU32    bufferType;
+    NvU32    firstPage;
+    NvU32    numPages;
+    NV_DECLARE_ALIGNED(NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES], 8);
+    NvBool   bNoMorePages;
+} NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS;
+
+/*!
+ * @ref NV0080_CTRL_CMD_GR_GET_INFO
+ * @ref NV0080_CTRL_CMD_GR_GET_INFO_V2
+ * @ref NV2080_CTRL_CMD_GR_GET_INFO
+ * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2A" */
+
+
+
+/*!
+ * @ref NV2080_CTRL_GR_INFO
+ */
+typedef struct NV2080_CTRL_INTERNAL_GR_INFO {
+    NvU32 index;
+    NvU32 data;
+} NV2080_CTRL_INTERNAL_GR_INFO;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO {
+    NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE];
+} NV2080_CTRL_INTERNAL_STATIC_GR_INFO;
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2C" */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO {
+    NvU32 widthAlignPixels;
+    NvU32 heightAlignPixels;
+    NvU32 pixelSquaresByAliquots;
+    NvU32 aliquotTotal;
+    NvU32 zcullRegionByteMultiplier;
+    NvU32 zcullRegionHeaderSize;
+    NvU32 zcullSubregionHeaderSize;
+    NvU32 subregionCount;
+    NvU32 subregionWidthAlignPixels;
+    NvU32 subregionHeightAlignPixels;
+} NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2E" */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO {
+    NvU32 ropUnitCount;
+    NvU32 ropOperationsFactor;
+    NvU32 ropOperationsCount;
+} NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x30" */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS {
+    NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+} NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES
+ * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO   (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x32" */
+
+
+
+#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x19
+
+typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO {
+    NvU32 size;
+    NvU32 alignment;
+} NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO {
+    NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT];
+} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x34" */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER {
+    NvU8 imla0;
+    NvU8 fmla16;
+    NvU8 dp;
+    NvU8 fmla32;
+    NvU8 ffma;
+    NvU8 imla1;
+    NvU8 imla2;
+    NvU8 imla3;
+    NvU8 imla4;
+} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
+
+/*
+ * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS
+ *
+ * This command obtains information from physical RM for use by CPU-RM.
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO      (0x20800a36) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * Maximum number of register bases to return.
+ * These are indexed by NV_REG_BASE_* constants from gpu.h, and this value needs
+ * to be updated if NV_REG_BASE_LAST ever goes over it. See the ct_assert() in gpu.h
+ */
+#define NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX 16
+#define NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID (0x36U)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS {
+    NvU8   chipSubRev;
+    NvU32  emulationRev1;
+    NvBool isCmpSku;
+    NvU32  bar1Size;
+    NvU32  pciDeviceId;
+    NvU32  pciSubDeviceId;
+    NvU32  pciRevisionId;
+    NvU32  regBases[NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX];
+} NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE
+ *
+ * Set whether or not context switch logging is enabled
+ *
+ * bEnable
+ *    Enable/Disable status for context switch logging
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE (0x20800a37) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE
+ *
+ * Retrieve whether or not context switch logging is enabled
+ *
+ * bEnable
+ *    Enable/Disable status for context switch logging
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE (0x20800a38) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvBool bEnable;
+} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS;
+#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U)
+
+typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS;
+#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U)
+
+typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET
+ *
+ * Set read offset into FECS context switch trace record
+ *
+ * offset
+ *   Value indicating number of records by which to offset
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET (0x20800a39) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET
+ *
+ * Set write offset into FECS context switch trace record
+ *
+ * offset
+ *   Value indicating number of records by which to offset
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET (0x20800a3a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID" */
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET
+ *
+ * Get read offset into FECS context switch trace record
+ *
+ * offset
+ *   Value indicating number of records by which to offset
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET (0x20800a3b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32 offset;
+} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U)
+
+typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS;
+#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU)
+
+typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS;
+#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU)
+
+typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE
+ *
+ * Get size of FECS record
+ *
+ * fecsRecordSize
+ *   Size of FECS record
+ */
+
+
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE (0x20800a3d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE {
+    NvU32 fecsRecordSize;
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3CU)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES
+ *
+ * Get HW defines used to extract information from FECS records
+ *
+ * fecsRecordSize
+ *  Size of FECS record
+ *
+ * timestampHiTagMask
+ *  Mask for high bits of raw timestamp to extract tag
+ *
+ * timestampHiTagShift
+ *  Shift for high bits of raw timestamp to extract tag
+ *
+ * timestampVMask
+ *  Mask to extract timestamp from raw timestamp
+ *
+ * numLowerBitsZeroShift
+ *  Number of bits timestamp is shifted by
+ */
+
+
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x3F" */
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES {
+    NvU32 fecsRecordSize;
+    NvU32 timestampHiTagMask;
+    NvU8  timestampHiTagShift;
+    NV_DECLARE_ALIGNED(NvU64 timestampVMask, 8);
+    NvU8  numLowerBitsZeroShift;
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8);
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE
+ *
+ * Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel.
+ */
+typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO {
+    NvU32 faultId;
+    NvU32 instanceId;
+    NvU32 typeEnum;
+    NvU32 resetId;
+    NvU32 devicePriBase;
+    NvU32 isEngine;
+    NvU32 rlEngId;
+    NvU32 runlistPriBase;
+    NvU32 groupId;
+} NV2080_CTRL_INTERNAL_DEVICE_INFO;
+#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 88
+
+#define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE   (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x40U)
+
+typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS {
+    NvU32                            numEntries;
+    NV2080_CTRL_INTERNAL_DEVICE_INFO deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES];
+} NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP              (0x20800a41) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE  4096
+#define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES 4096
+
+#define NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID (0x41U)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS {
+    NvU32 userRegisterAccessMapSize;
+    NvU32 compressedSize;
+    NvU8  compressedData[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE];
+    NvU32 profilingRangesSize;
+    NvU8  profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES];
+} NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS;
+
+typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO {
+    NvU32 engDesc;
+    NvU32 ctxAttr;
+    NvU32 ctxBufferSize;
+    NvU32 addrSpaceList;
+    NvU32 registerBase;
+} NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO;
+#define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS     0x40
+
+#define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0x42U)
+
+typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
+    NvU32                                        numConstructedFalcons;
+    NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS];
+} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
+
+/**
+ * Get GR PDB properties synchronized between Kernel and Physical
+ *
+ * bPerSubCtxheaderSupported
+ *   @ref PDB_PROP_GR_SUPPORTS_PER_SUBCONTEXT_CONTEXT_HEADER
+ */
+
+
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x48" */
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
+    NvBool bPerSubCtxheaderSupported;
+} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM
+ *
+ *   This command writes instance memory information in the display hardware registers.
+ *
+ *   instMemPhysAddr
+ *     GPU physical address or IOVA address of the display instance memory.
+ *
+ *   instMemSize
+ *     Size of the display instance memory.
+ *
+ *   instMemAddrSpace
+ *     Address space of the display instance memory.
+ *
+ *   instMemCpuCacheAttr
+ *     Cache attribute of the display instance memory.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID (0x49U)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 instMemSize, 8);
+    NvU32 instMemAddrSpace;
+    NvU32 instMemCpuCacheAttr;
+} NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS;
+
+/*
+ * NV2080_CTRL_INTERNAL_GPU_RECOVER_ALL_COMPUTE_CONTEXTS
+ *
+ * This command issues RC recovery for all compute contexts running on the given GPU.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS (0x20800a4a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4A" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION
+ *
+ *    This command obtains IP version of display engine for use by Kernel RM.
+ *
+ *   ipVersion
+ *     IP Version of display engine.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED - DISP has been disabled
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION       (0x20800a4b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4BU)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS {
+    NvU32 ipVersion;
+} NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE
+ *
+ *  This command determines the current status of MIG MODE from Physical RM.
+ *
+ *  smcMode [OUT]
+ *     Current MIG MODE of the GPU. Values range NV2080_CTRL_GPU_INFO_GPU_SMC_MODE*
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE (0x20800a4c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID (0x4CU)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS {
+    NvU32 smcMode;
+} NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR
+ *
+ *   head
+ *     This parameter specifies the head for which the callback is to be registered/unregistered. This value must be
+ *     less than the maximum number of heads supported by the GPU subdevice.
+ *
+ *   rgLineNum
+ *     This indicates the RG scanout line number on which the callback will be executed.
+ *
+ *   intrLine
+ *     Enable: [out] Which interrupt line was allocated for this head.
+ *     Disable: [in] Which interrupt line to deallocate.
+ *
+ *   bEnable
+ *     Should we allocate or deallocate an interrupt line?
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC - There was no available interrupt to allocate.
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR (0x20800a4d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID (0x4DU)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
+    NvU32  head;
+    NvU32  rgLineNum;
+    NvU32  intrLine;
+    NvBool bEnable;
+} NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS;
+
+/*!
+ * NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO
+ *
+ * Description of a supported GPU instance.
+ *
+ *   partitionFlag [OUT]
+ *     Allocation flag to be used to allocate a partition with this profile.
+ *
+ *   grCount [OUT]
+ *     # GR engines, including the GFX capable ones.
+ *
+ *   gfxGrCount [OUT]
+ *     # GR engines capable of Gfx, which is a subset of the GR engines included in grCount
+ *
+ *   gpcCount [OUT]
+ *     # total gpcs, including the GFX capable ones.
+ *
+ *   virtualGpcCount [OUT]
+ *     # virtualized gpcs, including the GFX capable ones.
+ *
+ *   gfxGpcCount [OUT]
+ *     # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount.
+ *
+ *   veidCount [OUT]
+ *     # total veids
+ *
+ *   smCount [OUT]
+ *     # total SMs
+ *
+ *   ceCount [OUT]
+ *     # CE engines
+ *
+ *   nvEncCount [OUT]
+ *     # NVENC engines
+ *
+ *   nvDecCount [OUT]
+ *     # NVDEC engines
+ *
+ *   nvJpgCount [OUT]
+ *     # NVJPG engines
+ *
+ *   nvOfaCount [OUT]
+ *     # NVOFA engines
+ *
+ *   validCTSIdMask [OUT]
+ *     # mask of CTS IDs which can be assigned under this profile
+ */
+#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES      20
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO {
+    NvU32 partitionFlag;
+    NvU32 grCount;
+    NvU32 gfxGrCount;
+    NvU32 gpcCount;
+    NvU32 virtualGpcCount;
+    NvU32 gfxGpcCount;
+    NvU32 veidCount;
+    NvU32 smCount;
+    NvU32 ceCount;
+    NvU32 nvEncCount;
+    NvU32 nvDecCount;
+    NvU32 nvJpgCount;
+    NvU32 nvOfaCount;
+    NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8);
+} NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO;
+
+/*!
+ * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS
+ *
+ * Returns the list of supported GPU instance profiles.
+ *
+ *   count [OUT]
+ *     Number of supported profiles.
+ *
+ *   table [OUT]
+ *     Supported profiles.
+ */
+typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS {
+    NvU32 count;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8);
+} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM
+ *
+ *  This command instructs the physical MemorySystem to set up memory partitioning
+ *  exterior boundaries in hardware.
+ *
+ *  partitionableMemSize [input]
+ *      Size of the partitionable memory in bytes
+ *
+ *  bottomRsvdSize [input]
+ *      Size of the reserved region below partitionable memory in bytes
+ *
+ *  topRsvdSize [input]
+ *      Size of the reserved region above partitionable memory in bytes
+ *
+ *  partitionableStartAddr [output]
+ *      Start address of the partitionable memory, aligned to HW constraints
+ *
+ *  partitionableEndAddr [output]
+ *      End address of the partitionable memory, aligned to HW constraints
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM (0x20800a51) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID (0x51U)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 partitionableMemSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 bottomRsvdSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 topRsvdSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 partitionableStartAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 partitionableEndAddr, 8);
+} NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS;
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 engineMask, 8);
+} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
+
+
+/*!
+ * NV2080_CTRL_INTERNAL_MEMDESC_INFO
+ *
+ * A generic container structure representing a memory region to be used as a
+ * component of other control call parameters.
+ *
+ */
+typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NV_DECLARE_ALIGNED(NvU64 alignment, 8);
+    NvU32 addressSpace;
+    NvU32 cpuCacheAttrib;
+} NV2080_CTRL_INTERNAL_MEMDESC_INFO;
+
+#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS         2
+#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID              64
+/*!
+ * NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS
+ *
+ * Promote a single partition's runlist buffers allocated by kernel Client RM to Physical RM
+ *
+ *   rlBuffers [IN]
+ *     2D array of runlist buffers for a single partition
+ *
+ *   runlistIdMask [IN]
+ *     Mask of runlists belonging to partition
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS (0x20800a53) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID (0x53U)
+
+typedef struct NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO rlBuffers[NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID][NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS], 8);
+    NV_DECLARE_ALIGNED(NvU64 runlistIdMask, 8);
+    NvU32 swizzId;
+} NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO (0x20800a54) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID (0x54U)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS {
+    TEGRA_IMP_IMPORT_DATA tegraImpImportData;
+} NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR
+ *
+ * This command triggers a sysmembar to flush VIDMEM writes.
+ * This command accepts no parameters.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR    (0x20800a70) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x70" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL
+ *
+ * Setup local PCIE P2P Mailbox
+ *
+ * local2Remote[IN]
+ *   Local peer ID of remote gpu on local gpu
+ *
+ * remote2Local[IN]
+ *   Remote peer ID of local gpu on remote gpu
+ *
+ * localP2PDomainRemoteAddr[IN]
+ *   P2P domain remote address on local gpu
+ *
+ * remoteP2PDomainLocalAddr[IN]
+ *   P2P domain local address on remote gpu
+ *
+ * remoteWMBoxLocalAddr[IN]
+ *   Local mailbox address on remote gpu
+ *
+ * p2pWmbTag[OUT]
+ *   Tag for mailbox to transport from local to remote GPU
+ *
+ * bNeedWarBug999673[IN]
+ *   Set to true if WAR for bug 999673 is required
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL (0x20800a71) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID (0x71U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS {
+    NvU32  local2Remote;
+    NvU32  remote2Local;
+    NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 remoteWMBoxLocalAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8);
+    NvBool bNeedWarBug999673;
+} NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS;
+
+ /*
+ * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE
+ *
+ * Setup remote PCIE P2P Mailbox
+ *
+ * local2Remote[IN]
+ *   Local peer ID of remote gpu on local gpu
+ *
+ * remote2Local[IN]
+ *   Remote peer ID of local gpu on remote gpu
+ *
+ * localP2PDomainRemoteAddr[IN]
+ *   P2P domain remote address on local gpu
+ *
+ * remoteP2PDomainLocalAddr[IN]
+ *   P2P domain local address on remote gpu
+ *
+ * remoteWMBoxAddrU64[IN]
+ *   Mailbox address on remote gpu
+ *
+ * p2pWmbTag[IN]
+ *   Tag for mailbox to transport from local to remote GPU
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE (0x20800a72) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID (0x72U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS {
+    NvU32 local2Remote;
+    NvU32 remote2Local;
+    NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 remoteWMBoxAddrU64, 8);
+    NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8);
+} NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX
+ *
+ * Destroy PCIE P2P Mailbox
+ *
+ * peerIdx[IN]
+ *   Peer ID of the P2P destination GPU
+ *
+ * bNeedWarBug999673[IN]
+ *   Set to true if WAR for bug 999673 is required
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX (0x20800a73) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID (0x73U)
+
+typedef struct NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS {
+    NvU32  peerIdx;
+    NvBool bNeedWarBug999673;
+} NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING
+ *
+ * Create C2C mapping to a given peer GPU
+ *
+ * peerId[IN]
+ *   Peer ID for local to remote GPU
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING (0x20800a74) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x74U)
+
+typedef struct NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS {
+    NvU32 peerId;
+} NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING
+ *
+ * Remove C2C mapping to a given peer GPU
+ *
+ * peerId[IN]
+ *   Peer ID for local to remote GPU
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING (0x20800a75) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x75U)
+
+typedef struct NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS {
+    NvU32 peerId;
+} NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES
+ *
+ * Retrieves the corresponding SPAs (per the given GFID's VMMU mappings)
+ * for the given array of GPAs.
+ *
+ *   gfid [IN]
+ *     GFID to translate GPAs for
+ *
+ *   numEntries [IN]
+ *     Number of entries (<= NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES)
+ *     to translate (i.e. number of elements in gpaEntries)
+ *
+ *   gpaEntries [IN]
+ *     Array of GPAs to translate
+ *
+ *   spaEntries [OUT]
+ *     Resulting array of SPAs
+ */
+#define NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES (0x20800a57) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES     128
+
+#define NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID (0x57U)
+
+typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS {
+    NvU32 gfid;
+    NvU32 numEntries;
+    NV_DECLARE_ALIGNED(NvU64 gpaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8);
+    NV_DECLARE_ALIGNED(NvU64 spaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8);
+} NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER
+ *
+ * Pass required pushbuffer parameters from kernel RM to Physical RM
+ *
+ *   addressSpace [IN]
+ *     Address space of pushbuffer whtether it is ADDR_SYSMEM or ADDR_FBMEM
+ *
+ *   physicalAddr [IN]
+ *     Physical address of pushbuffer
+ *
+ *   addressSpace [IN]
+ *     Limit of the pushbuffer address, it should be less than 4K
+ *
+ *   cacheSnoop [IN]
+ *     Cachesnoop supported or not
+ *
+ *   channelInstance [IN]
+ *     Channel instance pass by the client to get corresponding dispchannel
+ *
+ *   hclass [IN]
+ *     External class ID pass by the client to get the channel class
+ *
+ *   valid [IN]
+ *     This bit indicates whether pushbuffer parameters are valid or not
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID (0x58U)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
+    NvU32  addressSpace;
+    NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 limit, 8);
+    NvU32  cacheSnoop;
+    NvU32  hclass;
+    NvU32  channelInstance;
+    NvBool valid;
+} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO
+ *
+ *   This command obtains information from physical RM for use by CPU-RM.
+ *
+ *   replayableFaultBufferSize
+ *     Default size of replayable fault buffer
+ *
+ *   nonReplayableFaultBufferSize
+ *     Default size of non-replayable fault buffer
+ *
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO (0x20800a59) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x59U)
+
+typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS {
+    NvU32 replayableFaultBufferSize;
+    NvU32 nonReplayableFaultBufferSize;
+} NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES           (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x5A" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE
+ *
+ * Get heap reservation size needed by different module
+ */
+#define NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE (0x20800a5b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID (0x5BU)
+
+typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS {
+    NvU32 moduleIndex;
+    NvU32 size;
+} NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE
+ *
+ *   tableLen [OUT]
+ *     Number of valid records in table field.
+ *
+ *   table    [OUT]
+ *     Interrupt table for Kernel RM.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE       128
+
+typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
+    NvU16 engineIdx;
+    NvU32 pmcIntrMask;
+    NvU32 vectorStall;
+    NvU32 vectorNonStall;
+} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY;
+
+#define NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID (0x5CU)
+
+typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
+    NvU32                                            tableLen;
+    NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];
+} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
+
+/* Index to retrieve the needed heap space for specific module */
+#define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR           (0x00000000)
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK
+ *
+ * Checking if the reservation / release of the PERFMON HW is possible
+ *
+ *   bReservation [IN]
+ *     NV_TRUE -> request for reservation, NV_FALSE -> request for release
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK (0x20800a98) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID" */
+
+
+#define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID (0x98U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS {
+    NvBool bReservation;
+} NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET
+ *
+ * Reserving / Releasing PERFMON HW
+ *
+ *   bReservation [IN]
+ *     NV_TRUE -> request for reservation, NV_FALSE -> request for release
+ *
+ *   bClientHandlesGrGating [IN]
+ *     DM-TODO: Add comment for this
+ *
+ *   bRmHandlesIdleSlow [IN]
+ *     If the IDLE slowdown is required
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET (0x20800a99) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID (0x99U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS {
+    NvBool bReservation;
+    NvBool bClientHandlesGrGating;
+    NvBool bRmHandlesIdleSlow;
+} NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES
+ *
+ * Get active display devices
+ *
+ *   displayMask [OUT]
+ *     Get the mask of the active display devices in VBIOS
+ *
+ *   numHeads [OUT]
+ *     Number of heads display supported.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (0x20800a5d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID (0x5DU)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS {
+
+    NvU32 displayMask;
+    NvU32 numHeads;
+} NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
+ *
+ * Get FB Mem page ranges for all possible swizzIds
+ *
+ *   fbMemPageRanges [OUT]
+ *      Mem page ranges for each swizzId in the form of {lo, hi}
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a60) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID                                      15
+
+typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
+    NV_DECLARE_ALIGNED(NvU64 lo, 8);
+    NV_DECLARE_ALIGNED(NvU64 hi, 8);
+} NV2080_CTRL_INTERNAL_NV_RANGE;
+
+#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE fbMemPageRanges[NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID], 8);
+} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to get number of channels for a given runlist ID
+ *
+ *   runlistId   [IN]
+ *   numChannels [OUT]
+ */
+#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS (0x20800a61) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID (0x61U)
+
+typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
+    NvU32 runlistId;
+    NvU32 numChannels;
+} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES
+ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES                    (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x63" */
+
+/*!
+ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK
+ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK          (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES       (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x65" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x66" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG
+ *
+ * This command retrieves memory config from HW
+ *
+ *   memBoundaryCfgA [OUT]
+ *      Memory boundary config A (4KB aligned)
+ *
+ *   memBoundaryCfgB [OUT]
+ *      Memory boundary config B (4KB aligned)
+ *
+ *   memBoundaryCfgC [OUT]
+ *      Memory boundary config C (64KB aligned)
+ *
+ *   memBoundaryCfg [OUT]
+ *      Memory boundary config (64KB aligned)
+ *
+ *   memBoundaryCfgValInit [OUT]
+ *      Memory boundary config initial value (64KB aligned)
+ */
+#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG                  (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x67" */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG                   (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x68" */
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8);
+    NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgB, 8);
+    NvU32 memBoundaryCfgC;
+    NvU32 memBoundaryCfg;
+    NvU32 memBoundaryCfgValInit;
+} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE  (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x6BU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS {
+    NvU32 data[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE];
+} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT
+ *
+ * Invoke RC recovery after watchdog timeout is hit.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT      (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */
+
+/* !
+ *  This command disables cuda limit activation at teardown of the client.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE  (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */
+
+/*
+ *  This command is cleaning up OPTP when a client is found to have
+ *  been terminated unexpectedly.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR      (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */
+
+/* !
+ *  This command is used to get the current AUX power state of the sub-device.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE (0x20800a81) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x81U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS {
+    NvU32 powerState;
+} NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS;
+
+/*!
+ * This command can be used to boost P-State up one level or to the highest for a limited
+ * duration for the associated subdevice. Boosts from different clients are being tracked
+ * independently. Note that there are other factors that can limit P-States so the resulting
+ * P-State may differ from expectation.
+ *
+ *   flags
+ *     This parameter specifies the actual command. _CLEAR is to clear existing boost.
+ *     _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost
+ *     to the highest P-State.
+ *   duration
+ *     This parameter specifies the duration of the boost in seconds. This has to be less
+ *     than NV2080_CTRL_PERF_BOOST_DURATION_MAX.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID (0x9AU)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X {
+
+    NvBool flags;
+    NvU32  duration;
+} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X;
+
+#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE   0U
+#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK   1U
+#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST     NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK
+#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM      (0x2U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST + 1" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL
+ *
+ * Activate/Deactivate GPU Boost Sync algorithm
+ *
+ *   bActivate [IN]
+ *     GPU Boost Sync algorithm:
+ *      NV_TRUE  -> activate
+ *      NV_FALSE -> deactivate
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL (0x20800a7e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7EU)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS {
+    NvBool bActivate;
+} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS
+ *
+ * Apply given limits to a specific subdevice
+ *
+ *   flags [IN]
+ *     DM-TODO: write description here
+ *
+ *   bBridgeless [IN]
+ *     Bridgeless information, for now supporting only MIO bridges
+ *
+ *   currLimits
+ *     Array of limits that will be applied
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS (0x20800a7f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID (0x7FU)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS {
+    NvU32  flags;
+    NvBool bBridgeless;
+    NvU32  currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM];
+} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO
+ *
+ * Data for GPU Boost Sync structure initialization
+ *
+ *   hysteresisus [OUT]
+ *     Hysteresis value for GPU Boost synchronization hysteresis algorithm.
+ *
+ *   bHystersisEnable [OUT]
+ *     hysteresis algorithm for SLI GPU Boost synchronization:
+ *      NV_TRUE  -> enabled,
+ *      NV_FALSE -> disabled
+ *
+ *   bSliGpuBoostSyncEnable [OUT]
+ *     SLI GPU Boost feature is:
+ *      NV_TRUE  -> enabled,
+ *      NV_FALSE -> disabled
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO (0x20800a80) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID (0x80U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 hysteresisus, 8);
+    NvBool bHystersisEnable;
+    NvBool bSliGpuBoostSyncEnable;
+} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER
+ *
+ * This command sends replayable fault buffer pages allocated by CPU-RM
+ * to be setup and enabled in physical RM.
+ *
+ * hClient
+ *   Client handle.
+ *
+ * hObject
+ *   Object handle.
+ *
+ * faultBufferSize
+ *   Size of the replayable fault buffer to register.
+ *
+ * faultBufferPteArray
+ *   Pages of replayable fault buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER (0x20800a9b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES    256
+#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9BU)
+
+typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS {
+    NvHandle hClient;
+    NvHandle hObject;
+    NvU32    faultBufferSize;
+    NV_DECLARE_ALIGNED(NvU64 faultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES], 8);
+} NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER
+ *
+ * This command requests physical RM to disable the replayable fault buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER             (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER
+ *
+ * This command sends client shadow fault buffer pages allocated by CPU-RM
+ * to be setup and enabled in physical RM.
+ *
+ * shadowFaultBufferQueuePhysAddr
+ *   Physical address of shadow fault buffer queue.
+ *
+ * faultBufferSize
+ *   Size of the client shadow fault buffer to register.
+ *
+ * shadowFaultBufferPteArray
+ *   Pages of client shadow fault buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES    1500
+#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU)
+
+typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8);
+    NvU32 shadowFaultBufferSize;
+    NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8);
+} NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER
+ *
+ * Pin PDEs for  Global VA range on the server RM and then mirror the client's page
+ * directory/tables in the server.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER (0x20800a9f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID (0x9FU)
+
+typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS {
+    NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8);
+} NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER
+ *
+ * This command requests physical RM to disable the client shadow fault buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9E" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X
+ *
+ * This command can be used to boost P-State the highest for a limited
+ * duration for the associated subdevice. Boosts from different clients are being tracked
+ * independently. Note that there are other factors that can limit P-States so the resulting
+ * P-State may differ from expectation.
+ *
+ *   flags [IN]
+ *     This parameter specifies the actual command. _CLEAR is to clear existing boost.
+ *     and _BOOST_TO_MAX is to boost to the highest P-State.
+ *
+ *   boostDuration [IN]
+ *     This parameter specifies the duration of the boost in seconds. This has to be less
+ *     than NV2080_CTRL_PERF_BOOST_DURATION_MAX.
+ *
+ *   gfId [IN]
+ *     This specifies Id of the Kernel RM that is requesting the Boost
+ *
+ *   bOverrideInfinite[IN]
+ *      This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM.
+ *      This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM
+ *      and setting the boost duration to a next maximum duration registered for the Kernel RM in question.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X                          (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X {
+    NvU32  flags;
+    NvU32  boostDuration;
+    NvU32  gfId;
+    NvBool bOverrideInfinite;
+} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X
+ *
+ * Clear the boost for specific Kernel RM
+ *
+ *   bIsCudaClient [IN]
+ *     Specifies if the request is for clearing the CUDA boost or regular boost
+ *     NV_TRUE -> CUDA boost, NV_FALSE otherwise
+ *
+ *   gfId [IN]
+ *     Specifies Id of the Kernel RM that is requesting Boost clear
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X (0x20800aa1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID (0xA1U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X {
+
+    NvBool bIsCudaClient;
+    NvU32  gfId;
+} NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO
+ *
+ * Retrieves skyline information about the GPU. Params are sized to currently known max
+ * values, but will need to be modified in the future should that change.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO          (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES            8
+#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 8
+/*!
+ * NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO
+ * skylineVgpcSize[OUT]
+ *      - TPC count of non-singleton VGPCs
+ * singletonVgpcMask[OUT]
+ *      - Mask of active Singletons
+ * maxInstances[OUT]
+ *      - Max allowed instances of this skyline concurrently on a GPU
+ * computeSizeFlag
+ *      - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline
+ * numNonSingletonVgpcs
+ *      - Number of VGPCs with non-zero TPC counts which are not singletons
+ */
+typedef struct NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO {
+    NvU8  skylineVgpcSize[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS];
+    NvU32 singletonVgpcMask;
+    NvU32 maxInstances;
+    NvU32 computeSizeFlag;
+    NvU32 numNonSingletonVgpcs;
+} NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO;
+
+/*!
+ * NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS
+ * skylineTable[OUT]
+ *      - TPC count of non-singleton VGPCs
+ *      - Mask of singleton vGPC IDs active
+ *      - Max Instances of this skyline possible concurrently
+ *      - Associated compute size with the indexed skyline
+ *      - Number of VGPCs with non-zero TPC counts which are not singletons
+ * validEntries[OUT]
+ *      - Number of entries which contain valid info in skylineInfo
+ */
+#define NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0xA2U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS {
+    NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO skylineTable[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES];
+    NvU32                                   validEntries;
+} NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE  (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA3" */
+
+/*!
+ * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA4" */
+
+/*!
+ * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES      (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA5" */
+
+/*!
+ * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES      (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA6" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED
+ *
+ * Tell Physical RM whether any ZBC-kind surfaces are allocated.
+ * If PF and all VFs report false, ZBC table can be flushed by Physical RM.
+ *
+ *   bZbcReferenced [IN]
+ *     NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED     (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
+    NvBool bZbcSurfacesExist;
+} NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE
+ *
+ * Export the resource and placement information about a gpu instance such that a
+ * similar gpu instance can be recreated from scratch in the same position on the
+ * same or similar GPU. Note that different GPUs may have different physical
+ * resources due to floorsweeping, and an imported gpu instance is not guaranteed
+ * to get the exact same resources as the exported gpu instance, but the imported
+ * gpu instance should behave identically with respect to fragmentation and
+ * placement / span positioning.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE                     (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA7" */
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE                      (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA8" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE
+ *
+ * Create a gpu instance resembling the exported instance info. Note that
+ * different GPUs may have different physical resources due to floorsweeping,
+ * and an imported gpu instance is not guaranteed to get the exact same resources
+ * as the exported gpu instance, but the imported gpu instance should behave
+ * identically with respect to fragmentation and placement / span positioning.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE                     (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA9" */
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE                      (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xAA" */
+
+#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4
+typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO {
+    NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8);
+    NvU32 partitionFlags;
+    NvU32 gpcMask;
+    NvU32 virtualGpcCount;
+    NvU32 veidOffset;
+    NvU32 veidCount;
+} NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO;
+
+typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS {
+    NvU32 swizzId;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8);
+} NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT
+ *
+ * Invalidate and/or evict the L2 cache
+ *
+ *   flags [IN]
+ *     flags that specify required actions
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT (0x20800a6c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID (0x6cU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS {
+    NvU32 flags;
+} NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL          (0x00000001)
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST        (0x00000002)
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST         (0x00000004)
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL       (0x00000008)
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN        (0x00000010)
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL (0x00000020)
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES
+ *
+ * Flush all L2 Rams and Caches using the ELPG flush
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES       (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO
+ *
+ * This command obtains information from physical RM for use by CPU-RM
+ *
+ * Data fields ->
+ *   bPcieGen4Capable - tells whether PCIe is Gen4 capable
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO                       (0x20800aac) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xacU)
+
+typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS {
+    NvBool bPcieGen4Capable;
+    NvBool bIsC2CLinkUp;
+    NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8);
+} NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG
+ *
+ * Program HSHUB Peer Conn Config space.
+ *
+ *    programPeerMask[IN]
+ *      If nonzero, the peer mask for programming peers based on hshub connectivity.
+ *
+ *    invalidatePeerMask[IN]
+ *      If nonzero, the peer mask for invalidating peers.
+ *
+ *    programPciePeerMask[IN]
+ *      If nonzero, the peer mask for programming peers in pcie case.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_WARN_NOTHING_TO_DO
+ *     If all peer masks are zero.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG (0x20800a88) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID (0x88U)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS {
+    NvU32 programPeerMask;
+    NvU32 invalidatePeerMask;
+    NvU32 programPciePeerMask;
+} NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID
+ *
+ * Given a mask of link ids, find the first with a valid peerId.
+ *
+ *    linkMask[IN]
+ *      Mask of linkIds to check.
+ *
+ *    peerId[OUT]
+ *      The peerId for the lowest-index link with a valid peerId, if any.
+ *      If none found, NV2080_CTRLINTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER (return value will still be NV_OK).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID          (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER 0xffffffff
+
+#define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID (0x89U)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS {
+    NvU32 linkMask;
+    NvU32 peerId;
+} NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS
+ *
+ * Get the Hshub Ids connected to the other end of links.
+ *
+ *    linkMask[IN]
+ *      A mask of link ids to query.
+ *
+ *    hshubIds[OUT]
+ *      For each set bit in the link mask, the peer Hshub Id.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_WARN_NOTHING_TO_DO
+ *     If the mask is zero.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS        (0x20800a8a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE 32
+
+#define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID (0x8aU)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS {
+    NvU32 linkMask;
+    NvU8  hshubIds[NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE];
+} NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS
+ *
+ * Return the number of HSHUB units.
+ *
+ *    numHshubs[OUT]
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS (0x20800a8b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID (0x8bU)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS {
+    NvU32 numHshubs;
+} NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID
+ *
+ * Return the next hshubId after the given hshubId.
+ *
+ *    hshubId[IN/OUT]
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID (0x20800a8c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID (0x8cU)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS {
+    NvU8 hshubId;
+} NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR
+ *
+ * Enable compute peer addressing mode
+ * This command accepts no parameters.
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR (0x20800aad) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xad" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR
+ *
+ * Get/Set NVSwitch fabric address for FLA
+ *
+ * [In] bGet
+ *     Whether to get or set the NVSwitch fabric address
+ * [In/Out] addr
+ *     Address that is to be set or retrieved.
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID (0xaeU)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS {
+    NvBool bGet;
+    NV_DECLARE_ALIGNED(NvU64 addr, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR (0x20800aae) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS
+ *
+ * This command obtains information from physical RM for use by CPU-RM
+ *
+ * Data fields ->
+ *   bCyaMaskL1
+ *   bEnableAspmDtL1
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS               (0x20800ab0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID (0xb0U)
+
+typedef struct NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS {
+    NvBool bCyaMaskL1;
+    NvBool bEnableAspmDtL1;
+} NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT
+ *
+ * Sets number of VM slots that are active in VGPU's scheduler
+ *
+ *   maxActiveVGpuVMCount [IN]
+ *     Number of VM slots that are active in vGPU's scheduler.
+ *
+ * Possible status values returned are:
+ * NV_OK
+ * NV_ERR_OUT_OF_RANGE - Passed value is out of range
+ * NV_ERR_NO_MEMORY    - Out of memory
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT              (0x20800ab1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Maximum value of VM slots that are active in vGPU's scheduler.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE 32
+
+#define NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID (0xB1U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS {
+    NvU8 maxActiveVGpuVMCount;
+} NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS
+ *
+ * Disable all NVLINK FB peers
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS         (0x20800a6e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6E" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE
+ *
+ * Program GPU in raw / legacy compression mode
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE (0x20800a6f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID (0x6fU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS {
+    NvBool bRawMode;
+} NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_CCU_MAP
+ *
+ * This command gets the shared buffer memory descriptor from the CPU-RM and maps to it
+ * in physical-RM.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_ADDRESS
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CCU_MAP              (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1
+#define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U)
+
+typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 phyAddr[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8);
+} NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS;
+/*
+ * NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP
+ *
+ * This command unmaps the shared buffer memory mapping in physical-RM
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID (0xB4U)
+
+typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS {
+    NvBool bDevShrBuf;
+    NvBool bMigShrBuf;
+} NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO
+ *
+ * [in] gpuId
+ *   GPU ID.
+ * [in] gpuInstance
+ *   GPU instance.
+ * [in] p2pCaps
+ *   Peer to peer capabilities discovered between the GPUs.
+ *   See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values.
+ * [in] p2pOptimalReadCEs
+ *   Mask of CEs to use for p2p reads over Nvlink.
+ * [in] p2pOptimalWriteCEs
+ *   Mask of CEs to use for p2p writes over Nvlink.
+ * [in] p2pCapsStatus
+ *   Status of all supported p2p capabilities.
+ *   See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values.
+ * [in] busPeerId
+ *   Bus peer ID. For an invalid or a non-existent peer this field
+ *   has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
+ */
+typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO {
+    NvU32 gpuId;
+    NvU32 gpuInstance;
+    NvU32 p2pCaps;
+    NvU32 p2pOptimalReadCEs;
+    NvU32 p2pOptimalWriteCEs;
+    NvU8  p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
+    NvU32 busPeerId;
+} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS
+ *
+ * An internal call to propagate the peer to peer capabilities of peer GPUs
+ * to the Physical RM. These capabilities are to be consumed by the vGPU GSP plugin.
+ * This control is used to both add and and update the peer to peer capabilities.
+ * The existing GPU entries will be updated and those which don't exist will be added.
+ * Use NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS to remove the added entries.
+ *
+ *   [in] peerGpuCount
+ *     The number of the peerGpuInfos entries.
+ *   [in] peerGpuInfos
+ *     The array of NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS entries, describing
+ *     the peer to peer capabilities of the specified GPUs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount
+ *   NV_ERR_INSUFFICIENT_RESOURCES - Total GPU count exceeds the maximum value
+ */
+#define NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS (0x20800ab5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID (0xB5U)
+
+typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS {
+    NvU32                                       peerGpuCount;
+    NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO peerGpuInfos[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
+} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS
+ *
+ * An internal call to remove the cached peer to peer capabilities of peer GPUs
+ * from the Physical RM.
+ *
+ *   [in] peerGpuIdCount
+ *     The number of the peerGpuIds entries.
+ *   [in] peerGpuIds
+ *     The array of GPU IDs, specifying the GPU for which the entries need to be removed.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT - Invalid peerGpuIdCount
+ *   NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuIds[] entry
+ */
+#define NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS (0x20800ab6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB6U)
+
+typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS {
+    NvU32 peerGpuIdCount;
+    NvU32 peerGpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
+} NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS;
+
+
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_BUS_GET_PCIE_P2P_CAPS
+ *
+ * This command returns the GPU's PCIE P2P caps
+ *
+ *   [in]  bCommonPciSwitchFound
+ *     All GPUs are under the same PCI switch
+ *   [out] p2pReadCapsStatus
+ *   [out] p2pWriteCapsStatus
+ *     These members returns status of all supported p2p capabilities. Valid
+ *     status values include:
+ *       NV0000_P2P_CAPS_STATUS_OK
+ *         P2P capability is supported.
+ *       NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED
+ *         Chipset doesn't support p2p capability.
+ *       NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED
+ *         GPU doesn't support p2p capability.
+ *       NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED
+ *         IOH topology isn't supported. For e.g. root ports are on different
+ *         IOH.
+ *       NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY
+ *         P2P Capability is disabled by a regkey.
+ *       NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED
+ *         P2P Capability is not supported.
+ * 
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS (0x20800ab8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB8U)
+
+typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS {
+    NvBool bCommonPciSwitchFound;
+    NvU8   p2pReadCapsStatus;
+    NvU8   p2pWriteCapsStatus;
+} NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO
+ *
+ * Enable/disable PCIe Relaxed Ordering.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xB9U)
+
+typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
+    // Enable/disable PCIe relaxed ordering
+    NvBool enableRo;
+} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE
+ *
+ * An internal call to invoke the sequence VGA register reads & writes to 
+ * perform save and restore of VGA
+ *
+ *   [in] saveOrRestore
+ *     To indicate whether save or restore needs to be performed.
+ *   [in] useVbios
+ *     Primary VGA indication from OS.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS {
+
+    NvBool bSaveOrRestore;
+    NvBool bUseVbios;
+} NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE
+ *
+ * To perform restore operation from saved fonts.
+ *
+ *   [in] saveOrRestore
+ *     To indicate whether save or restore needs to be performed.
+ *   [in] useVbios
+ *     Primary VGA indication from OS.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID (0x77U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS {
+
+    NvBool bWriteCr;
+} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES
+ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xba" */
+
+/*!
+ * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE
+ *
+ * This structure specifies resources in an execution partition
+ *
+ *  computeSize[OUT]
+ *      - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile
+ *
+ *  gfxGpcCount[OUT]
+ *      - Total Number of GFX Supporting GPCs in this partition
+ *
+ *  gpcCount[OUT]
+ *      - Total Number of GPCs in this partition (including GFX Supported GPCs)
+ *
+ *  veidCount[OUT]
+ *      - Number of VEIDs allocated to this profile
+ *
+ *  smCount[OUT]
+ *      - Number of SMs usable in this profile
+ */
+typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE {
+    NvU8  computeSize;
+    NvU32 gfxGpcCount;
+    NvU32 gpcCount;
+    NvU32 veidCount;
+    NvU32 smCount;
+    NvU32 physicalSlots;
+} NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE;
+
+/*!
+ * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS
+ *
+ * This structure specifies resources in an execution partition
+ *
+ *  profileCount[OUT]
+ *      - Total Number of profiles filled
+ *
+ *  profiles[OUT]
+ *      - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles 
+ */
+#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS {
+    NvU32                                       profileCount;
+    NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
+} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE
+ *
+ * This command sets the ccu stream to enable/disable state.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE (0x20800abd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID (0xBDU)
+
+typedef struct NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS {
+    NvBool bStreamState;
+} NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT
+ *
+ * Attach GPU to the external device.
+ *
+ *   [in] bExtDevFound
+ *     To enable GPIO interrupts.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT (0x20800abe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID (0xBEU)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS {
+    NvBool bExtDevFound;
+} NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS
+ *
+ * Optimize the Gsync timing parameters
+ *
+ *   [in] timingParameters
+ *     Timing parameters passed by client.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS (0x20800abf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS {
+    NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters;
+} NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS
+ *
+ * Get displayIDs supported by the display.
+ *
+ *   [out] displayIds
+ *     Associated display ID with head.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS (0x20800ac0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_MAX_NUM_HEADS                           4
+
+#define NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID (0xC0U)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS {
+    NvU32 displayIds[NV2080_MAX_NUM_HEADS];
+} NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC
+ *
+ * Set the Stereo sync for Gsync
+ *
+ *   [in] slave
+ *     Slave GPU head status.
+ *   [in] localSlave
+ *     Slave GPU head status but are not coupled.
+ *   [in] master
+ *     Master GPU head status.
+ *   [in] regstatus
+ *     Register status of status1 register.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC (0x20800ac1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID (0xC1U)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS {
+    NvU32 slave[NV2080_MAX_NUM_HEADS];
+    NvU32 localSlave[NV2080_MAX_NUM_HEADS];
+    NvU32 master[NV2080_MAX_NUM_HEADS];
+    NvU32 regStatus;
+} NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES
+ *
+ * Get vertical active lines for given head.
+ *
+ *   [in] head
+ *     For the headIdx which we need active.
+ *   [out] vActiveLines
+ *     Vertical active lines.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES (0x20800ac4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID (0xC4U)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS {
+    NvU32 headIdx;
+    NvU32 vActiveLines;
+} NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID
+ *
+ * Verifies if this displayId is valid.
+ *
+ *   [in] displays
+ *     Displays given by the client
+ *
+ *   [out] displayId
+ *     DisplayId for the given display
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID (0x20800ac9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID (0xC9U)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS {
+    NvU32 displays;
+    NvU32 displayId;
+} NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC
+ *
+ * Disable the raster sync gpio on the other P2060 GPU 
+ * that's connected to master over Video bridge.
+ *
+ *   [in] bEnableMaster
+ *     If it is master gpu.
+ *
+ *   [out] bRasterSyncGpioSaved
+ *     If raster sync GPIO direction is saved or not.
+ *
+ *   [in/out] bRasterSyncGpioDirection
+ *     During save it gets the direction. 
+ *     In restores it sets the direction.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC (0x20800aca) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID (0xCAU)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
+    NvBool bEnableMaster;
+    NvBool bRasterSyncGpioSaved;
+    NvU32  bRasterSyncGpioDirection;
+} NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_FBSR_INIT
+ *
+ * Initialize FBSR on GSP to prepare for suspend-resume
+ *
+ *   [in] fbsrType
+ *     Fbsr object type
+ *   [in] numRegions
+ *     Number of regions that GSP should allocate records for
+ *   [in] hClient
+ *     Handle to client of SYSMEM memlist object
+ *   [in] hSysMem
+ *     Handle to SYSMEM memlist object
+ *   [in] gspFbAllocsSysOffset
+ *     Offset in SYSMEM for GSP's FB Allocations
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U)
+
+typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
+    NvU32    fbsrType;
+    NvU32    numRegions;
+    NvHandle hClient;
+    NvHandle hSysMem;
+    NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8);
+} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO
+ *
+ * Send info of FB region that will be saved/restored by GSP on suspend-resume
+ *
+ *   [in] fbsrType
+ *     Fbsr object type
+ *   [in] hClient
+ *     Handle to client of FBMEM memlist object
+ *   [in] hVidMem
+ *     Handle to FBMEM memlist object
+ *   [in] vidOffset
+ *     Offset in FBMEM region to save/restore
+ *   [in] sysOffset
+ *     Offset in SYSMEM region to save to/restore from
+ *   [in] size
+ *     Size of region being saved/restored 
+ */
+#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID (0xC3U)
+
+typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS {
+    NvU32    fbsrType;
+    NvHandle hClient;
+    NvHandle hVidMem;
+    NV_DECLARE_ALIGNED(NvU64 vidOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 sysOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+} NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB
+ *
+ * This command is used to get the amount of host reserved FB
+ *
+ *  hostReservedFb [OUT]
+ *      Amount of FB reserved for the host
+ *  vgpuTypeId [IN]
+ *      The Type ID for VGPU profile
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB (0x20800ac5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID (0xC5U)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8);
+    NvU32 vgpuTypeId;
+} NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD
+ *
+ * This command initiates brightc module state load.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_ACPI_DSM_READ_SIZE                   (0x1000) /* finn: Evaluated from "(4 * 1024)" */
+
+#define NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID (0xC6U)
+
+typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS {
+    NvU32 status;
+    NvU16 backLightDataSize;
+    NvU8  backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE];
+} NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS;
+
+/*
+ * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL
+ *
+ * Returns number of active links allowed per IOCTRL
+ *
+ * [Out] numActiveLinksPerIoctrl
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC7U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS {
+    NvU32 numActiveLinksPerIoctrl;
+} NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS;
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ac7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */
+/*
+ * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL
+ *
+ * Returns number of links per IOCTRL
+ *
+ * [Out] numLinksPerIoctrl
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC8U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS {
+    NvU32 numLinksPerIoctrl;
+} NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS;
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ac8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE
+ *
+ * Update the system control capability 
+ *
+ *   bIsSysCtrlSupported  [IN]
+        If the system control is supported
+ *   bIsPlatformLegacy [OUT]
+        If the platform is legacy
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE  (0x20800acb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID (0xCBU)
+
+typedef struct NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS {
+    NvBool bIsSysCtrlSupported;
+    NvBool bIsPlatformLegacy;
+} NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS;
+
+/*!
+ * Macros for PFM_REQ_HNDLR_STATE_SYNC data types.
+ */
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR   0x00U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM  0x01U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI 0x02U
+
+/*!
+ * Structure representing static data for a PFM_REQ_HNDLR_STATE_SYNC_SMBPBI.
+ */
+typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI {
+    /*!
+     * PFM sensor ID
+     */
+    NvU32 sensorId;
+
+    /*!
+     * PFM sensor limit value if required 
+     */
+    NvU32 limit;
+} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI;
+
+/*!
+ * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC data types.
+ */
+typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA {
+    /*!
+     * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_<xyz>
+     */
+    NvU8 type;
+
+    /*!
+     * Type-specific information.
+     */
+    union {
+        NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI smbpbi;
+    } data;
+} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA;
+
+/*!
+ * Macros for PFM_REQ_HNDLR_STATE_SYNC flags for specific operation.
+ */
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD       0x00U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT      0x01U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR 0x02U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET   0x03U
+
+/*!
+ * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC params.
+ */
+typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
+    /*!
+     * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_<xyz>
+     */
+    NvU8                                               flags;
+
+    /*!
+     * Type-specific information.
+     */
+    NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA syncData;
+} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC
+ *
+ * State sync with platform req handler and SMBPBI
+ *
+ *   flags [IN]
+ *     Flags that needs sync operation between physical and kernel
+ *
+ *   syncData [IN]
+ *     Sync payload data
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC  (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCC" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC
+ *
+ * State sync with platform req handler and SMBPBI
+ *
+ *   flags [IN]
+ *     Flags that needs sync operation between physical and kernel
+ *
+ *   syncData [IN]
+ *     Sync payload data
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCD" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE
+ *
+ * Query Coherent FB Aperture Size.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE       (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU)
+
+typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS {
+    // Get Coherent Fb Aperture Size
+    NV_DECLARE_ALIGNED(NvU64 coherentFbApertureSize, 8);
+} NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS;
+
+
+/*!
+ * Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag
+ */
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS 0x00U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS            0x01U
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE
+ *
+ * Queries PM1 Forced off / PM1 Available status
+ *
+ *   flag        [IN]
+ *     Fetch PM1 Forced off / PM1 Available status based on value.
+ *   bStatus     [OUT]
+ *     PM1 Forced off / PM1 Available is true or false.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMETS
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE    (0x20800ace) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID (0xCEU)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS {
+    /*!
+     * Fetch PM1 Forced off / PM1 Available status based on value.
+     */
+    NvU8   flag;
+
+    /*!
+     * PM1 Forced off / PM1 Available status
+     */
+    NvBool bStatus;
+} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE
+ *
+ * Set PM1 state to enabled / disabled (boost clocks).
+ *
+ *   bEnable   [IN]
+ *     NV_TRUE means enable PM1, NV_FALSE means disable.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE (0x20800acf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID (0xCFU)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS {
+
+    /*!
+     * NV_TRUE means enable PM1, NV_FALSE means disable.
+     */
+    NvBool bEnable;
+} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT
+ *
+ * Updates EDPpeak Limit of GPU
+ *
+ *   bEnable        [IN]
+ *     Enable or Reset the settings
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_NOT_READY
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT (0x20800ad0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID (0xD0U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS {
+    NvBool bEnable;
+} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT
+ *
+ * Updates Target Temperature of GPU
+ *
+ *   targetTemp        [IN]
+ *     Target Temperature Set from SBIOS
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT (0x20800ad1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID (0xD1U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS {
+    NvS32 targetTemp;
+} NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE
+ *
+ * Enable / disable CTGP MODE
+ *
+ *   bEnable        [IN]
+ *     Enable or Reset the settings
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE (0x20800ad2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID (0xD2U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS {
+    NvBool bEnable;
+} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2
+ *
+ * Configuration of the turbo v2 parameters for NVPCF-Turbo arb control
+ *
+ *   ctgpOffsetmW        [IN]
+ *     TGP MODE Offset in mW
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 (0x20800ad3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID (0xD3U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS {
+    NvU32 ctgpOffsetmW;
+} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO
+ *
+ * Query VPstatese info. Get VPS PS2.0 support / get highest VP State Idx and requested VP State Idx
+ *
+ *   bVpsPs20Supported     [OUT]
+ *     Reflects Vpstates PS20 support
+ *   vPstateIdxHighest     [OUT}
+ *     Reflects Highest VPstate Idx
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO (0x20800ad4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID (0xD4U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS {
+    /*!
+     * Reflects Vpstates PS20 support
+     */
+    NvBool bVpsPs20Supported;
+
+    /*!
+     * Get highest VPState Idx from VBIOS
+     */
+    NvU32  vPstateIdxHighest;
+} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING
+ *
+ * Get vPstate mapping for requested pStateIdx
+ *
+ *   pStateIdx     [IN]
+ *     Requested PState Idx
+ *   vPstateIdx    [OUT}
+ *     Mapped VPstate Idx
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING (0x20800ad5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID (0xD5U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS {
+    /*!
+     * Requested PState Idx
+     */
+    NvU32 pStateIdx;
+
+    /*!
+     * Mapped VPstate Idx
+     */
+    NvU32 vPstateIdxMapping;
+} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE
+ *
+ * Set requested VPstate
+ *
+ *   vPstateIdx   [IN]
+ *     VPstate Idx to be set
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE (0x20800ad6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID (0xD6U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS {
+
+    /*!
+     * NV_TRUE means enable PM1, NV_FALSE means disable.
+     */
+    NvU32 vPstateIdx;
+} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS;
+
+/*
+ *  This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */
+
+/* ctrl2080internal_h */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h
new file mode 100644
index 0000000..9a121f9
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h
@@ -0,0 +1,100 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn
+//
+
+
+
+/*!
+ * NV2080_CTRL_CMD_LPWR_DIFR_CTRL
+ *
+ * This command is used to control the DIFR
+ * feature behavior.
+ *
+ */
+#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL            (0x20802801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID" */
+
+/*!
+ * @brief Various Values for control
+ */
+// Disable the DIFR
+#define NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE        (0x00000001)
+// Enable the DIFR
+#define NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE         (0x00000002)
+
+// Support status for DIFR
+#define NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS (0x00000003)
+
+/*!
+ * Structure containing DIFR control call Parameters
+ */
+#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS {
+    NvU32 ctrlParamVal;
+} NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS;
+
+// Values for the SUPPORT Control Status
+#define NV2080_CTRL_LPWR_DIFR_SUPPORTED                          (0x00000001)
+#define NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED                      (0x00000002)
+
+/*!
+ * NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE
+ *
+ * This control call is used to send the prefetch response
+ *
+ */
+#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE              (0x20802802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID" */
+
+/*!
+ * @brief Various Values of Reponses for Prefetch Status
+ */
+
+// Prefetch is successfull.
+#define NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS                   (0x00000001)
+// OS Filps are enabled, so prefetch can not be done.
+#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED     (0x00000002)
+// Current Display surface can not fit in L2
+#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE (0x00000003)
+// Fatal and un recoverable Error
+#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR          (0x00000004)
+
+/*!
+ * Structure containing DIFR prefetch response control call Parameters
+ */
+#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS {
+    NvU32 responseVal;
+} NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS;
+
+
+// _ctrl2080lpwr_h_
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
new file mode 100644
index 0000000..2bb1c30
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
@@ -0,0 +1,325 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080mc.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "nvcfg_sdk.h"
+
+/* NV20_SUBDEVICE_XX mc control commands and parameters */
+
+/**
+ * NV2080_CTRL_CMD_MC_GET_ARCH_INFO
+ *
+ * This command returns chip architecture information from the
+ * master control engine in the specified GPU.
+ *
+ *   architecture
+ *       This parameter specifies the architecture level for the GPU.
+ *   implementation
+ *       This parameter specifies the implementation of the architecture
+ *       for the GPU.
+ *   revision
+ *       This parameter specifies the revision of the mask used to produce
+ *       the GPU.
+ *   subRevision
+ *       This parameter specific the sub revision of the GPU. Value is one of
+ *       NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_*
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_MC_GET_ARCH_INFO (0x20801701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
+    NvU32 architecture;
+    NvU32 implementation;
+    NvU32 revision;
+    NvU8  subRevision;
+} NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS;
+
+/* valid architecture values */
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X          (0xE0000023)
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100         (0x00000160)
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100         (0x00000170)
+
+
+
+/* valid ARCHITECTURE_T23X implementation values */
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234        (0x00000004)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D       (0x00000005)
+
+
+/* valid ARCHITECTURE_TU10x implementation values */
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100       (0x00000000)
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102       (0x00000002)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104       (0x00000004)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106       (0x00000006)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116       (0x00000008)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117       (0x00000007)
+
+
+/* valid ARCHITECTURE_GA10x implementation values */
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100       (0x00000000)
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102       (0x00000002)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103       (0x00000003)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104       (0x00000004)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106       (0x00000006)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107       (0x00000007)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B       (0x0000000B)
+
+
+
+/* Valid Chip sub revisions */
+#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)
+#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P              (0x00000001)
+#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q              (0x00000002)
+#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R              (0x00000003)
+
+/*
+ * NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS
+ *
+ * This command instructs the RM to service interrupts for the specified
+ * engine(s).
+ *
+ *   engines
+ *       This parameter specifies which engines should have their interrupts
+ *       serviced.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS               (0x20801702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_ENGINE_ID_GRAPHICS                   0x00000001
+#define NV2080_CTRL_MC_ENGINE_ID_ALL                        0xFFFFFFFF
+
+#define NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS {
+    NvU32 engines;
+} NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_MC_GET_MANUFACTURER
+ *
+ * This command returns the GPU manufacturer information for the associated
+ * subdevice.
+ *
+ *   manufacturer
+ *       This parameter returns the manufacturer value for the GPU.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_MC_GET_MANUFACTURER (0x20801703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS {
+    NvU32 manufacturer;
+} NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS
+ *
+ * This command is used to allow clients to query whether hostclk slowdown is
+ * disabled.
+ *
+ *  bDisabled
+ *    This parameter will hold the status of hostclk slowdown
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *
+ */
+#define NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS              (0x20801708) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS {
+    NvBool bDisabled;
+} NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS
+ *
+ * This command is used to allow clients to disable/enable hostclk slowdown.
+ *
+ *  bDisable
+ *    When this parameter is set to TRUE, RM should disable hostclk slowdown.
+ *    If it is set to FALSE, RM will attempt to enable hostclk slowdown, but
+ *    in this case, slowdown is NOT guaranteed to be enabled since there may
+ *    be other reason (like regkey) preventing slowdown.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *
+ */
+#define NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS (0x20801709) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS {
+    NvBool bDisable;
+} NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP
+ *
+ * This call will setup RM to either service or ignore the
+ * repayable fault interrupt.
+ * This is a privileged call that can only be called by the UVM driver
+ * when it will take ownership of the repalayable fault interrupt.
+ *
+ * Possible status values returned are:
+ *   NVOS_STATUS_SUCCESS
+ *   NVOS_STATUS_ERROR_INVALID_ARGUMENT
+ *   NVOS_STATUS_ERROR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP (0x2080170c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS {
+    NvBool bOwnedByRm;
+} NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS
+ *
+ *  This command gets the notification interrupt vectors device for all VGPU engines from Host RM.
+ *
+ *  Parameters:
+ *
+ *    entries [out]
+ *      A buffer to store up to MAX_ENGINES entries of type
+ *      NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY.
+ *
+ *    numEntries [out]
+ *      Number of populated entries in the provided buffer.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ */
+#define NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS         (0x2080170d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES 256
+
+typedef struct NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY {
+    NvU32 nv2080EngineType;
+    NvU32 notificationIntrVector;
+} NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY;
+
+#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS {
+    NvU32                                                numEntries;
+    NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY entries[NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES];
+} NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE
+ *
+ *  This command gets the static interrupts needed by VGPU from Host RM.
+ *
+ *  Parameters:
+ *
+ *    entries [out]
+ *      A buffer to store up to MAX_ENGINES entries of type
+ *      NV2080_CTRL_MC_STATIC_INTR_ENTRY.
+ *
+ *    numEntries [out]
+ *      Number of populated entries in the provided buffer.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ */
+#define NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE    (0x2080170e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX    32
+
+// Interface defines for static MC_ENGINE_IDX defines
+#define NV2080_INTR_TYPE_NULL                       (0x00000000)
+#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT       (0x00000001)
+#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR (0x00000002)
+#define NV2080_INTR_TYPE_INFO_FAULT                 (0x00000003)
+#define NV2080_INTR_TYPE_REPLAYABLE_FAULT           (0x00000004)
+#define NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR     (0x00000005)
+#define NV2080_INTR_TYPE_ACCESS_CNTR                (0x00000006)
+#define NV2080_INTR_TYPE_TMR                        (0x00000007)
+#define NV2080_INTR_TYPE_CPU_DOORBELL               (0x00000008)
+#define NV2080_INTR_TYPE_GR0_FECS_LOG               (0x00000009)
+#define NV2080_INTR_TYPE_GR1_FECS_LOG               (0x0000000A)
+#define NV2080_INTR_TYPE_GR2_FECS_LOG               (0x0000000B)
+#define NV2080_INTR_TYPE_GR3_FECS_LOG               (0x0000000C)
+#define NV2080_INTR_TYPE_GR4_FECS_LOG               (0x0000000D)
+#define NV2080_INTR_TYPE_GR5_FECS_LOG               (0x0000000E)
+#define NV2080_INTR_TYPE_GR6_FECS_LOG               (0x0000000F)
+#define NV2080_INTR_TYPE_GR7_FECS_LOG               (0x00000010)
+
+typedef struct NV2080_CTRL_MC_STATIC_INTR_ENTRY {
+    NvU32 nv2080IntrType;
+    NvU32 pmcIntrMask;
+    NvU32 intrVectorStall;
+    NvU32 intrVectorNonStall;
+} NV2080_CTRL_MC_STATIC_INTR_ENTRY;
+
+#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS {
+    NvU32                            numEntries;
+    NV2080_CTRL_MC_STATIC_INTR_ENTRY entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX];
+} NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS;
+
+/* _ctrl2080mc_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
new file mode 100644
index 0000000..f1e490b
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
@@ -0,0 +1,338 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080nvd.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+#include "ctrl/ctrlxxxx.h"
+/*
+ * NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE
+ *
+ * This command gets the expected dump size of a particular GPU dump component.
+ * Note that events that occur between this command and a later
+ * NV2080_CTRL_CMD_NVD_GET_DUMP command could alter the size of
+ * the buffer required.
+ *
+ *   component
+ *     One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to estimate
+ *     the size of.
+ *   size
+ *     This parameter returns the expected size.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT if component is invalid.
+ *
+ */
+
+#define NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE (0x20802401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS {
+    NvU32 component;
+    NvU32 size;
+} NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVD_GET_DUMP
+ *
+ * This command gets a dump of a particular GPU dump component. If triggers
+ * is non-zero, the command waits for the trigger to occur
+ * before it returns.
+ *
+ *   pBuffer
+ *     This parameter points to the buffer for the data.
+ *  component
+ *     One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to select
+ *     for dumping.
+ *  size
+ *     On entry, this parameter specifies the maximum length for
+ *     the returned data. On exit, it specifies the number of bytes
+ *     returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_ERROR_INVALID_ARGUMENT if component is invalid.
+ *   NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid
+ *   NVOS_ERROR_INVALID_???? if the buffer was too small
+ *
+ *
+ */
+#define NV2080_CTRL_CMD_NVD_GET_DUMP (0x20802402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_NVD_GET_DUMP_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pBuffer, 8);
+    NvU32 component;
+    NvU32 size;
+} NV2080_CTRL_NVD_GET_DUMP_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL
+ *
+ * This command returns the contents of the Journal used by  NOCAT, and
+ * optionally clears the data
+ *
+ *   clear:
+ *     [IN] indicates if should the data be cleared after reporting
+ *
+ *   JournalRecords :
+ *     [OUT] an array of Journal records reported.
+ *
+ *   outstandingAssertCount:
+ *     [OUT] number of asserts that remain to be reported on.
+ *
+ *   reportedAssertCount:
+ *     [OUT] the number of asserts contained in the report
+ *
+ *   asserts:
+ *     [OUT] an array of up to NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS assert reports
+ */
+
+
+#define NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL    (0x20802409) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER     1024
+#define NV2080_NOCAT_JOURNAL_MAX_STR_LEN         65
+#define NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS 10
+#define NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS  32
+
+// structure to hold clock details.
+typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS {
+    NvS32 userMinOffset;
+    NvS32 userMaxOffset;
+    NvU32 factoryMinOffset;
+    NvU32 factoryMaxOffset;
+    NvU32 lastActiveClock;
+    NvU32 lastActiveVolt;
+    NvU32 lastActivePoint;
+    NvU32 kappa;
+} NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS;
+
+
+// structure to hold clock configuration & state.
+typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG {
+    NvU32                                  pstateVer;
+    NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS gpcOverclock;
+    NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS mclkOverclock;
+    NvBool                                 bUserOverclocked;
+    NvBool                                 bFactoryOverclocked;
+} NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG;
+
+// structure to hold the GPU context at the time of the report.
+typedef struct NV2080_NOCAT_JOURNAL_GPU_STATE {
+    NvBool                             bValid;
+    NvU32                              strap;
+    NvU16                              deviceId;
+    NvU16                              vendorId;
+    NvU16                              subsystemVendor;
+    NvU16                              subsystemId;
+    NvU16                              revision;
+    NvU16                              type;
+    NvU32                              vbiosVersion;
+    NvBool                             bOptimus;
+    NvBool                             bMsHybrid;
+    NvBool                             bFullPower;
+    NvU32                              vbiosOemVersion;
+    NvU16                              memoryType;
+    NvU8                               tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU8                               vbiosProject[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvBool                             bInFullchipReset;
+    NvBool                             bInSecBusReset;
+    NvBool                             bInGc6Reset;
+    NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG overclockCfg;
+} NV2080_NOCAT_JOURNAL_GPU_STATE;
+
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN  0
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK 1
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE   2
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_TDR      3
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_RC       4
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT   5
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_ANY      6
+
+// this should be relative to the highest type value
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT    (0x7) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REC_TYPE_ANY + 1" */
+typedef struct NV2080_NOCAT_JOURNAL_ENTRY {
+    NvU8  recType;
+    NvU32 bugcheck;
+    NvU32 tdrBucketId;
+    NvU8  source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU32 subsystem;
+    NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
+    NvU32 diagBufferLen;
+    NvU8  diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER];
+    NvU8  faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU32 mmuFaultType;
+    NvU32 mmuErrorSrc;
+    NvU8  tdrReason[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+} NV2080_NOCAT_JOURNAL_ENTRY;
+
+typedef struct NV2080_NOCAT_JOURNAL_RECORD {
+    NvU32                          GPUTag;
+    NV_DECLARE_ALIGNED(NvU64 loadAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 timeStamp, 8);
+    NV_DECLARE_ALIGNED(NvU64 stateMask, 8);
+    NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState;
+    NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_ENTRY nocatJournalEntry, 8);
+} NV2080_NOCAT_JOURNAL_RECORD;
+
+// NOCAT activity counter indexes
+// collection activity
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX         0
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX           1
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX           2
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX        3
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX      4
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_DROPPED_IDX 5
+
+// reporting activity
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX           6
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX            7
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX             8
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX              9
+
+// update activity
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX          10
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX             11
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX       12
+
+// general errors
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX                13
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX           14
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX            15
+
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX                16
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX                17
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CACHE_UPDATE_IDX        18
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX      19
+
+// this should be relative to the highest counter index
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT           (0x14) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX + 1" */
+
+#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY         0:0
+#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES                      1
+#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO                       0
+
+#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS        1:1
+#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES                     1
+#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO                      0
+
+
+#define NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
+    NvU32 flags;
+    NvU32 nocatRecordCount;
+    NvU32 nocatOutstandingRecordCount;
+    NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_RECORD journalRecords[NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS], 8);
+    NvU32 activityCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT];
+    NvU8  reserved[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+} NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS;
+
+ /*
+ * NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA
+ *
+ * This command reports the TDR data collected by KMD to be added to the
+ * nocat record
+ *
+ *   dataType:
+ *     [IN] specifies the type of data provided.
+ *  targetRecordType
+ *     [IN] specifies record type the data is intended for.
+ *  nocatJournalData
+ *     [IN] specifies the data to be added.
+ */
+
+#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA        (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */
+
+// data types & structures
+#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY         0
+#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON    1
+#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2
+#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG       3
+
+#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE                   0
+#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY                 1
+#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP               2
+#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET               3
+#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET              4
+#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL       5
+#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET            6
+#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST                   7
+
+typedef struct NV2080CtrlNocatJournalDataTdrReason {
+    NvU32 flags;
+    NvU8  source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU32 subsystem;
+    NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
+    NvU32 reasonCode;
+} NV2080CtrlNocatJournalDataTdrReason;
+
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR         0:0
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES     1
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO      0
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER     1:1
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO  0
+typedef struct NV2080CtrlNocatJournalInsertRecord {
+    NvU32 flags;
+    NvU8  recType;
+    NvU32 bugcheck;
+    NvU8  source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU32 subsystem;
+    NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
+    NvU8  faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU32 tdrReason;
+} NV2080CtrlNocatJournalInsertRecord;
+
+#define NV2080_CTRL_NOCAT_TAG_CLEAR                 0:0
+#define NV2080_CTRL_NOCAT_TAG_CLEAR_YES 1
+#define NV2080_CTRL_NOCAT_TAG_CLEAR_NO  0
+typedef struct NV2080CtrlNocatJournalSetTag {
+    NvU32 flags;
+    NvU8  tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+} NV2080CtrlNocatJournalSetTag;
+
+#define NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS {
+    NvU32 dataType;
+    NvU32 targetRecordType;
+    union {
+        NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8);
+        NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8);
+        NV2080CtrlNocatJournalSetTag tagData;
+    } nocatJournalData;
+} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS;
+/* _ctr2080nvd_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
new file mode 100644
index 0000000..090f813
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
@@ -0,0 +1,2950 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX bus control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS
+ *
+ * This command returns the NVLink capabilities supported by the subdevice.
+ *
+ *   capsTbl
+ *     This is bit field for getting different global caps. The individual bitfields are specified by NV2080_CTRL_NVLINK_CAPS_* 
+ *   lowestNvlinkVersion
+ *     This field specifies the lowest supported NVLink version for this subdevice.
+ *   highestNvlinkVersion
+ *     This field specifies the highest supported NVLink version for this subdevice.
+ *   lowestNciVersion
+ *     This field specifies the lowest supported NCI version for this subdevice.
+ *   highestNciVersion
+ *     This field specifies the highest supported NCI version for this subdevice.
+ *   discoveredLinkMask
+ *     This field provides a bitfield mask of NVLink links discovered on this subdevice.
+ *   enabledLinkMask
+ *     This field provides a bitfield mask of NVLink links enabled on this subdevice.
+ *
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
+    NvU32 capsTbl;
+
+    NvU8  lowestNvlinkVersion;
+    NvU8  highestNvlinkVersion;
+    NvU8  lowestNciVersion;
+    NvU8  highestNciVersion;
+
+    NvU32 discoveredLinkMask;
+    NvU32 enabledLinkMask;
+} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS;
+
+/* extract cap bit setting from tbl */
+#define NV2080_CTRL_NVLINK_GET_CAP(tbl,c)              (((NvU8)tbl[(1?c)]) & (0?c))
+
+/*
+ * NV2080_CTRL_NVLINK_CAPS
+ *
+ *   SUPPORTED
+ *     Set if NVLink is present and supported on this subdevice, NV_FALSE otherwise. This field is used for *global* caps only and NOT for per-link caps
+ *   P2P_SUPPORTED
+ *     Set if P2P over NVLink is supported on this subdevice, NV_FALSE otherwise.
+ *   SYSMEM_ACCESS
+ *     Set if sysmem can be accessed over NVLink on this subdevice, NV_FALSE otherwise.
+ *   PEER_ATOMICS
+ *     Set if P2P atomics are supported over NVLink on this subdevice, NV_FALSE otherwise.
+ *   SYSMEM_ATOMICS
+ *     Set if sysmem atomic transcations are supported over NVLink on this subdevice, NV_FALSE otherwise.
+ *   PEX_TUNNELING
+ *     Set if PEX tunneling over NVLink is supported on this subdevice, NV_FALSE otherwise.
+ *   SLI_BRIDGE
+ *     GLOBAL: Set if SLI over NVLink is supported on this subdevice, NV_FALSE otherwise.
+ *     LINK:   Set if SLI over NVLink is supported on a link, NV_FALSE otherwise.
+ *   SLI_BRIDGE_SENSABLE
+ *     GLOBAL: Set if the subdevice is capable of sensing SLI bridges, NV_FALSE otherwise.
+ *     LINK:   Set if the link is capable of sensing an SLI bridge, NV_FALSE otherwise.
+ *   POWER_STATE_L0
+ *     Set if L0 is a supported power state on this subdevice/link, NV_FALSE otherwise.
+ *   POWER_STATE_L1
+ *     Set if L1 is a supported power state on this subdevice/link, NV_FALSE otherwise.
+ *   POWER_STATE_L2
+ *     Set if L2 is a supported power state on this subdevice/link, NV_FALSE otherwise.
+ *   POWER_STATE_L3
+ *     Set if L3 is a supported power state on this subdevice/link, NV_FALSE otherwise.
+ *   VALID
+ *     Set if this link is supported on this subdevice, NV_FALSE otherwise. This field is used for *per-link* caps only and NOT for global caps.
+ *
+ */
+
+/* caps format is byte_index:bit_mask */
+#define NV2080_CTRL_NVLINK_CAPS_SUPPORTED                          0:0x01
+#define NV2080_CTRL_NVLINK_CAPS_P2P_SUPPORTED                      0:0x02
+#define NV2080_CTRL_NVLINK_CAPS_SYSMEM_ACCESS                      0:0x04
+#define NV2080_CTRL_NVLINK_CAPS_P2P_ATOMICS                        0:0x08
+#define NV2080_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS                     0:0x10
+#define NV2080_CTRL_NVLINK_CAPS_PEX_TUNNELING                      0:0x20
+#define NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE                         0:0x40
+#define NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE_SENSABLE                0:0x80
+#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L0                     1:0x01
+#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L1                     1:0x02
+#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L2                     1:0x04
+#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L3                     1:0x08
+#define NV2080_CTRL_NVLINK_CAPS_VALID                              1:0x10
+
+/*
+ * Size in bytes of nvlink caps table.  This value should be one greater
+ * than the largest byte_index value above.
+ */
+#define NV2080_CTRL_NVLINK_CAPS_TBL_SIZE               2U
+
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0     (0x00000001U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0     (0x00000002U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2     (0x00000004U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0     (0x00000005U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1     (0x00000006U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0     (0x00000007U)
+
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID    (0x00000000U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0        (0x00000001U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0        (0x00000002U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2        (0x00000004U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0        (0x00000005U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1        (0x00000006U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0        (0x00000007U)
+
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS         (0x20803001U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID" */
+
+/* 
+ * NV2080_CTRL_NVLINK_DEVICE_INFO
+ *
+ * This structure stores information about the device to which this link is associated
+ *
+ *   deviceIdFlags
+ *      Bitmask that specifies which IDs are valid for the device
+ *      Refer NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_* for possible values
+ *      If NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI is set, PCI information is valid
+ *      If NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID is set, UUID is valid
+ *   domain, bus, device, function, pciDeviceId
+ *      PCI information for the device
+ *   deviceType
+ *      Type of the device
+ *      See NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_* for possible values
+ *   deviceUUID
+ *      This field specifies the device UUID of the device. Useful for identifying the device (or version)
+ */
+typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO {
+    // ID Flags
+    NvU32 deviceIdFlags;
+
+    // PCI Information
+    NvU32 domain;
+    NvU16 bus;
+    NvU16 device;
+    NvU16 function;
+    NvU32 pciDeviceId;
+
+    // Device Type
+    NV_DECLARE_ALIGNED(NvU64 deviceType, 8);
+
+    // Device UUID
+    NvU8  deviceUUID[16];
+} NV2080_CTRL_NVLINK_DEVICE_INFO;
+
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS        31:0 
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI  (0x00000001U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002U)
+
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE  (0x00000000U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU      (0x00000001U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU      (0x00000002U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH   (0x00000003U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA    (0x00000004U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE     (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID  (0xFFFFFFFFU)
+
+/*
+ * NV2080_CTRL_NVLINK_NVLINK_LINK_STATUS_INFO
+ *
+ * This structure stores the per-link status of different NVLink parameters.
+ *
+ *   capsTbl
+ *     This is bit field for getting different global caps. The individual bitfields
+ *     are specified by NV2080_CTRL_NVLINK_CAPS_*
+ *   phyType
+ *     This field specifies the type of PHY (NVHS or GRS) being used for this link.
+ *   subLinkWidth
+ *     This field specifies the no. of lanes per sublink.
+ *   linkState
+ *     This field specifies the current state of the link.
+ *     See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_LINK_STATE_* for possible values.
+ *   rxSublinkStatus
+ *     This field specifies the current state of RX sublink.
+ *     See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_SUBLINK_RX_STATE_* for possible values.
+ *   txSublinkStatus
+ *     This field specifies the current state of TX sublink.
+ *     See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_SUBLINK_TX_STATE_* for possible values.
+ *   bLaneReversal
+ *     This field indicates that lane reversal is in effect on this link.
+ *   nvlinkVersion
+ *     This field specifies the NVLink version supported by the link.
+ *   nciVersion
+ *     This field specifies the NCI version supported by the link.
+ *   phyVersion
+ *     This field specifies the version of PHY being used by the link.
+ *   nvlinkLineRateMbps
+ *      Bit rate at which bits toggle on wires in megabits per second.
+ *      NOTE: This value is the full speed line rate, not the instantaneous line rate of the link.
+ *   nvlinkLinkClockMhz
+ *      Clock corresponding to link logic in mega hertz
+ *   nvlinkRefClkType
+ *      This field specifies whether the link clock is taken from NVHS reflck
+ *      or PEX refclk for the current GPU.
+ *   nvlinkLinkDataRateKiBps
+ *      Effective rate available for transactions after subtracting overhead,
+ *      as seen at Data Layer in kibibytes (1024 bytes) per second.
+ *      Only valid in GA100+, reported as 0 otherwise
+ *      NOTE: Because minion calculates these values, it will only be valid if
+ *            links are in ACTIVE state
+ *   nvlinkRefClkSpeedMhz
+ *      The input reference frequency to the PLL
+ *   connected
+ *     This field specifies if any device is connected on the other end of the link
+ *   loopProperty
+ *     This field specifies if the link is a loopback/loopout link. See NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_* for possible values.
+ *   remoteDeviceLinkNumber
+ *     This field specifies the link number on the remote end of the link 
+ *   remoteDeviceInfo
+ *     This field stores the device information for the remote end of the link
+ *
+ */
+typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
+    // Top level capablilites
+    NvU32  capsTbl;
+
+    NvU8   phyType;
+    NvU8   subLinkWidth;
+
+    // Link and sublink states
+    NvU32  linkState;
+    NvU8   rxSublinkStatus;
+    NvU8   txSublinkStatus;
+
+    // Indicates that lane reversal is in effect on this link.
+    NvBool bLaneReversal;
+
+    NvU8   nvlinkVersion;
+    NvU8   nciVersion;
+    NvU8   phyVersion;
+
+    // Legacy clock information (to be deprecated)
+    NvU32  nvlinkLinkClockKHz;
+    NvU32  nvlinkCommonClockSpeedKHz;
+    NvU32  nvlinkRefClkSpeedKHz;
+
+    NvU32  nvlinkCommonClockSpeedMhz;
+
+    // Clock Speed and Data Rate Reporting
+    NvU32  nvlinkLineRateMbps;
+    NvU32  nvlinkLinkClockMhz;
+    NvU8   nvlinkRefClkType;
+    NvU32  nvlinkLinkDataRateKiBps;
+    NvU32  nvlinkRefClkSpeedMhz;
+
+    // Connection information
+    NvBool connected;
+    NvU8   loopProperty;
+    NvU8   remoteDeviceLinkNumber;
+    NvU8   localDeviceLinkNumber;
+
+    //
+    // Added as part of NvLink 3.0
+    // Note: SID has link info appended to it when provided by minion
+    //
+    NV_DECLARE_ALIGNED(NvU64 remoteLinkSid, 8);
+    NV_DECLARE_ALIGNED(NvU64 localLinkSid, 8);
+
+    // Ampere+ only
+    NvU32  laneRxdetStatusMask;
+
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO remoteDeviceInfo, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO localDeviceInfo, 8);
+} NV2080_CTRL_NVLINK_LINK_STATUS_INFO;
+
+// NVLink link states
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT               (0x00000000U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG              (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG              (0x00000002U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE             (0x00000003U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT              (0x00000004U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP              (0x00000005U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY           (0x00000006U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC        (0x00000008U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX        (0x0000000aU)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID            (0xFFFFFFFFU)
+
+// NVLink Rx sublink states
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000U)
+// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE  (0x00000004) // Deprecated
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER    (0x00000004)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING     (0x00000005U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE    (0x00000006U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF          (0x00000007U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST         (0x00000008U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT        (0x0000000eU)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID      (0x000000FFU)
+
+// NVLink Tx sublink states
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000U)
+// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE  (0x00000004) // Deprecated
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER    (0x00000004)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING     (0x00000005U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE    (0x00000006U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF          (0x00000007U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST         (0x00000008U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT        (0x0000000eU)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID      (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_STATUS_PHY_NVHS                      (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_PHY_GRS                       (0x00000002U)
+#define NV2080_CTRL_NVLINK_STATUS_PHY_INVALID                   (0x000000FFU)
+
+// Version information
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0            (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0            (0x00000002U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2            (0x00000004U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0            (0x00000005U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1            (0x00000006U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0            (0x00000007U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID        (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0               (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0               (0x00000002U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2               (0x00000004U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0               (0x00000005U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1               (0x00000006U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0               (0x00000007U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID           (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0              (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID          (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0               (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID           (0x000000FFU)
+
+// Connection properties
+#define NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE                (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE               (0x00000000U)
+
+#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK        (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT         (0x00000002U)
+#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE            (0x00000000U)
+
+#define NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID    (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_MAX_LINKS                            32
+
+// NVLink REFCLK types
+#define NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID                  (0x00U)
+#define NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS                     (0x01U)
+#define NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX                      (0x02U)
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS {
+    NvU32  enabledLinkMask;
+    NvBool bSublinkStateInst; // whether instantaneous sublink state is needed 
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
+} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS
+ *
+ *   enabledLinkMask
+ *     This field specifies the mask of available links on this subdevice.
+ *   linkInfo
+ *     This structure stores the per-link status of different NVLink parameters. The link is identified using an index.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS (0x20803002U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_NVLINK_ERR_INFO
+ *   Error information per link
+ *
+ *   TLErrlog
+ *     Returns the error mask for NVLINK TL errors
+ *     Used in Pascal
+ *
+ *   TLIntrEn
+ *     Returns the intr enable mask for NVLINK TL errors
+ *     Used in Pascal
+ *
+ *   TLCTxErrStatus0
+ *     Returns the TLC Tx Error Mask 0
+ *     Used in Volta and later
+ *
+ *   TLCTxErrStatus1
+ *     Returns the TLC Tx Error Mask 1
+ *     Used in Ampere and later
+ *
+ *   TLCTxSysErrStatus0
+ *     Returns the TLC Tx Sys Error Mask 0
+ *     Used in Ampere and later.
+ *
+ *   TLCRxErrStatus0
+ *     Returns the TLC Rx Error Mask 0
+ *     Used in Volta and later
+ *
+ *   TLCRxErrStatus1
+ *     Returns the TLC Rx Error Mask 1
+ *     Used in Volta and later
+ *
+ *   TLCRxSysErrStatus0
+ *     Returns the TLC Rx Sys Error Mask 0
+ *     Used in Ampere and later.
+ *
+ *   TLCTxErrLogEn0
+ *     Returns the TLC Tx Error Log En 0
+ *     Used in Volta and later
+ *
+ *   TLCTxErrLogEn1
+ *     Returns the TLC Tx Error Log En 1
+ *     Used in Ampere and later
+ *
+ *   TLCTxSysErrLogEn0
+ *     Returns the TLC Tx Sys Error Log En 0
+ *     Used in Ampere and later
+ *
+ *   TLCRxErrLogEn0
+ *     Returns the TLC Rx Error Log En 0
+ *     Used in Volta and later
+ *
+ *   TLCRxErrLogEn1
+ *     Returns the TLC Rx Error Log En 1
+ *     Used in Volta and later
+ *
+ *   TLCRxSysErrLogEn0
+ *     Returns the TLC Rx Sys Error Log En 0
+ *     Used in Ampere and later
+ *
+ *   MIFTxErrStatus0
+ *     Returns the MIF Rx Error Mask 0
+ *     Used in Volta and Turing
+ *
+ *   MIFRxErrStatus0
+ *     Returns the MIF Tx Error Mask 0
+ *     Used in Volta and Turing
+ *
+ *   NVLIPTLnkErrStatus0
+ *     Returns the NVLIPT_LNK Error Mask 0
+ *     Used in Ampere and later
+ *
+ *   NVLIPTLnkErrLogEn0
+ *     Returns the NVLIPT_LNK Log En Mask 0
+ *     Used in Ampere and later
+ *
+ *   NVLIPTLnkCtrlLinkStateRequest
+ *     Returns the NVLIPT_LNK Control Link State Request value
+ *     Used in Ampere and later
+ *
+ *   DLSpeedStatusTx
+ *     Returns the NVLINK DL speed status for sublink Tx
+ *
+ *   DLSpeedStatusRx
+ *     Returns the NVLINK DL speed status for sublink Rx
+ *
+ *   NVLDLRxSlsmErrCntl
+ *     Returns the NVLDL_RXSLSM_ERR_CNTL value
+ *     Used in Hopper and later
+ *
+ *   NVLDLTopLinkState
+ *     Returns the NVLDL_TOP_LINK_STATE value
+ *     Used in Hopper and later
+ *
+ *   NVLDLTopIntr
+ *     Returns the NVLDL_TOP_INTR value
+ *     Used in Hopper and later
+ *
+ *   DLStatMN00
+ *     Returns the DLSTAT MN00 Code and subcode
+ *     Used in Hopper and later
+ *
+ *   DLStatUC01
+ *     Returns the DLSTAT UC01 value
+ *     Used in Hopper and later
+ *
+ *   MinionNvlinkLinkIntr
+ *     Returns the MINION_NVLINK_LINK_INTR code and subcode
+ *     Used in Hopper and later
+ *
+ *   bExcessErrorDL
+ *     Returns true for excessive error rate interrupt from DL
+ */
+typedef struct NV2080_CTRL_NVLINK_ERR_INFO {
+    NvU32  TLErrlog;
+    NvU32  TLIntrEn;
+    NvU32  TLCTxErrStatus0;
+    NvU32  TLCTxErrStatus1;
+    NvU32  TLCTxSysErrStatus0;
+    NvU32  TLCRxErrStatus0;
+    NvU32  TLCRxErrStatus1;
+    NvU32  TLCRxSysErrStatus0;
+    NvU32  TLCTxErrLogEn0;
+    NvU32  TLCTxErrLogEn1;
+    NvU32  TLCTxSysErrLogEn0;
+    NvU32  TLCRxErrLogEn0;
+    NvU32  TLCRxErrLogEn1;
+    NvU32  TLCRxSysErrLogEn0;
+    NvU32  MIFTxErrStatus0;
+    NvU32  MIFRxErrStatus0;
+    NvU32  NVLIPTLnkErrStatus0;
+    NvU32  NVLIPTLnkErrLogEn0;
+    NvU32  NVLIPTLnkCtrlLinkStateRequest;
+    NvU32  DLSpeedStatusTx;
+    NvU32  DLSpeedStatusRx;
+    NvU32  NVLDLRxSlsmErrCntl;
+    NvU32  NVLDLTopLinkState;
+    NvU32  NVLDLTopIntr;
+    NvU32  DLStatMN00;
+    NvU32  DLStatUC01;
+    NvU32  MinionNvlinkLinkIntr;
+    NvBool bExcessErrorDL;
+} NV2080_CTRL_NVLINK_ERR_INFO;
+
+/*
+ * NV2080_CTRL_NVLINK_COMMON_ERR_INFO
+ *   Error information per IOCTRL
+ *
+ *   NVLIPTErrStatus0
+ *     Returns the NVLIPT_COMMON Error Mask 0
+ *     Used in Ampere and later
+ *
+ *   NVLIPTErrLogEn0
+ *     Returns the NVLIPT_COMMON Log En Mask 0
+ *     Used in Ampere and later
+ */
+typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO {
+    NvU32 NVLIPTErrStatus0;
+    NvU32 NVLIPTErrLogEn0;
+} NV2080_CTRL_NVLINK_COMMON_ERR_INFO;
+
+/* Extract the error status bit for a given TL error index i */
+#define NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i)       (((1U << i) & (intr)) >> i)
+
+/* Extract the intr enable bit for a given TL error index i */
+#define NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT(intr, i)        NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i)
+
+/* Error status values for a given NVLINK TL error */
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE                               (0x00000001U)
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE                              (0x00000000U)
+
+/* Intr enable/disable for a given NVLINK TL error */
+#define NV2080_CTRL_NVLINK_TL_INTEN_TRUE                                (0x00000001U)
+#define NV2080_CTRL_NVLINK_TL_INTEN_FALSE                               (0x00000000U)
+
+/* NVLINK TL interrupt enable fields for errors */
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN                0U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN                1U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN                    2U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN                    3U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN               4U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN                5U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN                        6U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN                      7U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN               8U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN                9U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN                  10U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN                   12U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN                      13U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX                             14U
+
+/* NVLINK TL error fields */
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR              0U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR              1U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR                  2U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR                  3U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR             4U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR              5U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR                      6U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR                    7U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR             8U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR              9U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR                10U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR                 12U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR                    13U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX                            14U
+
+/* NVLINK DL speed status for sublink Tx*/
+#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS          (0x00000000U)
+#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE (0x00000004U)
+#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN       (0x00000005U)
+#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE        (0x00000006U)
+#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF         (0x00000007U)
+
+/* NVLINK DL speed status for sublink Rx*/
+#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS          (0x00000000U)
+#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE (0x00000004U)
+#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN       (0x00000005U)
+#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE        (0x00000006U)
+#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF         (0x00000007U)
+
+/* Flags to query different debug registers */
+#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT                       (0x0U)
+#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS                   (0x1U)
+#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS                    (0x2U)
+
+#define NV2080_CTRL_NVLINK_MAX_IOCTRLS                                  3U
+/*
+ *   NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS
+ *
+ *   linkMask
+ *     Returns the mask of links enabled
+ *
+ *   linkErrInfo
+ *     Returns the error information for all the links
+ *
+ *   ioctrlMask
+ *     Returns the mask of ioctrls
+ *
+ *   commonErrInfo
+ *     Returns the error information common to each IOCTRL
+ *
+ *   ErrInfoFlags
+ *     Input for determining which values to query. Possible values:
+ *     NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS
+ *     NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS
+ *
+ */
+#define NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS {
+    NvU32                              linkMask;
+    NV2080_CTRL_NVLINK_ERR_INFO        linkErrInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
+    NvU32                              ioctrlMask;
+    NV2080_CTRL_NVLINK_COMMON_ERR_INFO commonErrInfo[NV2080_CTRL_NVLINK_MAX_IOCTRLS];
+    NvU8                               ErrInfoFlags;
+} NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO
+ *     This command is used to query the NVLINK error information
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO                 (0x20803003U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * APIs for getting NVLink counters
+ */
+
+// These are the bitmask definitions for different counter types
+
+#define NV2080_CTRL_NVLINK_COUNTER_INVALID                  0x00000000U
+
+#define NV2080_CTRL_NVLINK_COUNTER_TL_TX0                   0x00000001U
+#define NV2080_CTRL_NVLINK_COUNTER_TL_TX1                   0x00000002U
+#define NV2080_CTRL_NVLINK_COUNTER_TL_RX0                   0x00000004U
+#define NV2080_CTRL_NVLINK_COUNTER_TL_RX1                   0x00000008U
+
+#define NV2080_CTRL_NVLINK_LP_COUNTERS_DL                   0x00000010U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L(i)      (1 << (i + 8))
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE 4U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0    0x00000100U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1    0x00000200U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2    0x00000400U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3    0x00000800U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT       0x00010000U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i)      (1 << (i + 17))
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE 8U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0    0x00020000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1    0x00040000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2    0x00080000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3    0x00100000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4    0x00200000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5    0x00400000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6    0x00800000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7    0x01000000U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY         0x02000000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY       0x04000000U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY         0x08000000U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED     0x10000000U
+
+/*
+ * Note that COUNTER_MAX_TYPES will need to be updated each time
+ * a new counter type gets added to the list above.
+ *
+ */
+#define NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES                32U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * [in] counterMask
+ *     Mask of counter types to be queried
+ *     One of NV2080_CTRL_NVLINK_COUNTERS_TYPE_* macros
+ *
+ * [in] linkMask
+ *     Mask of links to be queried
+ *
+ * [out] counters
+ *     Counter value returned
+ *
+ * [out] bTx0TlCounterOverflow
+ *  This boolean is set to NV_TRUE if TX Counter 0 has rolled over.
+ *
+ * [out] bTx1TlCounterOverflow
+ *  This boolean is set to NV_TRUE if TX Counter 1 has rolled over.
+ *
+ * [out] bRx0TlCounterOverflow
+ *  This boolean is set to NV_TRUE if RX Counter 0 has rolled over.
+ *
+ * [out] bRx1TlCounterOverflow
+ *  This boolean is set to NV_TRUE if RX Counter 1 has rolled over.
+ *
+ *     [out] value 
+ *  This array contains the error counts for each error type as requested from
+ *  the counterMask. The array indexes correspond to the mask bits one-to-one.
+ */
+typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES {
+    NvBool bTx0TlCounterOverflow;
+    NvBool bTx1TlCounterOverflow;
+    NvBool bRx0TlCounterOverflow;
+    NvBool bRx1TlCounterOverflow;
+    NV_DECLARE_ALIGNED(NvU64 value[NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES], 8);
+} NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES;
+
+#define NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS {
+    NvU32 counterMask;
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
+} NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS   (0x20803004U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID" */
+
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS
+ *  This command clears/resets the counters for the specified types.
+ *
+ * [in] linkMask
+ *  This parameter specifies for which links we want to clear the 
+ *  counters.
+ *
+ * [in] counterMask
+ *  This parameter specifies the input mask for desired counters to be
+ *  cleared. Note that all counters cannot be cleared.
+ *
+ *  NOTE: Bug# 2098529: On Turing all DL errors and LP counters are cleared
+ *        together. They cannot be cleared individually per error type. RM
+ *        would possibly move to a new API on Ampere and beyond
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS (0x20803005U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
+    NvU32 counterMask;
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_INJECT_ERROR
+ *  This command causes all the same actions to occur as if the related
+ *  error were to occur, either fatal or recoverable.
+ *
+ * [in] linkMask        size: 32 bits
+ *  Controls which links to apply error injection to.
+ * [in] bFatal
+ *  This parameter specifies that the error should be fatal.
+ *
+ */
+#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS {
+    NvU32  linkMask;
+    NvBool bFatalError;
+} NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS;
+
+/* NVLINK unit list - to be used with error notifiers */
+#define NV2080_CTRL_NVLINK_UNIT_DL                  0x01U
+#define NV2080_CTRL_NVLINK_UNIT_TL                  0x02U
+#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_0            0x03U
+#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_1            0x04U
+#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0            0x05U
+#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0            0x06U
+#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0            0x07U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES
+ *  This command gets the number of successful error recoveries
+ *
+ * [in]  linkMask        size: 32 bits
+ *    This parameter controls which links to get recoveries for.
+ * [out] numRecoveries
+ *    This parameter specifies the number of successful per link error recoveries
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES (0x20803007U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS {
+    NvU32 linkMask;
+    NvU32 numRecoveries[NV2080_CTRL_NVLINK_MAX_LINKS];
+} NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE
+ *
+ * This command queries the remote endpoint type of the link recorded at the
+ * time the last error occurred on the link.
+ *
+ *   [in] linkId
+ *     This parameter specifies the link to get the last remote endpoint type
+ *     recorded for.
+ *
+ *   [out] remoteType
+ *     This parameter returns the remote endpoint type of the link recorded at
+ *     the time the last error occurred on the link. Possible values are:
+ *       NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE
+ *         The link is not connected to an active remote endpoint.
+ *       NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU
+ *         The remote endpoint of the link is a peer GPU.
+ *       NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU
+ *         The remote endpoint of the link is the host system (e.g., an NPU
+ *         on IBM POWER platforms).
+ *       NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA
+ *         The remote endpoint of the link a tegra device
+ *
+ * Possible return status values are:
+ *   NV_OK
+ *     If the remoteType parameter value is valid upon return.
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the linkId parameter does not specify a valid link.
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on this GPU or the remote endpoint type is
+ *     not recorded in non-volatile storage.
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE (0x20803008U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS {
+    NvU32 linkId;
+    NvU32 remoteType;
+} NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS
+ *
+ * This command queries the number of each type of fatal errors that have
+ * occurred on the given link.
+ *
+ *   [in] linkId
+ *     This parameter specifies the link to get the fatal error information
+ *     for.
+ *
+ *   [out] supportedCounts
+ *     This parameter identifies which counts in the fatalErrorCounts array
+ *     are valid for the given link. A bit set in this field means that the
+ *     corresponding index is valid in the fatalErrorCounts array.
+ *
+ *   [out] fatalErrorCounts
+ *     This parameter returns an array of 8-bit counts, one for each type of
+ *     fatal error that can occur on the link. The valid indices of this array
+ *     are:
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_DL_DATA_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_DL_CTRL_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_RAM_DATA_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_RAM_HDR_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_TX_RAM_DATA_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_TX_RAM_HDR_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CTRL_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY
+ *
+ * Possible return status values are:
+ *   NV_OK
+ *     If the values in the fatalErrorCounts array are valid upon return.
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the linkId parameter does not specify a valid link.
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on this GPU or aggregate NVLINK fatal error
+ *     counts are not recorded in non-volatile storage.
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS                           (0x20803009U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVLink 1 Fatal Error Types
+ */
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY                     0U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY                     1U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL                           2U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW                           3U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY                    4U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY                     5U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP                               6U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON                             7U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY                    8U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY                     9U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT                             10U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY                   11U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY                         12U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG                      13U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM                          14U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE                    15U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE               16U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE               17U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL                  18U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT                           19U
+
+/*
+ * NVLink 2 Fatal Error Types
+ */
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY                    0U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY                    1U
+// No direct equivalent to:                 TL_RX_PROTOCOL                            2
+// No direct equivalent to:                 TL_RX_OVERFLOW                            3
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY                   4U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY                    5U
+// No direct equivalent to:                 TL_RX_RESP                                6
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD            7U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY                   8U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY                    9U
+// No direct equivalent to:                 TL_TX_CREDIT                             10
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY            11U
+// No direct equivalent to:                 TL_DL_HDR_PARITY                         12
+// Identical to NVLink 1:                   DL_TX_RECOVERY_LONG                      13
+// Identical to NVLink 1:                   DL_TX_FAULT_RAM                          14
+// Identical to NVLink 1:                   DL_TX_FAULT_INTERFACE                    15
+// Identical to NVLink 1:                   DL_TX_FAULT_SUBLINK_CHANGE               16
+// Identical to NVLink 1:                   DL_RX_FAULT_SUBLINK_CHANGE               17
+// Identical to NVLink 1:                   DL_RX_FAULT_DL_PROTOCOL                  18
+// Identical to NVLink 1:                   DL_LTSSM_FAULT                           19
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY                     20U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD              21U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD              22U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN                23U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN                           24U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC                      25U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC                  26U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE                    27U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS                   28U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS                   29U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ  30U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP 31U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE    32U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE       33U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE      34U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR         35U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP           36U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET                37U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST   38U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW                      39U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW                     40U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD                  41U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL              42U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW           43U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE 44U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE 45U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW               46U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW              47U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW         48U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW           49U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT                  50U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT            51U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET                52U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST   53U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY                   54U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY                    55U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY                   56U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY                    57U
+
+/*
+ * NVLink 3 Fatal Error Types
+ */
+// Identical to NVLink 2:                   TLC_RX_DL_DATA_PARITY                     0
+// Identical to NVLink 2:                   TLC_RX_DL_CTRL_PARITY                     1
+// No direct equivalent to:                 TL_RX_PROTOCOL                            2
+// No direct equivalent to:                 TL_RX_OVERFLOW                            3
+// No direct equivalent to:                 TLC_RX_RAM_DATA_PARITY                    4
+// No direct equivalent to:                 RX_RAM_HDR_PARITY                         5
+// No direct equivalent to:                 TL_RX_RESP                                6
+// No direct equivalent to:                 TLC_RX_DATA_POISONED_PKT_RCVD             7
+// No direct equivalent to:                 TLC_TX_RAM_DATA_PARITY                    8
+// No direct equivalent to:                 TLC_TX_RAM_HDR_PARITY                     9
+// No direct equivalent to:                 TL_TX_CREDIT                             10
+// Identical to NVLink 2:                   TLC_TX_DL_FLOW_CONTROL_PARITY            11
+// No direct equivalent to:                 TL_DL_HDR_PARITY                         12
+// No direct equivalent to:                 DL_TX_RECOVERY_LONG                      13
+// Identical to NVLink 1:                   DL_TX_FAULT_RAM                          14
+// Identical to NVLink 1:                   DL_TX_FAULT_INTERFACE                    15
+// Identical to NVLink 1:                   DL_TX_FAULT_SUBLINK_CHANGE               16
+// Identical to NVLink 1:                   DL_RX_FAULT_SUBLINK_CHANGE               17
+// Identical to NVLink 1:                   DL_RX_FAULT_DL_PROTOCOL                  18
+// No direct equivalent to:                 DL_LTSSM_FAULT                           19
+// Identical to NVLink 2:                   TLC_RX_DL_HDR_PARITY                     20
+// Identical to NVLink 2:                   TLC_RX_INVALID_AE_FLIT_RCVD              21
+// Identical to NVLink 2:                   TLC_RX_INVALID_BE_FLIT_RCVD              22
+// Identical to NVLink 2:                   TLC_RX_INVALID_ADDR_ALIGN                23
+// Identical to NVLink 2:                   TLC_RX_PKT_LEN                           24
+// Identical to NVLink 2:                   TLC_RX_RSVD_CMD_ENC                      25
+// Identical to NVLink 2:                   TLC_RX_RSVD_DAT_LEN_ENC                  26
+// No direct equivalent to:                 TLC_RX_RSVD_ADDR_TYPE                    27
+// No direct equivalent to:                 TLC_RX_RSVD_RSP_STATUS                   28
+// Identical to NVLink 2:                   TLC_RX_RSVD_PKT_STATUS                   29
+// Identical to NVLink 2:                   TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ  30
+// Identical to NVLink 2:                   TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP 31
+// No direct equivalent to:                 TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE    32
+// Identical to NVLink 2:                   TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE       33
+// Identical to NVLink 2:                   TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE      34
+// Identical to NVLink 2:                   TLC_RX_INVALID_PO_FOR_CACHE_ATTR         35
+// Identical to NVLink 2:                   TLC_RX_INVALID_COMPRESSED_RESP           36
+// No direct equivalent to:                 TLC_RX_RESP_STATUS_TARGET                37
+// No direct equivalent to:                 TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST   38
+// Identical to NVLink 2:                   TLC_RX_HDR_OVERFLOW                      39
+// Identical to NVLink 2:                   TLC_RX_DATA_OVERFLOW                     40
+// Identical to NVLink 2:                   TLC_RX_STOMPED_PKT_RCVD                  41
+// No direct equivalent to:                 TLC_RX_CORRECTABLE_INTERNAL              42
+// No direct equivalent to:                 TLC_RX_UNSUPPORTED_VC_OVERFLOW           43
+// No direct equivalent to:                 TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE 44
+// No direct equivalent to:                 TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE 45
+// No direct equivalent to:                 TLC_TX_HDR_CREDIT_OVERFLOW               46
+// No direct equivalent to:                 TLC_TX_DATA_CREDIT_OVERFLOW              47
+// No direct equivalent to:                 TLC_TX_DL_REPLAY_CREDIT_OVERFLOW         48
+// No direct equivalent to:                 TLC_TX_UNSUPPORTED_VC_OVERFLOW           49
+// No direct equivalent to:                 TLC_TX_STOMPED_PKT_SENT                  50
+// No direct equivalent to:                 TLC_TX_DATA_POISONED_PKT_SENT            51
+// No direct equivalent to:                 TLC_TX_RESP_STATUS_TARGET                52
+// No direct equivalent to:                 TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST   53
+// No direct equivalent to:                 MIF_RX_RAM_DATA_PARITY                   54
+// No direct equivalent to:                 MIF_RX_RAM_HDR_PARITY                    55
+// No direct equivalent to:                 MIF_TX_RAM_DATA_PARITY                   56
+// No direct equivalent to:                 MIF_TX_RAM_HDR_PARITY                    57
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE        58U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE                59U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY                     60U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP                        61U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN                      62U
+
+#define NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES                                     63U
+
+#define NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID(count, supportedCounts)    \
+    (!!((supportedCounts) & NVBIT64(count)))
+
+#define NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS {
+    NvU32 linkId;
+    NV_DECLARE_ALIGNED(NvU64 supportedCounts, 8);
+    NvU8  fatalErrorCounts[NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES];
+} NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES
+ *
+ * This command queries recent non-fatal error rates for the given link.
+ *
+ * The error rates specify the maximum number of errors per minute recorded
+ * for the given link within a 24-hour period for daily maximums or a 30-day
+ * period for monthly maximums.
+ *
+ *   [in] linkId
+ *     This parameter specifies the link to get the nonfatal error information
+ *     for.
+ *
+ *   [out] numDailyMaxNonfatalErrorRates
+ *     This parameter returns the number of valid nonfatal error rate entries
+ *     in the dailyMaxNonfatalErrorRates parameter.
+ *
+ *   [out] dailyMaxNonfatalErrorRates
+ *     This parameter returns maximum nonfatal error rate entries recorded
+ *     over the last few 24-hour periods. For example, index 0 contains the
+ *     maximum nonfatal error rate recorded in the current day, index 1
+ *     contains the maximum nonfatal error rate recorded yesterday ago, etc.
+ *
+ *   [out] numMonthlyMaxNonfatalErrorRates
+ *     This parameter returns the number of valid nonfatal error rate entries
+ *     in the monthlyMaxNonfatalErrorRates parameter.
+ *
+ *   [out] monthlyMaxNonfatalErrorRates
+ *     THis parameter returns maximum nonfatal error rate entries recorded
+ *     over the last few 30-day periods. For example, index 0 contains the
+ *     maximum nonfatal error rate recorded in the current month, index 1
+ *     contains the maximum nonfatal error recorded last month, etc.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If any nonfatal error rates are valid upon return.
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the linkId parameter does not specify a valid link.
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on this GPU or NVLINK nonfatal error rates
+ *     are not recorded in non-volatile storage.
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES (0x2080300aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE {
+    NvU32 errorsPerMinute;
+    NvU32 timestamp;
+} NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE;
+
+#define NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES 5U
+
+#define NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS {
+    NvU32                                  linkId;
+    NvU32                                  numDailyMaxNonfatalErrorRates;
+    NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE dailyMaxNonfatalErrorRates[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES];
+    NvU32                                  numMonthlyMaxNonfatalErrorRates;
+    NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE monthlyMaxNonfatalErrorRates[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES];
+} NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE
+ *
+ * This command sets the injection mode so that error handling and error
+ * logging software can be aware that errors cropping up on links are
+ * intentional and not due to HW failures.
+ *
+ *   [in] bEnabled
+ *     This parameter specifies whether injection mode should be enabled or
+ *     disabled.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If injection mode is enabled or disabled according to the parameters.
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on this GPU.
+ */
+#define NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE (0x2080300bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS {
+    NvBool bEnabled;
+} NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SETUP_EOM
+ *
+ * This command passes a packed 32bit params value to NV_PMINION_MISC_0_SCRATCH_SWRW_0
+ * and then issues an EOM DLCMD to minion for the desired link. Only one DLCMD 
+ * at a time can be issued to any given link.
+ *
+ * Params Packing is specified in Minion IAS
+ */
+#define NV2080_CTRL_CMD_NVLINK_SETUP_EOM (0x2080300cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS {
+    NvU8  linkId;
+    NvU32 params;
+} NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE
+ *
+ * This command sets the mask of links associated with the GPU
+ * to a target power state
+ *
+ * [in] linkMask
+ *     Mask of links that will be put to desired power state
+ *     Note: In Turing RM supports only tansitions into/out of L2
+ * [in] powerState
+ *     Target power state to which the links will transition
+ *     This can be any one of NV2080_CTRL_NVLINK_POWER_STATE_* states
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If all links transitioned successfully to the target state
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip or if the power state
+ *     is not enabled on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the any of the links in the mask is not enabled
+ *   NV_ERR_INVALID_REQUEST
+ *     If the power state transition is not supported
+ *   NV_WARN_MORE_PROCESSING_REQUIRED
+ *      Link has received the request for the power transition
+ *      The transition will happen when the remote end also agrees
+ *
+ *  Note: Currently only L0->L2 and L2->L0 is supported
+ */
+#define NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE (0x2080300dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS {
+    NvU32 linkMask;
+    NvU32 powerState;
+} NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS;
+
+// NVLink Power States
+#define NV2080_CTRL_NVLINK_POWER_STATE_L0      (0x00U)
+#define NV2080_CTRL_NVLINK_POWER_STATE_L1      (0x01U)
+#define NV2080_CTRL_NVLINK_POWER_STATE_L2      (0x02U)
+#define NV2080_CTRL_NVLINK_POWER_STATE_L3      (0x03U)
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE
+ *
+ * This command gets the power state of a link associated
+ * with the GPU
+ *
+ * [in] linkId
+ *     Link whose power state is being requested
+ * [out] powerState
+ *     Current power state of the link
+ *     Is any one the NV2080_CTRL_NVLINK_POWER_STATE_* states
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the power state is retrieved successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the link is not enabled on the GPU
+ *   NV_ERR_INVALID_STATE
+ *     If the link is in an invalid state
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE (0x2080300eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS {
+    NvU32 linkId;
+    NvU32 powerState;
+} NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR
+ *
+ * This command injects TLC_*_REPORT_INJECT error. An RM interrupt
+ * will be triggered after injection. Currently the injection call
+ * only deals with HW_ERR, UR_ERR, PRIV_ERR in TX_SYS and RX_LNK devices
+ *
+ * [in] linkId
+ *     Link whose power state is being requested.
+ * [in] errorType
+ *     error type that needs to be injected.
+ * [in] device
+ *     The device this injection is intended for.
+ * [in] bBroadcast
+ *     Whether the link report error should be fired in multiple links.
+
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the injection succeeds.
+ *   NV_ERR_NOT_SUPPORTED
+ *     If the error type of NVLINK is not supported on the chip
+ */
+#define NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR (0x2080300fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE {
+    TLC_RX_LNK = 0,
+    TLC_TX_SYS = 1,
+} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE;
+
+typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE {
+    TX_SYS_TX_RSP_STATUS_HW_ERR = 0,
+    TX_SYS_TX_RSP_STATUS_UR_ERR = 1,
+    TX_SYS_TX_RSP_STATUS_PRIV_ERR = 2,
+} NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE;
+
+typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE {
+    RX_LNK_RX_RSP_STATUS_HW_ERR = 0,
+    RX_LNK_RX_RSP_STATUS_UR_ERR = 1,
+    RX_LNK_RX_RSP_STATUS_PRIV_ERR = 2,
+} NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE;
+
+typedef union NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE {
+    NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE txSysErrorType;
+    NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE rxLnkErrorType;
+} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE;
+
+
+#define NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS {
+    NvU32                                      linkId;
+    NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE device;
+    NvBool                                     bBroadcast;
+    NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE   errorType;
+} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES
+ *
+ * This command returns the per-lane Figure Of Merit (FOM) Values from a link
+ *
+ * [in]  linkId
+ *     The NVLink link ID to report FOM values for
+ * [out] numLanes
+ *     This field specifies the no. of lanes per link
+ * [out] figureOfMeritValues
+ *     This field contains the FOM values per lane
+ *
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES (0x20803011U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_MAX_LANES               4U
+
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS {
+    NvU32 linkId;
+    NvU8  numLanes;
+    NvU16 figureOfMeritValues[NV2080_CTRL_NVLINK_MAX_LANES];
+} NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS;
+
+/*
+ * NV2080_CTRL_NVLINK_SET_NVLINK_PEER
+ *
+ * This command sets/unsets the USE_NVLINK_PEER bit for a given
+ *     mask of peers
+ *
+ * [in] peerMask
+ *     Mask of Peer IDs for which USE_NVLINK_PEER needs to be updated
+ * [in] bEnable
+ *     Whether the bit needs to be set or unset
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the USE_NVLINK_PEER bit was updated successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip, or
+ *     If unsetting USE_NVLINK_PEER bit is not supported
+ *
+ * NOTE: This is only supported on Windows
+ *
+ */
+#define NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER (0x20803012U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS {
+    NvU32  peerMask;
+    NvBool bEnable;
+} NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG
+ *
+ * This command packs the lane and addr values into NV_PMINION_MISC_0_SCRATCH_SWRW_0
+ * and then issues a READPADLANEREG DLCMD to minion for the desired link. Only one DLCMD 
+ * at a time can be issued to any given link.
+ * 
+ * After this command completes it is necessary to read the appropriate
+ * NV_PNVL_BR0_PAD_CTL_7_CFG_RDATA register to retrieve the results of the read
+ * Only GV100 should read NV_PNVL_BR0_PAD_CTL_7_CFG_RDATA.
+ * From TU102+ the ctrl the required data would be updated in phyConfigData.
+ *
+ * [in] linkId
+ *     Link whose pad lane register is being read
+ * [in] lane
+ *     Lane whose pad lane register is being read
+ * [in] addr
+ *     Address of the pad lane register to read
+ * [out] phyConfigData
+ *     Provides phyconfigaddr and landid
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the minion command completed successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the link is not enabled on the GPU or the lane is invalid
+ *   NV_ERR_TIMEOUT
+ *     If a timeout occurred waiting for minion response
+ */
+#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG (0x20803013U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS {
+    NvU8  linkId;
+    NvU8  lane;
+    NvU16 addr;
+    NvU32 phyConfigData;
+} NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS;
+
+/*
+ * Structure to store the ECC error data.
+ * valid
+ *     Is the lane valid or not
+ * eccErrorValue
+ *     Value of the Error.
+ * overflowed
+ *     If the error overflowed or not
+ */
+typedef struct NV2080_CTRL_NVLINK_LANE_ERROR {
+    NvBool bValid;
+    NvU32  eccErrorValue;
+    NvBool overflowed;
+} NV2080_CTRL_NVLINK_LANE_ERROR;
+
+/*
+ * Structure to store ECC error data for Links
+ * errorLane array index corresponds to the lane number.
+ *
+ * errorLane[]
+ *    Stores the ECC error data per lane.
+ */
+typedef struct NV2080_CTRL_NVLINK_LINK_ECC_ERROR {
+    NV2080_CTRL_NVLINK_LANE_ERROR errorLane[NV2080_CTRL_NVLINK_MAX_LANES];
+    NvU32                         eccDecFailed;
+    NvBool                        eccDecFailedOverflowed;
+} NV2080_CTRL_NVLINK_LINK_ECC_ERROR;
+
+/*
+ * NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS
+ *
+ * Control to get the values of ECC ERRORS
+ *
+ * Parameters:
+ *    linkMask [IN]
+ *      Links on which the ECC error data requested
+ *      A valid link/port mask returned by the port masks returned by
+ *      NVSWITCH_GET_INFO
+ *    errorLink[] [OUT]
+ *      Stores the ECC error related information for each link.
+ *      errorLink array index corresponds to the link Number.   
+ */
+
+#define NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS {
+    NvU32                             linkMask;
+    NV2080_CTRL_NVLINK_LINK_ECC_ERROR errorLink[NV2080_CTRL_NVLINK_MAX_LINKS];
+} NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS;
+
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS     (0x20803014U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID" */
+
+// Nvlink throughput counters reading data flits in TX
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX 0U
+
+// Nvlink throughput counters reading data flits in RX
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX 1U
+
+// Nvlink throughput counters reading all flits in TX
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX  2U
+
+// Nvlink throughput counters reading all flits in RX
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX  3U
+
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX     4U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS
+ *
+ * Reads reserved monotonically increasing NVLINK throughput counters for given linkIds
+ *
+ * [in] counterMask
+ *     Mask of counter types to be queried
+ *     One of NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_* macros
+ * [in] linkMask
+ *     Mask of links to be queried
+ * [out] value
+ *     Throughput counter value returned
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If command completed successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If numLinks is out-of-range or requested link is inactive
+ *
+ * Note:
+ * The following commands will be deprecated in favor of NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS:
+ *     NV90CC_CTRL_CMD_NVLINK_GET_COUNTERS
+ *     NV2080_CTRL_CMD_NVLINK_GET_COUNTERS
+ * Other commands that will be deprecated due to the change in design:
+ *     NV90CC_CTRL_CMD_NVLINK_RESERVE_COUNTERS
+ *     NV90CC_CTRL_CMD_NVLINK_RELEASE_COUNTERS
+ *     NV90CC_CTRL_CMD_NVLINK_SET_COUNTERS_FROZEN
+ *     NV90CC_CTRL_CMD_NVLINK_GET_TL_COUNTER_CFG
+ *     NV90CC_CTRL_CMD_NVLINK_SET_TL_COUNTER_CFG
+ *     NV90CC_CTRL_CMD_NVLINK_CLEAR_COUNTERS
+ *
+ * Also, note that there is no counter overflow handling for these calls.
+ * These counters would be counting in flits and assuming 25GB/s bandwidth per link,
+ * with traffic flowing continuously, it would take 174 years for overflow to happen.
+ * It is reasonable to assume an overflow will not occur within the GPU operation,
+ * given that the counters get reset at system reboot or GPU reset. Counters are 63-bit.
+ */
+
+typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES {
+    NV_DECLARE_ALIGNED(NvU64 value[NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX], 8);
+} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES;
+
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS {
+    NvU16 counterMask;
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
+} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS      (0x20803015U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE
+ *
+ * This command locks the link power state so that RM doesn't modify the state
+ * of the link during pstate switch.
+ *
+ *   [in] linkMask        Links for which power mode needs to be locked.
+ */
+#define NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE (0x20803016U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS {
+    NvBool bLockPowerMode;
+} NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER
+ *
+ * This command is used to enable RM NVLink enabled peer state.
+ * Note: This just updates the RM state. To reflect the state in the registers,
+ *       use NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER
+ *
+ * [in] peerMask
+ *     Mask of Peer IDs for which USE_NVLINK_PEER needs to be enabled
+ * [in] bEnable
+ *     Whether the bit needs to be set or unset
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the USE_NVLINK_PEER bit was enabled successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip, or
+ *     If unsetting USE_NVLINK_PEER bit is not supported
+ *
+ */
+#define NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER (0x20803017U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID (0x17U)
+
+typedef struct NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS {
+    NvU32  peerMask;
+    NvBool bEnable;
+} NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS;
+
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS   0U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER  2U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT  4U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP  5U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS    6U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS
+ *
+ * Reads NVLINK low power counters for given linkId
+ *
+ * [in] linkId
+ *     ID of the link to be queried
+ * [in,out] counterValidMask
+ *     Mask of valid counters
+ * [out] counterValues
+ *     Low power counter values returned
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If command completed successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If linkId is out-of-range or requested link is inactive
+ */
+
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
+    NvU32 linkId;
+    NvU32 counterValidMask;
+    NvU32 counterValues[NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS];
+} NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS                  (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVLINK Link states
+ * These should ALWAYS match the nvlink core library defines in nvlink.h
+ */
+#define NV2080_NVLINK_CORE_LINK_STATE_OFF                       0x00U
+#define NV2080_NVLINK_CORE_LINK_STATE_HS                        0x01U
+#define NV2080_NVLINK_CORE_LINK_STATE_SAFE                      0x02U
+#define NV2080_NVLINK_CORE_LINK_STATE_FAULT                     0x03U
+#define NV2080_NVLINK_CORE_LINK_STATE_RECOVERY                  0x04U
+#define NV2080_NVLINK_CORE_LINK_STATE_FAIL                      0x05U
+#define NV2080_NVLINK_CORE_LINK_STATE_DETECT                    0x06U
+#define NV2080_NVLINK_CORE_LINK_STATE_RESET                     0x07U
+#define NV2080_NVLINK_CORE_LINK_STATE_ENABLE_PM                 0x08U
+#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_PM                0x09U
+#define NV2080_NVLINK_CORE_LINK_STATE_SLEEP                     0x0AU
+#define NV2080_NVLINK_CORE_LINK_STATE_SAVE_STATE                0x0BU
+#define NV2080_NVLINK_CORE_LINK_STATE_RESTORE_STATE             0x0CU
+#define NV2080_NVLINK_CORE_LINK_STATE_PRE_HS                    0x0EU
+#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT        0x0FU
+#define NV2080_NVLINK_CORE_LINK_STATE_LANE_DISABLE              0x10U
+#define NV2080_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN             0x11U
+#define NV2080_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP             0x12U
+#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE1                0x13U
+#define NV2080_NVLINK_CORE_LINK_STATE_INITNEGOTIATE             0x14U
+#define NV2080_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE        0x15U
+#define NV2080_NVLINK_CORE_LINK_STATE_INITOPTIMIZE              0x16U
+#define NV2080_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE         0x17U
+#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT         0x18U
+#define NV2080_NVLINK_CORE_LINK_STATE_CONTAIN                   0x19U
+#define NV2080_NVLINK_CORE_LINK_STATE_INITTL                    0x1AU
+#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE5                0x1BU
+#define NV2080_NVLINK_CORE_LINK_STATE_ALI                       0x1CU
+#define NV2080_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING            0x1DU
+#define NV2080_NVLINK_CORE_LINK_STATE_INVALID                   0xFFU
+
+/*
+ * NVLINK TX Sublink states
+ * These should ALWAYS match the nvlink core library defines in nvlink.h
+ */
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS                  0x00U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE         0x04U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER           0x04U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN               0x05U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE                0x06U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF                 0x07U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE         0x08U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE 0x09U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY          0x0AU
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ                  0x0BU
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN             0x0CU
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS             0x0DU
+
+/*
+ * NVLINK RX Sublink states
+ * These should ALWAYS match the nvlink core library defines in nvlink.h
+ */
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS                  0x00U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE         0x04U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER           0x04U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN               0x05U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE                0x06U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF                 0x07U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL               0x08U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM           0x09U
+
+/*
+ * Link training seed values
+ * These should ALWAYS match the values defined in nvlink.h
+ */
+#define NV2080_CTRL_NVLINK_MAX_SEED_NUM                         6U
+#define NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE                 (0x7U) /* finn: Evaluated from "NV2080_CTRL_NVLINK_MAX_SEED_NUM + 1" */
+
+// NVLINK callback types
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE       0x00U
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE       0x01U
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE       0x02U
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE       0x03U
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE    0x04U
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE    0x05U
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE    0x06U
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE    0x07U
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT  0x08U
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT  0x09U
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN  0x0AU
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN   0x0BU
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE      0x0CU
+#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD          0x0DU
+
+/*
+ * Structure to store the GET_DL_MODE callback params.
+ * mode
+ *     The current Nvlink DL mode
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS {
+    NvU32 mode;
+} NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS;
+
+/*
+ * Structure to store the SET_DL_LINK_MODE callback OFF params
+ * seedData
+ *     The output seed data
+ */
+typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS {
+    NvU32 seedData[NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE];
+} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS;
+
+/*
+ * Structure to store the SET_DL_LINK_MODE callback PRE_HS params
+ * remoteDeviceType
+ *     The input remote Device Type
+ * ipVerDlPl
+ *     The input DLPL version
+ */
+typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS {
+    NvU32 remoteDeviceType;
+    NvU32 ipVerDlPl;
+} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS;
+
+/*
+ * Structure to store SET_DL_LINK_MODE callback INIT_PHASE1 params
+ * seedData[]
+ *     The input seed data
+ */
+typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS {
+    NvU32 seedData[NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE];
+} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS;
+
+/*
+ * Structure to store the Nvlink Remote and Local SID info
+ * remoteSid
+ *     The output remote SID
+ * remoteDeviceType
+ *     The output remote Device Type
+ * remoteLinkId
+ *     The output remote link ID
+ * localSid
+ *     The output local SID
+ */
+typedef struct NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO {
+    NV_DECLARE_ALIGNED(NvU64 remoteSid, 8);
+    NvU32 remoteDeviceType;
+    NvU32 remoteLinkId;
+    NV_DECLARE_ALIGNED(NvU64 localSid, 8);
+} NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO;
+
+/*
+ * Structure to store the SET_DL_LINK_MODE callback POST_INITNEGOTIATE params
+ * bInitnegotiateConfigGood
+ *     The output bool if the config is good
+ * remoteLocalSidInfo
+ *     The output structure containing the Nvlink Remote/Local SID info
+ */
+typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS {
+    NvBool bInitnegotiateConfigGood;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
+} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS;
+
+/*
+ * Structure to store the SET_DL_LINK_MODE callback POST_INITOPTIMIZE params
+ * bPollDone
+ *     The output bool if the polling has finished
+ */
+typedef struct NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS {
+    NvBool bPollDone;
+} NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS;
+
+/*
+ * Structure to store the SET_DL_LINK_MODE callback params
+ * mode
+ *     The input nvlink state to set
+ * bSync
+ *     The input sync boolean
+ * linkMode
+ *     The input link mode to be set for the callback
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 mode, 8);
+    NvBool bSync;
+    NvU32  linkMode;
+    union {
+        NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS              linkModeOffParams;
+        NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS           linkModePreHsParams;
+        NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS      linkModeInitPhase1Params;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS linkModePostInitNegotiateParams, 8);
+        NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS linkModePostInitOptimizeParams;
+    } linkModeParams;
+} NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS;
+
+/*
+ * Structure to store the GET_TL_MODE callback params.
+ * mode
+ *     The current Nvlink TL mode
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS {
+    NvU32 mode;
+} NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS;
+
+/*
+ * Structure to store the SET_TL_LINK_MODE callback params
+ * mode
+ *     The input nvlink mode to set
+ * bSync
+ *     The input sync boolean
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 mode, 8);
+    NvBool bSync;
+} NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS;
+
+/*
+ * Structure to store the GET_RX/TX_SUBLINK_MODE callback params
+ * sublinkMode
+ *     The current Sublink mode
+ * sublinkSubMode
+ *     The current Sublink sub mode
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS {
+    NvU32 sublinkMode;
+    NvU32 sublinkSubMode;
+} NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS;
+
+/*
+ * Structure to store the SET_TL_LINK_MODE callback params
+ * mode
+ *     The input nvlink mode to set
+ * bSync
+ *     The input sync boolean
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 mode, 8);
+    NvBool bSync;
+} NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS;
+
+/*
+ * Structure to store the SET_RX_SUBLINK_MODE callback params
+ * mode
+ *     The input nvlink mode to set
+ * bSync
+ *     The input sync boolean
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 mode, 8);
+    NvBool bSync;
+} NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS;
+
+/*
+ * Structure to store the GET_RX_SUBLINK_DETECT callback params
+ * laneRxdetStatusMask
+ *     The output RXDET per-lane status mask 
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS {
+    NvU32 laneRxdetStatusMask;
+} NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS;
+
+/*
+ * Structure to store the SET_RX_DETECT callback params
+ * bSync
+ *     The input bSync boolean
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS {
+    NvBool bSync;
+} NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS;
+
+/*
+ * Structure to store the RD_WR_DISCOVERY_TOKEN callback params
+ * ipVerDlPl
+ *     The input DLPL version
+ * token
+ *     The output token
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS {
+    NvU32 ipVerDlPl;
+    NV_DECLARE_ALIGNED(NvU64 token, 8);
+} NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS;
+
+/*
+ * Structure to store the GET_UPHY_LOAD callback params
+ * bUnlocked
+ *     The output unlocked boolean
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS {
+    NvBool bUnlocked;
+} NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS;
+
+/*
+ * Structure to store the Union of Callback params
+ * type
+ *     The input type of callback to be executed
+ */
+typedef struct NV2080_CTRL_NVLINK_CALLBACK_TYPE {
+    NvU8 type;
+    union {
+        NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS getDlLinkMode;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS setDlLinkMode, 8);
+        NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS getTlLinkMode;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS setTlLinkMode, 8);
+        NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getTxSublinkMode;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS setTxSublinkMode, 8);
+        NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getRxSublinkMode;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS setRxSublinkMode, 8);
+        NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS    getRxSublinkDetect;
+        NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS    setRxSublinkDetect;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS writeDiscoveryToken, 8);
+        NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS readDiscoveryToken, 8);
+        NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS    getUphyLoad;
+    } callbackParams;
+} NV2080_CTRL_NVLINK_CALLBACK_TYPE;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK
+ *
+ * Generic NvLink callback RPC to route commands to GSP
+ *
+ * [In] linkdId
+ *     ID of the link to be used
+ * [In/Out] callBackType
+ *     Callback params
+ */
+#define NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS {
+    NvU32 linkId;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_TYPE callbackType, 8);
+} NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK (0x20803019U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED
+ *
+ * Returns if ALI is enabled
+ *
+ * [Out] bEnableAli
+ *     Output boolean for ALI enablement
+ */
+#define NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x1aU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS {
+    NvBool bEnableAli;
+} NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED (0x2080301aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID
+ *
+ * Update Remote and Local Sid info via GSP
+ *
+ * [In] linkId
+ *     ID of the link to be used
+ * [Out] remoteLocalSidInfo
+ *     The output structure containing the Nvlink Remote/Local SID info
+ */
+#define NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID (0x1bU)
+
+typedef struct NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS {
+    NvU32 linkId;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
+} NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID   (0x2080301bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM 0x0U
+#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET   0x1U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_UPDATE_HSHUB_MUX
+ *
+ * Generic Hshub Mux Update RPC to route commands to GSP
+ *
+ * [In] updateType
+ *     HSHUB Mux update type to program or reset Mux
+ * [In] bSysMem
+ *     Boolean to differentiate between sysmen and peer mem
+ * [In] peerMask
+ *     Mask of peer IDs. Only parsed when bSysMem is false
+ */
+#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID (0x1cU)
+
+typedef struct NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
+    NvBool updateType;
+    NvBool bSysMem;
+    NvU32  peerMask;
+} NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_UPDATE_HSHUB_MUX (0x2080301cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER
+ *
+ * Performs all the necessary actions required before setting a peer on NVLink
+ *
+ * [In] peerId
+ *     Peer ID which will be set on NVLink
+ * [In] peerLinkMask
+ *     Mask of links that connects the given peer
+ * [In] bNvswitchConn
+ *     Is the GPU connected to NVSwitch
+ */
+#define NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x1dU)
+
+typedef struct NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
+    NvU32  peerId;
+    NvU32  peerLinkMask;
+    NvBool bNvswitchConn;
+} NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER (0x2080301dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER
+ *
+ * Performs all the necessary actions required after setting a peer on NVLink
+ *
+ * [In] peerMask
+ *     Mask of Peer IDs which has been set on NVLink
+ */
+#define NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x1eU)
+
+typedef struct NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS {
+    NvU32 peerMask;
+} NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER        (0x2080301eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U
+#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER   0x2U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_REMOVE_NVLINK_MAPPING
+ *
+ * Performs all the necessary actions required to remove NVLink mapping (sysmem or peer or both)
+ *
+ * [In] mapTypeMask
+ *     Remove NVLink mapping for the given map types (sysmem or peer or both)
+ * [In] peerMask
+ *     Mask of Peer IDs which needs to be removed on NVLink
+ *     Only parsed if mapTypeMask accounts peer
+ * [In] bL2Entry
+ *     Is the peer removal happening because links are entering L2 low power state?
+ *     Only parsed if mapTypeMask accounts peer
+ */
+#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID (0x1fU)
+
+typedef struct NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS {
+    NvU32  mapTypeMask;
+    NvU32  peerMask;
+    NvBool bL2Entry;
+} NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_REMOVE_NVLINK_MAPPING (0x2080301fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SAVE_RESTORE_HSHUB_STATE
+ *
+ * Performs all the necessary actions required to save/restore HSHUB state during NVLink L2 entry/exit
+ *
+ * [In] bSave
+ *     Whether this is a save/restore operation
+ * [In] linkMask
+ *     Mask of links for which HSHUB config registers need to be saved/restored
+ */
+#define NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS {
+    NvBool bSave;
+    NvU32  linkMask;
+} NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_SAVE_RESTORE_HSHUB_STATE (0x20803020U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET        (0x00000000)
+#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE       (0x00000001)
+#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE    (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_PROGRAM_BUFFERREADY
+ *
+ * Performs all the necessary actions required to save/restore bufferready state during NVLink L2 entry/exit
+ *
+ * [In] flags
+ *     Whether to set, save or restore bufferready
+ * [In] bSysmem
+ *     Whether to perform the operation for sysmem links or peer links
+ * [In] peerLinkMask
+ *     Mask of peer links for which bufferready state need to be set/saved/restored
+ */
+#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS {
+    NvU32  flags;
+    NvBool bSysmem;
+    NvU32  peerLinkMask;
+} NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_PROGRAM_BUFFERREADY (0x20803021U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_UPDATE_CURRENT_CONFIG
+ *
+ * Performs all the necessary actions required to update the current Nvlink configuration 
+ *
+ * [out] bNvlinkSysmemEnabled
+ *     Whether sysmem nvlink support was enabled
+ */
+#define NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS {
+    NvBool bNvlinkSysmemEnabled;
+} NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_UPDATE_CURRENT_CONFIG (0x20803022U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID" */
+
+//
+// Set the near end loopback mode using the following
+// Currently, three modes - NEA, NEDR, NEW
+//
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT              (0x00000000)
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA                  (0x00000001)
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR                 (0x00000002)
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW                 (0x00000003)
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE
+ *
+ * Generic NvLink callback for MODS
+ *
+ * [In] linkdId
+ *     ID of the link to be used
+ * [In] loopbackMode
+ *     This value will decide which loopback mode need to
+ *     set on the specified link.
+ *     Modes are NEA / NEDR / NEDW
+ */
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS {
+    NvU32 linkId;
+    NvU8  loopbackMode;
+} NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE (0x20803023U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_UPDATE_PEER_LINK_MASK
+ *
+ * Synchronizes the peerLinkMask between CPU-RM and GSP-RM
+ *
+ * [In] gpuInst
+ *     Gpu instance
+ * [In] peerLinkMask
+ *     Mask of links to the given peer GPU
+ */
+#define NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS {
+    NvU32 gpuInst;
+    NvU32 peerLinkMask;
+} NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_UPDATE_PEER_LINK_MASK (0x20803024U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION
+ *
+ * Updates the remote connection information for a link
+ *
+ * [In] linkId
+ *     Id of the link to be used
+ * [In] bConnected
+ *     Boolean that tracks whether the link is connected
+ * [In] remoteDeviceType
+ *     Tracks whether the remote device is switch/gpu/ibmnpu/tegra
+ * [In] remoteLinkNumber
+ *     Tracks the link number for the connected remote device
+ */
+#define NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8);
+    NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8);
+    NvU32  linkId;
+    NvU32  laneRxdetStatusMask;
+    NvU32  remoteLinkNumber;
+    NvU32  remotePciDeviceId;
+    NvU32  remoteDomain;
+    NvU8   remoteBus;
+    NvU8   remoteDevice;
+    NvU8   remoteFunction;
+    NvBool bConnected;
+} NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION (0x20803025U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY
+ *
+ * Enable links post topology via GSP
+ *
+ * [In]  linkMask
+ *     Mask of links to enable
+ * [Out] initializedLinks
+ *     Mask of links that were initialized
+ */
+#define NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID (0x26U)
+
+typedef struct NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS {
+    NvU32 linkMask;
+    NvU32 initializedLinks;
+} NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20803026U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI
+ *
+ * [In] linkMask
+ *     Mask of enabled links to train
+ * [In] bSync
+ *     The input sync boolean
+ */
+#define NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x27U)
+
+typedef struct NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS {
+    NvU32  linkMask;
+    NvBool bSync;
+} NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI (0x20803027U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
+
+//
+// Read Refresh counter - the pass/fail occurrences
+//
+
+typedef struct NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO {
+    // requested links or not
+    NvBool bValid;
+
+    // counters
+    NvU16  passCount;
+    NvU16  failCount;
+} NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO;
+
+#define NV2080_CTRL_NVLINK_MAX_LINK_COUNT 32
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS
+ *
+ *
+ * [In] linkMask
+ *     Specifies for which links we want to read the counters
+ * [Out] refreshCountPass
+ *     Count of number of times PHY refresh pass
+ * [Out] refreshCountFail
+ *     Count of number of times PHY refresh fail
+ */
+#define NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x28U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS {
+    NvU32                                      linkMask;
+    NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO refreshCount[NV2080_CTRL_NVLINK_MAX_LINK_COUNT];
+} NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS (0x20803028U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */
+
+//
+// Clear Refresh counter - the pass/fail occurrences
+//
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS
+ *
+ *
+ * [In] linkMask
+ *     Specifies for which links we want to clear the counters
+ */
+#define NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x29U)
+
+typedef struct NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS {
+    NvU32 linkMask;
+} NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS (0x20803029U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET
+ *
+ * Get link mask post Rx detection
+ *
+ * [Out] postRxDetLinkMask
+ *     Mask of links discovered
+ */
+#define NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID (0x2aU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS {
+    NvU32 postRxDetLinkMask;
+} NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET (0x2080302aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI
+ *
+ * [In] linkMask
+ *     Mask of enabled links to train
+ * [In] bSync
+ *     The input sync boolean
+ */
+#define NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x2bU)
+
+typedef struct NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS {
+    NvU32  linkMask;
+    NvBool bSync;
+} NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI (0x2080302bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES {
+    NvBool bValid;
+    NvU8   linkId;
+    NvU32  ioctrlId;
+    NvU8   pllMasterLinkId;
+    NvU8   pllSlaveLinkId;
+    NvU32  ipVerDlPl;
+} NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_DEVICE_INFO
+ *
+ * [Out] ioctrlMask
+ *    Mask of IOCTRLs discovered from PTOP device info table
+ * [Out] ioctrlNumEntries
+ *    Number of IOCTRL entries in the PTOP device info table
+ * [Out] ioctrlSize
+ *    Maximum number of entries in the PTOP device info table
+ * [Out] discoveredLinks
+ *    Mask of links discovered from all the IOCTRLs
+ * [Out] ipVerNvlink
+ *    IP revision of the NVLink HW
+ * [Out] linkInfo
+ *    Per link information
+ */
+
+#define NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID (0x2cU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS {
+    NvU32                                 ioctrlMask;
+    NvU8                                  ioctrlNumEntries;
+    NvU32                                 ioctrlSize;
+    NvU32                                 discoveredLinks;
+    NvU32                                 ipVerNvlink;
+    NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
+} NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_DEVICE_INFO (0x2080302cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_MAX_LINKS_PER_IOCTRL_SW    6U
+
+typedef struct NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES {
+    NvU32 ipVerIoctrl;
+    NvU32 ipVerMinion;
+} NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_IOCTRL_DEVICE_INFO
+ *
+ * [In] ioctrlIdx
+ *    IOCTRL index
+ * [Out] PublicId
+ *    PublicId of the IOCTRL discovered
+ * [Out] localDiscoveredLinks
+ *    Mask of discovered links local to the IOCTRL
+ * [Out] localGlobalLinkOffset
+ *    Global link offsets for the locally discovered links
+ * [Out] ioctrlDiscoverySize
+ *    IOCTRL table size
+ * [Out] numDevices
+ *    Number of devices discovered from the IOCTRL
+ * [Out] deviceIpRevisions
+ *    IP revisions for the devices discovered in the IOCTRL
+ */
+
+#define NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x2dU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS {
+    NvU32                                        ioctrlIdx;
+    NvU32                                        PublicId;
+    NvU32                                        localDiscoveredLinks;
+    NvU32                                        localGlobalLinkOffset;
+    NvU32                                        ioctrlDiscoverySize;
+    NvU8                                         numDevices;
+    NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES ipRevisions;
+} NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_IOCTRL_DEVICE_INFO (0x2080302dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_PROGRAM_LINK_SPEED
+ *
+ * Program NVLink Speed from OS/VBIOS
+ *
+ * [In] bPlatformLinerateDefined
+ *    Whether line rate is defined in the platform
+ * [In] platformLineRate
+ *    Platform defined line rate
+ * [Out] nvlinkLinkSpeed
+ *    The line rate that was programmed for the links
+ */
+#define NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID (0x2eU)
+
+typedef struct NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS {
+    NvBool bPlatformLinerateDefined;
+    NvU32  platformLineRate;
+    NvU32  nvlinkLinkSpeed;
+} NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_PROGRAM_LINK_SPEED (0x2080302eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED
+ *
+ * [In] linkMask
+ *     Mask of links whose state will be checked
+ * [In] bActiveOnly
+ *     The input boolean to check for Link Active state
+ * [Out] bIsLinkActive
+ *     Boolean array to track if the link is trained
+ */
+#define NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID (0x2fU)
+
+typedef struct NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS {
+    NvU32  linkMask;
+    NvBool bActiveOnly;
+    NvBool bIsLinkActive[NV2080_CTRL_NVLINK_MAX_LINKS];
+} NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED (0x2080302fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_RESET_FLAGS_ASSERT      (0x00000000)
+#define NV2080_CTRL_NVLINK_RESET_FLAGS_DEASSERT    (0x00000001)
+#define NV2080_CTRL_NVLINK_RESET_FLAGS_TOGGLE      (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_RESET_LINKS
+ *
+ * [In] linkMask
+ *     Mask of links which need to be reset
+ * [In] flags
+ *     Whether to assert, de-assert or toggle the Nvlink reset
+ */
+
+#define NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID (0x30U)
+
+typedef struct NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS {
+    NvU32 linkMask;
+    NvU32 flags;
+} NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_RESET_LINKS (0x20803030U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_DISABLE_DL_INTERRUPTS
+ *
+ * [In] linkMask
+ *     Mask of links for which DL interrrupts need to be disabled
+ */
+#define NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID (0x31U)
+
+typedef struct NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS {
+    NvU32 linkMask;
+} NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_DISABLE_DL_INTERRUPTS (0x20803031U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID" */
+
+/*
+ * Structure to store the GET_LINK_AND_CLOCK__INFO params
+ *
+ * [Out] bLinkConnectedToSystem
+ *     Boolean indicating sysmem connection of a link
+ * [Out] bLinkConnectedToPeer
+ *     Boolean indicating peer connection of a link
+ * [Out] bLinkReset
+ *     Whether the link is in reset
+ * [Out] subLinkWidth
+ *     Number of lanes per sublink
+ * [Out] linkState
+ *     Mode of the link
+ * [Out] txSublinkState
+ *     Tx sublink state
+ * [Out] rxSublinkState
+ *     Rx sublink state
+ * [Out] bLaneReversal
+ *     Boolean indicating if a link's lanes are reversed
+ * [Out] nvlinkLinkClockKHz
+ *     Link clock value in KHz
+ * [Out] nvlinkLineRateMbps
+ *     Link line rate in Mbps
+ * [Out] nvlinkLinkClockMhz
+ *     Link clock in MHz
+ * [Out] nvlinkLinkDataRateKiBps
+ *     Link Data rate in KiBps
+ * [Out] nvlinkRefClkType
+ *     Current Nvlink refclk source
+ * [Out] nvlinkReqLinkClockMhz
+ *     Requested link clock value
+ */
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
+    NvBool bLinkConnectedToSystem;
+    NvBool bLinkConnectedToPeer;
+    NvBool bLinkReset;
+    NvU8   subLinkWidth;
+    NvU32  linkState;
+    NvU32  txSublinkState;
+    NvU32  rxSublinkState;
+    NvBool bLaneReversal;
+    NvU32  nvlinkLinkClockKHz;
+    NvU32  nvlinkLineRateMbps;
+    NvU32  nvlinkLinkClockMhz;
+    NvU32  nvlinkLinkDataRateKiBps;
+    NvU8   nvlinkRefClkType;
+    NvU32  nvlinkReqLinkClockMhz;
+} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO
+ *
+ * [In] linkMask
+ *     Mask of enabled links to loop over
+ * [Out] nvlinkRefClkSpeedKHz
+ *     Ref clock value n KHz
+ * [Out] linkInfo
+ *     Per link information
+ */
+#define NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID (0x32U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS {
+    NvU32                                        linkMask;
+    NvU32                                        nvlinkRefClkSpeedKHz;
+    NvBool                                       bSublinkStateInst; // whether instantaneous sublink state is needed 
+    NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
+} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO (0x20803032U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SETUP_NVLINK_SYSMEM
+ *
+ * Updates the HSHUB sysmem config resgister state to reflect sysmem NVLinks
+ *
+ * [In] sysmemLinkMask
+ *     Mask of discovered sysmem NVLinks
+ */
+#define NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID (0x33U)
+
+typedef struct NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS {
+    NvU32 sysmemLinkMask;
+} NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_SETUP_NVLINK_SYSMEM (0x20803033U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_PROCESS_FORCED_CONFIGS
+ *
+ * Process NVLink forced configurations which includes setting of HSHUB and memory system
+ *
+ * [In] bLegacyForcedConfig
+ *     Tracks whether the forced config is legacy forced config or chiplib config
+ * [Out] bOverrideComputePeerMode
+ *     Whether compute peer mode was enabled
+ * [In] phase
+ *     Only applicable when bLegacyForcedConfig is true
+ *     Tracks the set of registers to program from the NVLink table
+ * [In] linkConnection
+ *     Array of chiplib configurations
+ */
+#define NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID (0x34U)
+
+typedef struct NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS {
+    NvBool bLegacyForcedConfig;
+    NvBool bOverrideComputePeerMode;
+    NvU32  phase;
+    NvU32  linkConnection[NV2080_CTRL_NVLINK_MAX_LINKS];
+} NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_PROCESS_FORCED_CONFIGS (0x20803034U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS
+ *
+ * Sync the NVLink lane shutdown properties with GSP-RM
+ *
+ * [In] bLaneShutdownEnabled
+ *     Whether nvlink shutdown is enabled for the chip
+ * [In] bLaneShutdownOnUnload
+ *     Whether nvlink shutdown should be triggered on driver unload
+ */
+#define NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID (0x35U)
+
+typedef struct NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS {
+    NvBool bLaneShutdownEnabled;
+    NvBool bLaneShutdownOnUnload;
+} NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS (0x20803035U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_ENABLE_SYSMEM_NVLINK_ATS
+ *
+ * Enable ATS functionality related to NVLink sysmem if hardware support is available
+ *
+ * [In] notUsed
+ */
+#define NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID (0x36U)
+
+typedef struct NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS {
+    NvU32 notUsed;
+} NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_ENABLE_SYSMEM_NVLINK_ATS (0x20803036U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK
+ *
+ *  Get the mask of Nvlink links connected to system
+ *
+ * [Out] sysmemLinkMask
+ *      Mask of Nvlink links connected to system
+ */
+#define NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID (0x37U)
+
+typedef struct NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
+    NvU32 sysmemLinkMask;
+} NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20803037U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR
+ *
+ * Get/Set NVSwitch FLA address
+ *
+ * [In] bGet
+ *     Whether to get or set the NVSwitch FLA address
+ * [In/Out] addr
+ *     Address that is to be set or retrieved.
+ */
+#define NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID (0x38U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS {
+    NvBool bGet;
+    NV_DECLARE_ALIGNED(NvU64 addr, 8);
+} NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR (0x20803038) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO
+ *
+ * Syncs the different link masks and vbios defined values between CPU-RM and GSP-RM
+ *
+ * [in]  discoveredLinks
+ *     Mask of links discovered from IOCTRLs
+ *
+ * [in]  connectedLinksMask
+ *     Mask of links which are connected (remote present)
+ *
+ * [in]  bridgeSensableLinks
+ *     Mask of links whose remote endpoint presence can be sensed
+ *
+ * [in]  bridgedLinks
+ *    Mask of links which are connected (remote present)
+ *    Same as connectedLinksMask, but also tracks the case where link
+ *    is connected but marginal and could not initialize
+ *
+ * [out] initDisabledLinksMask
+ *      Mask of links for which initialization is disabled
+ *
+ * [out] vbiosDisabledLinkMask
+ *      Mask of links disabled in the VBIOS
+ *
+ * [out] initializedLinks
+ *      Mask of initialized links
+ *
+ * [out] bEnableTrainingAtLoad
+ *      Whether the links should be trained to active during driver load
+ *
+ * [out] bEnableSafeModeAtLoad
+ *      Whether the links should be initialized to swcfg during driver load
+ */
+
+#define NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID (0x39U)
+
+typedef struct NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS {
+    NvU32  discoveredLinks;
+    NvU32  connectedLinksMask;
+    NvU32  bridgeSensableLinks;
+    NvU32  bridgedLinks;
+    NvU32  initDisabledLinksMask;
+    NvU32  vbiosDisabledLinkMask;
+    NvU32  initializedLinks;
+    NvBool bEnableTrainingAtLoad;
+    NvBool bEnableSafeModeAtLoad;
+} NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO (0x20803039U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS
+ *
+ * Enable pre-topology setup on the mask of enabled links
+ * This command accepts no parameters.
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS                   (0x2080303aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x3a" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS
+ *
+ * Process the init disabled NVLinks and filter those out
+ *
+ * [in/out]  initDisabledLinksMask
+ *     Mask of links initdisabled on a given GPU
+ *
+ * [in] bSkipHwNvlinkDisable
+ *     Whether to consider skipping the HW initdisable links
+ */
+
+#define NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID (0x3bU)
+
+typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS {
+    NvU32  initDisabledLinksMask;
+    NvBool bSkipHwNvlinkDisable;
+} NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS (0x2080303bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_EOM_CONTROL
+ *
+ * cmd [IN] enum identifying the EOM related command for the driver to process
+ * link [IN] linkId
+ * params [IN] NvU32 word that is written into NV_PMINION_SCRATCH_SWRW_0 before calling CONFIGEOM dlcmd
+ *
+ * Params Packing is specified in Minion IAS
+ */
+
+typedef enum NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND {
+    NVLINK_EOM_CONTROL_START_EOM = 0,
+    NVLINK_EOM_CONTROL_END_EOM = 1,
+    NVLINK_EOM_CONTROL_CONFIG_EOM = 2,
+    NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3,
+} NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND;
+
+#define NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID (0x3cU)
+
+typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS {
+    NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND cmd;
+    NvU32                                             linkId;
+    NvU32                                             params;
+} NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL     (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Inband Recieved Data
+ */
+#define NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE 4096
+#define NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID (0x3dU)
+
+typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS {
+    NvU8  data[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE];
+    NvU32 dataSize;
+} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS;
+
+#define NV2080_CTRL_NVLINK_L1_THRESHOLD_SET (0x00000000U)
+#define NV2080_CTRL_NVLINK_L1_THRESHOLD_GET (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_L1_THRESHOLD
+ *
+ * This command is used to get/set the L1 threshold value
+ *
+ * [in] flag
+ *     Whether to set or get the L1 threshold value
+ *
+ * [in/out] l1Threshold
+ *     Used to set or get the L1 threshold value
+ *
+ */
+#define NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3eU)
+
+typedef struct NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS {
+    NvU32 flag;
+    NvU32 l1Threshold;
+} NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_L1_THRESHOLD (0x2080303eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA
+ *
+ * RPC  for sending Inband data
+ *
+ * [In] data[]
+ *     data to be sent over inband
+ * [In] dataSize
+ *     Size of valid data in data array
+ */
+#define NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID (0x3fU)
+
+typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS {
+    NvU8  buffer[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE];
+    NvU32 dataSize;
+} NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA (0x2080303fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED
+ *
+ * RPC for Getting GPU degraded status upon link error
+ *
+ * [In] linkId
+ *     Id of the link on which error occured
+ * [In] bIsGpuDegraded
+ *     Boolean to track corresponding GPU is degraded or not
+ */
+#define NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID (0x40U)
+
+typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS {
+    NvU32  linkId;
+    NvBool bIsGpuDegraded;
+} NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED (0x20803040U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK
+ *
+ * This command is used to check for missing
+ * bridge/nvlink for direct connect GPU
+ *
+ * [out] bIsEnoughNvLink
+ *     Check if number of active nvlink meet the minimum requirements.
+ * [out] numBridge
+ *     Number of NVLink bridge
+ * [out] bridgePresenceMask
+ *     Bit mask of NVLink bridges's presence
+ */
+#define NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID (0x41U)
+
+typedef struct NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS {
+    NvBool bIsEnoughNvLink;
+    NvU32  numBridge;
+    NvU32  bridgePresenceMask;
+} NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK (0x20803041U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID" */
+
+
+/* _ctrl2080nvlink_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
new file mode 100644
index 0000000..b12521d
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
@@ -0,0 +1,578 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080perf.finn
+//
+
+#include "nvfixedtypes.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+#define NV_SUBPROC_NAME_MAX_LENGTH                    100
+
+#include "nvmisc.h"
+
+#include "ctrl/ctrl2080/ctrl2080clk.h"
+#include "ctrl/ctrl2080/ctrl2080gpumon.h"
+#include "ctrl/ctrl2080/ctrl2080volt.h"
+#include "ctrl/ctrl2080/ctrl2080vfe.h"
+#include "ctrl/ctrl2080/ctrl2080pmumon.h"
+#include "ctrl/ctrl0080/ctrl0080perf.h"
+//
+// XAPICHK/XAPI_TEST chokes on the "static NVINLINE" defines in nvmisc.h.
+// However, we don't need any of those definitions for those tests (XAPICHK is a
+// syntactical check, not a functional test).  So, instead, just #define out the
+// macros referenced below.
+//
+
+/*
+ * NV2080_CTRL_CMD_PERF_BOOST
+ *
+ * This command can be used to boost P-State up one level or to the highest for a limited
+ * duration for the associated subdevice. Boosts from different clients are being tracked
+ * independently. Note that there are other factors that can limit P-States so the resulting
+ * P-State may differ from expectation.
+ *
+ *   flags
+ *     This parameter specifies the actual command. _CLEAR is to clear existing boost.
+ *     _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost
+ *     to the highest P-State.
+ *   duration
+ *     This parameter specifies the duration of the boost in seconds. This has to be less
+ *     than NV2080_CTRL_PERF_BOOST_DURATION_MAX.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD                1:0
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR        (0x00000000)
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL (0x00000001)
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX (0x00000002)
+
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA               4:4
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO          (0x00000000)
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES         (0x00000001)
+
+#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC              5:5
+#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO         (0x00000000)
+#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES        (0x00000001)
+
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY          6:6
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT  (0x00000000)
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH     (0x00000001)
+
+#define NV2080_CTRL_PERF_BOOST_DURATION_MAX           3600 //The duration can be specified up to 1 hour
+#define NV2080_CTRL_PERF_BOOST_DURATION_INFINITE      0xffffffff // If set this way, the boost will last until cleared.
+
+#define NV2080_CTRL_CMD_PERF_BOOST                    (0x2080200a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_PERF_BOOST_PARAMS {
+    NvU32 flags;
+    NvU32 duration;
+} NV2080_CTRL_PERF_BOOST_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW
+ *
+ *  This command reserves HW Performance Monitoring capabilities for exclusive
+ *  use by the requester.  If the HW Performance Monitoring capabilities are
+ *  currently in use then NVOS_STATUS_ERROR_STATE_IN_USE is returned.
+ *
+ *   bAcquire
+ *     When set to TRUE this parameter indicates that the client wants to
+ *     acquire the Performance Monitoring capabilities on the subdevice.
+ *     When set to FALSE this parameter releases the Performance Monitoring
+ *     capabilities on the subdevice.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_ERROR_STATE_IN_USE
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW (0x20802093) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID (0x93U)
+
+typedef struct NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS {
+    NvBool bAcquire;
+} NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS;
+
+/*
+ * NV2080_CTRL_PERF_POWERSTATE
+ *
+ * This structure describes power state information.
+ *
+ *    powerState
+ *       This parameter specifies the type of power source.
+ *       Legal values for this parameter include:
+ *          NV2080_CTRL_PERF_POWER_SOURCE_AC
+ *             This values indicates that the power state is AC.
+ *          NV2080_CTRL_PERF_POWER_SOURCE_BATTERY
+ *             This values indicates that the power state is battery.
+ */
+#define NV2080_CTRL_PERF_POWER_SOURCE_AC      (0x00000000)
+#define NV2080_CTRL_PERF_POWER_SOURCE_BATTERY (0x00000001)
+
+typedef struct NV2080_CTRL_PERF_POWERSTATE_PARAMS {
+    NvU32 powerState;
+} NV2080_CTRL_PERF_POWERSTATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_SET_POWERSTATE
+ *
+ * This command can be used to set the perf power state as AC or battery.
+ *
+ *    powerStateInfo
+ *       This parameter specifies the power source type to set.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_PERF_SET_POWERSTATE (0x2080205b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID (0x5BU)
+
+typedef struct NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS {
+    NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo;
+} NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE
+ *
+ * This command allows the forcing of a performance level based on auxiliary
+ * power-states.
+ *
+ *   powerState
+ *     This parameter specifies the target auxiliary Power state. Legal aux
+ *     power-states for this parameter are defined by the
+ *     NV2080_CTRL_PERF_AUX_POWER_STATE_P* definitions that follow.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE (0x20802092) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x92U)
+
+typedef struct NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS {
+    NvU32 powerState;
+} NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS;
+
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_P0    (0x00000000)
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_P1    (0x00000001)
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_P2    (0x00000002)
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_P3    (0x00000003)
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_P4    (0x00000004)
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT (0x00000005)
+
+/*!
+ * Enumeration of the RATED_TDP arbitration clients which make requests to force
+ * enable/disable VF points above the RATED_TDP point.
+ *
+ * These clients are sorted in descending priority - the RM will arbitrate
+ * between all clients in order of priority, taking as output the first client
+ * whose input action != @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT.
+ */
+typedef enum NV2080_CTRL_PERF_RATED_TDP_CLIENT {
+    /*!
+     * Internal RM client corresponding to the RM's internal state and features.
+     * The RM client will either allow default behavior (@ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT) or will limit to RATED_TDP
+     * (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) when no power
+     * controllers are active.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = 0,
+    /*!
+     * This Client is specifically for Bug 1785342 where we need to limit the TDP
+     * to Min value on boot. And clear the Max TDP limit.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = 1,
+    /*!
+     * Global client request.  This client is expected to be used by a global
+     * switch functionality in an end-user tool, such as EVGA Precision, to
+     * either force enabling boost above RATED_TDP (@ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED) or to force limiting to
+     * RATED_TDP (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) across the
+     * board, regardless of any app-profie settings.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = 2,
+    /*!
+     * Operating system request.  This client is expected to be used by the
+     * operating system to set @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK
+     * for performance profiling.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = 3,
+    /*!
+     * App profile client requests.  This client is expected to be used by the
+     * app-profile settings to either default to whatever was requested by
+     * higher-priority clients (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT)
+     * or to limit to RATED_TDP (@ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) for apps which have shown
+     * bad behavior when boosting.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = 4,
+    /*!
+     * Number of supported clients.
+     *
+     * @Note MUST ALWAYS BE LAST!
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = 5,
+} NV2080_CTRL_PERF_RATED_TDP_CLIENT;
+
+/*!
+ * Enumeration RATED_TDP actions - these are the requested actions clients can
+ * make to change the behavior of the RATED_TDP functionality.
+ */
+typedef enum NV2080_CTRL_PERF_RATED_TDP_ACTION {
+    /*!
+     * The default action - meaning no explicit request from the client other
+     * than to take the default behavior (allowing boosting above RATED_TDP) or
+     * any explicit actions from lower priority clients.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = 0,
+    /*!
+     * Force allow boosting above RATED_TDP - this action explicitly requests
+     * boosting above RATED_TDP, preventing lower priority clients to limit to
+     * RATED_TDP.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = 1,
+    /*!
+     * Force to limit above RATED_TDP - this action explicitly requests to limit
+     * to RATED_TDP.  This is the opposite of the default behavior to allow
+     * boosting above RATED_TDP.  Clients specify this action when they
+     * explicitly need boost to be disabled (e.g. eliminating perf variation,
+     * special apps which exhibit bad behavior, etc.).
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = 2,
+    /*!
+     * Lock to RATED_TDP - this action requests the clocks to be fixed at the
+     * RATED_TDP.  Used for achieving stable clocks required for profiling.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = 3,
+    /*!
+     * Lock to Min TDP - This requests min to be fixed at RATED_TDP but allow
+     * boosting for max
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4,
+} NV2080_CTRL_PERF_RATED_TDP_ACTION;
+
+/*!
+ * Structure describing dynamic state of the RATED_TDP feature.
+ */
+#define NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID (0x6DU)
+
+typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS {
+    /*!
+     * Structure of internal RM state - these values are used to determine the
+     * behavior of NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM per the RM's @ref
+     * perfPwrRatedTdpLimitRegisterClientActive() interface.
+     */
+    struct {
+        /*!
+         * [out] - Mask of active client controllers (@ref
+         * PERF_PWR_RATED_TDP_CLIENT) which are currently regulating TDP.  When
+         * this mask is zero, NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request
+         * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
+         */
+        NvU32 clientActiveMask;
+        /*!
+         * [out] - Boolean indicating that user has requested locking to
+         * RATED_TDP vPstate via corresponding regkey
+         * NV_REG_STR_RM_PERF_RATED_TDP_LIMIT.  When the boolean value is true,
+         * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request
+         * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
+         */
+        NvU8  bRegkeyLimitRatedTdp;
+    } rm;
+
+    /*!
+     * [out] - Arbitrated output action of all client requests (@ref inputs).
+     * This is the current state of the RATED_TDP feature.  Will only be @ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED or @ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION output;
+    /*!
+     * [out] - Array of input client request actions, indexed via @ref
+     * NV2080_CTRL_PERF_RATED_TDP_CLIENT_<xyz>.  RM will arbitrate between these
+     * requests, choosing the highest priority request != @ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
+} NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL
+ *
+ * This command retrieves the current requested RATED_TDP action corresponding
+ * to the specified client.
+ *
+ * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
+ * parameters.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6E" */
+
+/*!
+ * NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL
+ *
+ * This command sets the requested RATED_TDP action corresponding to the
+ * specified client.  @Note, however, that this command is unable to set @ref
+ * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM.
+ *
+ * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
+ * parameters.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6F" */
+
+/*!
+ * Structure containing the requested action for a RATED_TDP client (@ref
+ * NV2080_CTRL_PERF_RATED_TDP_CLIENT).
+ */
+typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS {
+    /*!
+     * [in] - Specified client for request.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT client;
+    /*!
+     * [in/out] - Client's requested action.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION input;
+} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS;
+
+/*!
+ * This struct represents the GPU monitoring perfmon sample for an engine.
+ */
+typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE {
+    /*!
+     * Percentage during the sample that the engine remains busy. This
+     * is in units of pct*100.
+     */
+    NvU32 util;
+    /*!
+     * Scaling factor to convert utilization from full GPU to per vGPU.
+     */
+    NvU32 vgpuScale;
+    /*!
+     * Process ID of the process that was active on the engine when the
+     * sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID
+     * will be returned.
+     */
+    NvU32 procId;
+    /*!
+     * Process ID of the process in the vGPU VM that was active on the engine when
+     * the sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID
+     * will be returned.
+     */
+    NvU32 subProcessID;
+     /*!
+     * Process name of the process in the vGPU VM that was active on the engine when
+     * the sample was taken. If no process is active then NULL will be returned.
+     */
+    char  subProcessName[NV_SUBPROC_NAME_MAX_LENGTH];
+} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE;
+
+/*!
+ * This struct represents the GPU monitoring perfmon sample.
+ */
+typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE {
+    /*!
+     * Base GPU monitoring sample.
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPUMON_SAMPLE base, 8);
+    /*!
+     * FB bandwidth utilization sample.
+     */
+    NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb;
+    /*!
+     * GR utilization sample.
+     */
+    NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr;
+    /*!
+     * NV ENCODER utilization sample.
+     */
+    NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc;
+    /*!
+     * NV DECODER utilization sample.
+     */
+    NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec;
+} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE;
+
+/*!
+ * This struct represents the GPU monitoring samples of perfmon values that
+ * client wants the access to.
+ */
+#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID (0x83U)
+
+typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM;
+
+/*!
+ * Number of GPU monitoring sample in their respective buffers.
+ */
+#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL       72
+
+#define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE           \
+    NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) *     \
+    NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL
+
+/*!
+ * NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2
+ *
+ * This command returns perfmon gpu monitoring utilization samples.
+ * This command is not supported with SMC enabled.
+ *
+ * See NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_V2 for documentation
+ * on the parameters.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ * Note this is the same as NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES
+ * but without the embedded pointer.
+ *
+ */
+#define NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 (0x20802096) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID" */
+
+/*!
+ *  This structure represents the GPU monitoring samples of utilization values that
+ *  the client wants access to.
+ */
+#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID (0x96U)
+
+typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS {
+    /*!
+    * Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference.
+    */
+    NvU8  type;
+    /*!
+    * Size of the buffer, this should be
+    * bufSize ==  NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_*
+    *    sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE).
+    */
+    NvU32 bufSize;
+    /*!
+    * Number of samples in ring buffer.
+    */
+    NvU32 count;
+    /*!
+    * tracks the offset of the tail in the circular queue array pSamples.
+    */
+    NvU32 tracker;
+    /*!
+    * A circular queue with size == bufSize.
+    *
+    * @note This circular queue wraps around after 10 seconds of sampling,
+    * and it is clients' responsibility to query within this time frame in
+    * order to avoid losing samples.
+    * @note With one exception, this queue contains last 10 seconds of samples
+    * with tracker poiniting to oldest entry and entry before tracker as the
+    * newest entry. Exception is when queue is not full (i.e. tracker is
+    * pointing to a zeroed out entry), in that case valid entries are between 0
+    * and tracker.
+    * @note Clients can store tracker from previous query in order to provide
+    * samples since last read.
+    */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL], 8);
+} NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_GPU_IS_IDLE
+ *
+ * This command notifies RM to make p state switching aggressive by setting
+ * required limiting factors to speed up GC6 Entry initiation.
+ *
+ *  prevPstate [out]
+ *      This parameter will contain the pstate before the switch was initiated
+ *
+ * Possible status return values are:
+ *   NV_OK : If P State Switch is successful
+ *   NV_INVALID_STATE : If unable to access P State structure
+ *   NVOS_STATUS_ERROR   : If P State Switch is unsuccessful
+ */
+#define NV2080_CTRL_CMD_PERF_GPU_IS_IDLE (0x20802089) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID (0x89U)
+
+typedef struct NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS {
+    NvU32 prevPstate;
+    NvU32 action;
+} NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS;
+
+#define NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE             (0x00000001)
+#define NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE            (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY
+ *
+ * This command is for the KMD Aggressive P-state feature.
+ *
+ *  bGpuIsIdle [in]
+ *      When true, applies cap to lowest P-state/GPCCLK. When false, releases cap.
+ *  idleTimeUs [in]
+ *      The amount of time (in microseconds) the GPU was idle since previous
+ *      call, part of the GPU utilization data from KMD.
+ *  busyTimeUs [in]
+ *      The amount of time (in microseconds) the GPU was not idle since
+ *      previous call, part of the GPU utilization data from KMD.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+
+#define NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY (0x2080208f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID (0x8FU)
+
+typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS {
+    NvBool bGpuIsIdle;
+    NvBool bRestoreToMax;
+    NV_DECLARE_ALIGNED(NvU64 idleTimeUs, 8);
+    NV_DECLARE_ALIGNED(NvU64 busyTimeUs, 8);
+} NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS;
+
+
+/* _ctrl2080perf_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h
new file mode 100644
index 0000000..8eb6c01
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h
@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn
+//
+
+
+/* _ctrl2080perf_cf_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h
new file mode 100644
index 0000000..0a3e6b2
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn
+//
+
+
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h
new file mode 100644
index 0000000..fa476b5
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h
@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn
+//
+
+
+
+#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED  0U
+#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED      1U
+#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE 2U
+
+/*!
+ * NV2080_CTRL_PMGR_MODULE_INFO_PARAMS
+ *
+ * This provides information about different module properties
+ *
+ * moduleId[OUT]
+ *     - This is a static HW identifier that is unique for each module on a given baseboard.
+ *       For non-baseboard products this would always be 0.
+ * nvswitchSupport[OUT]
+ *     - NVSwitch present or not. Possible values are
+ *        NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED
+ *        NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED
+ *        NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE
+ */
+#define NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_PMGR_MODULE_INFO_PARAMS {
+    NvU32 moduleId;
+    NvU8  nvswitchSupport;
+} NV2080_CTRL_PMGR_MODULE_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO
+ *
+ * Control call to query the subdevice module INFO.
+ *
+ */
+#define NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO (0x20802609) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID << 8) | NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID" */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h
new file mode 100644
index 0000000..53cb620
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn
+//
+
+
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h
new file mode 100644
index 0000000..2d01ed5
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080power.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h
new file mode 100644
index 0000000..e2471c3
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h
@@ -0,0 +1,368 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080rc.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/*
+ * NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM
+ *
+ * This command returns data read from the specified virtual memory address for
+ * the associated subdevice.
+ *
+ *   hChannel
+ *      This parameter specifies the channel object handle from which the virtual
+ *      memory range applies.
+ *   virtAddress
+ *      This parameter specifies the GPU base virtual memory address from which data should
+ *      be read.  The amount of data read is specified by the bufferSize parameter.
+ *   bufferPtr
+ *      This parameter specifies the buffer address in the caller's address space into which
+ *      the data is to be returned.  The address must be aligned on an 8-byte boundary.
+ *      The buffer must be at least as big as the value specified bufferSize parameter (in bytes).
+ *   bufferSize
+ *      This parameter specifies the size of the buffer referenced by the bufferPtr parameter.
+ *      This parameter also indicates the total number of bytes to be returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_XLATE
+ */
+#define NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS {
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
+    NV_DECLARE_ALIGNED(NvP64 bufferPtr, 8);
+    NvU32    bufferSize;
+} NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS;
+
+#define NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM (0x20802204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_RC_GET_ERROR_COUNT
+ *
+ * This command returns the number of RC errors.
+ *
+ *   errorCount
+ *      Number of RC errors.
+ *
+ * Note: If SMC is enabled, mig/monitor capability must be acquired to query
+ * aggregate information. Otherwise, the control call returns
+ * NV_ERR_INSUFFICIENT_PERMISSIONS.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS.
+ */
+#define NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS {
+    NvU32 errorCount;
+} NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS;
+
+#define NV2080_CTRL_CMD_RC_GET_ERROR_COUNT      (0x20802205) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE (0x2000) /* finn: Evaluated from "(8 * 1024)" */
+
+#define NV2080_CTRL_CMD_RC_GET_ERROR            (0x20802206) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x6" */
+
+/*
+ * NV2080_CTRL_CMD_RC_GET_ERROR_V2
+ *
+ * This command returns an error element in the RC error list.
+ *
+ *   whichBuffer
+ *      Which Error to return (0 is oldest)
+ *   outputRecordSize
+ *      Output Size of Buffer -- Zero if error record doesn't exist
+ *   recordBuffer
+ *      buffer
+ *
+ * Note: If SMC is enabled, mig/monitor capability must be acquired to query
+ * aggregate information. Otherwise, the control call returns
+ * NV_ERR_INSUFFICIENT_PERMISSIONS.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS.
+ *
+ */
+
+#define NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_RC_GET_ERROR_V2_PARAMS {
+
+    NvU32 whichBuffer;                   // [IN]   - which error to return (0 is oldest)
+    NvU32 outputRecordSize;              // [OUT]
+    NvU8  recordBuffer[NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE];
+} NV2080_CTRL_RC_GET_ERROR_V2_PARAMS;
+
+#define NV2080_CTRL_CMD_RC_GET_ERROR_V2            (0x20802213) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY
+ *
+ * This command cleans error history.
+ *
+ * This command has no input parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY (0x20802207) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x7" */
+
+/*
+ * NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO
+ *
+ * This command returns information about the RC watchdog.
+ *
+ *   watchdogStatusFlags
+ *     This output parameter is a combination of one or more of the following:
+ *
+ *       NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE
+ *         This is the value of watchdogStatusFlags if no flags are set.
+ *
+ *       NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED
+ *         This means that the watchdog is disabled.
+ *
+ *       NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING
+ *         This means that the watchdog is running.
+ *
+ *       NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED
+ *         This means that the watchdog has been initialized.
+ *
+ *     A typical result would be either "running and initialized", or
+ *     "disabled".  However, "initialized, but not running, and not disabled"
+ *     is also quite reasonable (if the computer is hibernating, for example).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS {
+    NvU32 watchdogStatusFlags;
+} NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO               (0x20802209) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */
+
+/* valid values for watchdogStatusFlags */
+#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE        (0x00000000)
+#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED    (0x00000001)
+#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING     (0x00000002)
+#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED (0x00000004)
+
+/*
+ * NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG
+ *
+ * This command disables the RC watchdog, if possible.
+ * If, however, another RM client has already explicitly (via NV2080 call) enabled
+ * the RC watchdog, then this method returns NV_ERR_STATE_IN_USE.
+ *
+ * This command, if successful, will prevent other clients from enabling the
+ * watchdog until the calling RM client releases its request with
+ * NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS or frees its NV20_SUBDEVICE.
+ *
+ * See NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG for disabling the watchdog
+ * without preventing other clients from enabling it.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG                (0x2080220a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xA" */
+
+/*
+ * NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG
+ *
+ * This command enables the RC watchdog, if possible.
+ * If, however, another RM client has already explicitly (via NV2080 call) disabled
+ * the RC watchdog, then this method returns NV_ERR_STATE_IN_USE.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG                 (0x2080220b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xB" */
+
+/*
+ * NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS
+ *
+ * This command releases all of the RM client's outstanding requests to enable
+ * or disable the watchdog.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS       (0x2080220c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xC" */
+
+/*
+ * NV2080_CTRL_CMD_SET_RC_RECOVERY/NV2080_CTRL_CMD_GET_RC_RECOVERY
+ *
+ * This command disables/enables RC recovery.
+ *
+ *   rcEnable
+ *       NV2080_CTRL_CMD_SET_RC_RECOVERY_DISABLED
+ *         Disable robust channel recovery.
+ *
+ *       NV2080_CTRL_CMD_SET_RC_RECOVERY_ENABLED
+ *         Enable robust channel recovery with default breakpoint handling.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+typedef struct NV2080_CTRL_CMD_RC_RECOVERY_PARAMS {
+    NvU32 rcEnable;
+} NV2080_CTRL_CMD_RC_RECOVERY_PARAMS;
+
+#define NV2080_CTRL_CMD_SET_RC_RECOVERY       (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xD" */
+
+#define NV2080_CTRL_CMD_GET_RC_RECOVERY       (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xE" */
+
+/* valid values for rcEnable */
+#define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED  (0x00000000)
+#define NV2080_CTRL_CMD_RC_RECOVERY_ENABLED   (0x00000001)
+
+/*
+ * NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE
+ *
+ * This command can be used to set TDR timeout state.
+ *
+ * It can be used to indicate that a timeout has occurred and that a GPU
+ * reset will start. It can also be used to indicate that the reset has
+ * completed along with the corresponding complition status.
+ *
+ *   cmd
+ *    This parameter is used to indicate the stage of the TDR recovery
+ *    process. Legal values for this parameter are:
+ *     NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN
+ *      This value indicates that TDR recovery is about to begin.
+ *     NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END
+ *      This value indicates that TDR recovery has completed.
+ *
+ *   status
+ *     This parameter is valid when the cmd parameter is set to
+ *     NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END. It is used
+ *     to specify the completion status of the TDR recovery. Legal
+ *     values for this parameter include:
+ *       NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL
+ *         This value indicates the recovery failed.
+ *       NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS
+ *         This value indicates the recovery succeeded.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_COMMAND
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE (0x2080220f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS {
+    NvU32 cmd;
+    NvS32 status;
+} NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS;
+
+/* valid cmd values */
+#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN (0x00000000)
+#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END   (0x00000001)
+
+/* valid status values */
+#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS      (0x00000000)
+#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL         (0x00000001)
+
+/*
+ * NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG
+ *
+ * This command disables the RC watchdog, similarly to how
+ * NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG does. However, unlike that command, this
+ * command will not prevent another RM client from explicitly enabling the RC
+ * watchdog with NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG              (0x20802210) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x10" */
+
+/*
+ * NV2080_CTRL_CMD_GET_RC_INFO/NV2080_CTRL_CMD_SET_RC_INFO
+ *
+ * This command can be used to set robust channel parameters.
+ *
+ *   rcMode
+ *       NV2080_CTRL_CMD_SET_RC_INFO_MODE_DISABLE
+ *         Disable robust channel operation.
+ *
+ *       NV2080_CTRL_CMD_SET_RC_INFO_MODE_ENABLE
+ *         Enable robust channel operation.
+ *
+ *   rcBreak
+ *       NV2080_CTRL_CMD_SET_RC_INFO_BREAK_DISABLE
+ *         Disable breakpoint handling during robust channel operation.
+ *
+ *       NV2080_CTRL_CMD_SET_RC_INFO_BREAK_ENABLE
+ *         Enable breakpoint handling during robust channel operation.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+typedef struct NV2080_CTRL_CMD_RC_INFO_PARAMS {
+    NvU32 rcMode;
+    NvU32 rcBreak;
+} NV2080_CTRL_CMD_RC_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_SET_RC_INFO           (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x11" */
+
+#define NV2080_CTRL_CMD_GET_RC_INFO           (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x12" */
+
+/* valid rcMode values */
+#define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE  (0x00000000)
+#define NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE   (0x00000001)
+
+/* valid rcBreak values */
+#define NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE (0x00000000)
+#define NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE  (0x00000001)
+
+/* _ctrl2080rc_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h
new file mode 100644
index 0000000..448723c
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080spi.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h
new file mode 100644
index 0000000..abe66ef
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h
@@ -0,0 +1,30 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080thermal.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h
new file mode 100644
index 0000000..d018e20
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h
@@ -0,0 +1,233 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2008-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080tmr.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_TIMER related control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_TIMER_SCHEDULE
+ *
+ * This command schedules a GPU timer event to fire at the specified time interval.
+ * Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and
+ * NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags
+ *
+ *   time_nsec
+ *     This parameter specifies the time in nanoseconds at which the GPU timer
+ *     event is to fire.
+ *   flags
+ *     This parameter determines the interpretation of the value specified by
+ *     the time_nsec parameter:
+ *       NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS
+ *         This flag indicates that time_nsec is in absolute time.
+ *       NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL
+ *         This flag indicates that time_nsec is in relative time.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_TIMER_SCHEDULE (0x20800401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 time_nsec, 8);
+    NvU32 flags;
+} NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS;
+
+/* valid flag values */
+#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME               0:0
+#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS (0x00000000)
+#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL (0x00000001)
+
+/*
+ * NV2080_CTRL_CMD_TIMER_CANCEL
+ *
+ * This command cancels any pending timer events initiated with the
+ * NV2080_CTRL_CMD_TIMER_SCHEDULE command.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_TIMER_CANCEL              (0x20800402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | 0x2" */
+
+/* 
+ * NV2080_CTRL_CMD_TIMER_GET_TIME 
+ * 
+ * This command returns the current GPU timer value.  The current time is 
+ * expressed in elapsed nanoseconds since 00:00 GMT, January 1, 1970 
+ * (zero hour) with a resolution of 32 nanoseconds. 
+ *
+ * Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and
+ * NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags
+ * 
+ * Possible status values returned are: 
+ *   NV_OK 
+ *   NV_ERR_INVALID_ARGUMENT 
+ */
+#define NV2080_CTRL_CMD_TIMER_GET_TIME            (0x20800403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_TIMER_GET_TIME_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 time_nsec, 8);
+} NV2080_CTRL_TIMER_GET_TIME_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET
+ *
+ * The command returns the offset of the timer registers, so that clients may
+ * map them directly. 
+ *
+ * Possible status values returned are: 
+ *   NV_OK 
+ */
+
+#define NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET (0x20800404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS {
+    NvU32 tmr_offset;
+} NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS;
+
+/*
+ * NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE
+ *
+ * This structure describes the information obtained with
+ * NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO command.
+ *
+ *   gpuTime
+ *     GPU time is the value of GPU global timer (PTIMER) with a resolution
+ *     of 32 nano seconds.
+ *   cpuTime
+ *     CPU time. Resolution of the cpu time depends on its source. Refer to
+ *     NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_*  for more information.
+
+ */
+typedef struct NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE {
+    NV_DECLARE_ALIGNED(NvU64 cpuTime, 8);
+    NV_DECLARE_ALIGNED(NvU64 gpuTime, 8);
+} NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE;
+
+
+/*
+ * NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO
+ *
+ * This command returns correlation information between GPU time and CPU time
+ * for a given CPU clock type.
+ *
+ *   cpuClkId
+ *     This parameter specifies the source of the CPU clock. Legal values for
+ *     this parameter include:
+ *       NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME
+ *         This clock id will provide real time in microseconds since
+ *         00:00:00 UTC on January 1, 1970.
+ *       NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API
+ *         This clock id will provide time stamp that is constant-rate, high
+ *         precision using platform API that is also available in the user mode.
+ *       NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC
+ *         This clock id will provide time stamp using CPU's time stamp counter.
+ *
+ *   sampleCount
+ *     This field specifies the number of clock samples to be taken.
+ *     This value cannot exceed NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES.
+ *
+ *   samples
+ *     This field returns an array of requested samples. Refer to
+ *     NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE to get details about each entry
+ *     in the array.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO (0x20800406) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES              16
+
+#define NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS {
+    NvU8 cpuClkId;
+    NvU8 sampleCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE samples[NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES], 8);
+} NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS;
+
+/* Legal cpuClkId values */
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME       (0x00000001)
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC          (0x00000002)
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003)
+/*!
+ * NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ
+ *
+ * This command changes the frequency at which Graphics Engine time stamp is
+ * updated. Frequency can either be set to max or restored to default.
+ * Clients can independently use this call to increase the timer frequency 
+ * as a global reference count is maintained for requests to Max frequency.
+ * Client is assured that the system stays in this state till the requested
+ * client releases the state or is killed. Timer frequency will automatically
+ * be restored to default when there is no pending request to increase.
+ *
+ * Note that recursive requests for the same state from the same client
+ * are considered invalid.
+ *
+ * bSetMaxFreq
+ *      Set to NV_TRUE if GR tick frequency needs to be set to Max.
+ *
+ * See @ref NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS for
+ * documentation of parameters.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_OPERATION
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ            (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */
+
+/*!
+ * This struct contains bSetMaxFreq flag.
+ */
+#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS {
+    NvBool bSetMaxFreq;
+} NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS;
+
+/* _ctrl2080tmr_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h
new file mode 100644
index 0000000..e4995b8
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h
new file mode 100644
index 0000000..782e182
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h
@@ -0,0 +1,190 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080unix.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX OS control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT
+ *
+ * This command increases or decreases the value of the per-GPU GC6 blocker
+ * refCount used by Linux kernel clients to prevent the GPU from entering GC6.
+ *
+ * When the refCount is non-zero, the GPU cannot enter GC6. When the refCount
+ * transitions from zero to non-zero as a result of this command, the GPU will
+ * automatically come out of GC6.
+ *
+ * action   Whether to increment or decrement the value of the refCount.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT (0x20803d01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS {
+    NvU32 action;
+} NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS;
+
+// Possible values for action
+#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC   (0x00000001)
+#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC   (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF
+ *
+ * RM by default allows GCOFF but when the X driver disallows to enter in GCOFF
+ * then this rmcontrol sets flag as NV_FALSE and if it allows to enter in GCOFF
+ * then the flag is set as NV_TRUE.
+ *
+ * action   Whether to allow or disallow the user mode clients to enter in GCOFF.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF (0x20803d02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS {
+    NvU32 action;
+} NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS;
+
+// Possible values for action
+#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW    (0x00000001)
+#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER
+ *
+ * GPU can have integrated HDA (High Definition Audio) controller which
+ * can be in active or suspended state during dynamic power management.
+ * This command will perform HDA controller wakeup (if bEnter is false) or
+ * suspend (if bEnter is true).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER       (0x20803d03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS {
+    NvBool bEnter;
+} NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS
+ *
+ * Initialize cyclestats HWPM support in the kernel. This will set up a callback
+ * event for the channel indicated by hNotifierResource. This callback will execute
+ * perf register read / write commands enqueued in the shared buffer indicated by
+ * hNotifyDataMemory. Only one client may use HWPM functionality at a time.
+ *
+ * Additionally, if perfmonIdCount is greater than zero, mode-e HWPM streaming into
+ * the buffer indicated by hSnapshotMemory will be initialized (but not turned on).
+ * Data will be copied into the provided buffer every 10ms, or whenever a
+ * NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER command is issued.
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS (0x20803d04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS {
+    NvHandle hNotifierResource;
+    NvU32    notifyDataSize;
+    NvHandle hNotifyDataMemory;
+    NvU32    perfmonIdCount;
+    NvU32    snapshotBufferSize;
+    NvHandle hSnapshotMemory;
+} NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER
+ *
+ * Immediately copies any pending mode-e HWPM data into the previously
+ * installed snapshot buffer instead of waiting for the timer.
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER     (0x20803d05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x5" */
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER
+ *
+ * Stop the timer responsible for copying mode-e HWPM data to the snapshot buffer.
+ * The snapshot buffer must not be freed by the client before this command is issued.
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER             (0x20803d06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x6" */
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS
+ *
+ * This command will be used by clients to check if the GPU video memory will
+ * be persistent during system suspend/resume cycle.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS (0x20803d07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS {
+    NvBool bVidmemPersistent;
+} NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS
+ *
+ * This command will be used by clients to set restore TGP flag which will
+ * help to restore TGP limits when clients are destroyed.
+ *
+ * Possible status values returned are:
+ * NV_OK
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS (0x20803d08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS {
+    NvBool bUpdateTGP;
+} NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS;
+/* _ctrl2080unix_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h
new file mode 100644
index 0000000..a5a9db1
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080vfe.finn
+//
+
+
+
+/* _ctrl2080vfe_h_ */
+#include "nvfixedtypes.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080boardobj.h"
+#include "ctrl/ctrl2080/ctrl2080bios.h"
+
+/* --------------------------- Forward Defines ----------------------------- */
+/* --------------------------- VFE Variable -------------------------------- */
+/* --------------------------- VFE Equation -------------------------------- */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
new file mode 100644
index 0000000..2da2c80
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
@@ -0,0 +1,407 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrla081.h"
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK
+ *
+ * This command is used to bootload GSP VGPU plugin task.
+ * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature.
+ *
+ * dbdf                        - domain (31:16), bus (15:8), device (7:3), function (2:0)
+ * gfid                        - Gfid
+ * vgpuType                    - The Type ID for VGPU profile
+ * vmPid                       - Plugin process ID of vGPU guest instance
+ * swizzId                     - SwizzId
+ * numChannels                 - Number of channels
+ * numPluginChannels           - Number of plugin channels
+ * bDisableSmcPartitionRestore - If set to true, SMC default execution partition
+ *                               save/restore will not be done in host-RM
+ * guestFbPhysAddrList         - list of VMMU segment aligned physical address of guest FB memory
+ * guestFbLengthList           - list of guest FB memory length in bytes
+ * pluginHeapMemoryPhysAddr    - plugin heap memory offset
+ * pluginHeapMemoryLength      - plugin heap memory length in bytes
+ * bDeviceProfilingEnabled     - If set to true, profiling is allowed
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK (0x20804001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MAX_VMMU_SEGMENTS                                   384
+
+/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
+#define NV2080_GPU_MAX_ENGINES                                          0x3e
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS {
+    NvU32  dbdf;
+    NvU32  gfid;
+    NvU32  vgpuType;
+    NvU32  vmPid;
+    NvU32  swizzId;
+    NvU32  numChannels;
+    NvU32  numPluginChannels;
+    NvU32  chidOffset[NV2080_GPU_MAX_ENGINES];
+    NvBool bDisableDefaultSmcExecPartRestore;
+    NvU32  numGuestFbSegments;
+    NV_DECLARE_ALIGNED(NvU64 guestFbPhysAddrList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8);
+    NV_DECLARE_ALIGNED(NvU64 guestFbLengthList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8);
+    NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryPhysAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryLength, 8);
+    NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8);
+    NvBool bDeviceProfilingEnabled;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK
+ *
+ * This command is used to shutdown GSP VGPU plugin task.
+ * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature.
+ *
+ * gfid                        - Gfid
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK (0x20804002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS {
+    NvU32 gfid;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE
+ *
+ * This command is used to add a new vGPU config to the pGPU in physical RM.
+ * Unlike NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO, it does no validation
+ * and is only to be used internally.
+ *
+ * discardVgpuTypes [IN]
+ *  This parameter specifies if existing vGPU configuration should be
+ *  discarded for given pGPU
+ *
+ * vgpuInfoCount [IN]
+ *   This parameter specifies the number of entries of virtual GPU type
+*    information
+ *
+ * vgpuInfo [IN]
+ *   This parameter specifies virtual GPU type information
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE (0x20804003) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS {
+    NvBool discardVgpuTypes;
+    NvU32  vgpuInfoCount;
+    NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo[NVA081_MAX_VGPU_TYPES_PER_PGPU], 8);
+} NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS;
+
+/*
+ * NV2080_GUEST_VM_INFO
+ *
+ * This structure represents vGPU guest's (VM's) information
+ *
+ * vmPid [OUT]
+ *  This param specifies the vGPU plugin process ID
+ * guestOs [OUT]
+ *  This param specifies the vGPU guest OS type
+ * migrationProhibited [OUT]
+ *  This flag indicates whether migration is prohibited for VM or not
+ * guestNegotiatedVgpuVersion [OUT]
+ *  This param specifies the vGPU version of guest driver after negotiation
+ * frameRateLimit [OUT]
+ *  This param specifies the current value of FRL set for guest
+ * licensed [OUT]
+ *  This param specifies whether the VM is Unlicensed/Licensed
+ * licenseState [OUT]
+ *  This param specifies the current state of the GRID license state machine
+ * licenseExpiryTimestamp [OUT]
+ *  License expiry time in seconds since UNIX epoch
+ * licenseExpiryStatus [OUT]
+ *  License expiry status
+ * guestDriverVersion [OUT]
+ *  This param specifies the driver version of the driver installed on the VM
+ * guestDriverBranch [OUT]
+ *  This param specifies the driver branch of the driver installed on the VM
+ * guestVmInfoState [OUT]
+ *  This param stores the current state of guest dependent fields
+ *
+ */
+typedef struct NV2080_GUEST_VM_INFO {
+    NvU32               vmPid;
+    NvU32               guestOs;
+    NvU32               migrationProhibited;
+    NvU32               guestNegotiatedVgpuVersion;
+    NvU32               frameRateLimit;
+    NvBool              licensed;
+    NvU32               licenseState;
+    NvU32               licenseExpiryTimestamp;
+    NvU8                licenseExpiryStatus;
+    NvU8                guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE];
+    NvU8                guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE];
+    GUEST_VM_INFO_STATE guestVmInfoState;
+} NV2080_GUEST_VM_INFO;
+
+/*
+ * NV2080_GUEST_VGPU_DEVICE
+ *
+ * This structure represents host vgpu device's (assigned to VM) information
+ *
+ * gfid [OUT]
+ *  This parameter specifies the gfid of vGPU assigned to VM.
+ * vgpuPciId [OUT]
+ *  This parameter specifies vGPU PCI ID
+ * vgpuDeviceInstanceId [OUT]
+ *  This paramter specifies the vGPU device instance per VM to be used for supporting
+ *  multiple vGPUs per VM.
+ * fbUsed [OUT]
+ *  This parameter specifies FB usage in bytes
+ * eccState [OUT]
+ *  This parameter specifies the ECC state of the virtual GPU.
+ *  One of NVA081_CTRL_ECC_STATE_xxx values.
+ * bDriverLoaded [OUT]
+ *  This parameter specifies whether driver is loaded on this particular vGPU.
+ *
+ */
+typedef struct NV2080_HOST_VGPU_DEVICE {
+    NvU32  gfid;
+    NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8);
+    NvU32  vgpuDeviceInstanceId;
+    NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
+    NvU32  encoderCapacity;
+    NvU32  eccState;
+    NvBool bDriverLoaded;
+} NV2080_HOST_VGPU_DEVICE;
+
+/*
+ * NV2080_VGPU_GUEST
+ *
+ * This structure represents a vGPU guest
+ *
+ */
+typedef struct NV2080_VGPU_GUEST {
+    NV2080_GUEST_VM_INFO guestVmInfo;
+    NV_DECLARE_ALIGNED(NV2080_HOST_VGPU_DEVICE vgpuDevice, 8);
+} NV2080_VGPU_GUEST;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU
+ *
+ * This command enumerates list of vGPU guest instances per pGpu
+ *
+ * numVgpu [OUT]
+ *  This parameter specifies the number of virtual GPUs created on this physical GPU
+ *
+ * vgpuGuest [OUT]
+ *  This parameter specifies an array containing guest vgpu's information for
+ *  all vGPUs created on this physical GPU
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU (0x20804004) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS {
+    NvU32 numVgpu;
+    NV_DECLARE_ALIGNED(NV2080_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8);
+} NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO
+ *
+ * This command is used clear guest vm info. It should be used when
+ * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE
+ * is called with NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED state.
+ *
+ * gfid [IN]
+ *  This parameter specifies the gfid of vGPU assigned to VM.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO (0x20804005) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS {
+    NvU32 gfid;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE
+ *
+ * This command is used to get the FB usage of all vGPU instances running on a GPU.
+ *
+ * vgpuCount [OUT]
+ *  This field specifies the number of vGPU devices for which FB usage is returned.
+ * vgpuFbUsage [OUT]
+ *  This is an array of type NV2080_VGPU_FB_USAGE, which contains a list of vGPU gfid
+ *  and their corresponding FB usage in bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE (0x20804006) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_VGPU_FB_USAGE {
+    NvU32 gfid;
+    NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
+} NV2080_VGPU_FB_USAGE;
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS {
+    NvU32 vgpuCount;
+    NV_DECLARE_ALIGNED(NV2080_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8);
+} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY
+ *
+ * This command is used to set vGPU instance's (represented by gfid) encoder Capacity.
+ *
+ * gfid [IN]
+ *  This parameter specifies the gfid of vGPU assigned to VM.
+ * encoderCapacity [IN]
+ *  Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance
+ *  may be minimal for this GPU and software should fall back to CPU-based encode.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY (0x20804007) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS {
+    NvU32 gfid;
+    NvU32 encoderCapacity;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP
+ *
+ * This command is used to cleanup all the GSP VGPU plugin task allocated resources after its shutdown.
+ * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature.
+ *
+ * gfid [IN]
+ *  This parameter specifies the gfid of vGPU assigned to VM.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP (0x20804008) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS {
+    NvU32 gfid;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS;
+
+#define NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN             8
+#define NV2080_CTRL_MAX_GPC_COUNT                              32
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING
+ *
+ * Reroutes kvgpumgrGetPgpuFSEncoding to vgpuMgrGetPgpuFSEncoding.
+ *
+ * pgpuString [OUT]
+ *  Resulting PGPU string
+ * pgpuStringSize
+ *  PGPU string size
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING (0x20804009) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS {
+    NvU8  pgpuString[NVA081_PGPU_METADATA_STRING_SIZE];
+    NvU32 pgpuStringSize;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT
+ *
+ * Reroutes kvgpumgrCheckPgpuMigrationSupport to vgpuMgrCheckPgpuMigrationSupport.
+ *
+ * bIsMigrationSupported [OUT]
+ *  Resulting status of the migration support
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT (0x2080400a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS {
+    NvBool bIsMigrationSupported;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG
+ *
+ * Sets vgpu manager parameters. This control is used after GSP initialization.
+ *
+ * bSupportHeterogeneousTimeSlicedVgpuTypes [IN]
+ *  Enable/disable heterogeneous time-sliced vgpu types
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG (0x2080400b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS {
+    NvBool bSupportHeterogeneousTimeSlicedVgpuTypes;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS;
+
+/* _ctrl2080vgpumgrinternal_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h
new file mode 100644
index 0000000..eacd596
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl2080/ctrl2080volt.finn
+//
+
+
+
+/* _ctrl2080volt_h_ */
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080boardobj.h"
+#include "ctrl/ctrl2080/ctrl2080pmumon.h"
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f.h
new file mode 100644
index 0000000..b526aa3
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f.h
@@ -0,0 +1,51 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f.finn
+//
+
+
+
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl208f/ctrl208fpower.h"
+#include "ctrl208f/ctrl208ffifo.h"
+#include "ctrl208f/ctrl208ffb.h"
+#include "ctrl208f/ctrl208ffbio.h"
+
+
+#include "ctrl208f/ctrl208fbif.h"
+#include "ctrl208f/ctrl208fbus.h"
+#include "ctrl208f/ctrl208fevent.h"
+#include "ctrl208f/ctrl208fgpu.h"
+#include "ctrl208f/ctrl208fgr.h"
+#include "ctrl208f/ctrl208fclk.h"
+#include "ctrl208f/ctrl208fpmgr.h"
+#include "ctrl208f/ctrl208fdma.h"
+#include "ctrl208f/ctrl208fmmu.h"
+
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h
new file mode 100644
index 0000000..eb08864
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h
@@ -0,0 +1,71 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fbase.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV20_SUBDEVICE_DIAG: diagnostic class control commands and parameters */
+
+#define NV208F_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x208F, NV208F_CTRL_##cat, idx)
+
+/* Subdevice diag command categories (6bits) */
+#define NV208F_CTRL_RESERVED     (0x00)
+#define NV208F_CTRL_POWER        (0x01)
+#define NV208F_CTRL_THERMAL      (0x02)
+#define NV208F_CTRL_SEQ          (0x03)
+#define NV208F_CTRL_FIFO         (0x04)
+#define NV208F_CTRL_FB           (0x05)
+#define NV208F_CTRL_MC           (0x06)
+#define NV208F_CTRL_BIF          (0x07)
+#define NV208F_CTRL_CLK          (0x08)
+#define NV208F_CTRL_PERF         (0x09)
+#define NV208F_CTRL_FBIO         (0x0A)
+#define NV208F_CTRL_MMU          (0x0B)
+#define NV208F_CTRL_PMU          (0x0C)
+#define NV208F_CTRL_EVENT        (0x10)
+#define NV208F_CTRL_GPU          (0x11)
+#define NV208F_CTRL_GR           (0x12)
+#define NV208F_CTRL_PMGR         (0x13)
+#define NV208F_CTRL_DMA          (0x14)
+// const NV208F_CTRL_TMR = (0x15); // not supported
+#define NV208F_CTRL_RMFS         (0x16)
+#define NV208F_CTRL_GSPMSGTIMING (0x17)
+#define NV208F_CTRL_BUS          (0x18)
+
+/*
+ * NV208F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *     NV_OK
+ */
+#define NV208F_CTRL_CMD_NULL     (0x208f0000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* _ctrl208fbase_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h
new file mode 100644
index 0000000..3499ef9
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h
@@ -0,0 +1,194 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fbif.finn
+//
+
+#include "ctrl/ctrl208f/ctrl208fbase.h"
+
+/*
+* NV208F_CTRL_CMD_BIF_PBI_WRITE_COMMAND
+*
+* Control command to send a write command to the Post Box Interface
+*
+* Parameters:
+*
+*cmdFuncId
+*   this specifies the function that needs to be performed on pbi
+*data
+*   the data to be set in the data in register
+* status 
+*   this corresponds to pbi status register
+* sysNotify
+*   this corresponds to system notify event, i.e. whether system
+*   needs to be notified of command completion
+* drvNotify
+*   this corresponds to driver notify event, i.e. whether driver
+*   needs to be notified of command completion
+*
+* For the possible values of the above parameters refer rmpbicmdif.h
+*/
+#define NV208F_CTRL_CMD_BIF_PBI_WRITE_COMMAND (0x208f0701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS {
+    NvU8   cmdFuncId;
+    NvU32  data;
+    NvU8   status;
+    NvBool sysNotify;
+    NvBool drvNotify;
+} NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS;
+
+/*
+* NV208F_CTRL_CMD_BIF_CONFIG_REG_READ
+*   This command is used to read any of the PBI registers in the config space
+*
+* Parameters:
+*
+* RegIndex
+*   Defines the index of the PBI register
+* data
+*   Data that is read
+*/
+#define NV208F_CTRL_CMD_BIF_CONFIG_REG_READ (0x208f0702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS {
+    NvU8  RegIndex;
+    NvU32 data;
+} NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS;
+
+/*
+* NV208F_CTRL_CMD_BIF_CONFIG_REG_WRITE
+*   This command is used to write any of the PBI registers in the config space
+*
+* Parameters:
+*
+* RegIndex
+*   Defines the index of the PBI register
+* data
+*   Data that is to be written
+*/
+#define NV208F_CTRL_CMD_BIF_CONFIG_REG_WRITE (0x208f0703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS {
+    NvU8  RegIndex;
+    NvU32 data;
+} NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS;
+
+/*
+* NV208F_CTRL_CMD_BIF_INFO
+*   This command is used to read a bif property
+*
+* Parameters:
+*
+* index
+*   Defines the index of the property to read
+* data
+*   Data that is read 
+*/
+#define NV208F_CTRL_CMD_BIF_INFO (0x208f0704) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_BIF_INFO_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV208F_CTRL_BIF_INFO_PARAMS {
+    NvU32 index;
+    NvU32 data;
+} NV208F_CTRL_BIF_INFO_PARAMS;
+
+/* valid bif info index values */
+#define NV208F_CTRL_BIF_INFO_INDEX_L0S_ENABLED   (0x00000000)
+#define NV208F_CTRL_BIF_INFO_INDEX_L1_ENABLED    (0x00000001)
+
+/*
+ * NV208F_CTRL_CMD_BIF_ECC_INJECT_ERROR
+ *
+ * This ctrl call injects PCI-E XPL-EP ECC errors.  Please see the confluence
+ * page "ECC" for more information on ECC and ECC injection:
+ *
+ * Parameters:
+ *
+ * errorUnit
+ *   Specifies the HW unit where the injection will occur.
+ *
+ * errorType
+ *   Specifies whether the injected error will be correctable or uncorrectable.
+ *   Correctable errors have no effect on running programs while uncorrectable
+ *   errors will cause all channels to be torn down.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV208F_CTRL_CMD_BIF_ECC_INJECT_ERROR     (0x208f0705) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */
+
+
+
+#define NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS {
+    NvU8 errorType;
+    NvU8 errorUnit;
+} NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_BIF_ECC_INJECTION_SUPPORTED
+ *
+ * Reports if error injection is supported for XPL-EP
+ *
+ * bCorrectableSupported [out]:
+ *      Boolean value that shows if correcatable errors can be injected.
+ *
+ * bUncorrectableSupported [out]:
+ *      Boolean value that shows if uncorrecatable errors can be injected.
+ *
+ * Return values:
+ *      NV_OK on success
+ *      NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled.
+ *      NV_ERR_NOT_SUPPORTED otherwise
+ *
+ *
+ */
+#define NV208F_CTRL_CMD_BIF_ECC_INJECTION_SUPPORTED (0x208f0706) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS {
+    NvU8   errorUnit;
+    NvBool bCorrectableSupported;
+    NvBool bUncorrectableSupported;
+} NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS;
+
+/* _ctrl208fbif_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h
new file mode 100644
index 0000000..11fd26e
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h
@@ -0,0 +1,113 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fbus.finn
+//
+
+#include "ctrl/ctrl208f/ctrl208fbase.h"
+
+/*
+ * NV208F_CTRL_CMD_BUS_IS_BAR1_VIRTUAL
+ *
+ * This command checks whether or not BAR1 is in virtual mode.
+ * This API is intended for internal testing only.
+ *
+ *   bIsVirtual
+ *     Whether or not Bar1 is in virtual mode.
+ */
+#define NV208F_CTRL_CMD_BUS_IS_BAR1_VIRTUAL (0x208f1801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS {
+    NvBool bIsVirtual;
+} NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_BUS_ECC_INJECT_ERROR
+ *
+ * This ctrl call injects BUS ECC errors.  Please see the confluence
+ * page "ECC" for more information on ECC and ECC injection:
+ *
+ * Parameters:
+ *
+ * location
+ *   Specifies the BUS HW unit where the injection will occur.
+ *
+ * errorType
+ *   Specifies whether the injected error will be correctable or uncorrectable.
+ *   Correctable errors have no effect on running programs while uncorrectable
+ *   errors will cause all channels to be torn down.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV208F_CTRL_CMD_BUS_ECC_INJECT_ERROR     (0x208f1802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */
+
+
+
+#define NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS {
+    NvU8 errorType;
+    NvU8 errorUnit;
+} NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_BUS_ECC_INJECTION_SUPPORTED
+ *
+ * Reports if error injection is supported for BUS units
+ *
+ * bCorrectableSupported [out]:
+ *      Boolean value that shows if correcatable errors can be injected.
+ *
+ * bUncorrectableSupported [out]:
+ *      Boolean value that shows if uncorrecatable errors can be injected.
+ *
+ * Return values:
+ *      NV_OK on success
+ *      NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled.
+ *      NV_ERR_NOT_SUPPORTED otherwise
+ *
+ *
+ */
+#define NV208F_CTRL_CMD_BUS_ECC_INJECTION_SUPPORTED (0x208f1803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS {
+    NvU8   errorUnit;
+    NvBool bCorrectableSupported;
+    NvBool bUncorrectableSupported;
+} NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS;
+
+/* _ctrl208fbus_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h
new file mode 100644
index 0000000..450d881
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h
@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fclk.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h
new file mode 100644
index 0000000..a302d42
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fdma.finn
+//
+
+#include "ctrl/ctrl208f/ctrl208fbase.h"
+
+/*
+ * NV208F_CTRL_CMD_DMA_IS_SUPPORTED_SPARSE_VIRTUAL
+ *
+ * This command checks whether or not "sparse" virtual address ranges are
+ * supported for a given chip. This API is intended for debug-use only.
+ *
+ *   bIsSupported
+ *     Whether or not "sparse" virtual address ranges are supported.
+ */
+#define NV208F_CTRL_CMD_DMA_IS_SUPPORTED_SPARSE_VIRTUAL (0x208f1401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID << 8) | NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS {
+    NvBool bIsSupported;
+} NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_DMA_GET_VAS_BLOCK_DETAILS
+ *
+ * This command retrieves various details of the virtual address space block
+ * allocated from the virtual address space heap for the given virtual address.
+ *
+ *   virtualAddress
+ *     Virtual address to get information about.
+ *
+ *   beginAddress
+ *     Start address of the corresponding virtual address space block.
+ *
+ *   endAddress
+ *     End address (inclusive) of the corresponding virtual address space
+ *     block.
+ *
+ *   alignedAddress
+ *     Aligned address of the corresponding virtual address space block.
+ *
+ *   pageSize
+ *     Page size of the virtual address space block.
+ *
+ *   hVASpace
+ *     Handle to an allocated VA space. If 0, it is assumed that the device's
+ *     VA space should be used.
+ */
+#define NV208F_CTRL_CMD_DMA_GET_VAS_BLOCK_DETAILS (0x208f1402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID << 8) | NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 virtualAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 beginAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 endAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 alignedAddress, 8);
+    NvU32    pageSize;
+    NvHandle hVASpace;
+} NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS;
+
+/* _ctrl208fdma_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h
new file mode 100644
index 0000000..3777829
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h
@@ -0,0 +1,93 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2009-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fevent.finn
+//
+
+#include "ctrl/ctrl208f/ctrl208fbase.h"
+
+/* NV20_SUBDEVICE_DIAG event-related control commands and parameters */
+
+/*
+ * NV208F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * This command sets event notification state for the associated subdevice.
+ * This command requires that an instance of NV01_EVENT has been previously
+ * bound to the associated subdevice object.
+ *
+ *   event
+ *     This parameter specifies the type of event to which the specified
+ *     action is to be applied.  This parameter must specify a valid
+ *     NV208F_NOTIFIERS value (see cl208f.h for more details) and should
+ *     not exceed one less NV208F_NOTIFIERS_MAXCOUNT.
+ *   action
+ *     This parameter specifies the desired event notification action.
+ *     Valid notification actions include:
+ *       NV208F_CTRL_SET_EVENT_NOTIFICATION_DISABLE
+ *         This action disables event notification for the specified
+ *         event for the associated subdevice object.
+ *       NV208F_CTRL_SET_EVENT_NOTIFICATION_SINGLE
+ *         This action enables single-shot event notification for the
+ *         specified event for the associated subdevice object.
+ *       NV208F_CTRL_SET_EVENT_NOTIFICATION_REPEAT
+ *         This action enables repeated event notification for the specified
+ *         event for the associated system controller object.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV208F_CTRL_CMD_EVENT_SET_NOTIFICATION (0x208f1001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID << 8) | NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
+    NvU32 event;
+    NvU32 action;
+} NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NV208F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
+#define NV208F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  (0x00000001)
+#define NV208F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  (0x00000002)
+
+/*
+ * NV208F_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * This command triggers a software event for the associated subdevice.
+ * This command accepts no parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV208F_CTRL_CMD_EVENT_SET_TRIGGER                 (0x208f1002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID << 8) | 0x2" */
+
+/* _ctrl208fevent_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h
new file mode 100644
index 0000000..ec16916
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h
@@ -0,0 +1,611 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208ffb.finn
+//
+
+#include "ctrl/ctrl208f/ctrl208fbase.h"
+
+/*
+ * NV208F_CTRL_CMD_FB_GET_INFO
+ *
+ * This command returns fb engine information for the associated GPU.
+ * The client specifies what information to query through 'index' param.
+ * On success, the information is stored in the 'data' param.
+ *
+ *   index
+ *     Specify what information to query. Please see below for valid values of
+ *     indexes for this command.
+ *   data
+ *     On success, this param will hold the data that the client queried for.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV208F_CTRL_CMD_FB_GET_INFO (0x208f0501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV208F_CTRL_FB_GET_INFO_PARAMS {
+    NvU32 index;
+    NV_DECLARE_ALIGNED(NvU64 data, 8);
+} NV208F_CTRL_FB_GET_INFO_PARAMS;
+
+/* valid fb info index values */
+#define NV208F_CTRL_FB_INFO_INDEX_FREE_CONTIG_COMPRESSION_SIZE (0x00000001)
+
+#define NV208F_CTRL_FB_INFO_INDEX_MAX                          NV208F_CTRL_FB_INFO_INDEX_FREE_CONTIG_COMPRESSION_SIZE
+
+/*
+ * NV208F_CTRL_CMD_FB_GET_ZBC_REFCOUNT
+ *
+ * This command gets the ZBC reference count associated with a given
+ * compression tag address.  It is not supported on GPUs which support class
+ * GF100_ZBC_CLEAR as it is specific to a different hardware implementation.
+ * 
+ *   compTagAddress
+ *     The input parameter indicating the compression tag address for which the
+ *     associated ZBC refcount should be looked up.
+ *   zbcRefCount
+ *     An array of reference counts for the ZBC clear values associated with
+ *     compTagAddress.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV208F_CTRL_CMD_FB_GET_ZBC_REFCOUNT                    (0x208f0505) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | 0x5" */ // Deprecated, removed form RM
+
+#define NV208F_CTRL_FB_GET_ZBC_REFCOUNT_MAX_REFCOUNTS          2
+typedef struct NV208F_CTRL_FB_GET_ZBC_REFCOUNT_PARAMS {
+    NvU32 compTagAddress;
+    NvU32 zbcRefCount[NV208F_CTRL_FB_GET_ZBC_REFCOUNT_MAX_REFCOUNTS];
+} NV208F_CTRL_FB_GET_ZBC_REFCOUNT_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_FB_CTRL_GPU_CACHE
+ *
+ * This command controls the state of a cache which all GPU memory accesses go
+ * through.  If supported, it allows changing of the power state and the write
+ * mode.  This is only supported when NV_VERIF_FEATURES is defined.  An error
+ * will be returned if the requested combination of settings is not possible.
+ *
+ *   writeMode
+ *     Specifies the write mode of the cache.  Possible values are defined in
+ *     NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE. Passing _DEFAULT means to
+ *     maintain the current write mode.  It is illegal to change the write mode
+ *     while the cache is disabled or in the same call as a request to disable
+ *     it.
+ *   powerState
+ *     Specifies the power state of the cache.  Possible values are defined in
+ *     NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE.  Passing _DEFAULT means
+ *     to maintain the current power state.
+ *   rcmState
+ *     Specifies the reduced cache mode of the cache.  Possible values are
+ *     defined in NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE.  Passing _DEFAULT
+ *     means to maintain the current RCM state.
+ *   vgaCacheMode
+ *     Specifies whether or not to enable VGA out-of-cache mode.  Possible
+ *     values are defined in NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE.  Passing
+ *     _DEFAULT means to maintain the current VGA caching mode.  
+ *   cacheReset
+ *     Triggers a hardware reset of the cache.  Possible values are defined in
+ *     NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET.  Passing _DEFAULT does
+ *     nothing while passing _RESET clears all data in the cache.
+ *   flags
+ *     Contains flags to control the details of how transitions should be
+ *     handled.  Possible values are defined in
+ *     NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS.  Passing _DEFAULT for any of
+ *     the fields means to use the defaults specified by the Resource Manager.
+ *     Note not all options are available for all transitions.  Flags that are
+ *     set but not applicable will be silently ignored.
+ *   bypassMode
+ *     (Fermi only) Specifies the bypass mode of the L2 cache.  Normal GPU
+ *     operation is _DISABLE.  For TEST ONLY, setting _ENABLE enables a debug
+ *     mode where all transactions miss in L2 and no writes are combined,
+ *     essentially disabling the caching feature of the L2 cache.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV208F_CTRL_CMD_FB_CTRL_GPU_CACHE (0x208f0506) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS {
+    NvU32 writeMode;
+    NvU32 powerState;
+    NvU32 rcmState;
+    NvU32 vgaCacheMode;
+    NvU32 cacheReset;
+    NvU32 flags;
+    NvU32 bypassMode;
+} NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS;
+
+/* valid values for writeMode */
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_DEFAULT      (0x00000000)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_WRITETHROUGH (0x00000001)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_WRITEBACK    (0x00000002)
+
+/* valid values for powerState */
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_DEFAULT     (0x00000000)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_ENABLED     (0x00000001)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_DISABLED    (0x00000002)
+
+/* valid values for rcmState */
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_DEFAULT       (0x00000000)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_FULL          (0x00000001)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_REDUCED       (0x00000002)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_ZERO_CACHE    (0x00000003)
+
+/* valid values for vgaCacheMode */
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_DEFAULT        (0x00000000)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_ENABLED        (0x00000001)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_DISABLED       (0x00000002)
+
+/* valid values for cacheReset */
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET_DEFAULT     (0x00000000)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET_RESET       (0x00000001)
+
+/* valid fields and values for flags */
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE                   1:0
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_DEFAULT      (0x00000000)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_RM           (0x00000001)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_PMU          (0x00000002)
+
+/* valid values for bypassMode */
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_DEFAULT     (0x00000000)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_DISABLED    (0x00000001)
+#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_ENABLED     (0x00000002)
+
+
+
+/*
+ * NV208F_CTRL_CMD_FB_SET_STATE
+ *
+ * This command is used to put fb engine in a state requested by the caller. 
+ * 
+ *   state
+ *     This parameter specifies the desired engine state:
+ *       NV208F_CTRL_FB_SET_STATE_STOPPED
+ *         This value stops/halts the fb engine.
+ *       NV208F_CTRL_FB_SET_STATE_RESTART      
+ *         This value restarts fb from a stopped state. 
+ *   
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV208F_CTRL_CMD_FB_SET_STATE                          (0x208f0508) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_SET_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_SET_STATE_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV208F_CTRL_FB_SET_STATE_PARAMS {
+    NvU32 state;
+} NV208F_CTRL_FB_SET_STATE_PARAMS;
+
+/* valid values for state */
+#define NV208F_CTRL_FB_SET_STATE_STOPPED  (0x00000000)
+#define NV208F_CTRL_FB_SET_STATE_RESTART  (0x00000001)
+
+/*
+ * NV208F_CTRL_CMD_GPU_ECC_SCRUB_DIAG
+ * 
+ * This command reads all the settings internal to scrubbing (both asynchronous
+ * and synchronous.
+ *
+ * Currently implemented: FB offset scrubber has completed, FB offset that scrubber
+ * is completing to, whether or not asynchronous scrubbing is enabled.
+ * 
+ *   fbOffsetCompleted
+ *      This is the offset into FB that the scrubber has completed up to at the
+ *      time this function is invoked. Note that the scrubber is top-down. Therefore
+ *      the memory that remains unscrubbed is from 0x0 to fbOffsetCompleted.
+ *
+ *   fbEndOffset
+ *       This is the offset of the base of the last block that ECC asynchronous
+ *       scrubber has been tasked to scrub.
+ *
+ *   bAsyncScru bDisabled
+ *       This is NV_TRUE if asynchronous scrubbing is disabled and NV_FALSE if
+ *       asynchronous scrubbing is enabled.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG (0x208f0509) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 fbOffsetCompleted, 8);
+    NV_DECLARE_ALIGNED(NvU64 fbEndOffset, 8);
+    NvBool bAsyncScrubDisabled;
+} NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_GPU_ECC_ASYNCH_SCRUB_REGION
+ *
+ * This command launches the ECC scrubber in asynchronous mode. The scrubber, as
+ * in normal operation, will continue to operate until all of FB (excluding
+ * dedicated system memory) has been scrubbed. Like usual operation, scrubbing is
+ * only done on silicon.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION (0x208f050a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 startBlock, 8);
+    NV_DECLARE_ALIGNED(NvU64 endBlock, 8);
+} NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_GPU_ECC_ERROR_INFO
+ * This is a structure that is defined here for diag/debug purposes in mods.
+ * It is used to return the error information as part of the callback to 
+ * kernel clients registering for SBE/DBE callbacks.
+ */
+
+typedef struct NV208F_CTRL_CMD_FB_ECC_ERROR_INFO {
+    NvU32 row;
+    NvU32 bank;
+    NvU32 col;
+    NvU32 extBank;
+    NvU32 xbarAddress;
+    NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
+} NV208F_CTRL_CMD_FB_ECC_ERROR_INFO;
+
+
+#define NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS (0x208f050c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 pAddr, 8);
+    NvU32 row;
+    NvU32 bank;
+    NvU32 col;
+    NvU32 extBank;
+    NvU32 rank;
+    NvU32 sublocation;
+    NvU32 partition;
+    NvU32 writeKillPtr0;
+    NvU32 injectionAddr;
+    NvU32 injectionAddrExt;
+    NvU32 rbcAddress;
+    NvU32 rbcAddressExt;
+    NvU32 rbcAddressExt2;
+    NvU32 eccCol;
+} NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_FB_ECC_SET_KILL_PTR
+ *
+ * This command sets the kill pointer for the specified DRAM address.  If
+ * the kill pointer is set to NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE
+ * or NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE, accesses to the specified
+ * address will result in ECC errors until all kill pointers are unset
+ * using NV208F_CTRL_FB_ERROR_TYPE_NONE.
+ *
+ * Only one kill pointer can be set at a time.  Setting a kill pointer will
+ * clear all currently set kill pointers and set the new kill pointer.
+ * Calling NV208F_CTRL_FB_ERROR_TYPE_NONE simply clears all currently set
+ * kill pointers.
+ *
+ *   errorType
+ *      The type of kill pointer to set.  NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE
+ *      will set a single kill pointer resulting in a correctable error.
+ *      NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE will set both kill pointers
+ *      resulting in an uncorrectable error.  NV208F_CTRL_FB_ERROR_TYPE_NONE
+ *      will clear all kill pointers, which stops the associated addresses
+ *      from generating ECC errors if NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE
+ *      or NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE was previously set.
+ *      Only one kill pointer can be set at a time and setting a new
+ *      kill pointer will clear the previous kill pointer.
+ *
+ *    address
+ *      The physical DRAM address to be targeted by the kill pointer
+ *
+ *    bProdInjection
+ *      Whether the kill pointer is set through the production injection flow or not
+ */
+#define NV208F_CTRL_CMD_FB_ECC_SET_KILL_PTR (0x208f050e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS_MESSAGE_ID" */
+
+typedef enum NV208F_CTRL_FB_ERROR_TYPE {
+    NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE = 0,
+    NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE = 1,
+    NV208F_CTRL_FB_ERROR_TYPE_NONE = 2,
+} NV208F_CTRL_FB_ERROR_TYPE;
+
+#define NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS {
+    NV208F_CTRL_FB_ERROR_TYPE errorType;
+    NV_DECLARE_ALIGNED(NvU64 address, 8);
+    NvBool                    bProdInjection;
+} NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS;
+
+
+
+/*
+ * NV208F_CTRL_CMD_FB_INJECT_LTC_ECC_ERROR
+ *
+ * This API allows a client to inject ECC errors in the L2.
+ *
+ *   ltc:
+ *      The physical LTC number to inject the error into.
+ *   slice:
+ *      THe physical slice number within the LTC to inject the error into.
+ *   locationMask
+ *      LTC location subtype(s) where error is to be injected. (Valid on Ampere and later)
+ *   errorType
+ *      Type of error to inject
+ *      NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE for SBE.
+ *      NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE for DBE.
+ *
+ */
+#define NV208F_CTRL_CMD_FB_INJECT_LTC_ECC_ERROR     (0x208f050f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS {
+    NvU8                      ltc;
+    NvU8                      slice;
+    NvU8                      locationMask;
+    NV208F_CTRL_FB_ERROR_TYPE errorType;
+} NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_FB_ECC_INJECTION_SUPPORTED
+ *
+ * Reports if error injection is supported for a given HW unit
+ *
+ * location [in]:
+ *      The ECC protected unit for which ECC injection support is being checked.
+ *      The location type is defined by NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC.
+ *
+ * bCorrectableSupported [out]:
+ *      Boolean value that shows if correcatable errors can be injected.
+ *
+ * bUncorrectableSupported [out]:
+ *      Boolean value that shows if uncorrecatable errors can be injected.
+ *
+ * Return values:
+ *      NV_OK on success
+ *      NV_ERR_INVALID_ARGUMENT if the requested location is invalid.
+ *      NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled.
+ *      NV_ERR_NOT_SUPPORTED otherwise
+ *
+ *
+ */
+#define NV208F_CTRL_CMD_FB_ECC_INJECTION_SUPPORTED (0x208f0510) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS {
+    NvU8   location;
+    NvBool bCorrectableSupported;
+    NvBool bUncorrectableSupported;
+} NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS;
+
+#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC          0:0
+#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_LTC  (0x00000000)
+#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_DRAM (0x00000001)
+
+/*
+ * NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL
+ *
+ * This command sets the write kill for the specified DRAM address.  If set,
+ * writes to the specified address won't update the ECC checkbits.  When unset,
+ * writes the specified address will update the ECC checkbits.
+ *
+ * Only one write kill register can be set at a time.  Setting a write kill
+ * will clear all currently set write kills and set the new write kill.
+ * Calling this ctrl call with setWriteKill = false simply clears all currently
+ * set write kills.
+ *
+ *   setWriteKill
+ *      When true, the ECC checkbits for the specified address won't update on
+ *      writes. When false, the ECC checkbits for the specified address will
+ *      revert to normal behavior and update on all writes.
+ *
+ *   address
+ *      The physical DRAM address to be targeted by the write kill
+ */
+#define NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL           (0x208f0511) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS {
+    NvBool setWriteKill;
+    NV_DECLARE_ALIGNED(NvU64 address, 8);
+} NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS;
+
+/*
+ * NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO
+ *
+ *   physicalAddress
+ *     Physical address to be remapped
+ *   source
+ *     The reason for retirement. Valid values for this parameter are
+ *     from NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_*
+ *   status
+ *     Reason for row remapping failure. Valid values are:
+ *       NV208F_CTRL_FB_REMAP_ROW_STATUS_OK
+ *         No error
+ *       NV208F_CTRL_FB_REMAP_ROW_STATUS_REMAPPING_PENDING
+ *         The remapping is pending
+ *       NV208F_CTRL_FB_REMAP_ROW_STATUS_TABLE_FULL
+ *         Table full
+ *       NV208F_CTRL_FB_REMAP_ROW_STATUS_ALREADY_REMAPPED
+ *         Attempting to remap a reserved row
+ *       NV208F_CTRL_FB_REMAP_ROW_STATUS_INTERNAL_ERROR
+ *         Some other RM failure
+ */
+typedef struct NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO {
+    NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8);
+    NvU8  source;
+    NvU32 status;
+} NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO;
+
+/* valid values for status */
+#define NV208F_CTRL_FB_REMAP_ROW_STATUS_OK                (0x00000000)
+#define NV208F_CTRL_FB_REMAP_ROW_STATUS_REMAPPING_PENDING (0x00000001)
+#define NV208F_CTRL_FB_REMAP_ROW_STATUS_TABLE_FULL        (0x00000002)
+#define NV208F_CTRL_FB_REMAP_ROW_STATUS_ALREADY_REMAPPED  (0x00000003)
+#define NV208F_CTRL_FB_REMAP_ROW_STATUS_INTERNAL_ERROR    (0x00000004)
+
+#define NV208F_CTRL_FB_REMAPPED_ROWS_MAX_ROWS             (0x00000200)
+/*
+ * NV208F_CTRL_CMD_FB_REMAP_ROW
+ *
+ * This command will write entries to Inforom. During init the entries will be
+ * read and used to remap a row.
+ *
+ *   addressList
+ *     This input parameter is an array of NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO
+ *     structures containing information used for row remapping. Valid entries
+ *     are adjacent
+ *   validEntries
+ *     This input parameter specifies the number of valid entries in the
+ *     address array
+ *   numEntriesAdded
+ *     This output parameter specifies how many validEntries were successfully
+ *     added to the Inforom
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ */
+#define NV208F_CTRL_CMD_FB_REMAP_ROW                      (0x208f0512) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_REMAP_ROW_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_REMAP_ROW_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV208F_CTRL_FB_REMAP_ROW_PARAMS {
+    NV_DECLARE_ALIGNED(NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO addressList[NV208F_CTRL_FB_REMAPPED_ROWS_MAX_ROWS], 8);
+    NvU32 validEntries;
+    NvU32 numEntriesAdded;
+} NV208F_CTRL_FB_REMAP_ROW_PARAMS;
+
+
+#define NV208F_CTRL_CMD_FB_REVERSE_MAP_RBC_ADDR_TO_PA (0x208f0513) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 address, 8);
+    NvU32 rbcAddress;
+    NvU32 rbcAddressExt;
+    NvU32 rbcAddressExt2;
+    NvU32 partition;
+    NvU32 sublocation;
+} NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS;
+
+/**
+ * NV208F_CTRL_CMD_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF
+ *
+ * This command will convert a physical address when ECC is on to the physical
+ * address when ECC is off or vice versa
+ *
+ * @params[in] NvU64 inputAddress
+ *     Input physical address
+ *
+ * @params[in] NvBool eccOn
+ *     Whether or not input physical address is with ECC on or off
+ *
+ * @params[out] NvU64 outputAddress
+ *     Output physical address
+ */
+#define NV208F_CTRL_CMD_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF (0x208f0514) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 inputAddress, 8);
+    NvBool eccOn;
+    NV_DECLARE_ALIGNED(NvU64 outputAddress, 8);
+} NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_FB_CLEAR_REMAPPED_ROWS
+ *
+ * This command clears remapping entries from the Inforom's row remapping table.
+ *
+ *   sourceMask
+ *     This is a bit mask of NV2080_CTRL_FB_REMAPPED_ROW_SOURCE. Rows
+ *     remapped from the specified sources will be cleared/removed from the
+ *     Inforom RRL object entries list.
+ *
+ *   Possbile status values returned are:
+ *     NV_OK
+ *     NV_ERR_NOT_SUPPORTED
+ */
+#define NV208F_CTRL_CMD_FB_CLEAR_REMAPPED_ROWS (0x208f0515) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS {
+    NvU32 sourceMask;
+} NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK
+ *
+ * This command calculates the floorswept fbpa mask by taking 1/2 HBM
+ * floorsweeping into account
+ *
+ *   fbpaMask
+ *     This value of the mask.
+ *
+ *   Possbile status values returned are:
+ *     NV_OK
+ *     NV_ERR_NOT_SUPPORTED
+ */
+#define NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK (0x208f0516) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS {
+    NvU32 fbpaMask;
+} NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS;
+
+/* _ctrl208ffb_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h
new file mode 100644
index 0000000..a523160
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h
@@ -0,0 +1,249 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208ffbio.finn
+//
+
+#include "ctrl/ctrl208f/ctrl208fbase.h"
+
+/*
+ * NV208F_CTRL_CMD_FBIO_SETUP_TRAINING_EXP
+ *
+ * This command defines an fbio training experiment for later use.
+ *
+ * This command has the form of a 'cmd' operation descriminant
+ * followed by a union populated with an operand to match the 'cmd'.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_COMMAND
+ *
+ */
+#define NV208F_CTRL_CMD_FBIO_SETUP_TRAINING_EXP                     (0x208f0a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_NULL
+ * 
+ * This command has no effect when used.
+ */
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_NULL                    0
+
+/*
+ * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS
+ *
+ * This command defines the number of register modification slots to be used
+ * in the setup phase of the pass/fail training exercise.  Using this cmd
+ * causes any previously defined modification table to be cleared/released.
+ * The maximum size of the table is defined by
+ *     _SETUP_FBIO_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS__MAX
+ * Using the value of zero for number of mod slots is valid.  "Mod slots"
+ * are defined below.
+ *
+ * Possible status values returned are:
+ *   NV_ERR_INVALID_LIMIT
+ *     if modSlots is > __MAX
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ *     if we're out of memory setting up the mod slot table
+ */
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS 1
+typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS {
+    NvU32 modSlots;
+} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS;
+
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS__MAX 256
+
+/*
+ * NV208F_CTRL_FBIO_SETUPFBIO_TRAINING_EXP_SET_MOD_SLOT
+ *
+ * This command is used to define each individual element of the the sequence
+ * of operations which will be performed before running the pass/fail training
+ * exercise.  Note that this cmd is multi-cmd (with a null cmd all its own,
+ * etc).
+ *
+ * Possible status values returned are:
+ *   NV_ERR_INVALID_INDEX
+ *     if seq is out of range for previously set SET_NUMBER_OF_MOD_SLOTS
+ *     operation.
+ *   NV_ERR_INVALID_COMMAND
+ *     if cmd isn't recognized
+ */
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT                 2
+
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_NULL            0
+
+/*
+ * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER
+ *
+ * This cmd is used to define a register transaction to be applied in
+ * sequence before running the pass/fail experiment.  This is where
+ * NV_PFB_TRAINING_ADR, NV_PFB_TRAINING_CMD, NV_PFB_TRAINING_DP(i),
+ * NV_PFB_TRAINING_THRESHOLD and NV_PFB_TRAINING_MASK, etc. should be 
+ * configured before calling back with cmd
+ * NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP.
+ *
+ *   reg
+ *     This parameter specifies the BAR0 register offset to affect.
+ *   andMask
+ *   orMask
+ *     These parameter specify the RMW values to be used in the following:
+ *       write32(reg, (read32(reg) & andMask) | orMask)
+ */
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER    1
+typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS {
+    NvU32 reg;
+    NvU32 andMask;
+    NvU32 orMask;
+} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS;
+
+/*
+ * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY
+ *
+ * This cmd is used to define a delay to be applied in the setup sequence
+ * before running the pass/fail experiment.
+ *
+ *  usec
+ *    Specifies delay to be used in microseconds.
+ */
+
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY 2
+typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS {
+    NvU32 usec;
+} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS;
+
+/*
+ * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_INIT_LT
+ *
+ * This cmd is used to define a point where normal link training initialization
+ * may be executed in the sequence before running the pass/fail experiment.  
+ * In general, this is not needed since it is done during normal
+ * initialization, but does allow re-initialization during the sequence.
+ */
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_INIT_LT  3
+
+/*
+ * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_RUN_LT
+ *
+ * This cmd is used to define a point where normal link training may be
+ * executed in the sequence before running the pass/fail experiment.
+ * In general, this is not needed since it is somewhat redundant.
+ */
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_RUN_LT   4
+
+/*
+ * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_STOP_SEQ
+ *
+ * This cmd is used to define a point where the sequence stops without
+ * running the pass/fail experiment.  
+ */
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_STOP_SEQ 5
+
+
+
+typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS {
+    NvU32 cmd;
+    /* C form: NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_OPERANDS op; */
+    union {
+
+        NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS setRegister;
+
+        NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS        delay;
+    } op;
+    NvU32 seq;
+} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS;
+
+
+
+#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS {
+    NvU32 cmd;
+
+    /* C form: NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_OPERANDS op; */
+    union {
+
+        NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS setNumberOfModSlots;
+
+        NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS              setModSlot;
+    } op;
+} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP
+ *
+ * This command runs the previously defined experiment and returns status on
+ * pass/fail.  NV_OK is returned in the case of both pass
+ * and fail.
+ *
+ * The risingPasses and fallingPasses outputs represents the results across
+ * all partitions and bytelanes.  Each array entry corresponds to a partition
+ * and the bits within each member represent the bytelane.  So e.g.:
+ * risingPasses[4] represents the rising pass results for all of partition 4's
+ * byte lanes.
+ *
+ * The partitionsValid bitmask represents the partitions for which the results
+ * in risingPasses and fallingPasses are valid (not floorswept).
+ *
+ * The bytelanesValid bitmask represents the bytelanes for which the results
+ * are valid (available bytelanes).
+ *
+ * The failingDebug[] represent debug data for why (if so) a test fails.
+ * This is basically NV_PFB_TRAINING_DEBUG(i)
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_TIMEOUT
+ *       if hardware doesn't respond to request in a timely manner.
+ *   NV_ERR_INVALID_DATA
+ *       if there was some sort of very weird data corruption issue.
+ */
+#define NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP          (0x208f0a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE 8
+#define NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS {NvU32 risingPasses[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE];
+    NvU32 fallingPasses[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE];
+    NvU32 failingDebug[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE];
+    NvU32 partitionsValid;
+    NvU32 bytelanesValid;
+} NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS;
+
+#define NV208F_CTRL_CMD_FBIO_GET_TRAINING_CAPS (0x208f0a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS {
+    NvU32 supported;
+} NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS;
+
+// _ctrl208ffbio_h_
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h
new file mode 100644
index 0000000..dba64cd
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h
@@ -0,0 +1,159 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208ffifo.finn
+//
+
+#include "ctrl/ctrl208f/ctrl208fbase.h"
+
+/*
+ * NV208F_CTRL_CMD_FIFO_CHECK_ENGINE_CONTEXT
+ *
+ * This command checks whether or not engine context exists for a given
+ * engine for the channel with a given channel ID. This API is intended
+ * for testing virtual context. For debug only.
+ *
+ *   hChannel
+ *     The handle to the channel.
+ *   engine
+ *     The engine ID.
+ *     Valid values are:
+ *        NV2080_ENGINE_TYPE_GRAPHICS
+ *   exists
+ *     The output are TRUE or FALSE.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_CHANNEL
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV208F_CTRL_CMD_FIFO_CHECK_ENGINE_CONTEXT (0x208f0401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS {
+    NvHandle hChannel;
+    NvU32    engine;
+    NvBool   exists;
+} NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_FIFO_ENABLE_VIRTUAL_CONTEXT
+ *
+ * This command enables virtual context for a given channel (for all engines).
+ * This API is intended for testing virtual context. For debug only.
+ *
+ *   hChannel
+ *     The handle to the channel.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_CHANNEL
+ */
+#define NV208F_CTRL_CMD_FIFO_ENABLE_VIRTUAL_CONTEXT (0x208f0402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS {
+    NvHandle hChannel;
+} NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_FIFO_GET_CHANNEL_STATE
+ *
+ * This command returns the fifo channel state for the given channel.
+ * This is for testing channel behavior.  For debug only.
+ *
+ *   hChannel 
+ *    The handle to the channel
+ *   hClient 
+ *    The handle to the client
+ *   bound
+ *      The channel has been bound to channel RAM
+ *   enabled
+ *      The channel is able to run.
+ *   scheduled
+ *      The channel has been scheduled to run.
+ *   cpuMap
+ *      There is a cpu mapping available to this channel.
+ *   contention
+ *      The virtual channel is under contention
+ *   runlistSet
+ *      A runlist has been chosen for this channel
+ *   deferRC
+ *      An RC error has occurred, but recovery will occur at channel teardown.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_CHANNEL
+ */
+#define NV208F_CTRL_CMD_FIFO_GET_CHANNEL_STATE (0x208f0403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS {
+    NvHandle hChannel;
+    NvHandle hClient;
+    NvBool   bBound;
+    NvBool   bEnabled;
+    NvBool   bScheduled;
+    NvBool   bCpuMap;
+    NvBool   bContention;
+    NvBool   bRunlistSet;
+    NvBool   bDeferRC;
+} NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_FIFO_GET_CONTIG_RUNLIST_POOL
+ *
+ * This command returns the location of the pool runlists are allocated from for
+ * WPR testing.
+ * For debug only.
+ *
+ * physAddr [out]
+ *    Physical address of the pool
+ *
+ * size [out]
+ *    Size in bytes of the pool
+ *
+ */
+#define NV208F_CTRL_CMD_FIFO_GET_CONTIG_RUNLIST_POOL (0x208f0404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+} NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS;
+
+/* _ctrl208ffifo_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h
new file mode 100644
index 0000000..d473f11
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h
@@ -0,0 +1,161 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2009-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fgpu.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080gr.h"        /* 208F is partially derivative of 2080 */
+#include "ctrl/ctrl208f/ctrl208fbase.h"
+
+/*
+ * NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES
+ *
+ * This command can be used to get the RAM SVOP values.
+ *
+ *    sp
+ *     This field outputs RAM_SVOP_SP
+ *    rg
+ *     This field outputs RAM_SVOP_REG
+ *    pdp
+ *     This field outputs RAM_SVOP_PDP
+ *    dp
+ *     This field outputs RAM_SVOP_DP
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES (0x208f1101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x1" */
+
+typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS {
+    NvU32 sp;
+    NvU32 rg;
+    NvU32 pdp;
+    NvU32 dp;
+} NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES
+ *
+ * This command can be used to set the RAM SVOP values.
+ *
+ *    sp
+ *     Input for RAM_SVOP_SP
+ *    rg
+ *     Input for RAM_SVOP_REG
+ *    pdp
+ *     Input for RAM_SVOP_PDP
+ *    dp
+ *     Input for RAM_SVOP_DP
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES     (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x2" */
+
+
+
+/*
+ * NV208F_CTRL_CMD_GPU_VERIFY_INFOROM
+ *
+ * This command can be used by clients to determine if an InfoROM
+ * with a valid image is present. If the SKU in question does
+ * not feature an InfoROM, the NV_ERR_NOT_SUPPORTED
+ * error is returned. Else the RM attempts to read the ROM object
+ * and any objects listed in the ROM object. The checksum of
+ * each object read is verified. If all checksums are valid, the
+ * RM will report the InfoROM as being valid. If image is valid then
+ * RM will return a checksum for all of the dynamically configurable
+ * data in InfoROM. This checksum is expected to be same for all the
+ * boards with an identical InfoROM version and similarly configured.
+ *
+ * result
+ *    The result of the InfoROM verification attempt. Possible
+ *    values are:
+ *      NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_NONE
+ *         This value indicates that a validation couldn't be done
+ *         due to some software/OS related error.
+ *      NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_IO_ERROR
+ *         This value indicates that a validation couldn't be done
+ *         due to some IO error.
+ *      NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_VALID
+ *         This value indicates that all InfoROM objects have valid
+ *         checksum.
+ *      NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_INVALID
+ *         This value indicates that some InfoROM objects have invalid
+ *         checksum.
+ * checksum
+ *    Checksum for all of the dynamically configurable data
+ *    in InfoROM for e.g. PWR and CFG objects.
+ *
+ * NOTE: For the result values to be valid, return status should be:
+ *   NV_OK
+ *
+ * Possible return status values:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV208F_CTRL_CMD_GPU_VERIFY_INFOROM (0x208f1105) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS {
+    NvU32 result;
+    NvU32 checksum;
+} NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS;
+
+/* valid result values */
+#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_NONE     (0x00000000)
+#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_IO_ERROR (0x00000001)
+#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_VALID    (0x00000002)
+#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_INVALID  (0x00000003)
+
+/*
+ * NV208F_CTRL_CMD_GPU_DISABLE_ECC_INFOROM_REPORTING
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+
+
+#define NV208F_CTRL_CMD_GPU_DISABLE_ECC_INFOROM_REPORTING    (0x208f1107) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x7" */
+
+
+
+/* _ctrl208fgpu_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h
new file mode 100644
index 0000000..357ac1f
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h
@@ -0,0 +1,109 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fgr.finn
+//
+
+#include "ctrl/ctrl208f/ctrl208fbase.h"
+
+#include "ctrl/ctrl2080/ctrl2080gr.h"
+
+
+
+/*
+ * NV208F_CTRL_CMD_GR_ECC_INJECT_ERROR
+ *
+ * Control command to inject a gr ecc error
+ *
+ * Parameters:
+ *
+ * location
+ *   location index
+ * sublocation
+ *   sublocation index
+ * unit
+ *   unit to inject error into
+ * errorType
+ *   SBE or DBE
+ * grRouteInfo
+ *   Routing info for SMC
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV208F_CTRL_CMD_GR_ECC_INJECT_ERROR (0x208f1203) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS {
+    NvU32 location;
+    NvU32 sublocation;
+    NvU8  unit;
+    NvU8  errorType;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS;
+
+
+
+/*
+ * NV208F_CTRL_CMD_GR_ECC_INJECTION_SUPPORTED
+ *
+ * Reports if error injection is supported for a given HW unit
+ *
+ * unit [in]:
+ *      The ECC protected unit for which ECC injection support is being checked.
+ *
+ * bCorrectableSupported [out]:
+ *      Boolean value that shows if correcatable errors can be injected.
+ *
+ * bUncorrectableSupported [out]:
+ *      Boolean value that shows if uncorrecatable errors can be injected.
+ *
+ * Return values:
+ *      NV_OK on success
+ *      NV_ERR_INVALID_ARGUMENT if the requested unit is invalid.
+ *      NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled.
+ *      NV_ERR_NOT_SUPPORTED otherwise
+ *
+ *
+ */
+#define NV208F_CTRL_CMD_GR_ECC_INJECTION_SUPPORTED   (0x208f1204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS {
+    NvU8   unit;
+    NvBool bCorrectableSupported;
+    NvBool bUncorrectableSupported;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS;
+
+/* _ctrl208fgr_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h
new file mode 100644
index 0000000..2b298e6
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h
@@ -0,0 +1,128 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fmmu.finn
+//
+
+#include "ctrl/ctrl208f/ctrl208fbase.h"
+
+/*
+ * NV208F_CTRL_CMD_MMU_ECC_INJECT_ERROR
+ *
+ * This ctrl call injects MMU ECC errors.  Please see the confluence
+ * page "ECC" for more information on ECC and ECC injection:
+ *
+ * Parameters:
+ *
+ * location
+ *   Only used for HSHUBMMU.
+ *
+ * sublocation
+ *   Only used for HSHUBMMU.
+ *
+ * unit
+ *   Specifies the MMU HW unit where the injection will occur.
+ *
+ * errorType
+ *   Specifies whether the injected error will be correctable or uncorrectable.
+ *   Correctable errors have no effect on running programs while uncorrectable
+ *   errors will cause all channels to be torn down.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV208F_CTRL_CMD_MMU_ECC_INJECT_ERROR (0x208f0b01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS {
+    NvU32 location;
+    NvU32 sublocation;
+    NvU8  unit;
+    NvU8  errorType;
+} NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS;
+
+
+
+/*
+ * NV208F_CTRL_CMD_MMU_ECC_INJECTION_SUPPORTED
+ *
+ * Reports if error injection is supported for a given HW unit
+ *
+ * unit [in]:
+ *      The ECC protected unit for which ECC injection support is being checked.
+ *
+ * bCorrectableSupported [out]:
+ *      Boolean value that shows if correcatable errors can be injected.
+ *
+ * bUncorrectableSupported [out]:
+ *      Boolean value that shows if uncorrecatable errors can be injected.
+ *
+ * Return values:
+ *      NV_OK on success
+ *      NV_ERR_INVALID_ARGUMENT if the requested location is invalid.
+ *      NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled.
+ *      NV_ERR_NOT_SUPPORTED otherwise
+ *
+ */
+#define NV208F_CTRL_CMD_MMU_ECC_INJECTION_SUPPORTED                 (0x208f0b02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */
+
+
+
+#define NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS {
+    NvU8   unit;
+    NvBool bCorrectableSupported;
+    NvBool bUncorrectableSupported;
+} NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS;
+
+/*
+ * NV208F_CTRL_CMD_MMU_GET_NUM_HSHUBMMUS
+ *
+ * Returns the number of ECC Capable HSHUBMMUS.
+ *
+ * numHshubmmus [out]
+ *   Number of Hshubmmus
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV208F_CTRL_CMD_MMU_GET_NUM_HSHUBMMUS (0x208f0b03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS_MESSAGE_ID" */
+
+#define NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS {
+    NvU32 numHshubmmus;
+} NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS;
+
+/* _ctrl208fmmu_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h
new file mode 100644
index 0000000..d7ea299
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fpmgr.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h
new file mode 100644
index 0000000..e225c7b
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl208f/ctrl208fpower.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl30f1.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl30f1.h
new file mode 100644
index 0000000..fdfa8fb
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl30f1.h
@@ -0,0 +1,1493 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl30f1.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV30_GSYNC_CTRL control commands and parameters */
+
+#define NV30F1_CTRL_CMD(cat,idx)             NVXXXX_CTRL_CMD(0x30F1, NV30F1_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NV30F1_CTRL_RESERVED (0x00)
+#define NV30F1_CTRL_GSYNC    (0x01)
+
+/*
+ * NV30F1_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV30F1_CTRL_CMD_NULL (0x30f10000) /* finn: Evaluated from "(FINN_NV30_GSYNC_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/* NV30F1_CTRL_GSYNC 
+ *
+ * Gsync board access/control functionality.
+ *
+ */
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_GET_VERSION
+ *
+ * This command will get the current gsync api version info.
+ *
+ * version
+ *   The api's major version. Does not change often.
+ * 
+ * revision
+ *   The api's minor version.
+ *   Bumped with each change, no matter how minor.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *
+ */
+#define NV30F1_CTRL_CMD_GSYNC_GET_VERSION (0x30f10101) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS {
+    NvU32 version;
+    NvU32 revision;
+} NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS;
+
+#define NV30F1_CTRL_GSYNC_API_VER                1
+#define NV30F1_CTRL_GSYNC_API_REV                0
+
+/*
+ * NV30F1_CTRL_GSYNC api
+ *
+ * The gsync interface provides access to gsync devices in the system.
+ *
+ * There are  commands:
+ *   NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS 
+ *     Status on input sync signals.
+ *   NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS
+ *     Get gsync parameters.
+ *   NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS
+ *     Get gsync parameters.
+ *   NV30F1_CTRL_CMD_GSYNC_GET_INFO_CAPS
+ *     Get basic info about the device and its connected displays
+ *   NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC
+ *     Enable frame sync.
+ *   NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC
+ *     Disable frame sync.
+ *   NV30F1_CTRL_CMD_GSYNC_GET_STATUS
+ *     Get status info relevant for the control panel
+ *   NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING
+ *     Test signal enabling/disabling
+ *   NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG
+ *     Control the gsync watchdog
+ *   NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE
+ *     Set the interlace mode
+ * 
+ */
+
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS
+ *
+ * This command returns information associated with incoming signals to the
+ * gsync device.
+ *
+ * RJ45
+ *   This parameter contains the signal information for each of the two RJ45
+ *   ports on the gsync device. A value of ~0 indicates that a signal is 
+ *   detected, but no rate information is available. Anything else is a rate 
+ *   in units of 10e-4 Hz.
+ * house
+ *   This parameter contains the signal information for the house sync signal
+ *   (i.e. the bnc port). A value of 0 means that no signal is present. A value
+ *   of ~0 indicates that a signal is detected, but no rate information is 
+ *   available. Anything else is a rate in units of 10e-4 Hz.
+ * rate
+ *   A mask representing signals for which we would like rate information (if 
+ *   available).
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   
+ */
+
+#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS (0x30f10102) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS {
+    NvU32 RJ45[2];
+    NvU32 house;
+    NvU32 rate;
+} NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS;
+
+/*
+ * rate values 
+ *
+ */
+
+#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_0 (0x00000001)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_1 (0x00000002)
+#define NV30F1_CTRL_GSYNC_GET_SIGNALS_HOUSE         (0x00000004)
+
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS
+ * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS
+ *
+ * These commands respectively return and set state related to the operation
+ * of the gsync device.
+ *
+ * which
+ *   This value is a mask set by the client representing which parameters are 
+ *   to be updated. In the case of a GET command, these parameters will
+ *   be used to change the state of the hardware. For both a GET
+ *   command and a SET command, the hardware state will be returned by
+ *   the RM in the respective parameter. All other parameters are untouched.
+ * syncPolarity
+ *   This parameter specifies which edge of the house sync signal to sync with.
+ * videoMode
+ *   This parameter specifies which video mode to use to decode the house sync
+ *   signal.
+ * nSync
+ *   This parameter specifies the number of pulses to wait between frame lock
+ *   signal generation. 0 indicates that every incomming pulse should result in
+ *   a frame lock sync pulse being generated (i.e. the input and output rate 
+ *   matches).
+ * syncSkew
+ *   This parameter specifies the time delay between the frame sync signal and
+ *   the GPUs signal in units of 0.977 us. Maximum value for SyncSkew is defined
+ *   in respective header files of gsync boards. e.g. For P2060 board value
+ *   is defined in drivers/resman/kernel/inc/dacp2060.h
+ * syncStartDelay
+ *   In master mode, the amount of time to wait before generating the first
+ *   sync pulse in units of 7.81 us, max 512 ms (i.e 65535 units).
+ * useHouseSync
+ *   When a house sync signal is detected, this parameter indicates that it 
+ *   should be used as the reference to generate the frame sync signal.
+ *   
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_GENERIC
+ */
+
+#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS    (0x30f10103) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS    (0x30f10104) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS {
+    NvU32 which;
+    NvU32 syncPolarity;
+    NvU32 syncVideoMode;
+    NvU32 nSync;
+    NvU32 syncSkew;
+    NvU32 syncStartDelay;
+    NvU32 useHouseSync;
+} NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS;
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS;
+
+/*
+ * which values
+ *
+ */
+
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY              0x0001
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE                 0x0002
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC                      0x0004
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW                  0x0008
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY           0x0010
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE             0x0020
+
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY              NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE                 NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC                      NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW                  NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY           NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE             NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE
+
+/* 
+ * syncPolarity values
+ *
+ */
+
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE  0
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES   2
+
+/*
+ * syncVideoMode values
+ * Video_Mode_Composite is valid for P2060 only.
+ *
+ */
+
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE            0
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL             1
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM    2
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV            3
+
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE            NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL             NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM    NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV            NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE       4
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_GET_CAPS
+ *
+ * This command returns the capabilities of this gsync device.
+ *
+ * revId
+ *  This parameter is set by the RM to indicate the combined 
+ *  FPGA revision (low 4 bits) and board ID (high 4 bits).
+ * 
+ * boardId
+ *  This parameter is set by the RM to indicate the board ID,
+ *  allowing disambiguation of P2060 and so forth.
+ *
+ * minRevRequired
+ *  This parameter is set by the RM to indicate the minimum
+ *  Qsync FPGA revision required for a specific CHIP Familiy
+ *
+ * isFirmwareRevMismatch
+ * This parameter is set to TRUE by RM when the Qsync Firmware
+ * Revision is incompatibled with the connected GPU chip family.
+ *
+ * revision
+ *  This parameter is set by the RM to indicate the device revision,
+ *  also known as major version.
+ *
+ * extendedRevision
+ *  This parameter is set by the RM to indicate the device extended
+ *  revision, also known as minor version.
+ *
+ * capFlags
+ *  This parameter is set by the RM to indicate capabilities of
+ *  the board, preventing the client from needing to keep track
+ *  of the feature lists supported by each revision of each board.
+ *
+ * maxSyncSkew
+ *  This parameter returns that maximum units of sync skew the 
+ *  board supports. The value prgrammed into the board has to be
+ *  between 0 and maxSyncSkew, inclusive. The value of each unit
+ *  can be learned from the syncSkewResolution parameter.
+ * 
+ * syncSkewResolution
+ *  This parameter returns the number of nanoseconds that one unit
+ *  of sync skew corresponds to.
+ *
+ * maxStartDelay
+ *  This parameter returns that maximum units of sync start delay
+ *  the board supports. The value prgrammed into the board has to be
+ *  between 0 and maxStartDelay, inclusive. The value of each unit
+ *  can be learned from the startDelayResolution parameter.
+ * 
+ * startDelayResolution
+ *  This parameter returns the number of nanoseconds that one unit
+ *  of sync start delay corresponds to.
+ *
+ * maxSyncInterval
+ *  This parameter returns the maximum duration of house sync interval
+ *  between frame lock sync cycle that the board supports. The value
+ *  programmed into the board has to be between 0 and maxSyncInterval,
+ *  inclusive.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS                           (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS {
+    NvU32  revId;
+    NvU32  boardId;
+    NvU32  minRevRequired;
+    NvBool isFirmwareRevMismatch;
+    NvU32  revision;
+    NvU32  extendedRevision;
+    NvU32  capFlags;
+    NvU32  maxSyncSkew;
+    NvU32  syncSkewResolution;
+    NvU32  maxStartDelay;
+    NvU32  startDelayResolution;
+    NvU32  maxSyncInterval;
+} NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS;
+
+#define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060                         (0x00002060)
+#define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2061                         (0x00002061)
+
+#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_2DPS           (0x00000001)
+#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_3DPS           (0x00000002)
+#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_4DPS           (0x00000004)
+
+#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR      (0x00000010)
+
+#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_SYNC_LOCK_EVENT              (0x10000000)
+#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_HOUSE_SYNC_EVENT             (0x20000000)
+#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FRAME_COUNT_EVENT            (0x40000000)
+
+#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_PRIMARY_CONNECTOR_EVENT (0x01000000)
+#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ALL_CONNECTOR_EVENT          (0x02000000)
+
+// For P2060, clients can only request for video modes at BNC connector
+// e.g. NO HS, TTL and Composite etc.
+#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_GET_VIDEO_MODE          (0x00100000)
+
+/*
+ * NV30F1_CTRL_CMD_GET_GSYNC_GPU_TOPOLOGY
+ * 
+ * This command returns the list of GPU IDs connected with the associated
+ * gsync device.
+ *
+ * gpus
+ *   This array is set by RM to contain the gpu connection information
+ *   for gpus attached to the gsync device. Valid entries are contiguous,
+ *   beginning with the first entry in the list. The elements of this array contain
+ *   the following fields:
+ *   gpuId
+ *     This field contains the ID of the connected GPU. If the entry in the 
+ *     table is invalid, this fields contains  NV30F1_CTRL_GPU_INVALID_ID.
+ *   connector
+ *     This field indicates which connector on the device the GPU is connected
+ *     to (i.e. the primary or secondary connector), if any.
+ *   proxyGpuId
+ *     If the 'connector' field indicates that the GPU is not connected to
+ *     a G-Sync device directly, then this field contains the ID of the
+ *     GPU that acts as a proxy, i.e. the GPU to which this GPU should be
+ *     a RasterLock slave.
+ * connectorCount
+ *    This parameter indicates the number of GPU connectors available on
+ *    the gsync device.  The connector count of the gsync device may be
+ *    less than NV30F1_CTRL_MAX_GPUS_PER_GSYNC.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV30F1_CTRL_CMD_GET_GSYNC_GPU_TOPOLOGY                            (0x30f10106) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_MAX_GPUS_PER_GSYNC                                    4
+#define NV30F1_CTRL_GPU_INVALID_ID                                        (0xffffffff)
+
+#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS {
+    struct {
+        NvU32 gpuId;
+        NvU32 connector;
+        NvU32 proxyGpuId;
+    } gpus[NV30F1_CTRL_MAX_GPUS_PER_GSYNC];
+    NvU32 connectorCount;
+} NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS;
+
+/*
+ * connector values
+ *
+ */
+#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE                                           1
+#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_TWO                                           2
+#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_THREE                                         3
+#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_FOUR                                          4
+
+#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_NONE                                          0
+#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PRIMARY                                       NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE
+#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_SECONDARY                                     NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_TWO
+
+
+
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC
+ *
+ * This command enables frame sync on displays.
+ *
+ * gpuId
+ *   The parameter is set by the client to indicate the gpuId on which
+ *   frame lock will be enabled.
+ * master
+ *   This parameter is set by the client to specify whether this/these 
+ *   displays should be set as the master or as slaves. If this is a GET
+ *   and displays is not 0, this will be set by the RM to indicate if
+ *   the display can be the master.
+ * displays
+ *   This is a device mask set by the client to indicate which display(s)
+ *   are to be synched. Note that only one display may be set as master.
+ *   If this is a GET, this set by the client to indicate which display
+ *   is to be queried. If the display cannot be synched to this device, 
+ *   the RM will overwrite the mask with a 0.
+ * validateExternal
+ *   This parameter is set by the client to tell the RM to validate the
+ *   presence of an external sync source when enabling a master.
+ * refresh
+ *   This parameter is set by the client to indicate the desired refresh rate
+ *   The value is in 0.0001 Hertz (i.e. it has been multiplied by 10000).
+ * configFlags
+ *   contains flags for specific options. So far only 
+ *   NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED
+ *   is supported which allows the caller to prevent the rm code to automatically
+ *   enable the swapbarrier on framelock masters on fpga revisions <= 5.
+ * 
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ * 
+ */
+#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SYNC                                           (0x30f10110) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC                                           (0x30f10111) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID" */
+
+// If set the swapbarrier is not enable automatically when enablign a framelock master on fpga revs <= 5.
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED (0x00000001)
+
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS {
+    NvU32 gpuId;
+    NvU32 master;
+    NvU32 displays;
+    NvU32 validateExternal;
+    NvU32 refresh;
+    NvU32 configFlags;
+} NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS;
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x11U)
+
+typedef NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS;
+
+/* 
+ * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC
+ *
+ * This command disables frame sync on displays
+ *
+ * gpuId
+ *   The parameter is set by the client to indicate the gpuId on which
+ *   frame lock will be disabled.
+ * master
+ *   This parameter is set by the client to specify whether this/these
+ *   display(s) to be unset is a master/are slaves.
+ * displays
+ *   This is a device mask set by the client to indicate which display(s)
+ *   are to be unsynched.
+ * retainMaster
+ *   Retain the designation as master, but unsync the displays. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC (0x30f10112) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS {
+    NvU32 gpuId;
+    NvU32 master;
+    NvU32 displays;
+    NvU32 retainMaster;
+} NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS;
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC
+ *
+ * This command gets the sync state for the gpus attached to the
+ * framelock device. Note that the frame lock device only has
+ * knowledge of sync status at the gpu level, not the display
+ * device level.
+ *
+ * gpuId
+ *   The parameter is set by the client to indicate which gpuId is to be
+ *   queried.
+ * bTiming
+ *   This parameter is set by the RM to indicate that timing on the GPU is
+ *   in sync with the master sync signal.
+ * bStereoSync 
+ *   This parameter is set by the RM to indicate whether the phase of the
+ *   timing signal coming from the GPU is the same as the phase of the 
+ *   master sync signal.
+ * bSyncReady
+ *   This parameter is set by the RM to indicate if a sync signal has
+ *   been detected.
+ * 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+
+#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC (0x30f10113) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS {
+    NvU32 gpuId;
+    NvU32 bTiming;
+    NvU32 bStereoSync;
+    NvU32 bSyncReady;
+} NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS;
+
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_GET_STATUS
+ *
+ * This command gets status information for the frame lock device 
+ * relevant to a control panel.
+ *
+ * which
+ *   This is a mask set by the client describing which of the other 
+ *   parameters we should collect status information for.
+ * bLeadingEdge
+ *   This parameter is set by the RM to indicate that the gsync device is
+ *   set to sync to the leading edge of a house sync signal. Note that
+ *   this does not mean that house sync is the signal source.
+ * bFallingEdge
+ *   This parameter is set by the RM to indicate that the gsync device is
+ *   set to sync to the falling edge of a house sync signal. Note that
+ *   this does not mean that house sync is the signal source.
+ * syncDelay
+ *   This parameter is set by the RM to indicate the sync delay in 
+ *   microseconds,
+ * refresh
+ *   This parameter is set by the RM to indicate the rate of frame sync pulse in
+ *   0.0001 Hertz (i.e. it has been multiplied by 10000). This is not the refresh
+ *   rate of display device. This is same as incoming house sync rate if
+ *   framelocked to an external house sync signal. Otherwise, this is same
+ *   as the refresh rate of the master display device.
+ * houseSyncIncomming
+ *   This parameter is set by the RM to indicate the rate of an incomming 
+ *   house sync signal in 0.0001 Hertz (i.e. it has been multiplied by 10000).
+ * syncInterval
+ *   This parameter is set by the RM to indicate the number of incoming 
+ *   sync pulses to wait before the generation of the frame sync pulse.
+ * bSyncReady
+ *   This paramater is set by the RM to indicate if a sync signal has 
+ *   been detected (this parameter is also available from the 
+ *   NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC method).
+ * bSwapReady
+ *   This paramater is set by the RM to indicate if the hardware is 
+ *   ready to swap. 
+ * bHouseSync
+ *   This parameter is set by the RM to indicate that a house sync signal
+ *   should be used as the source signal if it is available.
+ * bPort0Input
+ *   This parameter is set by the RM to indicate that RJ45 port 0 is 
+ *   configured as an input.
+ * bPort1Input
+ *   This parameter is set by the RM to indicate that RJ45 port 1 is
+ *   configured as an input
+ * bPort0Ehternet
+ *   This parameter is set by the RM to indicate that RJ45 port 0 has
+ *   been connected to an ethernet hub (this is not the right thing to do).
+ * bPort1Ehternet
+ *   This parameter is set by the RM to indicate that RJ45 port 1 has
+ *   been connected to an ethernet hub (this is not the right thing to do).
+ * universalFrameCount
+ *   This parameter is set by the RM to indicate the value of the 
+ *   Universal frame counter.
+ * bInternalSlave
+ *   This parameter is set by the RM to indicate that a p2061 has been
+ *   configured as internal slave.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS (0x30f10114) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS {
+    NvU32 which;
+    NvU32 bLeadingEdge;
+    NvU32 bFallingEdge;
+    NvU32 syncDelay;
+    NvU32 refresh;
+    NvU32 houseSyncIncoming;
+    NvU32 syncInterval;
+    NvU32 bSyncReady;
+    NvU32 bSwapReady;
+    NvU32 bHouseSync;
+    NvU32 bPort0Input;
+    NvU32 bPort1Input;
+    NvU32 bPort0Ethernet;
+    NvU32 bPort1Ethernet;
+    NvU32 universalFrameCount;
+    NvU32 bInternalSlave;
+} NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS;
+
+/*
+ * which values
+ *
+ */
+
+#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_POLARITY         (0x00000001)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_LEADING_EDGE          (0x00000001)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_FALLING_EDGE          (0x00000001)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_DELAY            (0x00000002)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_REFRESH               (0x00000004)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC_INCOMING   (0x00000008)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_INTERVAL         (0x00000010)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_READY            (0x00000020)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_SWAP_READY            (0x00000040)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_TIMING                (0x00000080)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_STEREO_SYNC           (0x00000100)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC            (0x00000200)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT_INPUT            (0x00000400)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT0_INPUT           (0x00000400)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT1_INPUT           (0x00000400)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT_ETHERNET         (0x00000800)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT0_ETHERNET        (0x00000800)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT1_ETHERNET        (0x00000800)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_UNIVERSAL_FRAME_COUNT (0x00001000)
+#define NV30F1_CTRL_GSYNC_GET_STATUS_INTERNAL_SLAVE        (0x00002000)
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING
+ *
+ * This command controls the test signal on the gsync device.
+ *
+ * bEmitTestSignal
+ *   This parameter is set by the client to emit or stop emitting the test
+ *   signal.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_TESTING          (0x30f10120) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING          (0x30f10121) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS {
+    NvU32 bEmitTestSignal;
+} NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS;
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x20U)
+
+typedef NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS;
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG
+ *
+ * This command enables and disables the gsync watchdog
+ *
+ * enable
+ *   This parameter is set by the client to enable or disable the
+ *   gsync watchdog.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG (0x30f10130) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS_MESSAGE_ID (0x30U)
+
+typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS {
+    NvU32 enable;
+} NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS;
+
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE
+ *
+ * This command enables or disables interlace mode.
+ *
+ * enable
+ *   This parameter is set by the client to enable or disable
+ *   interlace mode
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_INTERLACE_MODE (0x30f10140) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE (0x30f10141) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U)
+
+typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS {
+    NvU32 enable;
+} NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS;
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x40U)
+
+typedef NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS;
+
+/*
+ *
+ * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_BARRIER
+ * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER
+ *
+ * These commands enables or disables the swap barrier
+ * connection between a GPU and the rest of the gsync
+ * network
+ *
+ * gpuId
+ *   The parameter is set by the client to indicate which gpuId is to be
+ *   queried.
+ * enable
+ *   In a set command, this parameter is set by the client to 
+ *   indicate if the barrier should be enabled (i.e. connected 
+ *   to the rest of the network) or disabled (disconnected).
+ *   In both a set and a get command, if successful, the RM
+ *   uses this parameter to return the current (i.e. post-set)
+ *   value.
+ *   
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_BARRIER (0x30f10150) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER (0x30f10151) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U)
+
+typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS {
+    NvU32  gpuId;
+    NvBool enable;
+} NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS;
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x50U)
+
+typedef NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS;
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW
+ *
+ * This command allow clients to obtain time period for which SwapLock window will
+ * remain HIGH for GSYNC III (P2060) i.e. TswapRdyHi. RM clients will use this value
+ * for programming SWAP_LOCKOUT_START on all heads of GPU connected to P2060.
+ *
+ * tSwapRdyHi
+ *   RM will return swap lock window High time period in this variable. By default
+ *   tSwapRdyHi is 250 micro seconds. RM also provide regkey to change this value.
+ *   tSwapRdyHi also used by RM to configure value of LSR_MIN_TIME while programming
+ *   swap barrier.
+ *   Client should consider tSwapRdyHi only for Gsync III (P2060) network.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ */
+#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW (0x30f10153) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS_MESSAGE_ID (0x53U)
+
+typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS {
+    NvU32 tSwapRdyHi;
+} NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS;
+
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING
+ *
+ * This command allows the client to obtain suggested
+ * adjustments to vertical and horizontal timing values
+ * that will improve the ability of gsync to lock.
+ *
+ * gpuId
+ *   This parameter is set by the client to indicate the 
+ *   gpuId of the GPU to which the display to be optimized
+ *   is attached.
+ * display
+ *   This parameter is not used by RM currently.
+ *   Clients can ignore this parameter.  Note that this
+ *   parameter will be removed in future.
+ * output
+ *   This parameter is set by the client to indicate the 
+ *   output resource type of the display to be optimized.
+ *   For example, CRTs use DAC output, while DFPs use SOR
+ *   (Serial Output Resource) type.
+ * protocol
+ *   This parameter is set by the client to indicate the 
+ *   data protocol of output resource.  For DAC displays,
+ *   the format of the standard mode most closely matching
+ *   the desired mode is used.  For SOR display devices,
+ *   the LVDS/TMDS/etc format is the protocol.
+ * structure
+ *   This parameter is set by the client to indicate the 
+ *   raster structure of the mode, either progressive or
+ *   interlaced.  Diagrams of the raster structures are
+ *   provided below.
+ * adjust
+ *   This parameter is set by the client to specify which
+ *   of the timing values, other than hTotal and vTotal,
+ *   may be adjusted during optimization.
+ *   If the client does not obtain instructions from the
+ *   user about where adjustments should be applied, safe
+ *   default values for progressive/interlaced modes are
+ *   provided below.
+ * hTotal
+ *   This parameter is set by the client to specify the
+ *   initial Horizontal Pixel Total, from which the
+ *   RM will begin optimizing.  The RM also uses the 
+ *   parameter to return the optimized value.
+ * vTotal
+ *   This parameter is set by the client to specify the
+ *   initial Vertical Pixel Total, from which the
+ *   RM will begin optimizing.  The RM also uses the 
+ *   parameter to return the optimized value.
+ * hBlankStart
+ *   This parameter is set by the client to specify the
+ *   initial Horizontal Blanking Start, from which the
+ *   RM will begin optimizing.  The RM also uses the 
+ *   parameter to return the optimized value.
+ * vBlankStart
+ *   This parameter is set by the client to specify the
+ *   initial Vertical Blanking Start, from which the
+ *   RM will begin optimizing.  The RM also uses the 
+ *   parameter to return the optimized value.
+ * hBlankEnd
+ *   This parameter is set by the client to specify the
+ *   initial Horizontal Blanking End, from which the
+ *   RM will begin optimizing.  The RM also uses the 
+ *   parameter to return the optimized value.
+ * vBlankEnd
+ *   This parameter is set by the client to specify the
+ *   initial Vertical Blanking End, from which the
+ *   RM will begin optimizing.  The RM also uses the 
+ *   parameter to return the optimized value.
+ * vInterlacedBlankStart
+ *   This parameter is set by the client to specify the
+ *   initial Interlaced Vertical Blanking Start, from 
+ *   which the RM will begin optimizing.  The RM will
+ *   ignore this parameter for non-interlaced modes, as
+ *   it has no meaning in those modes.  In modes where
+ *   it is meaningful, the RM also uses the parameter
+ *   to return the optimized value. 
+ * vInterlacedBlankEnd
+ *   This parameter is set by the client to specify the
+ *   initial Interlaced Vertical Blanking End, from 
+ *   which the RM will begin optimizing.  The RM will
+ *   ignore this parameter for non-interlaced modes, as
+ *   it has no meaning in those modes.  In modes where
+ *   it is meaningful, the RM also uses the parameter 
+ *   to return the optimized value.
+ * hSyncEnd
+ *   This parameter is set by the client to specify the
+ *   initial Horizontal Raster Sync End, from which the
+ *   RM will begin optimizing.  The RM also uses the 
+ *   parameter to return the optimized value.
+ * vSyncEnd
+ *   This parameter is set by the client to specify the
+ *   initial Vertical Raster Sync End, from which the
+ *   RM will begin optimizing.  The RM also uses the 
+ *   parameter to return the optimized value.
+ * hDeltaStep
+ *   This parameter is set by the client to specify the
+ *   increments by which the Horizontal Pixel Total may
+ *   be adjusted by the RM, during optimization.
+ *   If the client does not obtain a custom value for  
+ *   this parameter from the user, setting all four of
+ *   hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax
+ *   to zero will result in a safe default for all four.
+ * vDeltaStep
+ *   This parameter is set by the client to specify the
+ *   increments by which the vertical timings of each 
+ *   frame (in interlaced modes, each field) may be 
+ *   adjusted by the RM, during optimization.
+ *   In interlaced modes, the adjustments to vTotal,
+ *   vInterlacedBlankStart, and vInterlacedBlankEnd may
+ *   be in increments of vDeltaStep or twice vDeltaStep, 
+ *   depending on where adjustments are made.
+ *   In progressive modes, the adjustment to the vTotal
+ *   will simply be in increments of vDeltaStep.
+ *   If the client does not obtain a custom value for  
+ *   this parameter from the user, setting all four of
+ *   hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax
+ *   to zero will result in a safe default for all four.
+ * hDeltaMax
+ *   This parameter is set by the client to specify the
+ *   maximum amount that the Horizontal Pixel Total may
+ *   be adjusted by the RM, during optimization.
+ *   If the client does not obtain a custom value for  
+ *   this parameter from the user, setting all four of
+ *   hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax
+ *   to zero will result in a safe default for all four.
+ * vDeltaMax
+ *   This parameter is set by the client to specify the
+ *   maximum amount that vertical timings of each frame
+ *   (in interlaced modes, each field) may be adjusted
+ *   by the RM, during optimization.
+ *   In interlaced modes, the adjustments to vTotal,
+ *   vInterlacedBlankStart, and vInterlacedBlankEnd may
+ *   be up to twice vDeltaMax.
+ *   In progressive modes, the adjustment to the vTotal
+ *   may simply be up to vDeltaMax.
+ *   If the client does not obtain a custom value for  
+ *   this parameter from the user, setting all four of
+ *   hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax
+ *   to zero will result in a safe default for all four.
+ * refreshX10K
+ *   This parameter is set by the client to specify the
+ *   desired refresh rate, multiplied by 10000.  This 
+ *   allows refresh rate to be set in units of 0.0001 Hz. 
+ *   For example, a 59.94 Hz rate would be set as 599400.
+ *   The client can alternatively specify a the 
+ *   pixelClockHz parameter (if the passed in refreshX10K
+ *   parameter is set to 0, the pixelClockHz parameter
+ *   will be used).
+ * pixelClockHz
+ *   This parameter is set by the client to specify the
+ *   desired pixel clock frequency in units of Hz. The 
+ *   client can alternatively specify the refreshX10K parameter.
+ *   This parameter is returned by the RM to report the
+ *   optimal pixel clock to use with the adjusted mode, 
+ *   in units of Hz. 
+ *
+ * Progressive Raster Structure
+ *
+ *                 hSyncEnd                            hTotal
+ *             0   |   hBlankEnd              hBlankStart   |
+ *             |   |   |                                |   |    vSync vBlank
+ *          0--+--------------------------------------------+     +-+     | 
+ *             |     Sync                                   |       |     | 
+ *   vSyncEnd--|   +----------------------------------------+     +-+     | 
+ *             |   |     Back Porch                         |     |       |
+ *  vBlankEnd--|   |   +--------------------------------+   |     |     +-+ 
+ *             |   |   |     Active Area                |   |     |     | 
+ *             |   |   |   +------------------------+   |   |     |     | 
+ *             |   |   |   |                        |   |   |     |     | 
+ *             | S | B | A |                        | A | F |     |     | 
+ *             | y | a | c |                        | c | r |     |     | 
+ *             | n | c | t |                        | t | o |     |     | 
+ *             | c | k | i |                        | i | n |     |     | 
+ *             |   |   | v |                        | v | t |     |     | 
+ *             |   | P | e |     Output Viewport    | e |   |     |     | 
+ *             |   | o |   |                        |   | P |     |     | 
+ *             |   | r | A |                        | A | o |     |     | 
+ *             |   | c | r |                        | r | r |     |     | 
+ *             |   | h | e |                        | e | c |     |     | 
+ *             |   |   | a |                        | a | h |     |     | 
+ *             |   |   |   |                        |   |   |     |     | 
+ *             |   |   |   +------------------------+   |   |     |     | 
+ *             |   |   |     Active Area                |   |     |     | 
+ * vBlankStart-|   |   +--------------------------------+   |     |     +-+ 
+ *             |   |     Front Porch                        |     |       | 
+ *     vTotal--+---+----------------------------------------+     +-+     | 
+ *              ___
+ *             /   \________________________________________/ hSync
+ *             ________                                  ____
+ *                     \________________________________/     hBlank
+ *
+ *
+ *
+ * Interlaced Raster Structure
+ *
+ *                 hSyncEnd                            hTotal
+ *             0   |   hBlankEnd              hBlankStart   |
+ *             |   |   |                                |   |    vSync vBlank
+ *          0--+--------------------------------------------+     +-+     | 
+ *             |     Sync                                   |       |     | 
+ *   vSyncEnd--|   +----------------------------------------+     +-+     | 
+ *             |   |     Back Porch                         |     |       |
+ *  vBlankEnd--|   |   +--------------------------------+   |     |     +-+ 
+ *             |   |   |     Active Area                |   |     |     | 
+ *             |   |   |   +------------------------+   |   |     |     | 
+ *             |   |   |   |                        |   |   |     |     | 
+ *             | S | B | A |                        | A | F |     |     | 
+ *             | y | a | c |                        | c | r |     |     | 
+ *             | n | c | t |                        | t | o |     |     | 
+ *             | c | k | i |                        | i | n |     |     | 
+ *             |   |   | v |                        | v | t |     |     | 
+ *             |   | P | e |     Output Viewport    | e |   |     |     | 
+ *             |   | o |   |                        |   | P |     |     | 
+ *             |   | r | A |                        | A | o |     |     | 
+ *             |   | c | r |                        | r | r |     |     | 
+ *             |   | h | e |                        | e | c |     |     | 
+ *             |   |   | a |                        | a | h |     |     | 
+ *             |   |   |   |                        |   |   |     |     | 
+ *             |   |   |   +------------------------+   |   |     |     | 
+ *             |   |   |     Active Area                |   |     |     | 
+ * vBlankStart-|   |   +--------------------------------+   |     |     +-+ 
+ *             |   |                                        |     |       | 
+ *             |   |     Front Porch   +--------------------+     |       | 
+ *             |   |                   |                    |     +-+     | 
+ *             |   +-------------------+                    |       |     | 
+ *             |                                            |       |     | 
+ *             |     Sync              +--------------------+       |     | 
+ *             |                       |                    |     +-+     | 
+ *             |   +-------------------+                    |     |       |
+ * vInterlaced |   |     Back Porch                         |     |       | 
+ *   BlankEnd--|   |   +--------------------------------+   |     |     +-+ 
+ *             |   |   |     Active Area                |   |     |     | 
+ *             |   |   |   +------------------------+   |   |     |     | 
+ *             |   |   |   |                        |   |   |     |     | 
+ *             | S | B | A |                        | A | F |     |     | 
+ *             | y | a | c |                        | c | r |     |     | 
+ *             | n | c | t |                        | t | o |     |     | 
+ *             | c | k | i |                        | i | n |     |     | 
+ *             |   |   | v |                        | v | t |     |     | 
+ *             |   | P | e |     Output Viewport    | e |   |     |     | 
+ *             |   | o |   |                        |   | P |     |     | 
+ *             |   | r | A |                        | A | o |     |     | 
+ *             |   | c | r |                        | r | r |     |     | 
+ *             |   | h | e |                        | e | c |     |     | 
+ *             |   |   | a |                        | a | h |     |     | 
+ *             |   |   |   |                        |   |   |     |     | 
+ *             |   |   |   +------------------------+   |   |     |     | 
+ * vInterlaced |   |   |     Active Area                |   |     |     | 
+ *  BlankStart-|   |   +--------------------------------+   |     |     +-+
+ *             |   |     Front Porch                        |     |       |
+ *     vTotal--+---+----------------------------------------+     +-+     |
+ *              ___
+ *             /   \________________________________________/ hSync
+ *             ________                                  ____
+ *                     \________________________________/     hBlank
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+*/
+
+#define NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING (0x30f10160) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID (0x60U)
+
+typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS {
+    NvU32 gpuId;
+    NvU32 display;
+    NvU32 output;
+    NvU32 protocol;
+    NvU32 structure;
+    NvU32 adjust;
+    NvU32 hDeltaStep;
+    NvU32 hDeltaMax;
+    NvU32 vDeltaStep;
+    NvU32 vDeltaMax;
+    NvU32 hSyncEnd;
+    NvU32 hBlankEnd;
+    NvU32 hBlankStart;
+    NvU32 hTotal;
+    NvU32 vSyncEnd;
+    NvU32 vBlankEnd;
+    NvU32 vBlankStart;
+    NvU32 vInterlacedBlankEnd;
+    NvU32 vInterlacedBlankStart;
+    NvU32 vTotal;
+    NvU32 refreshX10K;
+    NvU32 pixelClockHz;
+} NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS;
+
+/* output values */
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_OUTPUT_DAC        (0x00000001)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_OUTPUT_SOR        (0x00000004)
+
+/* protocol values for DAC displays (e.g. CRTs) */
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_DAC_RGB_CRT       (0x00000000)
+
+/* protocol values for SOR displays (e.g. DFPs) */
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_LVDS_CUSTOM   (0x00000000)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DUAL_TMDS     (0x00000005)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DP_A          (0x00000008)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DP_B          (0x00000009)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_HDMI_FRL      (0x0000000C)
+
+/* structure values */
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_STRUCTURE_PROGRESSIVE      (0x00000000)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_STRUCTURE_INTERLACED       (0x00000001)
+
+/* adjust values */
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_FRONT_PORCH       (0x00000001)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_FRONT_PORCH       (0x00000002)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_ACTIVE_AREA       (0x00000004)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_ACTIVE_AREA       (0x00000008)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_BACK_PORCH        (0x00000010)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_BACK_PORCH        (0x00000020)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_RASTER_SYNC       (0x00000040)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_RASTER_SYNC       (0x00000080)
+
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_DEFAULT_CRT         (0x00000030)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_DEFAULT_DFP         (0x00000020)
+
+/* DeltaStep and DeltaMax values to trigger default settings */
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_H_DELTA_STEP_USE_DEFAULTS  (0x00000000)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_H_DELTA_MAX_USE_DEFAULTS   (0x00000000)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_V_DELTA_STEP_USE_DEFAULTS  (0x00000000)
+#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_V_DELTA_MAX_USE_DEFAULTS   (0x00000000)
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_SET_EVENT_NOTIFICATION
+ *
+ * This command sets event notification state for the associated Gsync
+ * object.  This command requires that an instance of NV01_EVENT has
+ * been previously bound to the associated Gsync object.  
+ * 
+ * If one or more of the "smart event notification" options are set in the
+ * action parameter, multiple sequential events of the same type will only 
+ * trigger one notification.  After that, only an event of a different type
+ * will trigger a new notification.
+ *
+ *   action
+ *     This member specifies the desired event notification action.
+ *     Valid notification actions include:
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE
+ *       This action disables event notification for the associated
+ *       Gsync object.
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS
+ *       This action enables smart event notification for the
+ *       associated Gsync object, for "sync loss" events.
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN
+ *       This action enables smart event notification for the
+ *       associated Gsync object, for "sync gained" events.
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS
+ *       This action enables smart event notification for the
+ *       associated Gsync object, for "stereo lost" events.
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN
+ *       This action enables smart event notification for the
+ *       associated Gsync object, for "stereo gained" events.
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN
+ *       This action enables smart event notification for the
+ *       associated Gsync object, for "house sync (BNC) plug in" events.
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS
+ *       This action enables smart event notification for the
+ *       associated Gsync object, for "house sync (BNC) plug out" events.
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN
+ *       This action enables smart event notification for the
+ *       associated Gsync object, for "ethernet (RJ45) plug in" events.
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS
+ *       This action enables smart event notification for the
+ *       associated Gsync object, for "ethernet (RJ45) plug out" events.
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_COUNT_MATCH
+ *       This action enables smart event notification for the
+ *       associated Gsync object, for "frame counter match" events.
+ *     NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL
+ *       This action enables smart event notification for the
+ *       associated Gsync object, for any type of event.
+ * 
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV30F1_CTRL_CMD_GSYNC_SET_EVENT_NOTIFICATION                      (0x30f10170) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS_MESSAGE_ID (0x70U)
+
+typedef struct NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS {
+    NvU32 action;
+} NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS;
+
+/* valid action values */
+
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE           (0x00000000)
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS   (0x00000001)
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN   (0x00000002)
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS (0x00000004)
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN (0x00000008)
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN  (0x00000010)
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS  (0x00000020)
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN   (0x00000040)
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS   (0x00000080)
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_COUNT_MATCH (0x00000100)
+#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL         (0x000001FF)
+
+#define NV30F1_CTRL_GSYNC_EVENT_TYPES                                     9
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE
+ * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE
+ *
+ * These commands can be used to get/set the stereo lock assistance mode of
+ * the GSYNC device. This is supported by GSYNC III device only.
+ * 1] In this mode the GSYNC recreates the hidden VS either by ->
+ *    (a) using local stereo edge if stereo is toggle or
+ *    (b) counting lines and generate the missing VS.
+ * 2] Master GSYNC card recreates the stereo and passes it along to
+ *    the slave GSYNC cards.
+ * 3] Slave GSYNC cards generates the stereo raster sync structure to
+ *    synchronize the GPU.
+ * 4] For stereo sync status reporting, under this mode, the GSYNC automatically
+ *    reports stereo lock whenever it gets the master stereo signal. The
+ *    assumption is local stereo will be in synced with the new structure.
+ * 5] If the slave GSYNC card does not observed master stereo for any reason,
+ *    (a) it clears the stereo sync bit and
+ *    (b) it generates its own version of stereo and sync the GPU.
+ *
+ * Parameters:
+ *   gpuId
+ *     This parameter is set by the client to indicate the gpuId on which
+ *     the stereo lock mode should be enabled/disabled.
+ *
+ *   enable
+ *     In SET query, this parameter is set by the client to indicate whether
+ *     RM should enable or disable stereo lock mode for GPU specified in gpuId.
+ *     1 and 0 indicates enable and disable stereo lock mode respectively. In
+ *     GET query, RM will set this parameter to 1 or 0 depending on StereoLock
+ *     mode is enabled or not respectively for specified GPU.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE                (0x30f10172) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE                (0x30f10173) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U)
+
+typedef struct NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS {
+    NvU32 gpuId;
+    NvU32 enable;
+} NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS;
+#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x73U)
+
+typedef NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS;
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_READ_REGISTER
+ *
+ * This command is used to read raw i2c registers from the gsync device, via
+ * the given GPU (registers on the same gsync device may have different values
+ * depending on which GPU is used to do the read).
+ *
+ * This may only be used by a privileged client.
+ *
+ * Parameters:
+ *   gpuId
+ *     This parameter is set by the client to specify which GPU to use to
+ *     perform the read.
+ *
+ *   reg
+ *     This parameter is set by the client to specify which i2c register to
+ *     read.
+ *
+ *   data
+ *     This parameter is written by the RM and returned to the client upon a
+ *     successful read.
+ *
+ *  Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ */
+#define NV30F1_CTRL_CMD_GSYNC_READ_REGISTER (0x30f10180) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS_MESSAGE_ID (0x80U)
+
+typedef struct NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS {
+    NvU32 gpuId;
+    NvU8  reg;
+    NvU8  data;
+} NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS;
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_WRITE_REGISTER
+ *
+ * This command is used to write raw i2c registers on the gsync device, via the
+ * given GPU (registers on the same gsync device may have different values
+ * depending on which GPU is used to do the write).
+ *
+ * This may only be used by a privileged client.
+ *
+ * Parameters:
+ *   gpuId
+ *     This parameter is set by the client to specify which GPU to use to
+ *     perform the write.
+ *
+ *   reg
+ *     This parameter is set by the client to specify which i2c register to
+ *     write.
+ *
+ *   data
+ *     This parameter is set by the client to specify what data to write to the
+ *     given i2c register.
+ *
+ *  Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ */
+
+#define NV30F1_CTRL_CMD_GSYNC_WRITE_REGISTER (0x30f10181) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS_MESSAGE_ID (0x81U)
+
+typedef struct NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS {
+    NvU32 gpuId;
+    NvU8  reg;
+    NvU8  data;
+} NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS;
+
+
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_SET_LOCAL_SYNC
+ *
+ * This command enables/disables raster sync on displays i.e. 
+ * mosaic groups between gpus.
+ *
+ * gpuTimingSource
+ *   The parameter is set by the client to indicate the gpuId of the
+ *   Timing Source gpu for specified mosaic group.
+ * gpuTimingSlaves[]
+ *   This parameter is set by the client to indicate the gpuIds of the
+ *   timing slave gpus for specified mosaic group. It should not contain
+ *   more gpuids than slaveGpuCount.
+ * slaveGpuCount
+ *   This parameter is set by the client to indicate the count of timing
+ *   slave gpus under specified group.
+ *   Referring to gsync3-P2060, slaveGpuCount can vary from 0x01 to 0x03
+ *   as maximum possible connected gpus are four and one gpu must be
+ *   timing master for mosaic group.
+ * mosaicGroupNumber
+ *   This parameter is set by the client to tell the RM to which mosaic
+ *   group it should refer.
+ *   Referring to gsync3-P2060, mosaicGroupNumber can contain 0x00 or
+ *   0x01 as only two mosaic groups are possible.
+ * enableMosaic
+ *   This parameter is set by the client to indicate RM that whether RM
+ *   should enable mosaic or disable mosaic.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ * 
+ */
+#define NV30F1_CTRL_CMD_GSYNC_SET_LOCAL_SYNC (0x30f10185) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS_MESSAGE_ID (0x85U)
+
+typedef struct NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS {
+    NvU32  gpuTimingSource;
+    NvU32  gpuTimingSlaves[NV30F1_CTRL_MAX_GPUS_PER_GSYNC];
+    NvU32  slaveGpuCount;
+    NvU32  mosaicGroupNumber;
+    NvBool enableMosaic;
+} NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS;
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH
+ *
+ * This command configure GSYNC registers for pre-flash and post-flash
+ * operations. This is currenly used for GSYNC-3 (P2060) only. RM clients
+ * has to make sure that they perform both pre-flash and post-flash
+ * operations on GSYNC board. Avoiding, post-flash will cause mismatch
+ * between RM cached-data and GSYNC register values.
+ *
+ * Parameters:
+ *   gpuId
+ *     This parameter is set by the client to indicate the gpuId for which
+ *     GSYNC board connected to that GPU will be configured for pre-flash
+ *     or post-flash operation depending on preFlash value.
+ *
+ *   preFlash
+ *     This parameter is set by the client to indicate whether RM has to configure
+ *     GSYNC registers and SW state for pre-flash or post-flash operation. Values
+ *     1 and 0 indicates that RM will configure GSYNC board for pre-flash and
+ *     post-flash operations respectively.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH (0x30f10186) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS_MESSAGE_ID" */
+
+#define NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS_MESSAGE_ID (0x86U)
+
+typedef struct NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS {
+    NvU32 gpuId;
+    NvU32 preFlash;
+} NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS;
+
+/*
+ * NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE
+ * NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE
+ *
+ * These two commands gets/sets house sync mode as input or output.
+ *
+ * Parameters:
+ *   houseSyncMode
+ *     This parameter indicates whether the house sync mode is input or
+ *     output. For GET_HOUSE_SYNC_MODE, the current mode will be written 
+ *     by RM and returned to the client; for SET_HOUSE_SYNC_MODE, the client
+ *     will write the new mode value to this parameter and pass it to RM
+ *     for execution.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_STATE
+ *
+ */
+#define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x87" */
+
+#define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x88" */
+
+typedef struct NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS {
+    NvU8 houseSyncMode;
+} NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS;
+
+
+#define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_INPUT  (0x00)
+#define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_OUTPUT (0x01)
+
+/* _ctrl30f1_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl402c.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl402c.h
new file mode 100644
index 0000000..eb9bef5
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl402c.h
@@ -0,0 +1,971 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl402c.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV40_I2C control commands and parameters */
+#define NV402C_CTRL_CMD(cat,idx) \
+                                NVXXXX_CTRL_CMD(0x402C, NV402C_CTRL_##cat, idx)
+
+/* I2C command categories (6 bits) */
+#define NV402C_CTRL_RESERVED                              (0x00)
+#define NV402C_CTRL_I2C                                   (0x01)
+
+
+/* This field specifies the maximum regular port identifier allowed. */
+#define NV402C_CTRL_NUM_I2C_PORTS                         16
+/* This temporary field specifies the dynamic port identifier. */
+#define NV402C_CTRL_DYNAMIC_PORT                          NV_U8_MAX
+
+/*
+ * NV402C_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *     NV_OK
+ */
+#define NV402C_CTRL_CMD_NULL                              (0x402c0000) /* finn: Evaluated from "(FINN_NV40_I2C_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+/*
+ * NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED
+ *   The port exists on this hardware.
+ * NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED
+ *   The port has an entry in the DCB.
+ * NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL
+ *   The port is used to read EDIDs via DDC.
+ * NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED
+ *   The port is accessible via the CRTC register space.
+ * NV402C_CTRL_I2C_GET_PORT_INFO_VALID
+ *   The port is validated using I2C device.
+ */
+#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED                          0:0
+#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED_NO      0x00
+#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED_YES     0x01
+#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED                         1:1
+#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED_NO     0x00
+#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED_YES    0x01
+#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL                          2:2
+#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL_ABSENT  0x00
+#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL_PRESENT 0x01
+#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED                          3:3
+#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED_NO      0x00
+#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED_YES     0x01
+#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID                                4:4
+#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID_NO            0x00
+#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID_YES           0x01
+#define NV402C_CTRL_I2C_GET_PORT_INFO_ALL                                  4:0
+#define NV402C_CTRL_I2C_GET_PORT_INFO_ALL_DEFAULT         0x00
+
+/*
+ * NV402C_CTRL_CMD_I2C_GET_PORT_INFO
+ *
+ * Returns information for the first eight I2C ports.
+ *
+ *   info
+ *     This parameter is an output from the command and is ignored as an
+ *     input.  Each element contains the flags described previously named
+ *     NV402C_CTRL_I2C_GET_PORT_INFO*.  Note that the index into the info
+ *     array is one less than the port identifier that would be returned from
+ *     NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID; the port numbers here are
+ *     0-indexed as opposed to 1-indexed.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+
+#define NV402C_CTRL_CMD_I2C_GET_PORT_INFO (0x402c0101) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS_MESSAGE_ID" */
+
+
+
+#define NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS {
+    NvU8 info[NV402C_CTRL_NUM_I2C_PORTS];
+} NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS;
+#define NV402C_CTRL_I2C_INDEX_LENGTH_MAX                                        4
+#define NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX                                      4096
+
+//! Minimum and maximum valid read/write message length for block process protocol.
+#define NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MIN                              3
+#define NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX                              32
+
+/*
+ * NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE
+ *   A client uses this field to indicate the I2C addressing mode to be
+ *   used.
+ *   Possible values are:
+ *     NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT
+ *       The default, this value specifies the master to operate in the
+ *       basic 7-bit addressing mode, which is available on all
+ *       implementations.
+ *     NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_10BIT
+ *       This I2C mode allows for 10 bits of addressing space and is
+ *       reverse compatible with 7-bit addressing.
+ */
+#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE                                 0:0
+#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT                                 (0x00000000)
+#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_10BIT                                (0x00000001)
+#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_DEFAULT                              NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT
+/*
+ * NV402C_CTRL_I2C_FLAGS_SPEED_MODE
+ *   A client uses this field to indicate the target speed at which the
+ *   I2C master should attempt to drive the bus.  The master may throttle
+ *   its own speed for various reasons, and devices may slow the bus
+ *   using clock-streching.  Neither of these possibilities are
+ *   considered failures.
+ */
+#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE                                   4:1
+#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_100KHZ                                 (0x00000000)
+#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_200KHZ                                 (0x00000001)
+#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_400KHZ                                 (0x00000002)
+#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_33KHZ                                  (0x00000003)
+#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_10KHZ                                  (0x00000004)
+#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_3KHZ                                   (0x00000005)
+#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_DEFAULT                                (0x00000006)
+#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_300KHZ                                 (0x00000007)
+
+
+/*
+ * NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE
+ *   A client uses this field to specify a transaction mode.
+ *   Possible values are:
+ *     NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL
+ *       The default, this value indicates to use the normal I2C transaction 
+ *       mode which will involve read/write operations depending on client's
+ *       needs. 
+ *     NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING
+ *       This value specifies that the device only needs to be pinged. No need
+ *       of performing a complete read/write transaction. This will send a
+ *       single byte to the device to be pinged. On receiving an ACK, we will
+ *       get a confirmation on the device's availability.
+ */
+#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE                          11:10
+#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL                           (0x00000000)
+#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING                             (0x00000001)
+#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_DEFAULT                          NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL
+/*!
+ * NV402C_CTRL_I2C_FLAGS_RESERVED
+ *   A client must leave this field as 0, as it is reserved for future use.
+ */
+#define NV402C_CTRL_I2C_FLAGS_RESERVED                                  31:12
+
+/*!
+ * The following defines specify WAR flags that can be specified during
+ * I2C Quick Read or Write command (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW).
+ *
+ * _NONE
+ *    No workaround is needed.
+ *
+ * _TEST_PORT
+ *     Use this flag to have the client sent a request to test a port instead 
+ *     of performing any transaction on it. Transaction type has to be 
+ *     NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW.
+ */
+#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS                                          0:0
+#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_NONE                           0x00000000
+#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_TEST_PORT                      0x00000001
+
+/*!
+ * The following defines specify WAR flags that can be specified during
+ * I2C Register Read or Write buffer command 
+ * (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW)
+ *
+ * _NONE
+ *    No workaround is needed.
+ *
+ * _SI1930
+ *     SI1930 microcontroller register read or write requested by a client. 
+ *     Transaction type has to be NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW.
+ *
+ * _PX3540
+ *     Register read from PX3540 or PX3544 device. Transaction type has to be 
+ *     NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW and bWrite must be TRUE to 
+ *     indicate READ operation 
+ */
+#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS                                               1:0
+#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_NONE                                0x00000000
+#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_SI1930                              0x00000001
+#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_PX3540                              0x00000002
+
+/*!
+ * The following defines specify WAR flags that can be specified during
+ * I2C buffer Read or Write to Multibyte Register 
+ * (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW)
+ *
+ * _NONE
+ *    No workaround is needed.
+ *
+ * _NO_AUTO_INC
+ *   This value specifies that the device does not support auto-increment.
+ *   Most devices allow you to write multiple bytes after specifying a
+ *   register address, and the subsequent bytes will go to incremented
+ *   addresses. Without auto-increment, we write a buffer of data as a
+ *   sequence of address-register-value triplets separated by starts.
+ */
+#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS                       0:0
+#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NONE        0x00000000
+#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NO_AUTO_INC 0x00000001
+
+/*
+ * NV402C_CTRL_CMD_I2C_SYNC
+ *
+ * Perform a basic I2C transaction synchronously.
+ *
+ *   portId
+ *     This field must be specified by the client to indicate the logical
+ *     port/bus for which the transaction is requested. The port identifier
+ *     is one less than the value returned by
+ *     NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID unless that value was 0 (the
+ *     'dynamic' port).  For the 'dynamic' port, this should be 0xFF.  Note
+ *     that future versions of the API may obsolete use of the 'dynamic' port;
+ *     please contact the RM if you begin using this portion of the API so we
+ *     can help you migrate when the time comes.
+ *
+ *   bIsWrite
+ *     This field must be specified by the client to indicate whether the
+ *     command is a write (TRUE) or a read (FALSE).
+ *
+ *   flags
+ *     This parameter specifies optional flags used to control certain modal
+ *     features such as target speed and addressing mode.  The currently
+ *     defined fields are described previously; see NV402C_I2C_FLAGS_*.
+ *
+ *   address
+ *     The address of the I2C slave.  The address should be shifted left by
+ *     one.  For example, the I2C address 0x50, often used for reading EDIDs,
+ *     would be stored here as 0xA0.  This matches the position within the
+ *     byte sent by the master, as the last bit is reserved to specify the
+ *     read or write direction.
+ *
+ *   indexLength
+ *     This required parameter specifies how many bytes to write as part of the
+ *     first index.  If zero is specified, then no index will be sent.
+ *
+ *   index
+ *     This parameter, required of the client if index is one or more,
+ *     specifies the index to be written.  The buffer should be arranged such
+ *     that index[0] will be the first byte sent.
+ *
+ *   messageLength
+ *     This parameter, required of the client, specifies the number of bytes to
+ *     read or write from the slave after the index is written.
+ *
+ *   pMessage
+ *     This parameter, required of the client, specifies the data to be written
+ *     to the slave.  The buffer should be arranged such that pMessage[0] will
+ *     be the first byte read or written.  If the transaction is a read, then
+ *     it will follow the combined format described in the I2C specification.
+ *     If the transaction is a write, the message will immediately follow the
+ *     index without a restart.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_GENERIC, if the I2C transaction fails.
+ */
+#define NV402C_CTRL_I2C_INDEXED_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV402C_CTRL_I2C_INDEXED_PARAMS {
+    NvU8  portId;
+    NvU8  bIsWrite;
+    NvU16 address;
+    NvU32 flags;
+
+    NvU32 indexLength;
+    NvU8  index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX];
+
+    NvU32 messageLength;
+    NV_DECLARE_ALIGNED(NvP64 pMessage, 8);
+} NV402C_CTRL_I2C_INDEXED_PARAMS;
+
+#define NV402C_CTRL_CMD_I2C_INDEXED (0x402c0102) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_INDEXED_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV402C_CTRL_CMD_I2C_GET_PORT_SPEED
+ *
+ * Returns information for the I2C ports.
+ *
+ *   portSpeed
+ *     This parameter is an output from the command and is ignored as an
+ *     input.  Each element contains the current I2C speed of the port.
+ *     Note that the index into the info array is one less than the 
+ *     port identifier that would be returned from
+ *     NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID; the port numbers here are
+ *     0-indexed as opposed to 1-indexed.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS {
+    NvU32 portSpeed[NV402C_CTRL_NUM_I2C_PORTS];
+} NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS;
+
+#define NV402C_CTRL_CMD_I2C_GET_PORT_SPEED (0x402c0103) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV402C_CTRL_I2C_DEVICE_INFO
+ *
+ * This structure describes the basic I2C Device information.
+ *
+ *   type
+ *     This field return the type of device NV_DCB4X_I2C_DEVICE_TYPE_<xyz>
+ *   i2cAddress
+ *     This field contains the 7 bit/10 bit address of the I2C device.
+ *   i2cLogicalPort
+ *     This field contains the Logical port of the I2C device.
+ */
+typedef struct NV402C_CTRL_I2C_DEVICE_INFO {
+    NvU8  type;
+    NvU16 i2cAddress;
+    NvU8  i2cLogicalPort;
+    NvU8  i2cDevIdx;
+} NV402C_CTRL_I2C_DEVICE_INFO;
+
+/* Maximum number of I2C devices in DCB */
+#define NV402C_CTRL_I2C_MAX_DEVICES 32
+
+/*
+ * NV402C_CTRL_CMD_I2C_TABLE_GET_DEV_INFO
+ *
+ * RM Control to get I2C device info from the DCB I2C Devices Table.
+ *
+ *   i2cDevCount
+ *     The value of this parameter will give the number of
+ *     I2C devices found in DCB.
+ * 
+ *   i2cDevInfo 
+ *     For each device found in DCB the control call will write the info 
+ *     in this parameter.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS {
+    NvU8                        i2cDevCount;
+    NV402C_CTRL_I2C_DEVICE_INFO i2cDevInfo[NV402C_CTRL_I2C_MAX_DEVICES];
+} NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS;
+
+#define NV402C_CTRL_CMD_I2C_TABLE_GET_DEV_INFO (0x402c0104) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS_MESSAGE_ID" */
+
+/*!
+ * The IDs of each type of I2C command available.
+ */
+typedef enum NV402C_CTRL_I2C_TRANSACTION_TYPE {
+   /*!
+    * This transaction type is used to perform the Quick SMBus Read/write command 
+    * on a slave device. No data is sent or received, just used to verify the 
+    * presence of the device.
+    * Refer SMBus spec 2.0 (section 5.5.1 Quick Command)
+    * SMBus Quick Write : S Addr|Wr [A] P
+    * SMBus Quick Read  : S Addr|Rd [A] P
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW = 0,
+   /*!
+    * This transaction type is used to perform the I2C byte read/write from/to 
+    * a slave device. As per the spec last byte should be NA (Not Acknolwedged) 
+    * by slave.
+    * Refer I2CBus spec 3.0 (section 9 Fig 11 and Fig 12) or Refer SMBus spec 
+    * 2.0 (section 5.5.2 Send Byte and 5.5.3 Receive Byte).
+    * I2C Byte Write : S Addr|Wr [A] Data [NA] P
+    * I2C Byte Read  : S Addr|Rd [A] Data NA P
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW = 1,
+   /*!
+    * This transaction type is used to perform the I2C block (buffer) 
+    * read/write from/to a slave device. As per the spec last byte should be NA
+    * (Not Acknolwedged) by slave.
+    * Refer I2CBus spec 3.0 (section 9 Fig 11 and Fig 12)
+    * I2C Byte Write : S Addr|Wr [A] Data1 [A]...Data(N-1) [A] DataN [NA] P
+    * I2C Byte Read  : S Addr|Rd [A] Data1 A...Data(N-1) A DataN NA P
+    *
+    * Distinction between I2C_BLOCK and SMBUS_BLOCK protocol:
+    * In I2C Block write it is the slave device (and in I2C Block read it's 
+    * the master device) that determines the number of bytes to transfer by 
+    * asserting the NAK at last bit before stop. This differs from the SMBus 
+    * block mode write command in which the master determines the block 
+    * write transfer size. In I2c Block read there is no limit to maximum size 
+    * of data that could be transferred whereas in SMBus block it is restricted
+    * to 255 bytes (0xFF).
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW = 2,
+   /*!
+    * This transaction type is used to perform the I2C Buffer read/write 
+    * from/to a register of a slave device. It does not send bytecount as 
+    * part of data buffer.
+    * Not a part of SMBus spec.
+    * I2C Buffer Write : S Addr|Wr [A] cmd [A] Data1 [A]...DataN[A] P
+    * I2C Buffer Read  : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] Data1 A...
+    *                    DataN-1 A DataN A P
+    *
+    * Distinction between SMBUS_BLOCK and I2C_BUFFER protocol:
+    * In SMBUS_BLOCK Read/write the first byte of data buffer contains the 
+    * count size (The number of bytes to be transferred) and it is restricted 
+    * to 255 bytes whereas in I2C_BUFFER, count size is not sent during the 
+    * transfer and there is no restriction in terms of size.
+    *
+    * Distinction between I2C_BLOCK and I2C_BUFFER protocol:
+    * I2C_BUFFER takes the register address as argument whereas I2C_BLOCK does
+    * not have any register or command provision.
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW = 3,
+   /*!
+    * This transaction type is used to perform the I2C byte read/write from/to
+    * a slave device
+    * Refer SMBus spec 2.0 (section 5.5.4 Write Byte and 5.5.5 Read Byte)
+    * SMBus Byte Write : S Addr|Wr [A] cmd [A] Data [A] P
+    * SMBus Byte Read  : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] Data A P
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW = 4,
+   /*!
+    * This transaction type is used to perform the SMBus byte read/write 
+    * from/to a register of a slave device
+    * Refer SMBus spec 2.0 (section 5.5.4 Write Word and 5.5.5 Read Word)
+    * SMBus Word Write : S Addr|Wr [A] cmd [A] DataLow [A] DataHigh [A] P 
+    * SMBus Word Read  : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] DataLow A 
+    *                    DataHigh A P
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW = 5,
+   /*!
+    * This transaction type is used to perform the SMBus Block read/write 
+    * from/to a register of a slave device
+    * Refer SMBus spec 2.0 (section 5.5.7 Block Write/Read)
+    * SMBus Block Write : S Addr|Wr [A] cmd [A] ByteCount [A] Data1 [A]...
+    *                     DataN-1 [A] DataN[A] P
+    * SMBus Block Read  : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] ByteCount A 
+    *                     Data1 A...DataN-1 A DataN A P
+    *
+    * Distinction between I2C_BLOCK and SMBUS_BLOCK protocol:
+    * In I2C Block write it is the slave device (and in I2C Block read it's 
+    * the master device) that determines the number of bytes to transfer by 
+    * asserting the NAK at last bit before stop. This differs from the SMBus 
+    * block mode write/Read command in which the master determines the block 
+    * write transfer size. In I2c Block read/Write there is no limit to maximum
+    * size of data that could be transferred whereas in SMBus block it is 
+    * restricted to 255 bytes (0xFF).
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW = 6,
+   /*!
+    * This transaction type is used to perform the SMBus process call. It sends
+    * data and waits for the slave to return a value dependent on that data. 
+    * The protocol is simply a SMBus write Word followed by a SMBus Read Word 
+    * without the Read-Word command field and the Write-Word STOP bit. 
+    * Note that there is no STOP condition before the repeated START condition,
+    * and that a NACK signifies the end of the read transfer. 
+    *
+    * Refer SMBus spec 2.0 (section 5.5.6 Process Call)
+    * SMBus Process Call : S Addr|Wr [A] cmd [A] DataLow [A] DataHigh [A] 
+    *                      Sr Addr|Rd [A] DataLow [A] DataHigh [NA] P
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL = 7,
+   /*!
+    * This transaction type is used to perform the SMBus Block Write Block Read
+    * process call.
+    * The block write-block read process call is a two-part message. The call 
+    * begins with a slave address and a write condition. After the command code
+    * the host issues a write byte count (M) that describes how many more bytes
+    * will be written in the first part of the message.
+    * If a master has 6 bytes to send, the byte count field will have the value
+    * 6 (0000 0110b), followed by the 6 bytes of data. The write byte count (M)
+    * cannot be zero. 
+    * The second part of the message is a block of read data beginning with a 
+    * repeated start condition followed by the slave address and a Read bit.
+    * The next byte is the read byte count (N), which may differ from the write
+    * byte count (M). The read byte count (N) cannot be zero. The combined data
+    * payload must not exceed 32 bytes. 
+    * The byte length restrictions of this process call are summarized as 
+    * follows:
+    * M >= 1 byte 
+    * N >= 1 byte 
+    * M + N <= 32 bytes 
+    * Note that there is no STOP condition before the repeated START condition, 
+    * and that a NACK signifies the end of the read transfer.
+    *
+    * Refer SMBus spec 2.0 (section 5.5.8 Block Write Block Read Process Call)
+    * SMBus Process Call : S Addr|Wr [A] cmd [A] ByteCount=M [A] Data1 [A]...
+    *                      DataN-1 [A] DataM[A] Sr Addr|Rd [A] ByteCount=N [A] 
+    *                      Data1 [A]...DataN [NA] P
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL = 8,
+   /*!
+    * This transaction type is used to perform SMBus buffer read/write 
+    * from/to multiple registers of a slave device known as Auto Increment.
+    * It is not a part of any standard I2C/SMBus spec but a feature of many
+    * SMBus devices like EEPROM.
+    * It is also used for reading a block of bytes from a designated register 
+    * that is specified through the two Comm bytes.of a slave device or writing
+    * a block of bytes from a designated register of a slave device (Note : The
+    * command byte in this case could be 0, 2 or 4 Bytes)
+    * SMBus Multi-Byte Register Block Write : S Addr|Wr [A] cmd1 A cmd 2 [A]...
+    *                cmdN [A] data1 [A] Data2 [A].....DataN [A] P
+    * SMBus Multi-Byte Register Block Read : S Addr|Rd [A] cmd1 A cmd 2 [A]...
+    *                cmdN [A] data1 [A] Sr Addr [A] Data1 A Data2 A...DataN A P
+    *
+    * This transaction type could be also used for those devices which supports 
+    * AUTO_INC. Even though it is frequently related to I2C/SMBus, automatic 
+    * incrementation is not part of any I2C standard but rather a common
+    * feature found in many I2C devices. What it means is that the device
+    * maintains in internal pointer which is  automatically incremented upon 
+    * data read or write activities and which can be manually set to a fixed 
+    * value. This comes in handy when storing larger amounts of data for 
+    * instance in an ordinary I2C RAM or EEPROM.
+    * SMBus AUTO_INC Write : S Addr|Wr [A] cmd1 A Data1 [A] Data2 [A]...
+    *                        DataN [A] P
+    * SMBus AUTO_INC Read : S Addr|Rd [A] cmd1 A data1 [A] Sr Addr [A] Data1 A
+    *                       Data2 A...DataN A P
+    * If the device does not support AUTO_INC set warFlags of 
+    * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW to 
+    * NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NO_AUTO_INC.
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW = 9,
+   /*!
+    * This transaction type is used to perform the EDID read via DDC.
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC = 10,
+} NV402C_CTRL_I2C_TRANSACTION_TYPE;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW.
+ *
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW {
+   /*!
+    * This field must be specified by the client to indicate whether the
+    * command is a write (TRUE) or a read (FALSE).
+    */
+    NvBool bWrite;
+   /*!
+    * Transaction specific flags
+    * (see NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_*).
+    */
+    NvU32  warFlags;
+} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW.
+ *
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW {
+   /*!
+    * This field must be specified by the client to indicate whether the
+    * command is a write (TRUE) or a read (FALSE).
+    */
+    NvBool bWrite;
+   /*!
+    * The main message data.
+    */
+    NvU8   message;
+} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW.
+ *
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW {
+   /*!
+    * This field must be specified by the client to indicate whether the
+    * command is a write (TRUE) or a read (FALSE).
+    */
+    NvBool bWrite;
+   /*!
+    * This parameter specifies the number of bytes to read or
+    * write from the slave after the register address is written.
+    */
+    NvU32  messageLength;
+   /*!
+    * The main message data. 
+    */
+    NV_DECLARE_ALIGNED(NvP64 pMessage, 8);
+} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW.
+ *
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW {
+   /*!
+    * This field must be specified by the client to indicate whether the
+    * command is a write (TRUE) or a read (FALSE).
+    */
+    NvBool bWrite;
+   /*!
+    * The address of the register.
+    */
+    NvU8   registerAddress;
+   /*!
+    * The main message data.
+    */
+    NvU8   message;
+} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW.
+ *
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW {
+   /*!
+    * This field must be specified by the client to indicate whether the
+    * command is a write (TRUE) or a read (FALSE).
+    */
+    NvBool bWrite;
+   /*!
+    * The address of the register.
+    */
+    NvU8   registerAddress;
+   /*!
+    * The main message data.
+    */
+    NvU16  message;
+} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BUFFER_RW
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the.transaction type is 
+ * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BUFFER_RW.
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW {
+   /*!
+    * This field must be specified by the client to indicate whether the
+    * command is a write (TRUE) or a read (FALSE).
+    */
+    NvBool bWrite;
+   /*!
+    * Transaction specific flags to be set (see 
+    * NV_NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_*)
+    */
+    NvU32  warFlags;
+   /*!
+    * This parameter specifies how many bytes to write as part of the
+    * register address. If zero is specified, then no index will be sent.
+    */
+    NvU8   registerAddress;
+   /*!
+    * This parameter specifies the number of bytes to read or 
+    * write from the slave after the register address is written.
+    */
+    NvU32  messageLength;
+   /*!
+    * The main message data. 
+    * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX]
+    */
+    NV_DECLARE_ALIGNED(NvP64 pMessage, 8);
+} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the.transaction type is 
+ * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW.
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW {
+   /*!
+    * This field must be specified by the client to indicate whether the
+    * command is a write (TRUE) or a read (FALSE).
+    */
+    NvBool bWrite;
+   /*!
+    * This parameter specifies how many bytes to write as part of the
+    * register address. If zero is specified, then no index will be sent.
+    */
+    NvU8   registerAddress;
+   /*!
+    * This parameter specifies the number of bytes to read or 
+    * write from the slave after the register address is written.
+    */
+    NvU32  messageLength;
+   /*!
+    * The main message data.
+    * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX]
+    */
+    NV_DECLARE_ALIGNED(NvP64 pMessage, 8);
+} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the.transaction type is
+ * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL.
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL {
+   /*!
+    * This parameter specifies how many bytes to write as part of the
+    * register address. If zero is specified, then no index will be sent.
+    */
+    NvU8  registerAddress;
+   /*!
+    * The message data to be written to the slave.
+    */
+    NvU16 writeMessage;
+   /*!
+    * The message data to be read from the slave.
+    */
+    NvU16 readMessage;
+} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the.transaction type is 
+ * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL.
+ *
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL {
+   /*!
+    * This parameter specifies how many bytes to write as part of the
+    * register address. If zero is specified, then no index will be sent.
+    */
+    NvU8  registerAddress;
+   /*!
+    * This parameter specifies the number of bytes to write the the slave 
+    * after the writeByteCount is sent to the slave.
+    */
+    NvU32 writeMessageLength;
+   /*!
+    * The message buffer to be written to the slave.
+    * C form: NvU8 writeMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX]
+    */
+    NvU8  writeMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX];
+   /*!
+    * This parameter specifies the number of bytes to read from the slave 
+    * after the readByteCount is sent to the slave.
+    */
+    NvU32 readMessageLength;
+   /*!
+    * The message buffer to be read from the slave.
+    * C form: NvU8 readMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX]
+    */
+    NvU8  readMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX];
+} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the.transaction type is 
+ * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW.
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW {
+   /*!
+    * This field must be specified by the client to indicate whether the
+    * command is a write (TRUE) or a read (FALSE).
+    */
+    NvBool bWrite;
+   /*!
+    * Transaction specific flags (see 
+    * NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_*)
+    */
+    NvU32  warFlags;
+   /*!
+    * This parameter specifies how many bytes to write as part of the
+    * register address. If zero is specified, then no index will be sent.
+    */
+    NvU32  indexLength;
+   /*!
+    * Optional indexing data; aka register address.
+    * C form: NvU8 index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX]
+    */
+    NvU8   index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX];
+   /*!
+    * This parameter specifies the number of bytes to read or 
+    * write from the slave after the register address is written.
+    */
+    NvU32  messageLength;
+   /*!
+    * The main message data. 
+    * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX]
+    */
+    NV_DECLARE_ALIGNED(NvP64 pMessage, 8);
+} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC
+ *
+ * Specifies the structure of data filled by the client for I2C transaction 
+ * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC.
+ *
+ */
+typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC {
+    /*!
+     * The segment number of the EDID block which is to be read.
+     */
+    NvU8  segmentNumber;
+    /*!
+     * The address of the register.
+     */
+    NvU8  registerAddress;
+   /*!
+    * This parameter specifies the number of bytes to read or
+    * write from the slave after the register address is written.
+    */
+    NvU32 messageLength;
+   /*!
+    * The main message data. 
+    * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX]
+    */
+    NV_DECLARE_ALIGNED(NvP64 pMessage, 8);
+} NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC;
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_DATA
+ *
+ * This union encapsulates the transaction data corresponding to the 
+ * transaction type enlisted above.
+ */
+typedef union NV402C_CTRL_I2C_TRANSACTION_DATA {
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW.
+        */
+    NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW           smbusQuickData;
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW.
+        */
+    NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW              i2cByteData;
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW.
+        */
+    NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW i2cBlockData, 8);
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW.
+        */
+    NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW i2cBufferData, 8);
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW.
+        */
+    NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW            smbusByteData;
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW.
+        */
+    NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW            smbusWordData;
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW.
+        */
+    NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW smbusBlockData, 8);
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL.
+        */
+    NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL       smbusProcessData;
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL.
+        */
+    NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL smbusBlockProcessData;
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW.
+        */
+    NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW smbusMultibyteRegisterData, 8);
+       /*!
+        * This transaction data is to be filled when transaction type is 
+        * NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC.
+        */
+    NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC edidData, 8);
+} NV402C_CTRL_I2C_TRANSACTION_DATA;
+
+
+/*!
+ * NV402C_CTRL_I2C_TRANSACTION_PARAMS
+ *
+ * The params data structure for NV402C_CTRL_CMD_I2C_TRANSACTION.
+ */
+#define NV402C_CTRL_I2C_TRANSACTION_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV402C_CTRL_I2C_TRANSACTION_PARAMS {
+   /*!
+    * The logical port ID.
+    */
+    NvU8                             portId;
+   /*!
+    * This parameter specifies optional flags used to control certain modal
+    * features such as target speed and addressing mode. The currently
+    * defined fields are described previously; see NV402C_CTRL_I2C_FLAGS_* 
+    */
+    NvU32                            flags;
+   /*!
+    * The address of the I2C slave.
+    */
+    NvU16                            deviceAddress;
+   /*!
+    * The transaction type.
+    */
+    NV402C_CTRL_I2C_TRANSACTION_TYPE transType;
+   /*!
+    * The transaction data corresponding transaction type.
+    */
+    NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA transData, 8);
+} NV402C_CTRL_I2C_TRANSACTION_PARAMS;
+
+#define NV402C_CTRL_CMD_I2C_TRANSACTION (0x402c0105) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_TRANSACTION_PARAMS_MESSAGE_ID" */
+
+
+/* _ctrl402c_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c.h
new file mode 100644
index 0000000..e3a9532
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c.h
@@ -0,0 +1,200 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2011-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl503c.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl503c/ctrl503cbase.h"
+
+/*
+ * NV503C_CTRL_CMD_REGISTER_VA_SPACE
+ *
+ * This command registers the specified GPU VA space with the given
+ * NV50_THIRD_PARTY_P2P object, and returns a token that
+ * uniquely identifies the VA space within the object's parent
+ * client.
+ *
+ * Its parameter structure has the following fields:
+ *
+ *   hVASpace
+ *      This field specifies the GPU VA space to be registered
+ *      with the third-party P2P object.
+ *
+ *   vaSpaceToken
+ *     Upon successful completion of the regristration attempt,
+ *     this field holds the new VA space identifier.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_INVALID_OBJECT_HANDLE
+ *   NVOS_STATUS_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ */
+#define NV503C_CTRL_CMD_REGISTER_VA_SPACE (0x503c0102) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_MESSAGE_ID" */
+
+#define NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV503C_CTRL_REGISTER_VA_SPACE_PARAMS {
+    NvHandle hVASpace;
+    NV_DECLARE_ALIGNED(NvU64 vaSpaceToken, 8);
+} NV503C_CTRL_REGISTER_VA_SPACE_PARAMS;
+
+
+/*
+ * NV503C_CTRL_CMD_UNREGISTER_VA_SPACE
+ *
+ * This command unregisters (a previously registered) GPU VA space.
+ *
+ * Its parameter structure has the following field:
+ *
+ *   hVASpace
+ *      This field specifies the GPU VA space to be
+ *      unregistered.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV503C_CTRL_CMD_UNREGISTER_VA_SPACE (0x503c0103) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_MESSAGE_ID" */
+
+#define NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS {
+    NvHandle hVASpace;
+} NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS;
+
+
+/*
+ * NV503C_CTRL_CMD_REGISTER_VIDMEM
+ *
+ * This command registers a video memory allocation with the given
+ * NV50_THIRD_PARTY_P2P object.  Registration of video memory
+ * allocations is required if they are to be made accessible via the
+ * third-party P2P infrastructure.
+ *
+ * The vidmem allocation is made available to the users of the third-party P2P
+ * APIs. It's exposed at the range specified by address and size starting at the
+ * specified offset within the physical allocation. The same physical memory is
+ * exposed as the NvRmMapMemoryDma() API would make accessible to the GPU if
+ * used with equivalent parameters. Notably this API doesn't create any virtual
+ * mappings nor verifies that any mappings are present, it only registers the
+ * memory for the purpose of the third-party P2P infrastructure.
+ *
+ * The address range specified by address and size cannot overlap any previously
+ * registered ranges for the given NV50_THIRD_PARTY_P2P object.
+ *
+ * Its parameter structure has the following field:
+ *
+ *   hMemory
+ *      This field specifies the video memory allocation to be
+ *      registered with the third-party P2P object.
+ *
+ *   address
+ *      The address to register the video memory allocation at. Has to be
+ *      aligned to 64K.
+ *
+ *   size
+ *      Size in bytes, has to be non-0 and aligned to 64K. Offset + size cannot
+ *      be larger than the vidmem allocation.
+ *
+ *   offset
+ *      Offset within the video memory allocation where the registered address
+ *      range starts. Has to be aligned to 64K.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ */
+#define NV503C_CTRL_CMD_REGISTER_VIDMEM (0x503c0104) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_VIDMEM_PARAMS_MESSAGE_ID" */
+
+#define NV503C_CTRL_REGISTER_VIDMEM_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV503C_CTRL_REGISTER_VIDMEM_PARAMS {
+    NvHandle hMemory;
+    NV_DECLARE_ALIGNED(NvU64 address, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+} NV503C_CTRL_REGISTER_VIDMEM_PARAMS;
+
+
+/*
+ * NV503C_CTRL_CMD_UNREGISTER_VIDMEM
+ *
+ * This command unregisters (a previously registered) video memory
+ * allocation.
+ *
+ * Its parameter structure has the following field:
+ *
+ *   hMemory
+ *      This field specifies the video memory allocation to be
+ *      unregistered.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV503C_CTRL_CMD_UNREGISTER_VIDMEM (0x503c0105) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_MESSAGE_ID" */
+
+#define NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS {
+    NvHandle hMemory;
+} NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS;
+
+/*
+ * NV503C_CTRL_CMD_REGISTER_PID
+ * 
+ * This command registers the PID of the process that allocated
+ * the RM client identified by the hClient argument with the 
+ * third-party P2P object, granting this process access to any
+ * underlying video memory.
+ *
+ * Its parameter structure has the following field:
+ *
+ *   hClient
+ *      This field specifies the client id and should be the handle
+ *      to a valid NV01_ROOT_USER instance.
+ *
+ * Possible status values returned are:
+ *    NVOS_STATUS_SUCCES
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV503C_CTRL_CMD_REGISTER_PID (0x503c0106) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_PID_PARAMS_MESSAGE_ID" */
+
+#define NV503C_CTRL_REGISTER_PID_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV503C_CTRL_REGISTER_PID_PARAMS {
+    NvHandle hClient;
+} NV503C_CTRL_REGISTER_PID_PARAMS;
+
+/* _ctrl503c_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h
new file mode 100644
index 0000000..22f3fbe
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h
@@ -0,0 +1,50 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl503c/ctrl503cbase.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV50_THIRD_PARTY_P2P control commands and parameters */
+#define NV503C_CTRL_CMD(cat,idx)  NVXXXX_CTRL_CMD(0x503C,NV503C_CTRL_##cat,idx)
+
+/* NV50_THIRD_PARTY_P2P command categories (6bits) */
+#define NV503C_CTRL_RESERVED (0x00)
+#define NV503C_CTRL_P2P      (0x01)
+
+/*
+ * NV503C_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV503C_CTRL_CMD_NULL (0x503c0000) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* _ctrl503cbase_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl506f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl506f.h
new file mode 100644
index 0000000..7fd7c36
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl506f.h
@@ -0,0 +1,96 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl506f.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV50_GPFIFO control commands and parameters */
+
+#define NV506F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0x506F, NV506F_CTRL_##cat, idx)
+
+/* NV50_GPFIFO command categories (6bits) */
+#define NV506F_CTRL_RESERVED (0x00)
+#define NV506F_CTRL_GPFIFO   (0x01)
+#define NV506F_CTRL_EVENT    (0x02)
+
+/*
+ * NV506F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV506F_CTRL_CMD_NULL (0x506f0000) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/*
+ * NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL
+ *
+ * This command resets a channel which was isolated previously by RC recovery.
+ *
+ *   exceptType
+ *      This input parameter specifies the type of RC error that occurred. See the
+ *      description of the ROBUST_CHANNEL_* values in nverror.h for valid exceptType
+ *      values. info32 field of the error notifier is set with the exceptType when 
+ *      the error notifier is signaled.
+ *
+ *   engineID
+ *      This input parameter specifies the engine to be reset.  See the description 
+ *      of the NV2080_ENGINE_TYPE values in cl2080.h for valid engineID values.  info16 
+ *      field of the error notifier is set with the engineID when the error notifier is 
+ *      signaled.    
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+
+#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL (0x506f0105) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV506F_CTRL_CMD_EVENT_SET_TRIGGER  (deprecated on Fermi+)
+ *
+ * This command triggers a software event for the associated channel.
+ * This command accepts no parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+// #define NV506F_CTRL_CMD_EVENT_SET_TRIGGER         NV506F_CTRL_CMD(EVENT, 0x09)
+
+#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS {
+    NvU32 exceptType;
+    NvU32 engineID;
+} NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS;/* _ctrl506f.h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h
new file mode 100644
index 0000000..49297f7
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h
@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5070/ctrl5070base.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV5070_DISPLAY control commands and parameters */
+
+#define NV5070_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x5070, NV5070_CTRL_##cat, idx)
+
+/* Display command categories (6bits) */
+#define NV5070_CTRL_RESERVED (0x00)
+#define NV5070_CTRL_CHNCTL   (0x01)
+#define NV5070_CTRL_RG       (0x02)
+#define NV5070_CTRL_SEQ      (0x03)
+#define NV5070_CTRL_OR       (0x04)
+#define NV5070_CTRL_INST     (0x05)
+#define NV5070_CTRL_VERIF    (0x06)
+#define NV5070_CTRL_SYSTEM   (0x07)
+#define NV5070_CTRL_EVENT    (0x09)
+
+/*
+ * NV5070_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV5070_CTRL_CMD_NULL (0x50700000) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+// This struct must be the first member of all
+// 5070 control calls
+typedef struct NV5070_CTRL_CMD_BASE_PARAMS {
+    NvU32 subdeviceIndex;
+} NV5070_CTRL_CMD_BASE_PARAMS;
+
+/* _ctrl5070base_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h
new file mode 100644
index 0000000..1916d7f
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h
@@ -0,0 +1,1181 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5070/ctrl5070chnc.finn
+//
+
+#include "ctrl/ctrl5070/ctrl5070base.h"
+#include "ctrl5070common.h"
+#include "nvdisptypes.h"
+
+#define NV5070_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD 2
+
+
+
+#define NV5070_CTRL_IDLE_CHANNEL_ACCL_NONE             (0x00000000)
+#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI                    (NVBIT(0))
+#define NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF                   (NVBIT(1))
+#define NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA                    (NVBIT(2))
+#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK             (NVBIT(3))
+#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK              (NVBIT(4))
+#define NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY                   (NVBIT(5))
+#define NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT              (NVBIT(6))
+
+#define NV5070_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV5070_CTRL_IDLE_CHANNEL_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       channelClass;
+    NvU32                       channelInstance;
+
+    NvU32                       desiredChannelStateMask;
+    NvU32                       accelerators;        // For future expansion. Not yet implemented
+    NvU32                       timeout;             // For future expansion. Not yet implemented
+    NvBool                      restoreDebugMode;
+} NV5070_CTRL_IDLE_CHANNEL_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_STOP_OVERLAY
+ *
+ * This command tries to turn the overlay off ASAP.
+ *
+ *      channelInstance
+ *          This field indicates which of the two instances of the overlay
+ *          channel the cmd is meant for.
+ *
+ *      notifyMode
+ *          This field indicates the action RM should take once the overlay has
+ *          been successfully stopped. The options are (1) Set a notifier
+ *          (2) Set the notifier and generate and OS event
+ *
+ *      hNotifierCtxDma
+ *          Handle to the ctx dma for the notifier that must be written once
+ *          overlay is stopped. The standard NvNotification notifier structure
+ *          is used.
+ *
+ *      offset
+ *          Offset within the notifier context dma where the notifier begins
+ *          Offset must be 16 byte aligned.
+ *
+ *      hEvent
+ *          Handle to the event that RM must use to awaken the client when
+ *          notifyMode is WRITE_AWAKEN.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT: Invalid notify mode
+ *      NV_ERR_INVALID_CHANNEL: When the overlay is unallocated
+ *      NV_ERR_INVALID_OWNER: Callee isn't the owner of the channel
+ *      NV_ERR_INVALID_OBJECT_HANDLE: Notif ctx dma not found
+ *      NV_ERR_INVALID_OFFSET: Bad offset within notif ctx dma
+ *      NV_ERR_INSUFFICIENT_RESOURCES
+ *      NV_ERR_TIMEOUT: RM timedout waiting to inject methods
+ */
+#define NV5070_CTRL_CMD_STOP_OVERLAY                          (0x50700102) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_STOP_OVERLAY_NOTIFY_MODE_WRITE        (0x00000000)
+#define NV5070_CTRL_CMD_STOP_OVERLAY_NOTIFY_MODE_WRITE_AWAKEN (0x00000001)
+
+#define NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       channelInstance;
+    NvU32                       notifyMode;
+    NvHandle                    hNotifierCtxDma;
+    NvU32                       offset;
+    NV_DECLARE_ALIGNED(NvP64 hEvent, 8);
+} NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS;
+
+
+
+/*
+ * NV5070_CTRL_CMD_IS_MODE_POSSIBLE
+ *
+ * This command is used by DD to determine whether or not a given mode
+ * is possible given the current nvclk, mclk, dispclk and potentially some
+ * other parameters that are normally hidden from it. All the parameters
+ * except IsPossible (output), Force422(output), MinPstate (input/output),
+ * minPerfLevel (output), CriticalWatermark (output), worstCaseMargin (output),
+ * and worstCaseDomain (output) params are supplied by the caller.
+ *
+ *      HeadActive
+ *          Whether or not the params for this head are relevant.
+ *
+ *      PixelClock
+ *          Frequency: Pixel clk frequency in KHz.
+ *          Adj1000Div1001: 1000/1001 multiplier for pixel clock.
+ *
+ *      RasterSize
+ *          Width: Total width of the raster. Also referred to as HTotal.
+ *          Height: Total height of the raster. Also referred to as VTotal.
+ *
+ *      RasterBlankStart
+ *          X: Start of horizontal blanking for the raster.
+ *          Y: Start of vertical blanking for the raster.
+ *
+ *      RasterBlankEnd
+ *          X: End of horizontal blanking for the raster.
+ *          Y: End of vertical blanking for the raster.
+ *
+ *      RasterVertBlank2
+ *          YStart: Start of second blanking for second field for an
+ *              interlaced raster. This field is irrelevant when raster is
+ *              progressive.
+ *          YEnd: End of second blanking for second field for an
+ *              interlaced raster. This field is irrelevant when raster is
+ *              progressive.
+ *
+ *      Control
+ *          RasterStructure: Whether the raster ir progressive or interlaced.
+ *
+ *      OutputScaler
+ *          VerticalTaps: Vertical scaler taps.
+ *          HorizontalTaps: Horizontal scaler taps.
+ *          Force422: Whether OutputScaler is operating in 422 mode or not.
+ *
+ *      ViewportSizeOut
+ *          Width: Width of output viewport.
+ *          Height: Height of output viewport.
+ *          Both the above fields are irrelevant for G80.
+ *
+ *      ViewportSizeOutMin
+ *          Width: Minimum possible/expected width of output viewport.
+ *          Height: Minimum possible/expected height of output viewport.
+ *
+ *      ViewportSizeIn
+ *          Width: Width of input viewport.
+ *          Height: Height of input viewport.
+ *
+ *      Params
+ *          Format: Core channel's pixel format. See the enumerants following
+ *              the variable declaration for possible options.
+ *          SuperSample: Whether to use X1AA or X4AA in core channel.
+ *              This parameter is ignored for G80.
+ *
+ *      BaseUsageBounds
+ *          Usable: Whether or not the base channel is expected to be used.
+ *          PixelDepth: Maximum pixel depth allowed in base channel.
+ *          SuperSample: Whether or not X4AA is allowed in base channel.
+ *          BaseLutUsage: Base LUT Size
+ *          OutputLutUsage: Output LUT size
+ *
+ *      OverlayUsageBounds
+ *          Usable: Whether or not the overlay channel is expected to be used.
+ *          PixelDepth: Maximum pixel depth allowed in overlay channel.
+ *          OverlayLutUsage: Overlay LUT Size
+ *
+ *      BaseLutLo
+ *          Enable: Specifies Core Channel's Base LUT is enable or not.
+ *          Mode: Specifies the LUT Mode.
+ *          NeverYieldToBase: Specifies whether NEVER_YIELD_TO_BASE is enabled or not.
+ *
+ *      OutputLutLo
+ *          Enable: Specifies Core Channel's Output LUT is enable or not.
+ *          Mode: Specifies the LUT Mode.
+ *          NeverYieldToBase: Specifies whether NEVER_YIELD_TO_BASE is enabled or not.
+ *
+ *      outputResourcePixelDepthBPP
+ *          Specifies the output pixel depth with scaler mode.
+ *
+ *      CriticalWatermark
+ *          If MinPState is set to _NEED_MIN_PSTATE, this will return the critical
+ *          watermark level at the minimum Pstate.  Otherwise, this will return
+ *          the critical watermark at the level that the IMP calculations are
+ *          otherwise performed at.
+ *
+ *      pixelReplicateMode
+ *          Specifies the replication mode whether it is X2 or X4. Need to set the parameter
+ *          to OFF if there is no pixel replication.
+ *
+ *      numSSTLinks
+ *          Number of Single Stream Transport links which will be used by the
+ *          SOR.  "0" means to use the number indicated by the most recent
+ *          NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST call.
+ *
+ *      RequestedOperation
+ *          This parameter is used to determine whether
+ *          1. DD is simplying querying whether or not the specified mode is
+ *             possible (REQUESTED_OPER = _QUERY) or
+ *          2. DD is about to set the specified mode and RM should make
+ *             appropriate preparations to make the mode possible. DD should
+ *             never pass in a mode that was never indicated by RM as possible
+ *             when DD queried for the possibility of the mode. This
+ *             corresponds to REQUESTED_OPER = _PRE_MODESET.
+ *          3. DD just finished setting the specified mode. RM can go ahead
+ *             and make changes like lowering the perf level if desired. This
+ *             corresponds to REQUESTED_OPER = _POST_MODESET. This parameter is
+ *             useful when we are at a higher perf level in a mode that's not
+ *             possible at a lower perf level and want to go to a mode that is
+ *             possible even at a lower perf level. In such cases, lowering
+ *             perf level before modeset is complete is dangerous as it will
+ *             cause underflow. RM will wait until the end of modeset to lower
+ *             the perf level.
+ *
+ *      options
+ *          Specifies a bitmask for options.
+ *            NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN
+ *              Tells IMP to calculate worstCaseMargin and worstCaseDomain.
+ *
+ *      IsPossible
+ *          This is the first OUT param for this call. It indicates whether
+ *          or not the current mode is possible.
+ *
+ *      MinPState
+ *          MinPState is an IO (in/out) variable; it gives the minimum p-state
+ *          value at which the mode is possible on a PStates 2.0 system if the
+ *          parameter is initialized by the caller with _NEED_MIN_PSTATE.  If
+ *          _NEED_MIN_PSTATE is not specified, IMP query will just run at the
+ *          max available perf level and return results for that pstate.
+ *
+ *          If the minimum pstate is required, then MasterLockMode,
+ *          MasterLockPin, SlaveLockMode, and SlaveLockPin must all be
+ *          initialized.
+ *
+ *          On a PStates 3.0 system, the return value for MinPState is
+ *          undefined, but minPerfLevel can return the minimum IMP v-pstate.
+ *
+ *      minPerfLevel
+ *          On a PStates 3.0 system, minPerfLevel returns the minimum IMP
+ *          v-pstate at which the mode is possible.  On a PStates 2.0 system,
+ *          minPerfLevel returns the minimum perf level at which the mode is
+ *          possible.
+ *
+ *          minPerfLevel is valid only if MinPState is initialized to
+ *          _NEED_MIN_PSTATE.
+ *
+ *      worstCaseMargin
+ *          Returns the ratio of available bandwidth to required bandwidth,
+ *          multiplied by NV5070_CTRL_IMP_MARGIN_MULTIPLIER.  Available
+ *          bandwidth is calculated in the worst case bandwidth domain, i.e.,
+ *          the domain with the least available margin.  Bandwidth domains
+ *          include the IMP-relevant clock domains, and possibly other virtual
+ *          bandwidth domains such as AWP.
+ *
+ *          Note that IMP checks additional parameters besides the bandwidth
+ *          margins, but only the bandwidth margin is reported here, so it is
+ *          possible for a mode to have a more restrictive domain that is not
+ *          reflected in the reported margin result.
+ *
+ *          This result is not guaranteed to be valid if the mode is not
+ *          possible.
+ *
+ *          Note also that the result is generally calculated for the highest
+ *          pstate possible (usually P0).  But if _NEED_MIN_PSTATE is specified
+ *          with the MinPState parameter, the result will be calculated for the
+ *          min possible pstate (or the highest possible pstate, if the mode is
+ *          not possible).
+ *
+ *          The result is valid only if
+ *          NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN is set in
+ *          "options".
+ *
+ *      worstCaseDomain
+ *          Returns a short text string naming the domain for the margin
+ *          returned in "worstCaseMargin".  See "worstCaseMargin" for more
+ *          information.
+ *
+ *      bUseCachedPerfState
+ *          Indicates that RM should use cached values for the fastest
+ *          available perf level (v-pstate for PStates 3.0 or pstate for
+ *          PStates 2.0) and dispclk.  This feature allows the query call to
+ *          execute faster, and is intended to be used, for example, during
+ *          mode enumeration, when many IMP query calls are made in close
+ *          succession, and perf conditions are not expected to change between
+ *          query calls.  When IMP has not been queried recently, it is
+ *          recommended to NOT use cached values, in case perf conditions have
+ *          changed and the cached values no longer reflect the current
+ *          conditions.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_GENERIC
+ *
+ * Assumptions/Limitations:
+ *      - If the caller sends any methods to alter the State Cache, before calling of
+ *          the following functions:
+ *               NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY_USE_SC
+ *               NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET_USE_SC
+ *               NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET_USE_SC
+ *          the caller must repeatedly issue NV5070_CTRL_CMD_GET_CHANNEL_INFO, and delay until the
+ *          returned channelState is either:
+ *              NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_IDLE,
+ *              NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_WRTIDLE, or
+ *              NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_EMPTY.
+ *          This ensures that all commands have reached the State Cache before RM reads
+ *              them.
+ *
+ *
+ */
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE                                                  (0x50700109) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY                        (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET                  (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET                 (0x00000002)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY_USE_SC                 (0x00000003)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET_USE_SC           (0x00000004)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET_USE_SC          (0x00000005)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_SUPERVISOR                   (0x00000007)
+
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN                                   (0x00000001)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_IS_POSSIBLE_NO                                   (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_IS_POSSIBLE_YES                                  (0x00000001)
+
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_UNDEFINED                                    (0x00000000)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P0                                           (0x00000001)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P1                                           (0x00000002)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P2                                           (0x00000004)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P3                                           (0x00000008)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P8                                           (0x00000100)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P10                                          (0x00000400)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P12                                          (0x00001000)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P15                                          (0x00008000)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_MAX                                          NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P15
+#define NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE                                      (0x10101010)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE_DEFAULT                              (0x00000000)
+
+#define NV5070_CTRL_IMP_MARGIN_MULTIPLIER                                                 (0x00000400)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_HEAD_ACTIVE_NO                                   (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_HEAD_ACTIVE_YES                                  (0x00000001)
+
+#define NV5070_CTRL_IS_MODE_POSSIBLE_DISPLAY_ID_SKIP_IMP_OUTPUT_CHECK                     (0xAAAAAAAA)
+
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT                  (0x00000000)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422               (0x00000001)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444               (0x00000002)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422               (0x00000003)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422               (0x00000004)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444               (0x00000005)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444               (0x00000006)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422               (0x00000007)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444               (0x00000008)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444               (0x00000009)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PIXEL_CLOCK_ADJ1000DIV1001_NO                    (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PIXEL_CLOCK_ADJ1000DIV1001_YES                   (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_CONTROL_STRUCTURE_PROGRESSIVE                    (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_CONTROL_STRUCTURE_INTERLACED                     (0x00000001)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_1                    (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_2                    (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_3                    (0x00000002)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_3_ADAPTIVE           (0x00000003)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_5                    (0x00000004)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_1                  (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_2                  (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_8                  (0x00000002)
+
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_SCALER_FORCE422_MODE_DISABLE                  (0x00000000)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_SCALER_FORCE422_MODE_ENABLE                   (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_I8                                 (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_VOID16                             (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_VOID32                             (0x00000002)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_RF16_GF16_BF16_AF16                (0x00000003)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A8R8G8B8                           (0x00000004)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A2B10G10R10                        (0x00000005)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A8B8G8R8                           (0x00000006)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_R5G6B5                             (0x00000007)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A1R5G5B5                           (0x00000008)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_SUPER_SAMPLE_X1AA                         (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_SUPER_SAMPLE_X4AA                         (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_USE_CURRENT             (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_NO                      (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_YES                     (0x00000002)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_USE_CURRENT        (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_8                  (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_16                 (0x00000002)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_32                 (0x00000003)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_64                 (0x00000004)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_USE_CURRENT       (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_X1AA              (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_X4AA              (0x00000002)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_NONE            (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_257             (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_1025            (0x00000002)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE          (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257           (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025          (0x00000002)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_USE_CURRENT          (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_NO                   (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_YES                  (0x00000002)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_USE_CURRENT     (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_16              (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_32              (0x00000002)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_64              (0x00000003)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE      (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257       (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025      (0x00000002)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_ENABLE_DISABLE                       (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_ENABLE_ENABLE                        (0x00000001)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_LORES                           (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_HIRES                           (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE          (0x00000002)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE    (0x00000003)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE   (0x00000004)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE    (0x00000005)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE     (0x00000006)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE    (0x00000007)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE          (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE           (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_ENABLE_DISABLE                     (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_ENABLE_ENABLE                      (0x00000001)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_LORES                         (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_HIRES                         (0x00000001)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE        (0x00000002)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE  (0x00000003)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000004)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE  (0x00000005)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE   (0x00000006)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE  (0x00000007)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE        (0x00000000)
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE         (0x00000001)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_OFF                             (0x00000000)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X2                              (0x00000001)
+#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X4                              (0x00000002)
+
+#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    struct {
+        NvU32 HeadActive;
+        struct {
+            NvU32 Frequency;
+
+            NvU32 Adj1000Div1001;
+        } PixelClock;
+
+        struct {
+            NvU32 Width;
+            NvU32 Height;
+        } RasterSize;
+
+        struct {
+            NvU32 X;
+            NvU32 Y;
+        } RasterBlankStart;
+
+        struct {
+            NvU32 X;
+            NvU32 Y;
+        } RasterBlankEnd;
+
+        struct {
+            NvU32 YStart;
+            NvU32 YEnd;
+        } RasterVertBlank2;
+
+        struct {
+            NvU32             Structure;
+/*
+ * Note: For query calls, the lock modes and lock pins are used only if the min
+ * pstate is required (i.e., if MinPState is set to
+ * NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE).
+ */
+            NV_DISP_LOCK_MODE MasterLockMode;
+            NV_DISP_LOCK_PIN  MasterLockPin;
+            NV_DISP_LOCK_MODE SlaveLockMode;
+            NV_DISP_LOCK_PIN  SlaveLockPin;
+        } Control;
+
+        struct {
+            NvU32  VerticalTaps;
+            NvU32  HorizontalTaps;
+            NvBool Force422;
+        } OutputScaler;
+
+        struct {
+            NvU32 Width;
+            NvU32 Height;
+        } ViewportSizeOut;
+
+        struct {
+            NvU32 Width;
+            NvU32 Height;
+        } ViewportSizeOutMin;
+
+        struct {
+            NvU32 Width;
+            NvU32 Height;
+        } ViewportSizeOutMax;
+
+        struct {
+            NvU32 Width;
+            NvU32 Height;
+        } ViewportSizeIn;
+
+        struct {
+            NvU32 Format;
+            NvU32 SuperSample;
+        } Params;
+
+        struct {
+            NvU32 Usable;
+            NvU32 PixelDepth;
+            NvU32 SuperSample;
+            NvU32 BaseLutUsage;
+            NvU32 OutputLutUsage;
+        } BaseUsageBounds;
+
+        struct {
+            NvU32 Usable;
+            NvU32 PixelDepth;
+            NvU32 OverlayLutUsage;
+        } OverlayUsageBounds;
+
+        struct {
+            NvBool Enable;
+            NvU32  Mode;
+            NvBool NeverYieldToBase;
+        } BaseLutLo;
+
+        struct {
+            NvBool Enable;
+            NvU32  Mode;
+            NvBool NeverYieldToBase;
+        } OutputLutLo;
+
+        NvU32 displayId[NV5070_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD];
+        NvU32 outputResourcePixelDepthBPP;
+
+        NvU32 CriticalWatermark; // in pixels
+
+    } Head[NV5070_CTRL_CMD_MAX_HEADS];
+
+    struct {
+        NvU32 owner;
+        NvU32 protocol;
+    } Dac[NV5070_CTRL_CMD_MAX_DACS];
+
+    struct {
+//
+// owner field is deprecated. In the future, all client calls should set
+// ownerMask and bUseSorOwnerMask. bUseSorOwnerMask must be set in order
+// to use ownerMask.
+//
+        NvU32 owner;
+        NvU32 ownerMask; // Head mask owned this sor
+
+        NvU32 protocol;
+        NvU32 pixelReplicateMode;
+
+        NvU8  numSSTLinks;
+    } Sor[NV5070_CTRL_CMD_MAX_SORS];
+
+    NvBool bUseSorOwnerMask;
+
+    struct {
+        NvU32 owner;
+        NvU32 protocol;
+    } Pior[NV5070_CTRL_CMD_MAX_PIORS];
+
+
+    NvU32  RequestedOperation;
+// This argument is for VERIF and INTERNAL use only
+    NvU32  options;
+    NvU32  IsPossible;
+    NvU32  MinPState;
+
+    NvU32  minPerfLevel;
+//
+// Below are the possible Output values for MinPState variable.
+// Lower the p-state value higher the power consumption; if no p-states are defined on chip
+// then it will return as zero.
+//
+
+//
+// Below are the possible input values for MinPstate Variable, by default it calculate
+// mode is possible or not at max available p-state and return the same state in that variable.
+//
+    NvU32  worstCaseMargin;
+
+//
+// The calculated margin is multiplied by a constant, so that it can be
+// represented as an integer with reasonable precision.  "0x400" was chosen
+// because it is a power of two, which might allow some compilers/CPUs to
+// simplify the calculation by doing a shift instead of a multiply/divide.
+// (And 0x400 is 1024, which is close to 1000, so that may simplify visual
+// interpretation of the raw margin value.)
+//
+    char   worstCaseDomain[8];
+
+    NvBool bUseCachedPerfState;
+} NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS;
+
+
+
+/*
+ * NV5070_CTRL_CMD_GET_CHANNEL_INFO
+ *
+ * This command returns the current channel state.
+ *
+ *      channelClass
+ *          This field indicates the hw class number (507A-507E)
+ *
+ *      channelInstance
+ *          This field indicates which of the two instances of the channel
+ *          (in case there are two. ex: base, overlay etc) the cmd is meant for.
+ *          Note that core channel has only one instance and the field should
+ *          be set to 0 for core channel.
+ *
+ *      channelState
+ *          This field indicates the desired channel state in a mask form that
+ *          is compatible with NV5070_CTRL_CMD_IDLE_CHANNEL. A mask format
+ *          allows clients to check for one from a group of states.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ *
+ * Display driver uses this call to ensure that all it's methods have
+ * propagated through hardware's internal fifo
+ * (NV5070_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING) before it calls
+ * RM to check whether or not the mode it set up in Assembly State Cache will
+ * be possible. Note that display driver can not use completion notifier in
+ * this case because completion notifier is associated with Update and Update
+ * will propagate the state from Assembly to Armed and when checking the
+ * possibility of a mode, display driver wouldn't want Armed state to be
+ * affected.
+ */
+#define NV5070_CTRL_CMD_GET_CHANNEL_INFO (0x5070010b) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_IDLE                 NV5070_CTRL_CMD_CHANNEL_STATE_IDLE
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_WRTIDLE              NV5070_CTRL_CMD_CHANNEL_STATE_WRTIDLE
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_EMPTY                NV5070_CTRL_CMD_CHANNEL_STATE_EMPTY
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FLUSHED              NV5070_CTRL_CMD_CHANNEL_STATE_FLUSHED
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_BUSY                 NV5070_CTRL_CMD_CHANNEL_STATE_BUSY
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC              NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC_LIMBO        NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_LIMBO1               NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO1
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_LIMBO2               NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO2
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FCODEINIT            NV5070_CTRL_CMD_CHANNEL_STATE_FCODEINIT
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FCODE                NV5070_CTRL_CMD_CHANNEL_STATE_FCODE
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_VBIOSINIT            NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSINIT
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_VBIOSOPER            NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSOPER
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_UNCONNECTED          NV5070_CTRL_CMD_CHANNEL_STATE_UNCONNECTED
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_INITIALIZE           NV5070_CTRL_CMD_CHANNEL_STATE_INITIALIZE
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN1            NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN2            NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2
+#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING    (NV5070_CTRL_GET_CHANNEL_INFO_STATE_EMPTY | NV5070_CTRL_GET_CHANNEL_INFO_STATE_WRTIDLE | NV5070_CTRL_GET_CHANNEL_INFO_STATE_IDLE)
+#define NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       channelClass;
+    NvU32                       channelInstance;
+    NvBool                      IsChannelInDebugMode;
+
+    NvU32                       channelState;
+} NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS;
+
+
+
+/*
+ * NV5070_CTRL_CMD_SET_ACCL
+ *
+ *   This command turns accelerators on and off. The use of this command
+ *   should be restricted as it may have undesirable effects. It's
+ *   purpose is to provide a mechanism for clients to use the
+ *   accelerator bits to get into states that are either not detectable
+ *   by the RM or may take longer to reach than we think is reasonable
+ *   to wait in the RM.
+ *
+ * NV5070_CTRL_CMD_GET_ACCL
+ *
+ *   This command queries the current state of the accelerators.
+ *
+ *      channelClass
+ *          This field indicates the hw class number (507A-507E)
+ *
+ *      channelInstance
+ *          This field indicates which of the two instances of the channel
+ *          (in case there are two. ex: base, overlay etc) the cmd is meant for.
+ *          Note that core channel has only one instance and the field should
+ *          be set to 0 for core channel.
+ *
+ *      accelerators
+ *          Accelerators to be set in the SET_ACCEL command. Returns the
+ *          currently set accelerators on the GET_ACCEL command.
+ *
+ *      accelMask
+ *          A mask to specify which accelerators to change with the
+ *          SET_ACCEL command. This field does nothing in the GET_ACCEL
+ *          command.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_CHANNEL
+ *      NV_ERR_INVALID_OWNER
+ *      NV_ERR_GENERIC
+ *
+ */
+
+#define NV5070_CTRL_CMD_SET_ACCL (0x5070010c) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_ACCL (0x5070010d) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_ACCL_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_ACCL_NONE    NV5070_CTRL_IDLE_CHANNEL_ACCL_NONE
+#define NV5070_CTRL_ACCL_IGNORE_PI        NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI
+#define NV5070_CTRL_ACCL_SKIP_NOTIF       NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF
+#define NV5070_CTRL_ACCL_SKIP_SEMA        NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA
+#define NV5070_CTRL_ACCL_IGNORE_INTERLOCK NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK
+#define NV5070_CTRL_ACCL_IGNORE_FLIPLOCK  NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK
+#define NV5070_CTRL_ACCL_TRASH_ONLY       NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY
+#define NV5070_CTRL_ACCL_TRASH_AND_ABORT  NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT
+#define NV5070_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV5070_CTRL_SET_ACCL_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       channelClass;
+    NvU32                       channelInstance;
+
+    NvU32                       accelerators;
+    NvU32                       accelMask;
+} NV5070_CTRL_SET_ACCL_PARAMS;
+#define NV5070_CTRL_GET_ACCL_PARAMS_MESSAGE_ID (0xDU)
+
+typedef NV5070_CTRL_SET_ACCL_PARAMS NV5070_CTRL_GET_ACCL_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_STOP_BASE
+ *
+ * This command tries to turn the base channel off ASAP.
+ *
+ *      channelInstance
+ *          This field indicates which of the two instances of the base
+ *          channel the cmd is meant for.
+ *
+ *      notifyMode
+ *          This field indicates the action RM should take once the base
+ *          channel has been successfully stopped. The options are (1) Set a
+ *          notifier (2) Set the notifier and generate and OS event
+ *
+ *      hNotifierCtxDma
+ *          Handle to the ctx dma for the notifier that must be written once
+ *          base channel is stopped. The standard NvNotification notifier
+ *          structure is used.
+ *
+ *      offset
+ *          Offset within the notifier context dma where the notifier begins
+ *          Offset must be 16 byte aligned.
+ *
+ *      hEvent
+ *          Handle to the event that RM must use to awaken the client when
+ *          notifyMode is WRITE_AWAKEN.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT: Invalid notify mode
+ *      NV_ERR_INVALID_CHANNEL: When the overlay is unallocated
+ *      NV_ERR_INVALID_OWNER: Callee isn't the owner of the channel
+ *      NV_ERR_INVALID_OBJECT_HANDLE: Notif ctx dma not found
+ *      NV_ERR_INVALID_OFFSET: Bad offset within notif ctx dma
+ *      NV_ERR_INSUFFICIENT_RESOURCES
+ *      NV_ERR_TIMEOUT: RM timedout waiting to inject methods
+ */
+#define NV5070_CTRL_CMD_STOP_BASE                          (0x5070010e) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_STOP_BASE_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_STOP_BASE_NOTIFY_MODE_WRITE        (0x00000000)
+#define NV5070_CTRL_CMD_STOP_BASE_NOTIFY_MODE_WRITE_AWAKEN (0x00000001)
+
+#define NV5070_CTRL_CMD_STOP_BASE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV5070_CTRL_CMD_STOP_BASE_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       channelInstance;
+    NvU32                       notifyMode;
+    NvHandle                    hNotifierCtxDma;
+    NvU32                       offset;
+    NV_DECLARE_ALIGNED(NvP64 hEvent, 8);
+} NV5070_CTRL_CMD_STOP_BASE_PARAMS;
+
+
+
+/*
+ * NV5070_CTRL_CMD_GET_PINSET_COUNT
+ *
+ * Get number of pinsets on this GPU.
+ *
+ *   pinsetCount [out]
+ *     Number of pinsets on this GPU is returned in this parameter.
+ *     This count includes pinsets that are not connected.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV5070_CTRL_CMD_GET_PINSET_COUNT (0x50700115) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_COUNT_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_GET_PINSET_COUNT_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV5070_CTRL_GET_PINSET_COUNT_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       pinsetCount;
+} NV5070_CTRL_GET_PINSET_COUNT_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_GET_PINSET_PEER
+ *
+ * Retrieve the pinset/GPU that is connected to the specified pinset on
+ * this GPU.
+ *
+ *   pinset [in]
+ *     Pinset on this GPU for which peer info is to be returned must be
+ *     specified in this parameter.
+ *
+ *   peerGpuId [out]
+ *     Instance of the GPU on the other side of the connection is
+ *     returned in this parameter.
+ *
+ *   peerPinset [out]
+ *     Pinset on the other side of the connection is returned in this
+ *     parameter.  If there is no connection then the value is
+ *     NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_PINSET_NONE.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV5070_CTRL_CMD_GET_PINSET_PEER                       (0x50700116) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_PEER_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_GPUINSTANCE_NONE (0xffffffff)
+
+#define NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_PINSET_NONE      (0xffffffff)
+
+#define NV5070_CTRL_GET_PINSET_PEER_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV5070_CTRL_GET_PINSET_PEER_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       pinset;
+
+    NvU32                       peerGpuInstance;
+    NvU32                       peerPinset;
+} NV5070_CTRL_GET_PINSET_PEER_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_SET_RMFREE_FLAGS
+ *
+ * This command sets the flags for an upcoming call to RmFree().
+ * After the RmFree() API runs successfully or not, the flags are cleared.
+ *
+ *   flags
+ *     This parameter holds the NV0000_CTRL_GPU_SET_RMFREE_FLAGS_*
+ *     flags to be passed for the next RmFree() command only.
+ *     The flags can be one of those:
+ *     - NV0000_CTRL_GPU_SET_RMFREE_FLAGS_NONE:
+ *       explicitly clears the flags
+ *     - NV0000_CTRL_GPU_SET_RMFREE_FLAGS_FREE_PRESERVES_HW:
+ *       instructs RmFree() to preserve the HW configuration. After
+ *       RmFree() is run this flag is cleared.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV5070_CTRL_CMD_SET_RMFREE_FLAGS         (0x50700117) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_SET_RMFREE_FLAGS_NONE        0x00000000
+#define NV5070_CTRL_SET_RMFREE_FLAGS_PRESERVE_HW 0x00000001
+#define NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS_MESSAGE_ID (0x17U)
+
+typedef struct NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       flags;
+} NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS;
+
+
+/*
+ * NV5070_CTRL_CMD_IMP_SET_GET_PARAMETER
+ *
+ * This command allows to set or get certain IMP parameters. Change of
+ * values take effect on next modeset and is persistent across modesets
+ * until the driver is unloaded or user changes the override.
+ *
+ *   index
+ *     One of NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_XXX defines -
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IMP_ENABLE
+ *       Only supports "get" operation. If FALSE, IMP is being bypassed and
+ *       all Is Mode Possible queries are answered with "mode is possible"
+ *       and registers normally set by IMP are not changed from their defaults.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED
+ *       Should IMP consider using ASR. ASR won't be allowed unless it is set to
+ *       "allowed" through both _IS_ASR_ALLOWED and _IS_ASR_ALLOWED_PER_PSTATE.
+ *       Note that IMP will not run ASR and MSCG at the same time.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE
+ *       Should IMP consider using ASR when this pstate is being used. ASR won't
+ *       be allowed unless it is set to "allowed" through both
+ *       NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED and
+ *       NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE.
+ *       So when NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED
+ *       returns FALSE, IMP won't consider ASR for any p-state. Note that IMP
+ *       will not run ASR and MSCG at the same time. This function is valid
+ *       only on PStates 2.0 systems.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE
+ *       Should IMP consider using MSCG when this pstate is being used. MSCG
+ *       won't be allowed if the MSCG feature isn't enabled even if we set to
+ *       "allowed" through
+ *       NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE.
+ *       Use NV2080_CTRL_CMD_MC_QUERY_POWERGATING_PARAMETER to query if MSCG is
+ *       supported and enabled. Note that IMP will not run ASR and MSCG at the
+ *       same time. This function is valid only on PStates 2.0 systems.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE
+ *       Only supports "get" operation. Returns which stutter feature is being
+ *       engaged in hardware when running on the given pstate. Valid values are:
+ *         NV5070_CTRL_IMP_STUTTER_FEATURE_NONE
+ *           This value indicates no stutter feature is enabled.
+ *         NV5070_CTRL_IMP_STUTTER_FEATURE_ASR
+ *           This value indicates ASR is the current enabled stutter feature.
+ *         NV5070_CTRL_IMP_STUTTER_FEATURE_MSCG
+ *           This value indicates MSCG is the current enabled stutter feature.
+ *       Note that system will not run ASR and MSCG at the same time. This
+ *       function is valid only on PStates 2.0 systems.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE
+ *       Only supports "get" operation. Returns the efficiency which IMP
+ *       predicted for the engaged stutter feature (ASR or MSCG) when running
+ *       on the given pstate. Normally, the actual efficiency should be higher
+ *       than the calculated predicted efficiency. For MSCG, the predicted
+ *       efficiency assumes no mempool compression. If compression is enabled
+ *       with MSCG, the actual efficiency may be significantly higher. Returns
+ *       0 if no stutter feature is running. On PStates 3.0 systems, the
+ *       pstateApi parameter is ignored, and the result is returned for the min
+ *       IMP v-pstate possible.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS
+ *       Only supports "get" operation. Returns information about what the possible
+ *       mclk switch is.  Valid fields are:
+ *         NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE
+ *           This field is not head-specific and indicates if mclk switch is
+ *           possible with the current mode.
+ *         NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL
+ *           This field is not head-specific and indicates if mclk switch is
+ *           possible with the nominal mempool settings (_NO) or if special
+ *           settings are required in order for mclk switch to be possible (_YES).
+ *         NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK
+ *           Each head has its own setting for this field.  If this field is
+ *           set to _YES, then the specified head will allow mclk switch to
+ *           begin if mempool occupancy exceeds the MID_WATERMARK setting.
+ *         NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF
+ *           Each head has its own setting for this field.  If this field is
+ *           set to _YES, then the specified head will allow mclk switch to
+ *           begin if the head is in its DWCF interval, and the mempool
+ *           occupancy is greater than or equal to the DWCF watermark.
+ *       Note:  If neither _MID_WATERMARK nor _DWCF is set to _YES, then the
+ *       specified head is ignored when determining when it is OK to start an
+ *       mclk switch.  Mclk switch must be allowed (or ignored) by all heads
+ *       before an mclk switch will actually begin.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_FORCE_MIN_MEMPOOL
+ *       Should min mempool be forced.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MEMPOOL_COMPRESSION
+ *       Should mempool compression be enabled.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_CURSOR_SIZE
+ *       The cursor size (in horizontal pixels) used by IMP (rather than the
+ *       actual cursor size) for its computation.
+ *       A maximum value is in place for what can be set. It can be queried
+ *       after resetting the value - it gets reset to the maximum possible
+ *       value.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_ENABLE
+ *       This is to Enable/Disable ISO FB Latency Test.
+ *       The test records the max ISO FB latency for all heads during the test period (excluding modeset time).
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_WC_TOTAL_LATENCY
+ *       This is used to retrieve calculated wcTotalLatency of ISO FB Latency Test.
+ *       wcTotalLatency is the worst case time for a request's data to come back after the request is issued.
+ *       It is the sum of IMP calculated FbLatency and stream delay.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_LATENCY
+ *       This is used to retrieve the max latency among all heads during the whole ISO FB Latency Test.
+ *       The max latency can be used to compare with the wcTotalLatency we calculated.
+ *       It decides whether the ISO FB Latency Test is passed or not.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_TEST_PERIOD
+ *       This is used to retrieve the max test period during the whole ISO FB Latency Test.
+ *       By experimental result, the test period should be at least 10 secs to approximate the
+ *       worst case Fb latency in real situation.
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_GLITCHLESS_MODESET_ENABLE
+ *       This enables or disables glitchless modesets.  Modesets can be
+ *       glitchless if:
+ *       (1) There are no raster timing changes, and
+ *       (2) The resource requirements of all bandwidth clients are either not
+ *           changing, or they are all changing in the same direction (all
+ *           increasing or all decreasing).
+ *       If glitchless modeset is disabled, or is not possible, heads will be
+ *       blanked during the modeset transition.
+ *   pstateApi
+ *     NV2080_CTRL_PERF_PSTATES_PXXX value.
+ *     Required for NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE,
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE,
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE and
+ *     NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE
+ *     on PStates 2.0 systems. For other indices must be
+ *     NV2080_CTRL_PERF_PSTATES_UNDEFINED.  Not used on PStates 3.0 systems.
+ *   head
+ *     Head index, which is required when querying Mclk switch feature.
+ *     (index = NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS)
+ *   operation
+ *       NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_GET
+ *         Indicates a "get" operation.
+ *       NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_SET
+ *         Indicates a "set" operation.
+ *       NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_RESET
+ *         Indicates a "reset" operation. This operation will reset the values for
+ *         all indices to their RM defaults.
+ *   value
+ *     Value for new setting of a "set" operation, or the returned value of a
+ *     "get" operation; for enable/disable operations, "enable" is non-zero,
+ *     and "disable" is zero.
+ *
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_POINTER
+ *   NV_ERR_INVALID_INDEX            specified index is not supported
+ *   NV_ERR_INSUFFICIENT_RESOURCES   cannot handle any more overrides
+ *   NV_ERR_INVALID_OBJECT     the struct needed to get the specified information
+ *                                              is not marked as valid
+ *   NV_ERR_INVALID_STATE            the parameter has been set but resetting will
+ *                                              not be possible
+ */
+#define NV5070_CTRL_CMD_IMP_SET_GET_PARAMETER (0x50700118) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       index;
+    NvU32                       pstateApi;
+    NvU32                       head;
+    NvU32                       operation;
+    NvU32                       value;
+} NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS;
+
+/* valid operation values */
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_GET                                                0
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_SET                                                1
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_RESET                                              2
+
+/* valid index value */
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_NONE                                                   (0x00000000)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IMP_ENABLE                                             (0x00000001)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED                                         (0x00000002)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE                              (0x00000003)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE                             (0x00000004)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE                             (0x00000005)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE        (0x00000006)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS                            (0x00000007)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_FORCE_MIN_MEMPOOL                                      (0x00000008)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MEMPOOL_COMPRESSION                                    (0x00000009)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_CURSOR_SIZE                                            (0x0000000A)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_ENABLE                               (0x0000000B)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_WC_TOTAL_LATENCY                     (0x0000000C)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_LATENCY                          (0x0000000D)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_TEST_PERIOD                      (0x0000000E)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_GLITCHLESS_MODESET_ENABLE                              (0x0000000F)
+
+/* valid NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOHUB_STUTTER_FEATURE values */
+#define NV5070_CTRL_IMP_STUTTER_FEATURE_NONE                                                           0
+#define NV5070_CTRL_IMP_STUTTER_FEATURE_ASR                                                            1
+#define NV5070_CTRL_IMP_STUTTER_FEATURE_MSCG                                                           2
+
+/* valid NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE values */
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE                      0:0
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE_NO          (0x00000000)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE_YES         (0x00000001)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL              1:1
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL_NO  (0x00000000)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL_YES (0x00000001)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK                 2:2
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK_NO     (0x00000000)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK_YES    (0x00000001)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF                          3:3
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF_NO              (0x00000000)
+#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF_YES             (0x00000001)
+
+/*
+ * NV5070_CTRL_CMD_SET_MEMPOOL_WAR_FOR_BLIT_TEARING
+ *
+ * This command engages the WAR for blit tearing caused by huge mempool size and
+ * mempool compression. The EVR in aero off mode uses scanline info to predict
+ * where the scanline will be at a later time. Since RG scanline is used to perform
+ * front buffer blits and isohub buffers large amount of display data it may have
+ * fetched several lines of data ahead of where the RG is scanning out leading to
+ * video tearing. The WAR for this problem is to reduce the amount of data fetched.
+ *
+ *   base
+ *     This struct must be the first member of all 5070 control calls containing
+ *     the subdeviceIndex.
+ *   bEngageWAR
+ *     Indicates if mempool WAR has to be engaged or disengaged.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV5070_CTRL_CMD_SET_MEMPOOL_WAR_FOR_BLIT_TEARING                                               (0x50700119) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvBool                      bEngageWAR;
+} NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS;
+typedef struct NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS *PNV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS;
+
+#define NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE (0x50700120) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       head;
+    NvU32                       activeViewportBase;
+} NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS;
+typedef struct NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS *PNV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS;
+
+/* _ctrl5070chnc_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h
new file mode 100644
index 0000000..bbfa794
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h
@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5070/ctrl5070common.finn
+//
+
+
+
+#define NV5070_CTRL_CMD_CHANNEL_STATE_IDLE                              NVBIT(0)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_WRTIDLE                           NVBIT(1)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_QUIESCENT1                        NVBIT(2)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_QUIESCENT2                        NVBIT(3)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_EMPTY                             NVBIT(4)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_FLUSHED                           NVBIT(5)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_BUSY                              NVBIT(6)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC                           NVBIT(7)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO                     NVBIT(8)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO1                            NVBIT(9)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO2                            NVBIT(10)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_FCODEINIT                         NVBIT(11)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_FCODE                             NVBIT(12)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSINIT                         NVBIT(13)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSOPER                         NVBIT(14)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_UNCONNECTED                       NVBIT(15)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_INITIALIZE                        NVBIT(16)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1                         NVBIT(17)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2                         NVBIT(18)
+#define NV5070_CTRL_CMD_CHANNEL_STATE_INIT                              NVBIT(19)
+
+#define NV5070_CTRL_CMD_MAX_HEADS                       4U
+#define NV5070_CTRL_CMD_MAX_DACS                        4U
+#define NV5070_CTRL_CMD_MAX_SORS                        8U
+#define NV5070_CTRL_CMD_MAX_PIORS                       4U
+
+#define NV5070_CTRL_CMD_OR_OWNER_NONE                   (0xFFFFFFFFU)
+#define NV5070_CTRL_CMD_OR_OWNER_HEAD(i)                                (i)
+#define NV5070_CTRL_CMD_OR_OWNER_HEAD__SIZE_1           NV5070_CTRL_CMD_MAX_HEADS
+
+#define NV5070_CTRL_CMD_SOR_OWNER_MASK_NONE             (0x00000000U)
+#define NV5070_CTRL_CMD_SOR_OWNER_MASK_HEAD(i)                          (1 << i)
+
+#define NV5070_CTRL_CMD_DAC_PROTOCOL_RGB_CRT            (0x00000000U)
+
+
+
+#define NV5070_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_A      (0x00000000U)
+#define NV5070_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_B      (0x00000001U)
+#define NV5070_CTRL_CMD_SOR_PROTOCOL_DUAL_TMDS          (0x00000002U)
+#define NV5070_CTRL_CMD_SOR_PROTOCOL_LVDS_CUSTOM        (0x00000003U)
+#define NV5070_CTRL_CMD_SOR_PROTOCOL_DP_A               (0x00000004U)
+#define NV5070_CTRL_CMD_SOR_PROTOCOL_DP_B               (0x00000005U)
+#define NV5070_CTRL_CMD_SOR_PROTOCOL_SUPPORTED          (0xFFFFFFFFU)
+
+#define NV5070_CTRL_CMD_PIOR_PROTOCOL_EXT_TMDS_ENC      (0x00000000U)
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h
new file mode 100644
index 0000000..5154638
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h
@@ -0,0 +1,143 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5070/ctrl5070event.finn
+//
+
+#include "ctrl/ctrl5070/ctrl5070base.h"
+
+/* NV50_DISPLAY event-related control commands and parameters */
+
+/*
+ * NV5070_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * This command sets event notification state for the NV50_DISPLAY object.
+ * This command requires that an instance of NV01_EVENT has been previously
+ * bound to the NV50_DISPLAY object.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the NV50_DISPLAY
+ *     parent device to which the operation should be directed.  This parameter
+ *     must specify a value between zero and the total number of subdevices
+ *     within the parent device.  This parameter should be set to zero for
+ *     default behavior.
+ *   hEvent
+ *     This parameter specifies the handle of the NV01_EVENT instance
+ *     to be bound to the given subDeviceInstance.
+ *   event
+ *     This parameter specifies the type of event to which the specified
+ *     action is to be applied.  This parameter must specify a valid
+ *     NOTIFIERS value of display class.
+ *   action
+ *     This parameter specifies the desired event notification action.
+ *     Valid notification actions include:
+ *       NV5070_CTRL_SET_EVENT_NOTIFICATION_DISABLE
+ *         This action disables event notification for the specified
+ *         event for the associated subdevice object.
+ *       NV5070_CTRL_SET_EVENT_NOTIFICATION_SINGLE
+ *         This action enables single-shot event notification for the
+ *         specified event for the associated subdevice object.
+ *       NV5070_CTRL_SET_EVENT_NOTIFICATION_REPEAT
+ *         This action enables repeated event notification for the specified
+ *         event for the associated system controller object.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV5070_CTRL_CMD_EVENT_SET_NOTIFICATION (0x50700901) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
+    NvU32    subDeviceInstance;
+    NvHandle hEvent;
+    NvU32    event;
+    NvU32    action;
+} NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
+#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  (0x00000001)
+#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  (0x00000002)
+
+
+/*
+ * NV5070_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * This command triggers a software event for the NV50_DISPLAY object.
+ * This command accepts no parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV5070_CTRL_CMD_EVENT_SET_TRIGGER                 (0x50700902) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | 0x2" */
+
+
+/*
+ * NV5070_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
+ *
+ *     hMemory
+ *       This parameter specifies the handle of the memory object
+ *       that identifies the memory address translation for this
+ *       subdevice instance's notification(s).  The beginning of the
+ *       translation points to an array of notification data structures.
+ *       The size of the translation must be at least large enough to hold the
+ *       maximum number of notification data structures.
+ *       Legal argument values must be instances of the following classes:
+ *         NV01_NULL
+ *         NV04_MEMORY
+ *       When hMemory specifies the NV01_NULL_OBJECT value then any existing
+ *       memory translation connection is cleared.  There must not be any
+ *       pending notifications when this command is issued.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV5070_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES         (0x50700903) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
+    NvU32    subDeviceInstance;
+    NvHandle hMemory;
+} NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
+
+#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0
+#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_PENDING  1
+#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_ERROR    2
+
+
+
+/* _ctrl5070event_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h
new file mode 100644
index 0000000..11b79b2
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h
@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5070/ctrl5070impoverrides.finn
+//
+
+
+
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h
new file mode 100644
index 0000000..0052168
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h
@@ -0,0 +1,936 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5070/ctrl5070or.finn
+//
+
+#include "ctrl5070common.h"
+#include "ctrl/ctrl5070/ctrl5070base.h"
+
+
+
+/*
+ * NV5070_CTRL_CMD_SET_DAC_PWR
+ *
+ * This command sets the DAC power control register. orNumber, normalPower,
+ * and safePower will always have to be specified. However, HSync, VSync,
+ * and data for normal and/or safe mode can be empty, leaving the current
+ * values intact.
+ *
+ *      orNumber
+ *          The dac for which the settings need to be programmed.
+ *
+ *      normalHSync
+ *          The normal operating state for the H sync signal.
+ *
+ *      normalVSync
+ *          The normal operating state for the V sync signal.
+ *
+ *      normalData
+ *          The normal video data input pin of the d/a converter.
+ *
+ *      normalPower
+ *          The normal state of the dac macro power.
+ *
+ *      safeHSync
+ *          The safe operating state for the H sync signal.
+ *
+ *      safeVSync
+ *          The safe operating state for the V sync signal.
+ *
+ *      safeData
+ *          The safe video data input pin of the d/a converter.
+ *
+ *      safePower
+ *          The safe state of the dac macro power.
+ *
+ *      flags
+ *          The following flags have been defined:
+ *              (1) SPECIFIED_NORMAL: Indicates whether HSync, VSync, data,
+ *                  for normal state have been specified in the parameters.
+ *              (2) SPECIFIED_SAFE: Indicates whether HSync, VSync, data,
+ *                  for safe state have been specified in the parameters.
+ *              (3) SPECIFIED_FORCE_SWITCH: Indicates whether to force the
+ *                  change immediately instead of waiting for VSync
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ *      NV_ERR_TIMEOUT
+ */
+#define NV5070_CTRL_CMD_SET_DAC_PWR                            (0x50700404) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC                            1:0
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC_ENABLE        (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC_LO            (0x00000001)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC_HI            (0x00000002)
+
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC                            1:0
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC_ENABLE        (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC_LO            (0x00000001)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC_HI            (0x00000002)
+
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA                             1:0
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA_ENABLE         (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA_LO             (0x00000001)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA_HI             (0x00000002)
+
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_PWR                              0:0
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_PWR_OFF             (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_PWR_ON              (0x00000001)
+
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC                              1:0
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC_ENABLE          (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC_LO              (0x00000001)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC_HI              (0x00000002)
+
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC                              1:0
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC_ENABLE          (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC_LO              (0x00000001)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC_HI              (0x00000002)
+
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA                               1:0
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA_ENABLE           (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA_LO               (0x00000001)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA_HI               (0x00000002)
+
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_PWR                                0:0
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_PWR_OFF               (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_PWR_ON                (0x00000001)
+
+#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_NORMAL                  0:0
+#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_NORMAL_NO  (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_NORMAL_YES (0x00000001)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_SAFE                    1:1
+#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_SAFE_NO    (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_SAFE_YES   (0x00000001)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_FORCE_SWITCH                      2:2
+#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_FORCE_SWITCH_NO      (0x00000000)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_FORCE_SWITCH_YES     (0x00000001)
+#define NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+
+    NvU32                       normalHSync;
+    NvU32                       normalVSync;
+    NvU32                       normalData;
+    NvU32                       normalPower;
+    NvU32                       safeHSync;
+    NvU32                       safeVSync;
+    NvU32                       safeData;
+    NvU32                       safePower;
+    NvU32                       flags;
+} NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS;
+
+
+
+/*
+ * NV5070_CTRL_CMD_GET_SOR_PWM
+ *
+ * This command returns SOR's current PWM settings.
+ *
+ *      orNumber
+ *          The OR number for which the seq ctrls are to be modified.
+ *
+ *      targetFreq
+ *          The target PWM freq. This is the PWM frequency we planned on
+ *          programming.
+ *
+ *      actualFreq
+ *          Actual PWM freq programmed into PWM.
+ *
+ *      div
+ *          The divider being used currently for generating PWM clk.
+ *          A valued of 0 means that PWM is disabled.
+ *
+ *      resolution
+ *          The resolution of steps currently programmed or the max number of
+ *          clocks per cycle. The possible values for NV50 are 128, 256, 512
+ *          and 1024. This field is irrelevant when div is 0.
+ *
+ *      dutyCycle
+ *          Duty cycle in range 0-1024
+ *
+ *      sourcePCLK (OUT)
+ *          The PWM source clock selector. This field is non-zero if the PCLK
+ *          is selected as the PWM source clock. Otherwise, the PWM source
+ *          clock is XTAL.
+ *
+ *      head (IN)
+ *          The head for which the pixel clock is sourced from.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_GET_SOR_PWM                                (0x50700420) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+    NvU32                       targetFreq;
+    NvU32                       actualFreq;
+    NvU32                       div;
+    NvU32                       resolution;
+    NvU32                       dutyCycle;
+    NvU32                       sourcePCLK;
+    NvU32                       head;
+} NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS;
+
+
+/*
+ * NV5070_CTRL_CMD_SET_SOR_PWM
+ *
+ * This command returns SOR's current PWM settings.
+ *
+ *      orNumber
+ *          The OR number for which the seq ctrls are to be modified.
+ *
+ *      targetFreq
+ *          The target PWM freq to be programmed.
+ *
+ *      actualFreq
+ *          Actual PWM freq programmed into PWM after all the specified
+ *          settings have been applied.
+ *
+ *      div
+ *          The divider to use for generating PWM clk.
+ *          Set this to 0 to disable PWM. Note that only one of div
+ *          or targetFreq can be specified at a time since specifying one
+ *          automatically determines the value of the other. Selection is
+ *          done via USE_SPECIFIED_DIV flag.
+ *
+ *      resolution
+ *          The resolution or the max number of clocks per cycle desired.
+ *          Note that if it's not possible to program the given resolution
+ *          and frequency (or div) combination, RM would not attempt to
+ *          smartly lower the resolution. The call would return failure.
+ *          The possible values for NV50 are 128, 256, 512 and 1024. This
+ *          field is irrelevant when div is 0.
+ *
+ *      dutyCycle
+ *          Duty cycle in range 0-1024
+ *
+ *      flags
+ *          The following flags have been defined:
+ *              (1) USE_SPECIFIED_DIV: Indicates whether RM should use
+ *                  specified div or targetFreq when determining the divider
+ *                  for xtal clock.
+ *              (2) PROG_DUTY_CYCLE: Indicates whether or not the caller
+ *                  desires to program duty cycle. Normally whenever pwm freq
+ *                  and range need to be programmed, it's expected that duty
+ *                  cycle would be reprogrammed as well but this is not
+ *                  enforced.
+ *              (3) PROG_FREQ_AND_RANGE: Indicates whether or not the caller
+ *                  desires to program a new PWM setting (div and resolution).
+ *              (4) SOURCE_CLOCK: Indicates whether the PCLK or XTAL is used
+ *                  as the PWM clock source. GT21x and better.
+ *
+ *      head (IN)
+ *          The head for which the pixel clock is sourced from.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_SET_SOR_PWM                               (0x50700421) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV                 0:0
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV_NO    (0x00000000)
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV_YES   (0x00000001)
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE                   1:1
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE_NO      (0x00000000)
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE_YES     (0x00000001)
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE               2:2
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE_NO  (0x00000000)
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE_YES (0x00000001)
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK                      3:3
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK_XTAL       (0x00000000)
+#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK_PCLK       (0x00000001)
+
+#define NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+    NvU32                       targetFreq;
+    NvU32                       actualFreq;
+    NvU32                       div;                  // equivalent of NV_PDISP_SOR_PWM_DIV_DIVIDE
+    NvU32                       resolution;           // equivalent of NV_PDISP_SOR_PWM_DIV_RANGE
+    NvU32                       dutyCycle;
+    NvU32                       flags;
+    NvU32                       head;
+} NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS;
+
+
+/*
+ * NV5070_CTRL_CMD_GET_SOR_OP_MODE
+ *
+ * This command returns current settings for the specified SOR.
+ *
+ *      orNumber
+ *          The OR number for which the operating mode needs to be read.
+ *
+ *      category
+ *          Whether LVDS or CSTM setting are desired.
+ *
+ *      puTxda
+ *          Status of data pins of link A
+ *
+ *      puTxdb
+ *          Status of data pins of link B
+ *
+ *      puTxca
+ *          Status of link A clock
+ *
+ *      puTxcb
+ *          Status of link B clock
+ *
+ *      upper
+ *          Whether LVDS bank A is the upper, odd, or first pixel.
+ *
+ *      mode
+ *          Current protocol.
+ *
+ *      linkActA
+ *          Status of link B clock
+ *
+ *      linkActB
+ *          Status of link B clock
+ *
+ *      lvdsEn
+ *          Output driver configuration.
+ *
+ *      lvdsDual
+ *          Whether LVDS dual-link mode is turned on or not.
+ *
+ *      dupSync
+ *          Whether DE, HSYNC, and VSYNC are used for encoding instead of
+ *          RES, CNTLE, and CNTLF.
+ *
+ *      newMode
+ *          Whether new or old mode is being used.
+ *
+ *      balanced
+ *          Whether balanced encoding is enabled.
+ *
+ *      plldiv
+ *          Feedback divider for the hi-speed pll
+ *
+ *      rotClk
+ *          Skew of TXC clock.
+ *
+ *      rotDat
+ *          How much are the 8 bits of each color channel rotated by
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE                   (0x50700422) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY                            0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY_LVDS     0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY_CUSTOM   0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0                           0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1                           1:1
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2                           2:2
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3                           3:3
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3_ENABLE  0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0                           0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1                           1:1
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2                           2:2
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3                           3:3
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3_ENABLE  0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA                             0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA_DISABLE   0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA_ENABLE    0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB                             0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB_DISABLE   0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB_ENABLE    0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_UPPER                               0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_UPPER_UPPER_RESET 0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE                                0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE_LVDS         0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE_TMDS         0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA                            0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA_DISABLE  0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA_ENABLE   0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB                            0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB_DISABLE  0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB_ENABLE   0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN                             0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN_DISABLE   0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN_ENABLE    0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL                           0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL_ENABLE  0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC                            0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC_DISABLE  0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC_ENABLE   0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE                            0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE_DISABLE  0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE_ENABLE   0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED                            0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED_DISABLE  0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED_ENABLE   0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV                              0:0
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV_BY_7       0x00000000
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV_BY_10      0x00000001
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_ROTCLK                              3:0
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_ROTDAT                              2:0
+
+#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+
+    NvU32                       category;
+    NvU32                       puTxda;
+    NvU32                       puTxdb;
+    NvU32                       puTxca;
+    NvU32                       puTxcb;
+    NvU32                       upper;
+    NvU32                       mode;
+    NvU32                       linkActA;
+    NvU32                       linkActB;
+    NvU32                       lvdsEn;
+    NvU32                       lvdsDual;
+    NvU32                       dupSync;
+    NvU32                       newMode;
+    NvU32                       balanced;
+    NvU32                       plldiv;
+    NvU32                       rotClk;
+    NvU32                       rotDat;
+} NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS;
+
+
+/*
+ * NV5070_CTRL_CMD_SET_SOR_OP_MODE
+ *
+ * This command applies the specified settings to the specified SOR.
+ *
+ *      orNumber
+ *          The OR number for which the operating mode needs to be read.
+ *          Note that if DCB doesn't report LVDS for the specified orNumber,
+ *          the call will return failure.
+ *
+ *      category
+ *          Whether LVDS or CSTM settings are specified.
+ *
+ *      puTxda
+ *          Used to enable or disable the data pins of link A.
+ *
+ *      puTxdb
+ *          Used to enable or disable the data pins of link B.
+ *
+ *      puTxca
+ *          Used to enable or disable link A clock.
+ *
+ *      puTxcb
+ *          Used to enable or disable link B clock.
+ *
+ *      upper
+ *          Whether LVDS bank A should be the upper, odd, or first pixel.
+ *
+ *      mode
+ *          What protocol (LVDS/TMDS to use).
+ *
+ *      linkActA
+ *          Used to enable or disable the digital logic of link A.
+ *
+ *      linkActB
+ *          Used to enable or disable the digital logic of link B.
+ *
+ *      lvdsEn
+ *          Output driver configuration.
+ *
+ *      lvdsDual
+ *          Whether to turn on LVDS dual-link mode.
+ *
+ *      dupSync
+ *          Whether to use DE, HSYNC, and VSYNC for encoding instead of
+ *          RES, CNTLE, and CNTLF.
+ *
+ *      newMode
+ *          Whether to use new or old mode.
+ *
+ *      balanced
+ *          Whether or not to use balanced encoding.
+ *
+ *      plldiv
+ *          Feedback divider to use for the hi-speed pll.
+ *
+ *      rotClk
+ *          How much to skew TXC clock.
+ *
+ *      rotDat
+ *          How much to rotate the 8 bits of each color channel by.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE                   (0x50700423) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY                            0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY_LVDS     0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY_CUSTOM   0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0                           0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1                           1:1
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2                           2:2
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3                           3:3
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3_ENABLE  0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0                           0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1                           1:1
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2                           2:2
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2_ENABLE  0x00000001
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3                           3:3
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3_ENABLE  0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA                             0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA_DISABLE   0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA_ENABLE    0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB                             0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB_DISABLE   0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB_ENABLE    0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_UPPER                               0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_UPPER_UPPER_RESET 0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE                                0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE_LVDS         0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE_TMDS         0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA                            0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA_DISABLE  0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA_ENABLE   0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB                            0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB_DISABLE  0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB_ENABLE   0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN                             0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN_DISABLE   0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN_ENABLE    0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL                           0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL_DISABLE 0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL_ENABLE  0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC                            0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC_DISABLE  0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC_ENABLE   0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE                            0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE_DISABLE  0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE_ENABLE   0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED                            0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED_DISABLE  0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED_ENABLE   0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV                              0:0
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV_BY_7       0x00000000
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV_BY_10      0x00000001
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_ROTCLK                              3:0
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_ROTDAT                              2:0
+
+#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+
+    NvU32                       category;
+    NvU32                       puTxda;
+    NvU32                       puTxdb;
+    NvU32                       puTxca;
+    NvU32                       puTxcb;
+    NvU32                       upper;
+    NvU32                       mode;
+    NvU32                       linkActA;
+    NvU32                       linkActB;
+    NvU32                       lvdsEn;
+    NvU32                       lvdsDual;
+    NvU32                       dupSync;
+    NvU32                       newMode;
+    NvU32                       balanced;
+    NvU32                       plldiv;
+    NvU32                       rotClk;
+    NvU32                       rotDat;
+} NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_GET_PIOR_OP_MODE
+ *
+ * This command returns current settings for the specified PIOR.
+ *
+ *      orNumber
+ *          The OR number for which the operating mode needs to be programmed.
+ *
+ *      category
+ *          Whether ext TMDS, TV, DRO or DRI settings are desired.
+ *          EXT TV is not supported at the moment.
+ *          EXT DisplayPort is specified through EXT 10BPC 444.
+ *
+ *      clkPolarity
+ *          Whether or not output clock is inverted relative to generated clock.
+ *
+ *      clkMode
+ *          Whether data being transmitted is SDR or DDR.
+ *
+ *      clkPhs
+ *          Position of the edge on which data is launched.
+ *
+ *      unusedPins
+ *          Status of unused pins of this PIOR.
+ *
+ *      polarity
+ *          Whether or not sync and DE pin polarities are inverted.
+ *
+ *      dataMuxing
+ *          How are the bits are multiplexed together.
+ *
+ *      clkDelay
+ *          Extra delay for the clock.
+ *
+ *      dataDelay
+ *          Extra delay for the data.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE                        (0x50700430) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY                           2:0
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_TMDS      0x00000000
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_TV        0x00000001
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_DRO           0x00000003
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_DRI           0x00000004
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_10BPC_444 0x00000005
+
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY                       0:0
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY_NORMAL    0x00000000
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY_INV       0x00000001
+
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE                           0:0
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE_SDR           0x00000000
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE_DDR           0x00000001
+
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS                            1:0
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_0              0x00000000
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_1              0x00000001
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_2              0x00000002
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_3              0x00000003
+
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS                        0:0
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS_LO         0x00000000
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS_TS         0x00000001
+
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H                         0:0
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H_NORMAL      0x00000000
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H_INV         0x00000001
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V                         1:1
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V_NORMAL      0x00000000
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V_INV         0x00000001
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE                        2:2
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE_NORMAL     0x00000000
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE_INV        0x00000001
+
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING                        3:0
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_RGB_0      0x00000000
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_RGB_1      0x00000001
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_DIST_RNDR  0x00000003
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_YUV_0      0x00000004
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_UYVY       0x00000005
+
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_DLY                            2:0
+
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_DLY                           2:0
+
+#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS_MESSAGE_ID (0x30U)
+
+typedef struct NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+
+    NvU32                       category;
+    NvU32                       clkPolarity;
+    NvU32                       clkMode;
+    NvU32                       clkPhs;
+    NvU32                       unusedPins;
+    NvU32                       polarity;
+    NvU32                       dataMuxing;
+    NvU32                       clkDelay;
+    NvU32                       dataDelay;
+} NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS;
+
+
+/*
+ * NV5070_CTRL_CMD_SET_PIOR_OP_MODE
+ *
+ * This command applies the specified settings to the specified PIOR.
+ *
+ *      orNumber
+ *          The OR number for which the operating mode needs to be programmed.
+ *
+ *      category
+ *          Whether ext TMDS, TV, DRO or DRI settings are to be programmed.
+ *          EXT TV is not supported at the moment.
+ *          EXT DisplayPort is specified through EXT 10BPC 444.
+ *
+ *      clkPolarity
+ *          Whether or not to invert output clock relative to generated clock.
+ *
+ *      clkMode
+ *          Whether data being transmitted should be SDR or DDR.
+ *
+ *      clkPhs
+ *          Position of the edge on which data should be launched.
+ *
+ *      unusedPins
+ *          What to do with unused pins of this PIOR.
+ *
+ *      polarity
+ *          Whether or not to invert sync and DE pin polarities.
+ *
+ *      dataMuxing
+ *          How to multiplex the bits together.
+ *
+ *      clkDelay
+ *          Extra delay for the clock.
+ *
+ *      dataDelay
+ *          Extra delay for the data.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE                           (0x50700431) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY                           2:0
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_TMDS         0x00000000
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_TV           0x00000001
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_DRO              0x00000003
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_DRI              0x00000004
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_10BPC_444    0x00000005
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY                       0:0
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY_NORMAL       0x00000000
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY_INV          0x00000001
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE                           0:0
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE_SDR              0x00000000
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE_DDR              0x00000001
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS                            1:0
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_0                 0x00000000
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_1                 0x00000001
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_2                 0x00000002
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_3                 0x00000003
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS                        0:0
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS_LO            0x00000000
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS_TS            0x00000001
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H                         0:0
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H_NORMAL         0x00000000
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H_INV            0x00000001
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V                         1:1
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V_NORMAL         0x00000000
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V_INV            0x00000001
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE                        2:2
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE_NORMAL        0x00000000
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE_INV           0x00000001
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING                        3:0
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_RGB_0         0x00000000
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_RGB_1         0x00000001
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_DIST_RNDR     0x00000003
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_YUV_0         0x00000004
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_UYVY          0x00000005
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_DLY                            2:0
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_DLY                           2:0
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_MASTER                         1:0
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET                  2:0
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_NEITHER 0
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_A       1
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_B       2
+
+
+#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS_MESSAGE_ID (0x31U)
+
+typedef struct NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+
+    NvU32                       category;
+    NvU32                       clkPolarity;
+    NvU32                       clkMode;
+    NvU32                       clkPhs;
+    NvU32                       unusedPins;
+    NvU32                       polarity;
+    NvU32                       dataMuxing;
+    NvU32                       clkDelay;
+    NvU32                       dataDelay;
+    NvU32                       dro_master;
+    NvU32                       dro_drive_pin_set;
+} NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_SET_SOR_FLUSH_MODE
+ *
+ * Set the given SOR number into flush mode in preparation for DP link training.
+ *
+ *   orNumber [in]
+ *     The SOR number to set into flush mode.
+ *
+ *   bEnable [in]
+ *     Whether to enable or disable flush mode on this SOR.
+ * 
+ *   bImmediate [in]
+ *     If set to true, will enable flush in immediate mode.
+ *     If not, will enable flush in loadv mode.
+ *     NOTE: We do not support exit flush in LoadV mode.
+ * 
+ *   headMask [in]
+ *     Optional.  If set brings only the heads in the head mask out of flush
+ *     OR will stay in flush mode until last head is out of flush mode.
+ *     Caller can use _HEAD__ALL to specify all the heads are to be brought out.
+ *     NOTE: headMask would be considered only while exiting from flush mode.
+ * 
+ *   bForceRgDiv [in]
+ *      If set forces RgDiv. Should be used only for HW/SW testing
+ * 
+ *   bUseBFM [in]
+ *      If Set then it mean we are using BFM else executing on non-BFM paltforms.
+ * 
+ *   bFireAndForget [in]
+ *       Fire the flush mode & perform post-processing without waiting for it
+ *       to be done. This is required for special cases like GC5 where we have
+ *       ELV blocked, RG stall & we trigger flush for one shot mode & then do
+ *       a modeset by disabling it without actually waiting for it to get
+ *       disabled. We will not get any vblank interrupt in this case as we have
+ *       stalled RG.
+ * 
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV5070_CTRL_CMD_SET_SOR_FLUSH_MODE (0x50700457) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID (0x57U)
+
+typedef struct NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       sorNumber;
+    NvBool                      bEnable;
+    NvBool                      bImmediate;
+    NvU32                       headMask;
+    NvBool                      bForceRgDiv;
+    NvBool                      bUseBFM;
+    NvBool                      bFireAndForget;
+} NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS;
+
+#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD(i)          (i):(i)
+#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD__SIZE_1 NV5070_CTRL_CMD_MAX_HEADS
+#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD_ALL     0xFFFFFFFF
+
+
+
+/* _ctrl5070or_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h
new file mode 100644
index 0000000..64269d8
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h
@@ -0,0 +1,578 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5070/ctrl5070rg.finn
+//
+
+#include "ctrl/ctrl5070/ctrl5070base.h"
+
+
+
+/*
+ * NV5070_CTRL_CMD_GET_RG_STATUS
+ *
+ * This 'get' command returns the status of raster generator
+ *
+ *      head
+ *          The head for which RG status is desired.
+ *
+ *      scanLocked
+ *          Whether or not RG is scan (raster or frame) locked.
+ *      flipLocked
+ *          Whether or not RG is flip locked.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_GET_RG_STATUS                (0x50700202) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_RG_STATUS_SCANLOCKED_NO  (0x00000000)
+#define NV5070_CTRL_CMD_GET_RG_STATUS_SCANLOCKED_YES (0x00000001)
+
+#define NV5070_CTRL_CMD_GET_RG_STATUS_FLIPLOCKED_NO  (0x00000000)
+#define NV5070_CTRL_CMD_GET_RG_STATUS_FLIPLOCKED_YES (0x00000001)
+
+#define NV5070_CTRL_CMD_GET_RG_STATUS_STALLED_NO     (0x00000000)
+#define NV5070_CTRL_CMD_GET_RG_STATUS_STALLED_YES    (0x00000001)
+
+#define NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       head;
+
+    NvU32                       scanLocked;           // [OUT]
+    NvU32                       flipLocked;           // [OUT]
+    NvU32                       rgStalled;
+} NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_UNDERFLOW_PARAMS
+ *
+ * This structure contains data for
+ * NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP and
+ * NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP CTRL calls
+ *
+ *   head
+ *     The head for which RG underflow properties needed to be set/get.
+ *     Valid values for this parameter are 0 to NV5070_CTRL_CMD_MAX_HEADS.
+ *   enable
+ *     _SET_RG_: Whether to enable or disable RG underflow reporting.
+ *     _GET_RG_: Whether or not RG underflow reporting is enabled.
+ *   underflow
+ *     _SET_RG_: Clear underflow (CLEAR_UNDERFLOW_YES) or leave it alone
+ *               (CLEAR_UNDERFLOW_NO).
+ *               Note: The GET_RG function automatically clears the underflow.
+ *               It is recommended that GET_RG be used to clear any initial
+ *               underflows, and that the "underflow" field be set to
+ *               CLEAR_UNDERFLOW_NO in any SET_RG calls.  This field may be
+ *               deprecated in the future, for SET_RG calls.
+ *     _GET_RG_: UNDERFLOWED_YES if an RG underflow occurred since the most
+ *               recent prior call to to NV5070_CTRL_CMD_GET_RG_STATUS.
+ *   epfifoUnderflow
+ *     _SET_RG_: Not used.
+ *     _GET_RG_: EPFIFO_UNDERFLOWED_YES if an EPFIFO underflow occurred since
+ *               the most recent prior call to NV5070_CTRL_CMD_GET_RG_STATUS.
+ *   mode
+ *     _SET_RG_: What mode to use when underflow occurs. This is
+ *               independent from enable field. This is always active.
+ *     _GET_RG_: What mode is used when underflow occurs. This is
+ *               independent from enable field. This is always active.
+ */
+typedef struct NV5070_CTRL_CMD_UNDERFLOW_PARAMS {
+    NvU32 head;
+    NvU32 enable;
+    NvU32 underflow;
+    NvU32 epfifoUnderflow;
+    NvU32 mode;
+} NV5070_CTRL_CMD_UNDERFLOW_PARAMS;
+
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_NO             (0x00000000)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_YES            (0x00000001)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_NO         (0x00000000)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_YES        (0x00000001)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_EPFIFO_UNDERFLOWED_NO  (0x00000000)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_EPFIFO_UNDERFLOWED_YES (0x00000001)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_REPEAT            (0x00000000)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_RED               (0x00000001)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_NO              (0x00000000)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_YES             (0x00000001)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_NO     (0x00000000)
+#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_YES    (0x00000001)
+
+/*
+ * NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP
+ *
+ * This command returns the underflow reporting parameters inside
+ * NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure
+ *
+ *   underflowParams
+ *     Contains data for underflow logging.
+ *     Check NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP                 (0x50700203) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS      base;
+    NV5070_CTRL_CMD_UNDERFLOW_PARAMS underflowParams;
+} NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS;
+
+
+/*
+ * NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP
+ *
+ * This command sets up the underflow parameters using
+ * NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure
+ *
+ *   underflowParams
+ *     Contains data for underflow logging.
+ *     Check NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP (0x50700204) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS      base;
+    NV5070_CTRL_CMD_UNDERFLOW_PARAMS underflowParams;
+} NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS;
+
+
+/*
+ * NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP
+ *
+ * This command gets the timing parameters associated with the lockout period.
+ *
+ *      head
+ *          The head for which RG fliplock properties are desired.
+ *
+ *      maxSwapLockoutSkew
+ *          The maximum possible skew between the swap lockout signals for all
+ *          heads which are fliplocked to this head.
+ *
+ *      swapLockoutStart
+ *          Determines the start of the start lockout period, expressed as the
+ *          number of lines before the end of the frame. The minimum allowed
+ *          value is 1.
+
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP (0x50700205) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW          9:0
+
+#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START            15:0
+
+#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       head;
+
+    NvU32                       maxSwapLockoutSkew;
+    NvU32                       swapLockoutStart;
+} NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP
+ *
+ * This command sets the timing parameters associated with the lockout period.
+ *
+ *      head
+ *          The head for which RG fliplock properties are desired.
+ *
+ *      maxSwapLockoutSkew
+ *          The maximum possible skew between the swap lockout signals for all
+ *          heads which are fliplocked to this head.
+ *
+ *      swapLockoutStart
+ *          Determines the start of the start lockout period, expressed as the
+ *          number of lines before the end of the frame. The minimum allowed
+ *          value is 1.
+
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP                            (0x50700206) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW      9:0
+#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW_INIT (0x00000000)
+
+#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START         15:0
+#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START_INIT    (0x00000000)
+
+#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       head;
+
+    NvU32                       maxSwapLockoutSkew;
+    NvU32                       swapLockoutStart;
+} NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN
+ *
+ * This command returns which lockpin has been connected for the specified
+ * subdevice in the current SLI and/or framelock configuration.
+ *
+ *      head
+ *          The head for which the locking is associated with
+ *
+ *      masterScanLock
+ *          Indicate the connection status and pin number of master scanlock
+ *
+ *      slaveScanLock
+ *          Indicate the connection status and pin number of slave scanlock
+ *
+ *      flipLock
+ *          Indicate the connection status and pin number of fliplock
+ *
+ *      stereoLock
+ *          Indicate the connection status and pin number of stereo lock
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ */
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN                                (0x50700207) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED     0:0
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_NO  (0x00000000)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_YES (0x00000001)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_PIN           3:1
+
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED      0:0
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_NO   (0x00000000)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_YES  (0x00000001)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_PIN            3:1
+
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED       0:0
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_NO         (0x00000000)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_YES        (0x00000001)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_PIN             3:1
+
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED     0:0
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_NO       (0x00000000)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_YES      (0x00000001)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_PIN           3:1
+
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       head;
+
+    NvU32                       masterScanLock;
+    NvU32                       slaveScanLock;
+    NvU32                       flipLock;
+    NvU32                       stereoLock;
+} NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_SET_VIDEO_STATUS
+ *
+ * This command is used to set the current video playback status for use
+ * by the Display Power Saving (nvDPS) feature.  The playback status is
+ * used to maximize power savings by altering the DFP refresh rate used for
+ * video playback.
+ *
+ *   displayId
+ *     This parameter specifies the ID of the video playback display.
+ *     Only one display may be indicated in this parameter.
+ *   clientId
+ *     This parameter specifies the opaque client ID associated with
+ *     the video playback application.
+ *   mode
+ *     This parameter specifies the video playback mode.  Valid values
+ *     for this parameter include:
+ *       NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_NON_FULLSCREEN
+ *         This value indicates that there is either no video playback or
+ *         that video playback is windowed.
+ *       NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_FULLSCREEN
+ *         This value indicates that video playback is fullscreen.
+ *       NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_D3D
+ *         This value indicates that there is a D3D app started.
+ *   frameRate
+ *     The parameter indicates the current video playback frame rate.
+ *     The value is a 32 bit unsigned fixed point number, 24 bit unsigned
+ *     integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in
+ *     number of frames per second.
+ *     A value of 0 indicates that video playback is stopped or not playing.
+ *   frameRateAlarmUpperLimit
+ *     The parameter indicates the upper limit which will can be tolerated in
+ *     notifying frame rate change. If the frame rate changed but is still
+ *     below the limit. The newer frame rate doesn't have to be set till it's
+ *     over the limit.
+ *     The value is a 32 bit unsigned fixed point number, 24 bit unsigned
+ *     integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in
+ *     number of frames per second.
+ *     A value of 0 indicates no tolerance of frame rate notifying. Instant
+ *     frame rate has to be set when it has changed.
+ *   frameRateAlarmLowerLimit
+ *     The parameter indicates the lower limit which will can be tolerated in
+ *     notifying frame rate change. If the frame rate changed but is still
+ *     above the limit. The newer frame rate doesn't have to be set till it's
+ *     below the limit.
+ *     The value is a 32 bit unsigned fixed point number, 24 bit unsigned
+ *     integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in
+ *     number of frames per second.
+ *     A value of 0 indicates no tolerance of frame rate notifying. Instant
+ *     frame rate has to be set when it has changed.
+ *
+ *     The frameRateAlarm limit values can be used by the video client to
+ *     indicate the the range in which frame rate changes do not require
+ *     notification (i.e. frame rates outside these limits will result in
+ *     notification).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV5070_CTRL_CMD_SET_VIDEO_STATUS (0x50700209) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+
+    NvU32                       displayId;
+    NvU32                       clientId;
+    NvU32                       mode;
+    NvU32                       frameRate;
+    NvU32                       frameRateAlarmUpperLimit;
+    NvU32                       frameRateAlarmLowerLimit;
+} NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS;
+
+/* valid mode flags */
+#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_NON_FULLSCREEN                              (0x00000000)
+#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_FULLSCREEEN                                 (0x00000001)
+#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_D3D                                         (0x00000002)
+
+/*
+ * NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS
+ *
+ * This command returns which set of lockpins needs to be used in order to
+ * successfully raster lock two heads on different GPUs together.  The
+ * second GPU is not inferred from linked SLI state, if any, and needs to
+ * be specified explicitly.
+ *
+ *   head
+ *     The local head to be locked with the peer head.
+ *
+ *   peer.hDisplay
+ *     The handle identifying a display object allocated on another
+ *     GPU.  It specifies the peer of interest with a subdevice
+ *     index (see below) and needs to be be distinct from the handle
+ *     supplied directly to NvRmControl().
+ *
+ *   peer.subdeviceIndex
+ *     The index of the peer subdevice of interest.
+ *
+ *   peer.head
+ *     The peer head to be locked with the local head.
+ *
+ *   masterScanLockPin
+ *   slaveScanLockPin
+ *     Returns the master and slave scanlock pins that would need to
+ *     be used to lock the specified heads together, if any.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_OBJECT_PARENT
+ */
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS                                (0x5070020a) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED     0:0
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED_NO  (0x00000000)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED_YES (0x00000001)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_PIN           2:1
+
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED      0:0
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED_NO   (0x00000000)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED_YES  (0x00000001)
+#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_PIN            2:1
+
+#define NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       head;
+
+    struct {
+        NvHandle hDisplay;
+        NvU32    subdeviceIndex;
+        NvU32    head;
+    } peer;
+
+    NvU32 masterScanLock;
+    NvU32 slaveScanLock;
+} NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_GET_PINSET_LOCKPINS
+ *
+ * Get the lockpins for the specified pinset.
+ *
+ *   pinset [in]
+ *     The pinset whose corresponding lockpin numbers need to be determined
+ *     must be specified with this parameter.
+ *
+ *   scanLockPin [out]
+ *     The scanlock lockpin (rasterlock or framelock) index, which can be
+ *     either master or slave, is returned in this parameter.
+ *
+ *   flipLockPin [out]
+ *     The fliplock lockpin index, is returned in this parameter.
+ *
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV5070_CTRL_CMD_GET_PINSET_LOCKPINS                (0x5070020b) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_GET_PINSET_LOCKPINS_SCAN_LOCK_PIN_NONE 0xffffffff
+
+#define NV5070_CTRL_GET_PINSET_LOCKPINS_FLIP_LOCK_PIN_NONE 0xffffffff
+
+#define NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       pinset;
+    NvU32                       scanLockPin;
+    NvU32                       flipLockPin;
+} NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_GET_RG_SCAN_LINE
+ *
+ * This 'get' command returns the current scan line value from raster generator 
+ *
+ *      head
+ *          The head for which current scan line number is desired.
+ * 
+ *      scanLine
+ *          Current scan line number.
+ *
+ *      inVblank
+ *          Whether or not in vblank.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE               (0x5070020c) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_IN_VBLANK_NO  (0x00000000)
+#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_IN_VBLANK_YES (0x00000001)
+
+#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       head;
+    NvU32                       scanLine;             // [OUT]
+    NvU32                       inVblank;             // [OUT]
+} NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_GET_FRAMELOCK_HEADER_LOCKPINS
+ *
+ * This command returns FrameLock header lock pin information.
+ * Lock pin index returned by this command corresponds to the 
+ * evo lock pin number. Example - lock pin index 0 means 
+ * LOCKPIN_0. 
+ *
+ *   frameLockPin [out]
+ *     This parameter returns the FrameLock pin index 
+ *     connected to FrameLock header.
+ *
+ *   rasterLockPin [out]
+ *     This parameter returns the RasterLock pin index 
+ *     connected to FrameLock header.
+ *    
+ *   flipLockPin [out]
+ *     This parameter returns the FlipLock pin index 
+ *     connected to FrameLock header.
+ *
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED   
+ */
+
+#define NV5070_CTRL_CMD_GET_FRAMELOCK_HEADER_LOCKPINS                  (0x5070020d) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_FRAME_LOCK_PIN_NONE  (0xffffffff)
+#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_RASTER_LOCK_PIN_NONE (0xffffffff)
+#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_FLIP_LOCK_PIN_NONE   (0xffffffff)
+#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       frameLockPin;
+    NvU32                       rasterLockPin;
+    NvU32                       flipLockPin;
+} NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS;
+
+
+
+/* _ctrl5070rg_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h
new file mode 100644
index 0000000..0da723f
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h
@@ -0,0 +1,521 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5070/ctrl5070seq.finn
+//
+
+#include "ctrl/ctrl5070/ctrl5070base.h"
+
+/*
+ * NV5070_CTRL_CMD_GET_SOR_SEQ_CTL
+ *
+ * This command returns SOR sequencer's power up and down PCs and sequencer
+ * program to be used for power up and dowm.
+ *
+ *      orNumber
+ *          The OR number for which the seq ctrls are to be modified.
+ *
+ *      puPcAlt
+ *          Alternate power up PC.
+ *
+ *      pdPc
+ *          Power down PC.
+ *
+ *      pdPcAlt
+ *          Alternate power down PC.
+ *
+ *      normalStart
+ *          Whether normal mode is using normal or alt PC
+ *
+ *      safeStart
+ *          Whether safe mode is using normal or alt PC
+ *
+ *      normalState
+ *          Whether normal state is PD or PU.
+ *
+ *      safeState
+ *          Whether safe state is PD or PU.
+ *
+ *      flags
+ *          There is only one flag defined currently
+ *              1. GET_SEQ_PROG: Whether or not current seq program must be
+ *                 return back. Caller should set this to _YES to read the
+ *                 current seq program.
+ *
+ *      seqProgram
+ *          The sequencer program consisting of power up and down sequences.
+ *          For NV50, this consists of 16 DWORDS. The program is
+ *          relevant only when GET_SEQ_PROG flags is set to _YES.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL                         (0x50700301U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PU_PC_ALT_VALUE                     3:0
+
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PD_PC_VALUE                         3:0
+
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PD_PC_ALT_VALUE                     3:0
+
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL                    0:0
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U)
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL_ALT    (0x00000001U)
+
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL                      0:0
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL_NORMAL   (0x00000000U)
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL_ALT      (0x00000001U)
+
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL                    0:0
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PD     (0x00000000U)
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PU     (0x00000001U)
+
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL                      0:0
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL_PD       (0x00000000U)
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL_PU       (0x00000001U)
+
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG                  0:0
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_NO   (0x00000000U)
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_YES  (0x00000001U)
+
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SEQ_PROG_SIZE           16U
+#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+
+    NvU32                       puPcAlt;
+    NvU32                       pdPc;
+    NvU32                       pdPcAlt;
+    NvU32                       normalStart;
+    NvU32                       safeStart;
+    NvU32                       normalState;
+    NvU32                       safeState;
+    NvU32                       flags;
+    NvU32                       seqProgram[NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SEQ_PROG_SIZE];
+} NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_SET_SOR_SEQ_CTL
+ *
+ * This command does the following in that order
+ * (a) Loads a specified sequencer program for power up and down.
+ * (b) Updates SOR sequencer's power up and down PCs, tells seq to SKIP
+ * current wait for vsync and waits until sequencer actually SKIPs or halts
+ * (see more below under SKIP_WAIT_FOR_VSYNC flag) and
+ * (c) Update power settings (safe/normal start and state).
+ *
+ *      orNumber
+ *          The OR number for which the seq ctrls are to be modified.
+ *
+ *      puPcAlt
+ *          Alternate power up PC.
+ *
+ *      pdPc
+ *          Power down PC.
+ *
+ *      pdPcAlt
+ *          Alternate power down PC.
+ *
+ *      normalStart
+ *          Whether normal mode should use normal or alt PC.
+ *
+ *      safeStart
+ *          Whether safe mode should use normal or alt PC.
+ *
+ *      normalState
+ *          Whether normal state should be PD or PU.
+ *
+ *      safeState
+ *          Whether safe state should be PD or PU.
+ *
+ *      flags
+ *          The following flags have been defined
+ *              1. SKIP_WAIT_FOR_VSYNC: Should seq be forced to skip waiting
+ *                 for vsync if it's currently waiting on such an instruction.
+ *                 If the current instruction doesn't have a wait for vsync,
+ *                 SKIP will be applied to the next one and so on until
+ *                 either sequencer halts or an instruction with a wait for
+ *                 vsync is found. The call will block until seq halts or
+ *                 SKIPs a wait for vsync.
+ *              2. SEQ_PROG_PRESENT: Whether or not a new seq program has
+ *                 been specified.
+ *
+ *      seqProgram
+ *          The sequencer program consisting of power up and down sequences.
+ *          For NV50, this consists of 16 DWORDS. The program is
+ *          relevant only when SEQ_PROG_PRESENT flags is set to _YES.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL                               (0x50700302U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_VALUE                     3:0
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED               31:31
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_NO        (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_YES       (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_VALUE                         3:0
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED                   31:31
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED_NO            (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED_YES           (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_VALUE                     3:0
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED               31:31
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_NO        (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_YES       (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL                    0:0
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL_NORMAL       (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL_ALT          (0x00000001U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED            31:31
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED_NO     (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED_YES    (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL                      0:0
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL_NORMAL         (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL_ALT            (0x00000001U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED              31:31
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED_NO       (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED_YES      (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL                    0:0
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PD           (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PU           (0x00000001U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED            31:31
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_NO     (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_YES    (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL                      0:0
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL_PD             (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL_PU             (0x00000001U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED              31:31
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED_NO       (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED_YES      (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC               0:0
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_NO  (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_YES (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT                   1:1
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_NO     (0x00000000U)
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_YES    (0x00000001U)
+
+
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SEQ_PROG_SIZE                 16U
+#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+
+    NvU32                       puPcAlt;
+    NvU32                       pdPc;
+    NvU32                       pdPcAlt;
+    NvU32                       normalStart;
+    NvU32                       safeStart;
+    NvU32                       normalState;
+    NvU32                       safeState;
+    NvU32                       flags;
+    NvU32                       seqProgram[NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SEQ_PROG_SIZE];
+} NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL
+ *
+ * This command returns PIOR sequencer's power up and down PCs and sequencer
+ * program to be used for power up and dowm.
+ *
+ *      orNumber
+ *          The OR number for which the seq ctrls are to be modified.
+ *
+ *      puPcAlt
+ *          Alternate power up PC.
+ *
+ *      pdPc
+ *          Power down PC.
+ *
+ *      pdPcAlt
+ *          Alternate power down PC.
+ *
+ *      normalStart
+ *          Whether normal mode is using normal or alt PC
+ *
+ *      safeStart
+ *          Whether safe mode is using normal or alt PC
+ *
+ *      normalState
+ *          Whether normal state is PD or PU.
+ *
+ *      safeState
+ *          Whether safe state is PD or PU.
+ *
+ *      flags
+ *          There is only one flag defined currently
+ *              1. GET_SEQ_PROG: Whether or not current seq program must be
+ *                 return back. Caller should set this to _YES to read the
+ *                 current seq program.
+ *
+ *      seqProgram
+ *          The sequencer program consisting of power up and down sequences.
+ *          For NV50, this consists of 16 DWORDS. The program is
+ *          relevant only when GET_SEQ_PROG flags is set to _YES.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL                         (0x50700303U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PU_PC_ALT_VALUE                    3:0
+
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PD_PC_VALUE                        3:0
+
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PD_PC_ALT_VALUE                    3:0
+
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL                   0:0
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U)
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL_ALT    (0x00000001U)
+
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL                     0:0
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL_NORMAL   (0x00000000U)
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL_ALT      (0x00000001U)
+
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL                   0:0
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PD     (0x00000000U)
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PU     (0x00000001U)
+
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL                     0:0
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PD       (0x00000000U)
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PU       (0x00000001U)
+
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG                 0:0
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_NO   (0x00000000U)
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_YES  (0x00000001U)
+
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SEQ_PROG_SIZE           8U
+#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+
+    NvU32                       puPcAlt;
+    NvU32                       pdPc;
+    NvU32                       pdPcAlt;
+    NvU32                       normalStart;
+    NvU32                       safeStart;
+    NvU32                       normalState;
+    NvU32                       safeState;
+    NvU32                       flags;
+    NvU32                       seqProgram[NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SEQ_PROG_SIZE];
+} NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL
+ *
+ * This command does the following in that order
+ * (a) Loads a specified sequencer program for power up and down.
+ * (b) Updates PIOR sequencer's power up and down PCs, tells seq to SKIP
+ * current wait for vsync and waits until sequencer actually SKIPs or halts
+ * (see more below under SKIP_WAIT_FOR_VSYNC flag) and
+ * (c) Update power settings (safe/normal start and state).
+ *
+ *      orNumber
+ *          The OR number for which the seq ctrls are to be modified.
+ *
+ *      puPcAlt
+ *          Alternate power up PC.
+ *
+ *      pdPc
+ *          Power down PC.
+ *
+ *      pdPcAlt
+ *          Alternate power down PC.
+ *
+ *      normalStart
+ *          Whether normal mode should use normal or alt PC
+ *
+ *      safeStart
+ *          Whether safe mode should use normal or alt PC
+ *
+ *      normalState
+ *          Whether normal state should be PD or PU.
+ *
+ *      safeState
+ *          Whether safe state should be PD or PU.
+ *
+ *      flags
+ *          The following flags have been defined
+ *              1. SKIP_WAIT_FOR_VSYNC: Should seq be forced to skip waiting
+ *                 for vsync if it's currently waiting on such an instruction.
+ *                 If the current instruction doesn't have a wait for vsync,
+ *                 SKIP will be applied to the next one and so on until
+ *                 either sequencer halts or an instruction with a wait for
+ *                 vsync is found. The call will block until seq halts or
+ *                 SKIPs a wait for vsync.
+ *              2. SEQ_PROG_PRESENT: Whether or not a new seq program has
+ *                 been specified.
+ *
+ *      seqProgram
+ *          The sequencer program consisting of power up and down sequences.
+ *          For NV50, this consists of 8 DWORDS. The program is
+ *          relevant only when SEQ_PROG_PRESENT flags is set to _YES.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ */
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL                               (0x50700304U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_VALUE                    3:0
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED              31:31
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_NO        (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_YES       (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_VALUE                        3:0
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED                  31:31
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED_NO            (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED_YES           (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_VALUE                    3:0
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED              31:31
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_NO        (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_YES       (0x00000001U)
+
+
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL                        0:0
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL_NORMAL       (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL_ALT          (0x00000001U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED                31:31
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED_NO     (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED_YES    (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL                          0:0
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL_NORMAL         (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL_ALT            (0x00000001U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED                  31:31
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED_NO       (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED_YES      (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL                        0:0
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PD           (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PU           (0x00000001U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED                31:31
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_NO     (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_YES    (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL                          0:0
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PD             (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PU             (0x00000001U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED                  31:31
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED_NO       (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED_YES      (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC              0:0
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_NO  (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_YES (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT                  1:1
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_NO     (0x00000000U)
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_YES    (0x00000001U)
+
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SEQ_PROG_SIZE                 8U
+#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       orNumber;
+
+    NvU32                       puPcAlt;
+    NvU32                       pdPc;
+    NvU32                       pdPcAlt;
+    NvU32                       normalStart;
+    NvU32                       safeStart;
+    NvU32                       normalState;
+    NvU32                       safeState;
+    NvU32                       flags;
+    NvU32                       seqProgram[NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SEQ_PROG_SIZE];
+} NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS;
+
+/*
+ * NV5070_CTRL_CMD_CTRL_SEQ_PROG_SPEED
+ *
+ * This call allows a fast sequencer program to be selected. It's intended for
+ * situations where panel sequencing is not required and the usual sequencing
+ * delays cost too much time.
+ *
+ *     displayId
+ *       The corresponding display ID. (Note that this call is currently only
+ *       supported for LVDS on an internal encoder, i.e. a SOR.)
+ *     cmd
+ *       The command to perform. Valid values are:
+ *         NV5070_CTRL_SEQ_PROG_SPEED_CMD_GET
+ *           Get the current state.
+ *         NV5070_CTRL_SEQ_PROG_SPEED_CMD_SET
+ *           Set the current state.
+ *     state
+ *       The state of panel sequencing for this displayId. This is an input
+ *       when cmd = SET and an output when cmd = GET.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_PARAM_STRUCT
+ *    NV_ERR_NOT_SUPPORTED
+ *
+ */
+
+#define NV5070_CTRL_CMD_CTRL_SEQ_PROG_SPEED     (0x50700305U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_SEQ_PROG_SPEED_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_SEQ_PROG_SPEED_CMD_GET      (0x00000000U)
+#define NV5070_CTRL_SEQ_PROG_SPEED_CMD_SET      (0x00000001U)
+
+#define NV5070_CTRL_SEQ_PROG_SPEED_STATE_NORMAL (0x00000000U)
+#define NV5070_CTRL_SEQ_PROG_SPEED_STATE_FAST   (0x00000001U)
+
+#define NV5070_CTRL_SEQ_PROG_SPEED_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV5070_CTRL_SEQ_PROG_SPEED_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+
+    NvU32                       displayId;
+
+    NvU32                       cmd;
+    NvU32                       state;
+} NV5070_CTRL_SEQ_PROG_SPEED_PARAMS;
+
+/* _ctrl5070seq_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h
new file mode 100644
index 0000000..bbb07e6
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h
@@ -0,0 +1,81 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5070/ctrl5070system.finn
+//
+
+#include "ctrl/ctrl5070/ctrl5070base.h"
+#include "ctrl/ctrl5070/ctrl5070common.h" // NV5070_CTRL_CMD_MAX_HEADS
+
+/* extract cap bit setting from tbl */
+#define NV5070_CTRL_SYSTEM_GET_CAP(tbl,c)         (((NvU8)tbl[(1?c)]) & (0?c)) 
+
+/* caps format is byte_index:bit_mask */
+#define NV5070_CTRL_SYSTEM_CAPS_BUG_237734_REQUIRES_DMI_WAR                 0:0x01 // Deprecated
+#define NV5070_CTRL_SYSTEM_CAPS_STEREO_DIN_AVAILABLE                        0:0x02
+#define NV5070_CTRL_SYSTEM_CAPS_BUG_381003_MULTIWAY_AFR_WAR                 0:0x04
+#define NV5070_CTRL_SYSTEM_CAPS_BUG_538079_COLOR_COMPRESSION_SUPPORTED      0:0x08 // Deprecated
+#define NV5070_CTRL_SYSTEM_CAPS_BUG_2052012_GLITCHY_MCLK_SWITCH             0:0x10
+#define NV5070_CTRL_SYSTEM_CAPS_DEEP_COLOR_SUPPORT                          0:0x20
+#define NV5070_CTRL_SYSTEM_CAPS_BUG_644815_DNISO_VIDMEM_ONLY                0:0x40
+
+
+/* size in bytes of display caps table */
+#define NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE   1
+
+/*
+ * NV5070_CTRL_CMD_SYSTEM_GET_CAPS_V2
+ *
+ * This command returns the set of display capabilities for the parent device
+ * in the form of an array of unsigned bytes.  Display capabilities
+ * include supported features and required workarounds for the display
+ * engine(s) within the device, each represented by a byte offset into the
+ * table and a bit position within that byte.  The set of display capabilities
+ * will be normalized across all GPUs within the device (a feature capability
+ * will be set only if it's supported on all GPUs while a required workaround
+ * capability will be set if any of the GPUs require it).
+ *
+ *   [out] capsTbl
+ *     This caps table array is where the display cap bits will be transferred
+ *     by the RM. The caps table is an array of unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV5070_CTRL_CMD_SYSTEM_GET_CAPS_V2 (0x50700709) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID << 8) | NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS {
+    NV5070_CTRL_CMD_BASE_PARAMS base;
+
+    NvU8                        capsTbl[NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE];
+} NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS;
+
+/* _ctrl5070system_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h
new file mode 100644
index 0000000..6741891
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5070/ctrl5070verif.finn
+//
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5080.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5080.h
new file mode 100644
index 0000000..777bdab
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5080.h
@@ -0,0 +1,212 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl5080.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl0080/ctrl0080dma.h"  /* NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS */
+#include "ctrl/ctrl2080/ctrl2080dma.h"  /* NV2080_CTRL_DMA_* */
+#include "ctrl/ctrl2080/ctrl2080fb.h"   /* NV2080_CTRL_FB_* */
+#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_* */
+#include "ctrl/ctrl2080/ctrl2080gpu.h"  /* NV2080_CTRL_GPU_* */
+#include "ctrl/ctrl2080/ctrl2080gr.h"   /* NV2080_CTRL_GR_* */
+/* NV5080_DEFERRED_API - deferred RmControl commands */
+
+
+#define NV5080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x5080, NV5080_CTRL_##cat,idx)
+
+/* Command categories (6bits) */
+#define NV5080_CTRL_RESERVED (0x00)
+#define NV5080_CTRL_DEFERRED (0x01)
+
+/*
+ * NV5080_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ */
+#define NV5080_CTRL_CMD_NULL (0x50800000) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+
+/*
+ * NV5080_CTRL_CMD_DEFERRED_API (deprecated; use NV5080_CTRL_CMD_DEFERRED_API_V2 instead)
+ *
+ * This command sets up a deferred api call.
+ *    hApiHandle
+ *      Client Unique Handle which is used as the data of a sw method to invoke
+ *      the api in the future
+ *    cmd
+ *      The rmcontrol cmd to invoke as a deferred api.
+ *    flags_delete
+ *      Indicates if an explicit delete is needed (default behavior is to
+ *      auto delete after SW method has executed/completed).
+ *    flags_wait_for_tlb_flush
+ *      Indicates if the API should wait for an InvalidateTlb to also occur
+ *      (not just that it's executed) before being considered completed and
+ *      works in conjunction with flags_delete.
+ *    hClientVA, hDeviceVA
+ *      Client/Device handles of the owner of the virtual address space to
+ *      to be updated (used with the FillPteMem API bundle)
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV5080_CTRL_CMD_DEFERRED_API (0x50800101) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_DEFERRED_API_PARAMS_MESSAGE_ID" */
+
+#define NV5080_CTRL_DEFERRED_API_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV5080_CTRL_DEFERRED_API_PARAMS {
+    NvHandle hApiHandle;
+    NvU32    cmd;
+    NvU32    flags;
+    NvHandle hClientVA;
+    NvHandle hDeviceVA;
+
+    union {
+        NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS InitCtx, 8);
+
+        NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PromoteCtx, 8);
+
+        NV2080_CTRL_GPU_EVICT_CTX_PARAMS                 EvictCtx;
+
+        NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS            InvalidateTlb;
+
+        NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS FillPteMem, 8);
+
+        NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS     CacheAllocPolicy;
+
+        NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS ZcullCtxsw, 8);
+
+        NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS PmCtxsw, 8);
+
+        NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS CachePromotePolicy;
+
+        NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS PreemptionCtxsw, 8);
+    } api_bundle;
+} NV5080_CTRL_DEFERRED_API_PARAMS;
+
+#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE                       0:0
+#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE_EXPLICIT          (0x00000001)
+#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE_IMPLICIT          (0x00000000)
+
+#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH           1:1
+#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH_FALSE (0x00000000)
+#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH_TRUE  (0x00000001)
+/*
+ * NV5080_CTRL_CMD_DEFERRED_API_V2
+ *
+ * This command sets up a deferred api call.
+ *    hApiHandle
+ *      Client Unique Handle which is used as the data of a sw method to invoke
+ *      the api in the future
+ *    cmd
+ *      The rmcontrol cmd to invoke as a deferred api.
+ *    flags_delete
+ *      Indicates if an explicit delete is needed (default behavior is to
+ *      auto delete after SW method has executed/completed).
+ *    flags_wait_for_tlb_flush
+ *      Indicates if the API should wait for an InvalidateTlb to also occur
+ *      (not just that it's executed) before being considered completed and
+ *      works in conjunction with flags_delete.
+ *    hClientVA, hDeviceVA
+ *      Client/Device handles of the owner of the virtual address space to
+ *      to be updated (used with the FillPteMem API bundle)
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV5080_CTRL_CMD_DEFERRED_API_V2                             (0x50800103) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_DEFERRED_API_V2_PARAMS_MESSAGE_ID" */
+
+#define NV5080_CTRL_DEFERRED_API_V2_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV5080_CTRL_DEFERRED_API_V2_PARAMS {
+    NvHandle hApiHandle;
+    NvU32    cmd;
+    NvU32    flags;
+    NvHandle hClientVA;
+    NvHandle hDeviceVA;
+
+    union {
+        NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS InitCtx, 8);
+
+        NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PromoteCtx, 8);
+
+        NV2080_CTRL_GPU_EVICT_CTX_PARAMS                 EvictCtx;
+
+        NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS            InvalidateTlb;
+
+        NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS FillPteMem, 8);
+
+        NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS  CacheAllocPolicy;
+
+        NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS ZcullCtxsw, 8);
+
+        NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS PmCtxsw, 8);
+
+        NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS CachePromotePolicy;
+
+        NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS DisableChannels, 8);
+
+        NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS PreemptionCtxsw, 8);
+
+        NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS ChannelInfoUpdate, 8);
+    } api_bundle;
+} NV5080_CTRL_DEFERRED_API_V2_PARAMS;
+
+/*
+ * NV5080_CTRL_CMD_REMOVE_API
+ *
+ * This command removes an explicit deferred api call.
+ *    hApiHandle
+ *      Client Unique Handle which is used as the data of a sw method to invoke
+ *      the api in the future
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV5080_CTRL_CMD_REMOVE_API (0x50800102) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_REMOVE_API_PARAMS_MESSAGE_ID" */
+
+#define NV5080_CTRL_REMOVE_API_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV5080_CTRL_REMOVE_API_PARAMS {
+    NvHandle hApiHandle;
+} NV5080_CTRL_REMOVE_API_PARAMS;
+
+/* _ctrl5080_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de.h
new file mode 100644
index 0000000..12d792a
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de.h
@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2011-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl83de.finn
+//
+
+
+
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl83de/ctrl83dedebug.h"
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h
new file mode 100644
index 0000000..6ab74be
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h
@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl83de/ctrl83debase.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* GT200_DEBUG control commands and parameters */
+
+#define NV83DE_CTRL_CMD(cat,idx)             NVXXXX_CTRL_CMD(0x83DEU, NV83DE_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NV83DE_CTRL_RESERVED (0x00)
+#define NV83DE_CTRL_GR       (0x01)
+#define NV83DE_CTRL_FIFO     (0x02)
+#define NV83DE_CTRL_DEBUG    (0x03)
+#define NV83DE_CTRL_INTERNAL (0x04)
+
+
+/*
+ * NV83DE_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV83DE_CTRL_CMD_NULL (0x83de0000) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* _ctrl83debase_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h
new file mode 100644
index 0000000..c4c36b0
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h
@@ -0,0 +1,1106 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl83de/ctrl83dedebug.finn
+//
+
+#include "ctrl/ctrl83de/ctrl83debase.h"
+#include "nvstatus.h"
+
+#include "ctrl/ctrl2080/ctrl2080gpu.h"
+
+
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG
+ *
+ * This command sets the MMU DEBUG mode.  This is Fermi-onwards feature.
+ * If the query is made on an incorrect platform (for example, pre-Fermi)
+ * the call will return with an NV_ERR_NOT_SUPPORTED error.
+ *
+ *   action
+ *     The possible action values are:
+ *   - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE
+ *      This enables the MMU debug mode if possible. If however, any another
+ *      client has already disabled the mode (via NV83DE call) then this
+ *      operation returns  NV_ERR_STATE_IN_USE.
+ *
+ *   - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE
+ *      This disables the MMU debug mode if possible. If however, any another
+ *      client has already enabled the mode (via NV83DE call) then this
+ *      operation returns  NV_ERR_STATE_IN_USE.
+ *
+ *   - NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS
+ *      This operation releases all the client's outstanding requests to enable
+ *      or disable the MMU debug mode.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG (0x83de0307) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS {
+    NvU32 action;
+} NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS;
+
+#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE  (0x00000001)
+#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE (0x00000002)
+#define NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS (0x00000003)
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG
+ *
+ * This command gets the value of currently configured MMU DEBUG mode.
+ * This is Fermi-onwards feature. If the query is made on an incorrect
+ * platform (for example, pre-Fermi) the call will return with an
+ * NV_ERR_NOT_SUPPORTED error.
+ *
+ *   value
+ *     This parameter returns the configured value.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG         (0x83de0308) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS {
+    NvU32 value;
+} NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS;
+
+#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED  (0x00000001)
+#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED (0x00000002)
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK
+ *
+ * This command allows the caller to filter events (which are also referred to
+ * as "notifications", not to be confused with true notifiers), in the RM,
+ * fairly close to the source of the events. In other words, depending on the
+ * value of the exceptionMask, some events may not be raised.
+ *
+ * The original reason for creating this command is that the CUDA driver needs
+ * to place the RM and the GPU(s) into SM debug mode, for some GPUs, in order to
+ * activate various features and HW bug WARs. Being in SM debug mode has the
+ * side effect of exposing the caller to debug events, which are generally
+ * undesirable for the CUDA driver, but desirable for the CUDA debugger. This
+ * command allows each client to receive only the events that it is
+ * specifically interested in.
+ *
+ * If this command is never invoked, then the RM will behave as if
+ * exceptionMask==NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL.
+ *
+ * As with many of the debugger features, this is Fermi-onwards feature. If this
+ * API call is issued on an earlier platform, it will return an
+ * NV_ERR_NOT_SUPPORTED error.
+ *
+ *   exceptionMask
+ *     This identifies the category of notifications that the debug client
+ *     is interested in.
+ *
+ *     Here are the allowed values for exceptionMask:
+ *
+ *     - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL
+ *       This means that the caller wishes to receive events for any exceptions
+ *       that are classified as fatal. For example,
+ *       HWW_WARP_ESR_ERROR_PC_OVERFLOW is one such exception.
+ *
+ *       If any debug object, in any channel, has registered to receive events
+ *       for _FATAL exceptions, then RC recovery will be deferred if such an
+ *       exception occurs.
+ *
+ *       Also, if a client is registered for fatal exceptions, RC error recovery
+ *       will be deferred.  If not registered for fatal exceptions, then fatal
+ *       errors will (as usual) cause RC recovery to run immediately.
+ *
+ *     - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP
+ *       This means that an event will be raised when an SM executes a bpt.pause
+ *       instruction. Note that on Fermi, the SM raises HWW when bpt.trap is
+ *       executed as well, so this event will also be raised in that situation.
+ *
+ *     - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP
+ *       This means that an event will be raised a single step completion
+ *       interrupt is received.
+ *
+ *     - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT
+ *       This means that an event will be raised when an SM executes a bpt.int
+ *       instruction.
+ *
+ *     - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE
+ *       This means that no debug events will be raised.
+ *
+ *     - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL
+ *       This means that an event will be raised for any and all debug
+ *       exceptions. This is the default behavior.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK          (0x83de0309) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS {
+    NvU32 exceptionMask;
+} NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS;
+
+#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL              (0x00000001)
+#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP               (0x00000002)
+#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP        (0x00000004)
+#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT                (0x00000008)
+#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP               (0x00000010)
+#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED (0x00000020)
+#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE               (0x00000000)
+#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL                (0x0000FFFF)
+
+
+
+/*
+ * NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE
+ *
+ * This command reads the SM error state of a single SM. The error state
+ * consists of several 32-bit values.
+ *
+ * Note that this acts upon the currently resident GR (graphics) context. It is
+ * up to the RM client to ensure that the desired GR context is resident, before
+ * making this API call.
+ *
+ * See also: NV83DE_CTRL_CMD_READ_ALL_SM_ERROR_STATES.
+ *
+ * This is a Fermi-and-later feature. If this API call is issued on an earlier
+ * platform, it will return an NV_ERR_NOT_SUPPORTED error.
+ *
+ * Parameters:
+ *
+ *   hTargetChannel (input)
+ *     This identifies the channel.
+ *
+ *   smID (input)
+ *     This identifies the SM. Allowed values are any valid SM ID. The RM
+ *     grProgramSmIdNumbering_HAL() routines are a good place to look, in order
+ *     to see how SM IDs are set up. The main idea is that the RM chooses a
+ *     numbering scheme, and then informs the GPU hardware of that scheme, by
+ *     actually recording each SM ID into the GPU, via a series of PRI (GPU
+ *     register) writes.
+ *
+ *   smErrorState.hwwGlobalEsr (output)
+ *     Value of the Global Error Status Register.
+ *
+ *   smErrorState.hwwWarpEsr (output)
+ *     Value of the Warp Error Status Register.
+ *
+ *   smErrorState.hwwWarpEsrPc (output) : DEPRECATED for 64b PC below, will hold low 32b for now
+ *     Value of the Warp Error Status Register Program Counter.
+ *
+ *   smErrorState.hwwGlobalEsrReportMask (output)
+ *     Value of the Global Error Status Register Report Mask.
+ *
+ *   smErrorState.hwwWarpEsrReportMask (output)
+ *     Value of the Error Status Register Report Mask.
+ *
+ *   smErrorState.hwwWarpEsrPc64 (output)
+ *     Value of the 64b Warp Error Status Register Program Counter.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE (0x83de030b) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID" */
+
+typedef struct NV83DE_SM_ERROR_STATE_REGISTERS {
+    NvU32 hwwGlobalEsr;
+    NvU32 hwwWarpEsr;
+    NvU32 hwwWarpEsrPc;
+    NvU32 hwwGlobalEsrReportMask;
+    NvU32 hwwWarpEsrReportMask;
+    NV_DECLARE_ALIGNED(NvU64 hwwEsrAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 hwwWarpEsrPc64, 8);
+    NvU32 hwwCgaEsr;
+    NvU32 hwwCgaEsrReportMask;
+} NV83DE_SM_ERROR_STATE_REGISTERS;
+
+#define NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS {
+    NvHandle hTargetChannel;
+    NvU32    smID;
+    NV_DECLARE_ALIGNED(NV83DE_SM_ERROR_STATE_REGISTERS smErrorState, 8);
+} NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_READ_ALL_SM_ERROR_STATES
+ *
+ * This command reads the SM error state of all SMs.
+ *
+ * Note that this acts upon the currently resident GR (graphics) context. It is
+ * up to the RM client to ensure that the desired GR context is resident, before
+ * making this API call.
+ *
+ * Parameters:
+ *
+ *   hTargetChannel (input)
+ *     This identifies the channel.
+ *
+ *   numSMsToRead (input)
+ *     This should be set to the number of SMs that the RM is supposed to read.
+ *     It will typically be the total number of SMs in the GPU. For best
+ *     results, you should not pass in a value that is greater than the number
+ *     of SMs that the GPU actually contains.
+ *
+ *   startingSM (input)
+ *      This should be set to the starting index of the first SM to read.
+ *      Clients may use this to read data from SMs beyond the maximum specified
+ *      in NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL.
+ *
+ *   smErrorStateArray (output)
+ *     This is an array of NV83DE_SM_ERROR_STATE_REGISTERS structs. Please see
+ *     the description of NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE, above, for
+ *     a description of the individual fields.
+ *
+ *   mmuFault.valid (output)
+ *     This is NV_TRUE if an MMU fault occurred on the target channel since the last call to
+ *     NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES to this channel.
+ *
+ *   mmuFault.faultInfo (output)
+ *     This is the value of the first NV_PFIFO_INTR_MMU_FAULT_INFO that caused the MMU fault.
+ *
+ *   mmuFaultInfo (output)
+ *     Deprecated field, see mmuFault.faultInfo
+ *
+ * This is a Fermi-and-later feature. If this API call is issued on an earlier
+ * platform, it will return an NV_ERR_NOT_SUPPORTED error.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES (0x83de030c) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL             100
+
+typedef struct NV83DE_MMU_FAULT_INFO {
+    NvBool valid;
+    NvU32  faultInfo;
+} NV83DE_MMU_FAULT_INFO;
+
+#define NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS {
+    NvHandle              hTargetChannel;
+    NvU32                 numSMsToRead;
+    NV_DECLARE_ALIGNED(NV83DE_SM_ERROR_STATE_REGISTERS smErrorStateArray[NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL], 8);
+    NvU32                 mmuFaultInfo;       // Deprecated, use mmuFault field instead
+    NV83DE_MMU_FAULT_INFO mmuFault;
+    NvU32                 startingSM;
+} NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_CLEAR_SINGLE_SM_ERROR_STATE
+ *
+ * This command clears the SM error state of a single SM. The error state
+ * consists of several 32-bit values.
+ *
+ * Note that this acts upon the currently resident GR (graphics) context. It is
+ * up to the RM client to ensure that the desired GR context is resident, before
+ * making this API call.
+ *
+ * See also: NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES.
+ *
+ * This API call has a slightly different effect than what would occur as a
+ * result of issuing a read-modify-write via _READ_SINGLE_SM_ERROR_STATE and
+ * _WRITE_SINGLE_SM_ERROR_STATE. The difference arises due to the fact that RM
+ * is caching the error state, to compensate for the fact that the real GPU
+ * error state must be cleared very early on in the exception handling routine.
+ *
+ * In other words, the _READ data is stale by design, and cannot be used in a
+ * read-modify-write routine from user space. Therefore, in order to clear the
+ * SM error state, a separate RM API call is required.
+ *
+ * This is a Fermi-and-later feature. If this API call is issued on an earlier
+ * platform, it will return an NV_ERR_NOT_SUPPORTED error.
+ *
+ * Parameters:
+ *
+ *   hTargetChannel (input)
+ *     This identifies the channel.
+ *
+ *   smID (input)
+ *     This identifies the SM. Allowed values are any valid SM ID. Please see
+ *     NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE for further details.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE (0x83de030f) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS {
+    NvHandle hTargetChannel;
+    NvU32    smID;
+} NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES
+ *
+ * This command clears the SM error state of all SMs.
+ *
+ * Note that this acts upon the currently resident GR (graphics) context. It is
+ * up to the RM client to ensure that the desired GR context is resident, before
+ * making this API call.
+ *
+ * Parameters:
+ *
+ *   hTargetChannel (input)
+ *     This identifies the channel.
+ *
+ *   numSMsToClear (input)
+ *     This should be set to the number of SMs that the RM is supposed to write.
+ *     It will typically be the total number of SMs in the GPU. For best
+ *     results, you should not pass in a value that is greater than the number
+ *     of SMs that the GPU actually contains.
+ *
+ *     Please see the description of
+ *     NV83DE_CTRL_CMD_CLEAR_SINGLE_SM_ERROR_STATE, above, for a description of
+ *     why these two _CLEAR API calls are required.
+ *
+ * This is a Fermi-and-later feature. If this API call is issued on an earlier
+ * platform, it will return an NV_ERR_NOT_SUPPORTED error.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES (0x83de0310) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS {
+    NvHandle hTargetChannel;
+    NvU32    numSMsToClear;
+} NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS;
+
+
+
+#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED       1
+#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL 1
+typedef struct NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS {
+    NvU32    waitForEvent;
+    NvHandle hResidentChannel;
+} NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS;
+
+
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE
+ *
+ * This command set the type of action we want on RM encountering an error
+ * and issuing a STOP_TRIGGER. The action will be to either braodcast the
+ * STOP_TRIGGER to all SM's, or just send to the SM hitting an exception.
+ *
+ *   stopTriggerType
+ *     This identifies trigger type to initiate.
+ *
+ *     Here are the allowed values for stopTriggerType:
+ *
+ *     - NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM
+ *       This means that we will issue STOP_TRIGGER to the single SM
+ *       noted in the exception
+ *
+ *     - NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCAST
+ *       This means that we will issue STOP_TRIGGER to all SM's
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE     (0x83de0313) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS {
+    NvU32 stopTriggerType;
+} NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS;
+
+#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM   (0x00000001)
+#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT   (0x00000002)
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING
+ *
+ * This command sets the type of action we want on RM encountering a
+ * SINGLE_STEP exception while in CILP debug mode.  In the normal case,
+ * non-pausing, we ignore these exceptions as on prior chips.  When the
+ * user selects pausing, it will cause the exception to be treated just
+ * like we had seen an SM error or BPT_PAUSE.
+ *
+ *   singleStepHandling
+ *     This identifies single step handling type to use.
+ *
+ *     Here are the allowed values for singleStepHandling:
+ *
+ *     - NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING
+ *       Treat SINGLE_STEP exceptions while in debug mode as non-pausing,
+ *       which is the default/normal mode in the interrupt pre-process
+ *       function, where they are ignored.
+ *
+ *     - NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING
+ *       Treat SINGLE_STEP exceptions while in debug mode as pausing,
+ *       which means in the interrupt pre-process function they will
+ *       be treated like BPT_PAUSE and SM error exceptions
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING (0x83de0314) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS {
+    NvU32 singleStepHandling;
+} NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS;
+
+#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING (0x00000001)
+#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING    (0x00000002)
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_READ_MEMORY
+ *
+ *   This command reads a block of memory.
+ *   This command is deprecated in favor of NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY
+ *
+ *   hMemory [IN]
+ *       The handle to the memory being accessed. If hMemory is not accessible
+ *       from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS
+ *       is returned.
+ *
+ *   length [IN/OUT]
+ *       Number of bytes to read, as well as the number of bytes actually read
+ *       returned.
+ *
+ *   offset [IN]
+ *      The offset into the physical memory region given by the handle above.
+ *
+ *   buffer [OUT]
+ *       The data read is returned in this buffer.
+ *
+ * Possible status values returned are
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ *    NV_ERR_INVALID_ACCESS_TYPE
+ *    NV_ERR_INSUFFICIENT_PERMISSIONS
+ *
+ */
+#define NV83DE_CTRL_CMD_DEBUG_READ_MEMORY                               (0x83de0315) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS {
+    NvU32 hMemory;
+    NvU32 length;
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+    NV_DECLARE_ALIGNED(NvP64 buffer, 8);
+} NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY
+ *
+ *   This command writes a block of memory.
+ *   This command is deprecated in favor of NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY
+ *
+ *   hMemory [IN]
+ *       The handle to the memory being accessed. If hMemory is not accessible
+ *       from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS
+ *       is returned.
+ *
+ *   length [IN/OUT]
+ *       Number of bytes to write, as well as the number of bytes actually
+ *       written.
+ *
+ *   offset [IN]
+ *      The offset into the physical memory region given by the handle above.
+ *
+ *   buffer [IN]
+ *       The data to be written is sent in this buffer.
+ *
+ * Possible status values returned are
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ *    NV_ERR_INVALID_ACCESS_TYPE
+ *    NV_ERR_INSUFFICIENT_PERMISSIONS
+ */
+#define NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY (0x83de0316) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS {
+    NvU32 hMemory;
+    NvU32 length;
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+    NV_DECLARE_ALIGNED(NvP64 buffer, 8);
+} NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT
+ *
+ * This command suspends a SM context associated with the debugger object.
+ *
+ * When the suspend call returns, context associated with the debugger object
+ * should not be actively executing any code on any SM. The channel will have
+ * been disabled if not resident on GR, or have its SM suspended if it was resident.
+ *
+ * This is a Fermi-and-later feature. If this API call is issued on an earlier
+ * platform, it will return an NV_ERR_NOT_SUPPORTED error.
+ *
+ *   waitForEvent
+ *     This return param indicates if the call had to issue a Preempt,
+ *     therefore it is in process and user may need to wait for it.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT (0x83de0317) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID (0x17U)
+
+typedef NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT
+ *
+ * This command safely resumes the SM context associated with the debugger object.
+ *
+ * This is a Fermi-and-later feature. If this API call is issued on an earlier
+ * platform, it will return an NV_ERR_NOT_SUPPORTED error.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT (0x83de0318) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x18" */
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_GET_HANDLES
+ *
+ * This command returns relevant handles for the debug object
+ * This command is only available on debug and develop builds.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_CLIENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *
+ */
+#define NV83DE_CTRL_CMD_DEBUG_GET_HANDLES    (0x83de0319) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x19" */
+
+typedef struct NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS {
+    NvHandle hChannel;
+    NvHandle hSubdevice;
+} NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_READ_SURFACE
+ *
+ * This command allows the caller to copy the data from a specified gpuVA
+ * to a usermode buffer. Before copying, this command validates whether or
+ * not the virtual address (VA) range provided as input has valid and allocated
+ * pages mapped to it in its entirety.
+ *
+ * This command's input is NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS which
+ * contains a buffer of NV83DE_CTRL_DEBUG_ACCESS_OPs
+ *
+ * Possible return values:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ *     NV_ERR_INVALID_XLATE
+ */
+#define NV83DE_CTRL_CMD_READ_SURFACE  (0x83de031a) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1A" */
+
+/*
+ * NV83DE_CTRL_CMD_WRITE_SURFACE
+ *
+ * This command allows the caller to copy the data from a provided usermode
+ * buffer to a specified GPU VA. Before copying, this command validates whether or
+ * not the virtual address (VA) range provided as input has valid and allocated
+ * pages mapped to it in its entirety.
+ *
+ * This command's input is NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS which
+ * contains a buffer of NV83DE_CTRL_DEBUG_ACCESS_OPs
+ *
+ * Possible return values:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ *     NV_ERR_INVALID_XLATE
+ */
+#define NV83DE_CTRL_CMD_WRITE_SURFACE (0x83de031b) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1B" */
+
+#define MAX_ACCESS_OPS                64
+
+typedef struct NV83DE_CTRL_DEBUG_ACCESS_OP {
+    NV_DECLARE_ALIGNED(NvU64 gpuVA, 8);   // IN
+    NV_DECLARE_ALIGNED(NvP64 pCpuVA, 8);  // IN/OUT  Debugger CPU Pointer of buffer
+    NvU32 size;                           // IN      Size in bytes
+    NvU32 valid;                          // OUT     Whether the GpuVA is accessible
+} NV83DE_CTRL_DEBUG_ACCESS_OP;
+
+typedef struct NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS {
+    NvU32 count;          // IN  Number of ops in this call
+    NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_ACCESS_OP opsBuffer[MAX_ACCESS_OPS], 8);
+} NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS;
+
+/*
+ * NV83DE_CTRL_CMD_GET_MAPPINGS
+ *
+ * This command traverses through the virtual memory page hierarchy and
+ * fetches the valid virtual mappings and their sizes for a provided virtual
+ * address (VA) range.
+ * If a given VA range has more than MAX_GET_MAPPINGS_OPS valid mappings,
+ * hasMore is set to 1, and opsBuffer is still filled with MAX_GET_MAPPINGS_OPS
+ * valid mappings. In this case, this command should be called again with
+ *     vaLo = opsBuffer[MAX_GET_MAPPINGS_OPS - 1].gpuVA +
+ *            opsBuffer[MAX_GET_MAPPINGS_OPS - 1].size;
+ * and vaHi set to the next desired upper limit.
+ *
+ * This command's input is NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS which
+ * contains a buffer of NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP
+ *
+ * Possible return values:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ *     NV_ERR_INVALID_XLATE
+ */
+#define NV83DE_CTRL_CMD_GET_MAPPINGS (0x83de031c) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1C" */
+
+#define MAX_GET_MAPPINGS_OPS         64
+
+typedef struct NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP {
+    NV_DECLARE_ALIGNED(NvU64 gpuVA, 8);  // OUT     Start of GPU VA for this mapping
+    NvU32 size;                          // OUT     Size in bytes of this mapping
+} NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP;
+
+typedef struct NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS {
+    NV_DECLARE_ALIGNED(NvU64 vaLo, 8);   // IN      Lower VA range, inclusive
+    NV_DECLARE_ALIGNED(NvU64 vaHi, 8);   // IN      Upper VA range, inclusive
+    NvU32 count;                         // OUT     Number of ops in this call
+    NvU32 hasMore;                       // OUT     Whether there are more valid mappings in this range than MAX_GET_MAPPINGS_OPS
+    NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP opsBuffer[MAX_GET_MAPPINGS_OPS], 8);
+} NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS;
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS
+ *
+ * This command is used to submit a buffer containing one or more
+ * NV2080_CTRL_GPU_REG_OP structures for processing.  Each entry in the
+ * buffer specifies a single read or write operation.  Each entry is checked
+ * for validity in an initial pass over the buffer with the results for
+ * each operation stored in the corresponding regStatus field. Unless
+ * bNonTransactional flag is set to true, if any invalid entries are found
+ * during this initial pass then none of the operations are executed. Entries
+ * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL
+ * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries.
+ *
+ * [IN]     bNonTransactional
+ *     This field specifies if command is non-transactional i.e. if set to
+ *     true, all the valid operations will be executed.
+ *
+ * [IN]     regOpCount
+ *     This field specifies the number of valid entries in the regops list.
+ *
+ * [IN/OUT] regOps
+ *     This field is to be filled with the desired register information that is
+ *     to be retrieved.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS   (0x83de031d) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS 100
+#define NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x1DU)
+
+typedef struct NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS {
+    NvBool                 bNonTransactional;
+    NvU32                  regOpCount;
+    // C form: NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_GPU_EXEC_REG_OPS_MAX_OPS]
+    NV2080_CTRL_GPU_REG_OP regOps[NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS];
+} NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR
+ *
+ * This command sets the Errbar Debug mode. This is Volta-onwards feature.
+ * If the query is made on an incorrect platform (for example, pre-Volta)
+ * the call will return with an NV_ERR_NOT_SUPPORTED error.
+ *
+ *   action
+ *     The possible action values are:
+ *   - NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_ENABLE
+ *      This enables the Errbar debug mode.
+ *
+ *   - NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DISABLE
+ *      This disables the Errbar debug mode.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_WRITE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG (0x83de031f) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID (0x1FU)
+
+typedef struct NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS {
+    NvU32 action;
+} NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS;
+
+#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE (0x00000000)
+#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE  (0x00000001)
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR
+ *
+ * This command gets the value of currently configured Errbar DEBUG mode.
+ * This is Volta-onwards feature. If the query is made on an incorrect
+ * platform (for example, pre-Volta) the call will return with an
+ * NV_ERR_NOT_SUPPORTED error.
+ *
+ *   value
+ *     This parameter returns the configured value.
+ *
+ * Possible return values:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_READ
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG         (0x83de0320) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS {
+    NvU32 value;
+} NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS;
+
+#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED (0x00000000)
+#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED  (0x00000001)
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP
+ *
+ * This command either enables or disables single step mode for the given SM.
+ *
+ *   smID (input)
+ *     This identifies the SM.
+ *   bSingleStep (input)
+ *     This indicates the single step mode. NV_TRUE for ENABLED.
+ */
+#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP      (0x83de0321) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS {
+    NvU32  smID;
+    NvBool bSingleStep;
+} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER
+ *
+ * This command sets or clears the stop trigger for the given SM.
+ *
+ *   smID (input)
+ *     This identifies the SM.
+ *   bStopTrigger (input)
+ *     This indicates whether to set or clear the trigger. NV_TRUE for ENABLED.
+ */
+#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER (0x83de0322) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_BROADCAST ((NvU32)~0)
+
+#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS {
+    NvU32  smID;
+    NvBool bStopTrigger;
+} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER
+ *
+ * This command sets or clears the run trigger for the given SM.
+ *
+ *   smID (input)
+ *     This identifies the SM.
+ *   bRunTrigger (input)
+ *     This indicates whether to set or clear the trigger. NV_TRUE for ENABLED.
+ */
+#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER (0x83de0323) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS {
+    NvU32  smID;
+    NvBool bRunTrigger;
+} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT
+ *
+ * This command enables or disables skip idle warp detect for the given sm.
+ *
+ *   smID (input)
+ *     This identifies the SM.
+ *   bSkipIdleWarpDetect (input)
+ *     This indicates whether to enable or disable the mode. NV_TRUE for ENABLED.
+ */
+#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT (0x83de0324) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS {
+    NvU32  smID;
+    NvBool bSkipIdleWarpDetect;
+} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS;
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS
+ *
+ * This command retrieves the debugger status states of the given SM.
+ *
+ *   smID (input)
+ *     This identifies the SM.
+ *   bInTrapMode (output)
+ *     This indicates whether the SM is in trap mode.
+ *   bCrsFlushDone (output)
+ *     Deprecated GK110+. Always 0 Volta+.
+ *   bRunTriggerInProgress (output)
+ *     Deprecated GM10X+. Always 0 Volta+.
+ *   bComputeContext (output)
+ *     Deprecated GM10X+. Always 0 Volta+.
+ *   bLockedDown (output)
+ *     This indicates whether the SM is locked down.
+ */
+#define NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS (0x83de0325) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID" */
+
+typedef struct NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS {
+    NvBool bInTrapMode;
+    NvBool bCrsFlushDone;
+    NvBool bRunTriggerInProgress;
+    NvBool bComputeContext;
+    NvBool bLockedDown;
+} NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS;
+
+#define NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS {
+    NvU32                                       smID;
+    NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS smDebuggerStatus;
+} NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS;
+
+/*!
+ * NV83DE_CTRL_CMD_DEBUG_ACCESS_MEMORY_ENTRY
+ *
+ *   This struct represents a requet to read/write a block of memory.
+ *
+ *   hMemory [IN]
+ *       The handle to the memory being accessed. If hMemory is not accessible
+ *       from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS
+ *       is returned.
+ *
+ *   length [IN]
+ *       Number of bytes to read/write
+ *
+ *   memOffset [IN]
+ *      The offset into the physical memory region given by the handle above.
+ *
+ *   dataOffset [IN]
+ *      An offset into the usermode memory region provided by the enclosing
+ *      params indicating where to read/write data from/to.
+ *
+ *   status [OUT]
+ *       The result status of the operation will be output. If NV_OK, even if
+ *       command returned error status, the given operation was successful. If
+ *       not NV_OK, it is guaranteed that the command will return error status. 
+ */
+typedef struct NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY {
+    NvHandle  hMemory;
+    NvU32     length;
+    NV_DECLARE_ALIGNED(NvU64 memOffset, 8);
+    NvU32     dataOffset;
+    NV_STATUS status;
+} NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY;
+
+/*!
+ * NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY
+ *
+ * Execute a batch of read memory operations.
+ *
+ *   count [IN]
+ *     Number of read/write operations to perform.
+ *
+ *   dataLength [IN]
+ *     Length of the usermode buffer passed in, in bytes.
+ *
+ *   pData [OUT]
+ *     Usermode buffer to store the output of the read operations. Each
+ *     operation is expected to provide an offset into this buffer.
+ *
+ *   entries [IN]
+ *     List of operations to perform. First `count` entries are used.
+ */
+#define NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY  (0x83de0326) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x26" */
+
+/*!
+ * NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY
+ *
+ * Execute a batch of write memory operations.
+ *
+ *   count [IN]
+ *     Number of read/write operations to perform.
+ *
+ *   dataLength [IN]
+ *     Length of the usermode buffer passed in, in bytes.
+ *
+ *   pData [IN]
+ *     Usermode buffer to store the input of the write operations. Each
+ *     operation is expected to provide an offset into this buffer.
+ *
+ *   entries [IN]
+ *     List of operations to perform. First `count` entries are used.
+ */
+#define NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY (0x83de0327) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x27" */
+
+#define MAX_ACCESS_MEMORY_OPS                    150
+typedef struct NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pData, 8);
+    NvU32 dataLength;
+    NvU32 count;
+    NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY entries[MAX_ACCESS_MEMORY_OPS], 8);
+} NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS;
+
+/*
+ * NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY
+ *
+ *   faultAddress (OUT)
+ *     Faulting address
+ *   faultType (OUT)
+ *     Type of MMU fault
+ *   accessType (OUT)
+ *     Type of access that caused this fault
+ */
+#define NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES 4
+typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY {
+    NV_DECLARE_ALIGNED(NvU64 faultAddress, 8);
+    NvU32 faultType;
+    NvU32 accessType;
+} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY;
+
+/*
+ * NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO
+ *
+ *   mmuFaultInfoList (OUT)
+ *     Entries of MMU faults recorded for the attached context. The cached data is only cleared via LRU policy when new MMU faults arrive so repeat data may be returned by this command.
+ *   count (OUT)
+ *     Number of MMU fault entries contain valid data.
+ */
+#define NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO (0x83de0328) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x28U)
+
+typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY mmuFaultInfoList[NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES], 8);
+    NvU32 count;
+} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS;
+
+/* _ctrl83dedebug_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9010.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9010.h
new file mode 100644
index 0000000..43dada9
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9010.h
@@ -0,0 +1,83 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl9010.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#define NV9010_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0x9010, NV9010_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NV9010_CTRL_RESERVED        (0x00)
+#define NV9010_CTRL_VBLANK_CALLBACK (0x01)
+
+
+/*
+ * NV9010_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ */
+#define NV9010_CTRL_CMD_NULL        (0x90100000) /* finn: Evaluated from "(FINN_NV9010_VBLANK_CALLBACK_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+/*
+ * NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION
+ *
+ * This command is used to enable and disable vblank notifications. This 
+ * is specially intended for cases where the RM client is calling from a
+ * high IRQL context, where other mechanisms to toggle vblank notification
+ * (such as freeing and reallocating the NV9010_VBLANK_CALLBACK object)
+ * would not be suitable. As this is being invoked at the high IRQL, 
+ * locking can be bypassed, if the NVOS54_FLAGS_LOCK_BYPASS flag is set on 
+ * the control call.Here the OS will take care of the synchronization. 
+ * The Windows Display Driver for Cobalt requires this, for example.
+ *
+ *    bSetVBlankNotifyEnable
+ *       This parameter tell whether to enable or disable the Vblank notification
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION (0x90100101) /* finn: Evaluated from "(FINN_NV9010_VBLANK_CALLBACK_INTERFACE_ID << 8) | NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS_MESSAGE_ID (0x01U)
+
+typedef struct NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS {
+    NvBool bSetVBlankNotifyEnable;
+} NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS;
+
+/* _ctrl9010_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9067.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9067.h
new file mode 100644
index 0000000..62cb948
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9067.h
@@ -0,0 +1,150 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl9067.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* Subcontext control commands and parameters */
+#define NV9067_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x9067, NV9067_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NV9067_CTRL_RESERVED      (0x00)
+#define NV9067_CTRL_TPC_PARTITION (0x01)
+#define NV9067_CTRL_CWD_WATERMARK (0x02)
+
+/*!
+ * Does nothing.
+ */
+#define NV9067_CTRL_CMD_NULL      (0x90670000) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*!
+ * NV9067_CTRL_CMD_GET_TPC_PARTITION_TABLE
+ *    This command gets the current partition table configuration of a subcontext
+ *
+ * NV9067_CTRL_CMD_SET_TPC_PARTITION_TABLE
+ *    This command sets the partition table of a subcontext
+ *
+ * NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS
+ *     This structure defines the parameters used for SET/GET per-subcontext TPC partitioning table configuration
+ *
+ *       numUsedTpc [in/out]
+ *           Specifies the number of TPCs used by the subcontext
+ *           While querying the enabled TPCs, this is an output paramter
+ *           While configuring the TPCs, this is an input parameter
+ *
+ *       tpcList [in/out]
+ *           Array containing the TPCs enabled for the subcontext.
+ *           The first numUsedTpc in the array interpreted as the valid entries.
+ *
+ *           Only applicable for STATIC and DYNAMIC modes.
+ *
+ * NV9067_CTRL_TPC_PARTITION_TABLE_MAX_TPC_COUNT
+ *     Max TPC count supported by this ctrl call
+ *     
+ * NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO
+ *   This structure defines the parameters for a TPC
+ *
+ *       globalTpcIndex
+ *          Global logical index of the enabled TPC
+ *
+ *       lmemBlockIndex
+ *          Block index of the Local memory backing store for the enabled TPC.
+ *          For GET command, we will return the current lmem block assigment for STATIC & DYNAMIC modes.
+ *          For SET command, this index is relevant only for STATIC mode.
+ *          HW automatically assign it for other modes. So should be zeroed out for other modes.
+ *
+ */
+#define NV9067_CTRL_CMD_GET_TPC_PARTITION_TABLE       (0x90670101) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID << 8) | 0x1" */
+
+#define NV9067_CTRL_CMD_SET_TPC_PARTITION_TABLE       (0x90670102) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID << 8) | NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV9067_CTRL_TPC_PARTITION_TABLE_TPC_COUNT_MAX 256
+
+typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO {
+    NvU16 globalTpcIndex;
+    NvU16 lmemBlockIndex;
+} NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO;
+
+#define NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS {
+    NvU16                                    numUsedTpc;
+    NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO tpcList[NV9067_CTRL_TPC_PARTITION_TABLE_TPC_COUNT_MAX];
+} NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS;
+
+
+/*!
+ * NV9067_CTRL_CMD_GET_CWD_WATERMARK
+ *    This command gets the cached watermark value for a subcontext
+ *
+ * NV9067_CTRL_CMD_SET_CWD_WATERMARK
+ *    This command sets the watermark value for a subcontexts
+ *
+ * NV9067_CTRL_CWD_WATERMARK_PARAMS
+ *     This structure defines the parameters used to SET/GET watermark value per-subcontext.
+ *
+ *        watermarkValue [in/out]
+ *            Value of watermark per-subcontext
+ *            Acts as a output parameter to get the current value of watermark for a subcontext.
+ *            Acts as a input parameter to set the current value of watermark for a subcontexts.
+ *
+ * NV9067_CTRL_CWD_WATERMARK_VALUE_MIN
+ *     Minimum value of watermark for any subcontext
+ *     RM will throw an error if any value less than this value is specified
+ *
+ * NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT
+ *     Default value of watermark for any subcontext
+ *     RM will set watermark of a subcontext to this value when the subcontext
+ *     is created/initialized for the first time
+ *
+ * NV9067_CTRL_CWD_WATERMARK_VALUE_MAX
+ *     Maximum value of watermark for any subcontext
+ *     RM will throw an error if any value more than this value is specified
+ *
+ */
+
+#define NV9067_CTRL_CMD_GET_CWD_WATERMARK       (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x1" */
+
+#define NV9067_CTRL_CMD_SET_CWD_WATERMARK       (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x2" */
+
+#define NV9067_CTRL_CWD_WATERMARK_VALUE_MIN     1
+#define NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT 2
+#define NV9067_CTRL_CWD_WATERMARK_VALUE_MAX     256
+
+typedef struct NV9067_CTRL_CWD_WATERMARK_PARAMS {
+    NvU32 watermarkValue;
+} NV9067_CTRL_CWD_WATERMARK_PARAMS;
+
+
+/* _ctrl9067_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl906f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl906f.h
new file mode 100644
index 0000000..8be99d2
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl906f.h
@@ -0,0 +1,261 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl906f.finn
+//
+
+
+
+
+/* GF100_GPFIFO control commands and parameters */
+
+#include "ctrl/ctrlxxxx.h"
+#define NV906F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0x906F, NV906F_CTRL_##cat, idx)
+
+/* GF100_GPFIFO command categories (6bits) */
+#define NV906F_CTRL_RESERVED (0x00)
+#define NV906F_CTRL_GPFIFO   (0x01)
+#define NV906F_CTRL_EVENT    (0x02)
+
+
+/*
+ * NV906F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV906F_CTRL_CMD_NULL (0x906f0000) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+
+/*
+ * NV906F_CTRL_GET_CLASS_ENGINEID
+ *
+ * Takes an object handle as input and returns
+ * the Class and Engine that this object uses.
+ *
+ * hObject
+ *   Handle to an object created. For example a
+ *   handle to object of type FERMI_A created by
+ *   the client. This is supplied by the client
+ *   of this call.
+ *
+ * classEngineID
+ *   A concatenation of class and engineid
+ *   that the object with handle hObject
+ *   belongs to. This is returned by RM. The internal
+ *   format of this data structure is opaque to clients.
+ *
+ * classID
+ *   ClassID for object represented by hObject
+ *
+ * engineID
+ *   EngineID for object represented by hObject
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   If the call was successful.
+ *
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   No object of handle hObject was found.
+ */
+#define NV906F_CTRL_GET_CLASS_ENGINEID (0x906f0101) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
+
+#define NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS {
+    NvHandle hObject;
+    NvU32    classEngineID;
+    NvU32    classID;
+    NvU32    engineID;
+} NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS;
+
+/*
+ * NV906F_CTRL_RESET_CHANNEL
+ *
+ * This command resets the channel corresponding to specified engine and also
+ * resets the specified engine.
+ *
+ * Takes an engine ID as input.
+ *
+ * engineID
+ *   This parameter specifies the engine to be reset.  See the description of the
+ *   NV2080_ENGINE_TYPE values in cl2080.h for more information.
+ * subdeviceInstance
+ *   This parameter specifies the subdevice to be reset when in SLI.
+ * resetReason
+ *   Specifies reason to reset a channel.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_DEFAULT             0
+#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_VERIF               1
+#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_MMU_FLT             2
+#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX            3
+/*
+ * Internal values for NV906F_CTRL_CMD_RESET_REASON. External values will be
+ * checked and enforced to be < NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX
+ */
+#define NV906F_CTRL_CMD_INTERNAL_RESET_CHANNEL_REASON_FAKE_ERROR (0x4) /* finn: Evaluated from "NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX + 1" */
+
+
+#define NV906F_CTRL_CMD_RESET_CHANNEL                            (0x906f0102) /* finn: Evaluated from "((FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID)" */
+
+#define NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS {
+    NvU32 engineID;
+    NvU32 subdeviceInstance;
+    NvU32 resetReason;
+} NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS;
+
+/*
+ * NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * This command sets event notification state for the associated channel.
+ * This command requires that an instance of NV01_EVENT has been previously
+ * bound to the associated channel object.
+ *
+ *   event
+ *     This parameter specifies the type of event to which the specified
+ *     action is to be applied.  This parameter must specify a valid
+ *     NV906F_NOTIFIERS value (see cl906f.h for more details) and should
+ *     not exceed one less NV906F_NOTIFIERS_MAXCOUNT.
+ *   action
+ *     This parameter specifies the desired event notification action.
+ *     Valid notification actions include:
+ *       NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_DISABLE
+ *         This action disables event notification for the specified
+ *         event for the associated channel object.
+ *       NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_SINGLE
+ *         This action enables single-shot event notification for the
+ *         specified event for the associated channel object.
+ *       NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_REPEAT
+ *         This action enables repeated event notification for the specified
+ *         event for the associated channel object.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION (0x906f0203) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID << 8) | NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
+    NvU32 event;
+    NvU32 action;
+} NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
+#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  (0x00000001)
+#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  (0x00000002)
+
+/*
+ * NV906F_CTRL_CMD_GET_DEFER_RC_STATE
+ *
+ * If SM Debugger is attached then on a MMU fault, RM defers the RC error
+ * recovery and keeps a flag indicating that RC is deferred. This command
+ * checks whether or not deferred RC is pending in RM for the associated
+ * channel.
+ *
+ *   bDeferRCPending
+ *     The output are TRUE and FALSE.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE (0x906f0105) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS {
+    NvBool bDeferRCPending;
+} NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS;
+
+#define NV906F_CTRL_CMD_GET_MMU_FAULT_INFO                         (0x906f0106) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * Shader types supported by MMU fault info
+ * The types before compute shader refer to NV9097_SET_PIPELINE_SHADER_TYPE
+ */
+#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000
+#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_VERTEX                   0x00000001
+#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_TESSELLATION_INIT        0x00000002
+#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_TESSELLATION             0x00000003
+#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_GEOMETRY                 0x00000004
+#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_PIXEL                    0x00000005
+#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_COMPUTE                  0x00000006
+#define NV906F_CTRL_MMU_FAULT_SHADER_TYPES                         7
+
+/*
+ * NV906F_CTRL_CMD_GET_MMU_FAULT_INFO
+ *
+ * This command returns MMU fault information for a given channel. The MMU
+ * fault information will be cleared once this command is executed.
+ *
+ *   addrHi - [out]
+ *      Upper 32 bits of faulting address
+ *   addrLo [out]
+ *      Lower 32 bits of faulting address
+ *   faultType [out]
+ *      MMU fault type. Please see NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE_* in
+ *      dev_fifo.h for details about MMU fault type.
+ *   faultString [out]
+ *      String indicating the MMU fault type
+ *   shaderProgramVA [out]
+ *      an array of shader program virtual addresses to indicate faulted shaders in the pipeline
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV906F_CTRL_MMU_FAULT_STRING_LEN                           32
+#define NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS {
+    NvU32 addrHi;
+    NvU32 addrLo;
+    NvU32 faultType;
+    char  faultString[NV906F_CTRL_MMU_FAULT_STRING_LEN];
+    NV_DECLARE_ALIGNED(NvU64 shaderProgramVA[NV906F_CTRL_MMU_FAULT_SHADER_TYPES], 8);
+} NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
+
+
+/* _ctrl906f.h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9072.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9072.h
new file mode 100644
index 0000000..8c3cceb
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9072.h
@@ -0,0 +1,86 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl9072.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#define NV9072_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0x9072, NV9072_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NV9072_CTRL_RESERVED (0x00)
+#define NV9072_CTRL_DISP_SW  (0x01)
+
+
+/*
+ * NV9072_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ */
+#define NV9072_CTRL_CMD_NULL (0x90720000) /* finn: Evaluated from "(FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+ * NV9072_CTRL_CMD_NOTIFY_ON_VBLANK
+ *
+ * This command implements an out-of-band version of the
+ * GF100_DISP_SW class's NV9072_NOTIFY_ON_VBLANK method.
+ *
+ * Parameters:
+ *
+ *   data
+ *     Valid data accepted by the NV9072_NOTIFY_ON_VBLANK method.
+ *   bHeadDisabled
+ *     Specifies whether head is active while adding vblank
+ *     callback.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NVOS_STATUS_INVALID_PARAM_STRUCT
+ *    NV_ERR_INVALID_STATE
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV9072_CTRL_CMD_NOTIFY_ON_VBLANK (0x90720101) /* finn: Evaluated from "(FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID << 8) | NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS_MESSAGE_ID" */
+
+#define NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS {
+    NvU32  data;
+    NvBool bHeadDisabled;
+} NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS;
+
+/* _ctrl9072.h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9074.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9074.h
new file mode 100644
index 0000000..47b8d2f
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9074.h
@@ -0,0 +1,148 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl9074.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#define NV9074_CTRL_CMD(cat,idx)  NVXXXX_CTRL_CMD(0x9074, NV9074_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NV9074_CTRL_RESERVED (0x00)
+#define NV9074_CTRL_SEM      (0x01)
+
+/*
+ * NV9074_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ */
+#define NV9074_CTRL_CMD_NULL (0x90740000) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+ * NV9074_CTRL_CMD_FLUSH
+ *
+ * This command is intended to aid in idling/flushing a channel containing
+ * methods invoked against a specific NV9074 object.
+ *
+ * This control manipulates an NV9074 object's  "flushing" state.
+ *
+ * Typical usage is:
+ * NvRmControl(NV9074_CTRL_CMD_FLUSH, {TRUE, flushDelay});
+ * NvRmIdleChannel(channel_containing_the_9074_object);
+ * NvRmControl(NV9074_CTRL_CMD_FLUSH, {FALSE, 0});
+ *
+ * When an NV9074 object is placed into the flushing state, a snaphot of the
+ * current timer value is taken, and "maxFlushTime" is added to this. This
+ * value is the "flush limit timestamp". Any previously or newly invoked
+ * NV9074_SEMAPHORE_SCHED methods and NV9074_CTRL_CMD_RELEASE requests that
+ * specify a release timestamp at or after this "flush limit timestamp" will
+ * immediately release the specified semaphore, without waiting for the
+ * specified timestamp, and write a DONE_FORCED value to the specified notifier.
+ */
+#define NV9074_CTRL_CMD_FLUSH (0x90740101) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_FLUSH_PARAMS_MESSAGE_ID" */
+
+#define NV9074_CTRL_CMD_FLUSH_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV9074_CTRL_CMD_FLUSH_PARAMS {
+    NvU32 isFlushing;
+    NV_DECLARE_ALIGNED(NvU64 maxFlushTime, 8);
+} NV9074_CTRL_CMD_FLUSH_PARAMS;
+
+/*
+ * NV9074_CTRL_CMD_GET_TIME
+ *
+ * Retrieve the current time value.
+ */
+#define NV9074_CTRL_CMD_GET_TIME (0x90740102) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_GET_TIME_PARAMS_MESSAGE_ID" */
+
+#define NV9074_CTRL_CMD_GET_TIME_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV9074_CTRL_CMD_GET_TIME_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 currentTime, 8);
+} NV9074_CTRL_CMD_GET_TIME_PARAMS;
+
+/*
+ * NV9074_CTRL_CMD_RELEASE
+ *
+ * This command adds a timed semaphore release request. When the desired time is
+ * reached, the semaphore is written with the release value, the notifier is
+ * filled with status and timestamp, and optionally an event is sent to all the
+ * client waiting on it.
+ *
+ *   notifierGPUVA
+ *     This parameter specifies the GPU VA of the notifier to receive the status
+ *     for this particular release.
+ *
+ *   semaphoreGPUVA
+ *     This parameter specifies the GPU VA of the semaphore to release.
+ *
+ *   waitTimestamp
+ *     This parameter specifies the timestamp at which to release the semaphore.
+ *
+ *   releaseValue
+ *     This parameter specifies the semaphore value to release.
+ *
+ *   releaseFlags
+ *     This parameter specifies the flags:
+ *       _NOTIFY wake client or not.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ADDRESS
+ *   NV_ERR_INVALID_EVENT
+ *   NV_ERR_INVALID_STATE
+ *
+ */
+#define NV9074_CTRL_CMD_RELEASE (0x90740103) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_RELEASE_PARAMS_MESSAGE_ID" */
+
+#define NV9074_CTRL_CMD_RELEASE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV9074_CTRL_CMD_RELEASE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 notifierGPUVA, 8);
+    NV_DECLARE_ALIGNED(NvU64 semaphoreGPUVA, 8);
+    NV_DECLARE_ALIGNED(NvU64 waitTimestamp, 8);
+    NvU32 releaseValue;
+    NvU32 releaseFlags;
+} NV9074_CTRL_CMD_RELEASE_PARAMS;
+
+#define NV9074_CTRL_CMD_RELEASE_FLAGS
+#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY                                 1:0        
+#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY_WRITE_ONLY        (0x00000000)
+#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY_WRITE_THEN_AWAKEN (0x00000001)
+
+/* _ctrl9074.h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9096.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9096.h
new file mode 100644
index 0000000..4aaca21
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9096.h
@@ -0,0 +1,444 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl9096.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#define NV9096_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0x9096, NV9096_CTRL_##cat, idx)
+
+/* NV9096 command categories (6bits) */
+#define NV9096_CTRL_RESERVED                                            (0x00U)
+#define NV9096_CTRL_ZBC                                                 (0x01U)
+
+
+/*
+ * NV9096_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV9096_CTRL_CMD_NULL                                            (0x90960000U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/*
+ * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_
+ * These are various possible CtFormats which 
+ * the Client passes down to RM to set in the DS
+ * Color Table.
+ */
+
+
+
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_INVALID             0x00000000U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_ZERO                0x00000001U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_UNORM_ONE           0x00000002U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RF32_GF32_BF32_AF32 0x00000004U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_R16_G16_B16_A16     0x00000008U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RN16_GN16_BN16_AN16 0x0000000cU
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RS16_GS16_BS16_AS16 0x00000010U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RU16_GU16_BU16_AU16 0x00000014U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RF16_GF16_BF16_AF16 0x00000016U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8R8G8B8            0x00000018U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8RL8GL8BL8         0x0000001cU
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A2B10G10R10         0x00000020U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AU2BU10GU10RU10     0x00000024U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8B8G8R8            0x00000028U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8BL8GL8RL8         0x0000002cU
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AN8BN8GN8RN8        0x00000030U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AS8BS8GS8RS8        0x00000034U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AU8BU8GU8RU8        0x00000038U
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A2R10G10B10         0x0000003cU
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_BF10GF11RF11        0x00000040U
+
+/*
+ * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR
+ *
+ * This command attempts to add a new entry to Color ZBC Tables.
+ *
+ *  colorFB
+ *    This field sets the raw framebuffer values for the ZBC table entries. Prior to 
+ *    GA10x, these values are written into the "L2" table.
+ *    From GA10x and later, these values are written in "CROP" table.
+ *  colorDS
+ *    This field sets format-independent values for ZBC table entries. Prior to GA10X, 
+ *    these values are written in the "DS" table and  matched with the format-independent 
+ *    clear color sent in the 3D class. These values are ignored on GA10X and later 
+ *  format
+ *    This field specifies color format for ZBC table entries and should be one of the 
+ *    NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT* enums. Prior to GA10X, these values 
+ *    are written in the format field of the hardware ZBC table entry and are matched 
+ *    against the color format sent in the 3D class. These values are ignored on GA10X and later.
+ *  bSkipL2Table
+ *    This parameter specifies if the L2 ZBC table should be updated or not. If
+ *    this parameter is set to a non-zero value, the L2 ZBC table will not be
+ *    updated. If this parameter is set to 0, the L2 ZBC table will be updated. This 
+ *    parameter will skip programming DS table values in Pre-GA10x. From GA10x and later
+ *    this parameter will skip programming CROP table entries. 
+ *    Note: This parameter will only be supported in verification platforms. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_INSUFFICIENT_RESOURCES
+ */
+#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR        (0x90960101U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_MESSAGE_ID" */
+
+#define NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE 4U
+#define NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS {
+    NvU32  colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
+    NvU32  colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
+    NvU32  format;
+    NvBool bSkipL2Table;
+} NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS;
+
+
+/*
+ * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL
+ * These are various possible formats which the Client passes down to RM to set in the ZBC clear 
+ * Table.
+ * 
+ * Though the "Depth" data written in both the DS as well as L2 Version of the 
+ * depth table are of (only available!) FP32 Format. Still the format 
+ * support is currently given with _CTRL_CMD_SET_ZBC_DEPTH_CLEAR as this format will
+ * be used later on to disable/remove an entry from the table.
+ * In future this field is going to be significant for
+ * "Depth" entries too.
+ */
+
+#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL_INVALID 0x00000000U
+// Fix me: Fix the name to FMT_VAL_FP32
+#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_FP32        0x00000001U
+
+/*
+ * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR
+ *
+ * This command attempts to add a new entry to Depth ZBC Tables.
+ *
+ *  depth
+ *    This field specifies the ZBC depth clear value to be set.
+ *  format
+ *    This field specifies the Depth format for the data send in  by the client. 
+ *  bSkipL2Table
+ *    This parameter specifies if the L2 ZBC table should be updated or not. If
+ *    this parameter is set to a non-zero value, the L2 ZBC table will not be
+ *    updated. If this parameter is set to 0, the L2 ZBC table will be updated.
+ *    Note: This parameter will only be supported in verification platforms. 
+ * 
+
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_INSUFFICIENT_RESOURCES
+ */
+#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR                 (0x90960102U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_MESSAGE_ID" */
+
+#define NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS {
+    NvU32  depth;
+    NvU32  format;
+    NvBool bSkipL2Table;
+} NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS;
+
+/*
+ * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE
+ *
+ *
+ * This command is used to get the ZBC Clear Color/Depth/Stencil table data i.e. color 
+ * values and the status "Use-satatus" of each value in the table from RM. 
+ *
+ *   colorFB
+ *      This value returns raw framebuffer values for color ZBC table entries. Pre-GA10x, these values
+ *      are taken from the "L2" table. From GA10x+, these values are taken from CROP table. This value is
+ *      set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR"
+ *   colorDS
+ *      Pre-GA10x, returns the DS color value set for ZBC. From GA10x+, returns zeroes since this format is
+ *      deprecated in HW. This value is set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR"
+ *   depth
+ *     This field returns the ZBC depth clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH".
+ *   stencil
+ *     This field returns the ZBC stencil clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL"
+ *   format
+ *      This field returns the format of color, depth, or stencil ZBC table entries, using the
+ *      NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT,
+ *      NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT,
+ *      NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT* enums depending on the table identified by valType.
+ *      On GA10X and later, color ZBC table entries do not have a format in hardware and this query 
+ *      returns a format of "INVALID".
+ *   valType
+ *     This filed specifies the type of the Table  data to be fetched.
+ *     Possible Types are :
+ *       NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR
+ *       NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH
+ *       NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL
+ *   indexUsed
+ *     This boolean parameter indicates if a particular index of the table is valid or not.
+ *
+ *   Note: The following parameters are deprecated after Tegra interface is also changed. Clients need 
+ *   to use NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE to query the (start, end) indexes of respective ZBC tables
+ *
+ *   indexSize
+ *     This parameter is used to fetch the table size when "valType" parameter
+ *     is specified as " 0 ".(INVALID TYPE). It is also used to pass in the
+ *     index of the ZBC table for which we want the COLOR/DEPTH info.
+ *   indexStart
+ *      This parameter is used to return the valid starting index of ZBC table, when
+ *      "valType" parameter is specified as "INVALID_TYPE". It will also be used
+ *       as input index to query the ZBC table for COLOR/QUERY/STENCIL Info. 
+ *   indexEnd
+ *       This parameter is used to return the valid ending index of ZBC table, when
+ *       "valType" parameter is specified as "INVALID_TYPE".
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE       (0x90960103U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_INVALID 0U
+#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR   1U
+#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH   2U
+#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL 3U
+#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS {
+    struct {
+        NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
+        NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
+        NvU32 depth;
+        NvU32 stencil;
+    } value;
+    NvU32 indexSize;
+    NvU32 indexStart;
+    NvU32 indexEnd;
+    NvU32 indexUsed; /* TODO: Change to NvBool, need to fix the tegra interface too */
+    NvU32 format;
+    NvU32 valType;
+} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS;
+
+/*
+ * Note: This ctrl call is deprecated. To program ZBC table entries, please use 
+ *  NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR
+ *  NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR
+ *  NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR
+ *  which will update a single entry in single table at a time. 
+ *  
+ *  
+ * NV9096_CTRL_CMD_SET_ZBC_CLEAR_TABLE
+ *
+ * This command is used to set the ZBC Clear Color/Depth/Stencil table data at a specified
+ * index. The parameters to this command are described below.
+ *
+ *  colorFB
+ *    This array field specifies the L2 color value to be written to the ZBC table.
+ *  colorDS
+ *    This array field specifies the DS color value to be written to the ZBC table.
+ *  colorFormat
+ *    This field specifies the ZBC color format to be set. This field must be set
+ *    to one of the valid NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL* defines.
+ *  depth
+ *    This field specifies the ZBC depth clear value to be set.
+ *  depthFormat
+ *    This field specifies the ZBC depth format to be set. This field must be set
+ *    to one of the valid NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL* defines.
+ *  stencil
+ *    This field specifies the ZBC stencil clear value to be set.
+ *  stencilFormat
+ *    This field specifies the ZBC stencil format to be set. This field must be set
+ *    to one of the valid NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL* defines.
+ *  index
+ *    This field specifies the index at which the color/depth data is to be
+ *    written into the ZBC table. Legal values for this field must lie between
+ *    1 and the value returned in the indexSize parameter of the
+ *    NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE control call when called with the
+ *    parameter valType set to NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_INVALID.
+ *  bSkipL2Table
+ *    This parameter specifies if the L2 ZBC table should be updated or not. If
+ *    this parameter is set to a non-zero value, the L2 ZBC table will not be
+ *    updated. If this parameter is set to 0, the L2 ZBC table will be updated.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_INSUFFICIENT_RESOURCES
+ */
+#define NV9096_CTRL_CMD_SET_ZBC_CLEAR_TABLE (0x90960104U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS {
+    NvU32  colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
+    NvU32  colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
+    NvU32  colorFormat;
+    NvU32  depth;
+    NvU32  depthFormat;
+    NvU32  stencil;
+    NvU32  stencilFormat;
+    NvU32  index;
+    NvBool bSkipL2Table;
+} NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS;
+
+/*
+ * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL_
+ * These are various possible Formats which the Client passes down to RM to set in the 
+ * ZBC clear(DSS) Table.
+ */
+
+#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL_INVALID 0x00000000U
+// Fix me: Change it to CLEAR_FMT_VAL_U8
+#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_U8          0x00000001U
+
+/*
+ * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR
+ *
+ * This command attempts to add a new entry to Stencil ZBC Tables.
+ *
+ *  stencil
+ *    This field specifies the ZBC stencil clear value to be set.
+ *  format
+ *    This field specifies the stencil format for the data send in  by the client.
+ *  bSkipL2Table
+ *    This parameter specifies if the L2 ZBC table should be updated or not. If
+ *    this parameter is set to a non-zero value, the L2 ZBC table will not be
+ *    updated. If this parameter is set to 0, the L2 ZBC table will be updated.
+ *    Note: This parameter will only be supported in verification platforms.
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_INSUFFICIENT_RESOURCES
+ */
+#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR                 (0x90960105U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_MESSAGE_ID" */
+
+#define NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS {
+    NvU32  stencil;
+    NvU32  format;
+    NvBool bSkipL2Table;
+} NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS;
+
+/*
+ * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE
+ *   This command returns the range of valid indices in the color, depth, or stencil ZBC tables.
+ * 
+ *   indexStart
+ *      This parameter is used to return the first valid index in the color, depth, or stencil ZBC table,
+ *      depending on the value passed in the tableType 
+ *   indexEnd
+ *      This parameter is used to return the last valid index in the color, depth, or stencil ZBC table,
+ *      depending on the value passed in the tableType
+ *   tableType
+ *     This field specifies the type of the Table  data to be fetched.
+ *     Possible Types are :
+ *       NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR
+ *       NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH
+ *       NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+typedef enum NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE {
+    NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_INVALID = 0,
+    NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR = 1,
+    NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH = 2,
+    NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL = 3,
+    NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT = 4,
+} NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE;
+
+#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE (0x90960106U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS {
+    NvU32                            indexStart;
+    NvU32                            indexEnd;
+    NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE tableType;
+} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS;
+
+/*
+ * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY
+ *   This command returns the ZBC entry stored in the color, depth or stencil ZBC tables
+ *
+ *   colorFB[out]
+ *      This value returns raw framebuffer values for color ZBC table entries. Pre-GA10x, these values
+ *      are taken from the "L2" table. From GA10x+, these values are taken from CROP table. This value is
+ *      set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR"
+ *   colorDS[out]
+ *      Pre-GA10x, returns the DS color value set for ZBC. From GA10x+, returns zeroes since this format is
+ *      deprecated in HW. This value is set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR"
+ *   depth[out]
+ *      This field specifies the ZBC depth clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH".
+ *   stencil[out]
+ *      This field specifies the ZBC stencil clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL"
+ *   format
+ *      This field returns the format of color, depth, or stencil ZBC table entries, using the
+ *      NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL*,
+ *      NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT*,
+ *      NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT* enums depending on the table identified by valType.
+ *      On GA10X and later, color ZBC table entries do not have a format in hardware and this query 
+ *      returns a format of "INVALID".
+ *   index[in]
+ *      This field specifies table index for which the ZBC entry information needs to be fetched. 
+ *   bIndexValid[out]
+ *      This field specifies whether the entry is valid or not. 
+ *   tableType[in]
+ *      This field specifies the type of the Table  data to be fetched.
+ *      Possible Types are :
+ *       NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR
+ *       NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH
+ *       NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY (0x90960107U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_MESSAGE_ID" */
+
+#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS {
+    struct {
+        NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
+        NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
+        NvU32 depth;
+        NvU32 stencil;
+    } value;
+    NvU32                            format;
+    NvU32                            index;
+    NvBool                           bIndexValid;
+    NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE tableType;
+} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS;
+
+/* _ctrl9096_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc.h
new file mode 100644
index 0000000..fa02e75
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc.h
@@ -0,0 +1,455 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl90cc.finn
+//
+
+
+
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl90cc/ctrl90ccbase.h"
+
+#include "ctrl90cc/ctrl90cchwpm.h"
+
+
+#include "ctrl90cc/ctrl90ccpower.h"
+
+
+/*
+ * NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM
+ *
+ * This command is deprecated; please use NV90CC_CTRL_CMD_HWPM_RESERVE.
+ *
+ * This command attempts to reserve the perfmon for use by the calling client.
+ * If this object was allocated as a child of a subdevice, then the
+ * reservation will be global among all contexts on that subdevice. If this
+ * object was allocated as a child of a channel group or a channel, then the
+ * reservation will only be for the hardware context of that channel group or
+ * channel.
+ *
+ * If the global reservation is held on a subdevice by another client, then
+ * this command will fail, regardless of the parent class.
+ *
+ * If one or more per-context reservations are held by other clients, then
+ * this command will fail if the parent object is a subdevice or another
+ * client already holds the perfmon reservation for the parent context.
+ *
+ * This command will return NV_ERR_STATE_IN_USE for all of the failure
+ * cases described above. A return status of NV_OK guarantees
+ * that the client holds the perfmon reservation of the appropriate scope.
+ *
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_STATE_IN_USE
+ */
+#define NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM              NV90CC_CTRL_CMD_HWPM_RESERVE
+
+/*
+ * NV90CC_CTRL_CMD_PROFILER_RELEASE_HWPM
+ *
+ * This command is deprecated; please use NV90CC_CTRL_CMD_HWPM_RELEASE.
+ *
+ * This command releases an existing reservation of the perfmon for the
+ * calling client. If the calling client does not currently have the perfmon
+ * reservation as acquired by NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM, this
+ * command will return NV_ERR_INVALID_REQUEST.
+ *
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_REQUEST
+ */
+#define NV90CC_CTRL_CMD_PROFILER_RELEASE_HWPM              NV90CC_CTRL_CMD_HWPM_RELEASE
+
+
+
+/*
+ * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS
+ *
+ * This command is deprecated; please use
+ * NV90CC_CTRL_CMD_POWER_REQUEST_POWER_FEATURES.
+ *
+ * This command attempts to enable or disable various clock-gating features of
+ * the GPU on behalf of the profiler. If this command is unable to set the
+ * clock-gating feature state of any of the requested features, this command
+ * will fail and none of the requested features will be modified. If this
+ * command fails because one or more clock-gating feature requests were
+ * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus
+ * parameter and the fields in the statusMask parameter for the features for
+ * which the requests were rejected will have the value
+ * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED.
+ * If a given feature is not supported on the GPU, the field for that clock-
+ * gating feature will have the value
+ * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED in the
+ * statusMask parameter, but this condition by itself will not cause the
+ * command to fail. Even if this command fails, the field for clock-gating
+ * features which would have successfully changed will have the value
+ * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_FULFILLED in the statusMask
+ * parameter.
+ *
+ * Each of the clock-gating features is reference-counted individually, so
+ * that multiple GF100_PROFILER objects may request and rely on the same
+ * settings for the features simultaneously. Each clock-gating feature is
+ * locked to the requested state until the GF100_PROFILER object is freed or
+ * the NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS command is called for that
+ * feature.
+ *
+ * Currently, only GF100_PROFILER requests for power features using this
+ * command are reference counted. Changes to the power feature settings made
+ * either by other control commands or the RM itself may interfere with the
+ * settings requested by GF100_PROFILER instances.
+ *
+ * This command will always return NV_OK when given valid
+ * parameters. If there is any other failure that prevents the clock-gating
+ * features from being set appropriately, the globalStatus parameter will
+ * indicate this and the statusMask parameter will indicate which clock-gating
+ * feature requests failed and why.
+ *
+ *   controlMask
+ *     This parameter indicates which clock-gating features the request should
+ *     apply to. This parameter has the following fields:
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG
+ *         The value of this field indicates whether this request should apply
+ *         to engine-level clock-gating of the GR engine. Valid values for
+ *         this field are:
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE
+ *             This value indicates that the GR engine-level clock-gating
+ *             should be ignored. This will not affect the reference count for
+ *             this feature.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE
+ *             This value indicates that the GR engine-level clock-gating
+ *             should be disabled.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE
+ *             This value indicates that the GR engine-level clock-gating
+ *             should be enabled.
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG
+ *         The value of this field indicates whether this request should apply
+ *         to block-level clock-gating. Valid values for this field are:
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE
+ *             This value indicates that block-level clock-gating should be
+ *             ignored. This will not affect the reference count for this
+ *             feature.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE
+ *             This value indicates that block-level clock-gating should be
+ *             disabled.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE
+ *             This value indicates that block-level clock-gating should be
+ *             enabled.
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG
+ *         The value of this field indicates whether this request should apply
+ *         to second-level clock-gating. Valid values for this field are:
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE
+ *             This value indicates that second-level clock-gating should be
+ *             ignored. This will not affect the reference count for this
+ *             feature.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE
+ *             This value indicates that second-level clock-gating should be
+ *             disabled.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE
+ *             This value indicates that second-level clock-gating should be
+ *             enabled.
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG
+ *         The value of this field indicates whether this request should apply
+ *         to GR engine-level power-gating. Valid values for this field are:
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE
+ *             This value indicates that engine-level power-gating should be
+ *             ignored. This will not affect the reference count for this
+ *             feature.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE
+ *             This value indicates that engine-level power-gating should be
+ *             disabled.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE
+ *             This value indicates that engine-level power-gating should be
+ *             enabled.
+ *         Note that this field is only temporary to allow reference counting
+ *         restricted to GF100_PROFILER instances, until the time when the
+ *         existing controls for this power feature can be updated to support
+ *         reference counting across all clients and the RM.
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN
+ *         The value of this field indicates whether this request should apply
+ *         to SM idle slowdown. Valid values for this field are:
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE
+ *             This value indicates that SM idle slowdown should be ignored.
+ *             This will not affect the reference count for this feature.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE
+ *             This value indicates that SM idle slowdown should be disabled.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE
+ *             This value indicates that SM idle slowdown should be enabled.
+ *         Note that this field is only temporary to allow reference counting
+ *         restricted to GF100_PROFILER instances, until the time when the
+ *         existing controls for this power feature can be updated to support
+ *         reference counting across all clients and the RM.
+  *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT
+ *         The value of this field indicates whether this request should apply
+ *         to VAT. Valid values for this field are:
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE
+ *             This value indicates that VAT should be ignored.
+ *             This will not affect the reference count for this feature.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE
+ *             This value indicates that VAT should be disabled.
+ *           NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE
+ *             This value indicates that VAT should be enabled.
+ *         Note that this field is only temporary to allow reference counting
+ *         restricted to GF100_PROFILER instances, until the time when the
+ *         existing controls for this power feature can be updated to support
+ *         reference counting across all clients and the RM.
+ *   globalStatus
+ *     This parameter returns the overall status of the requests for all
+ *     clock-gating controls. If the value of this parameter is not
+ *     NV_OK, none of the clock-gating controls will be set as
+ *     requested. Possible values for this parameter are:
+ *       NV_OK
+ *         This value indicates that all of the clock-gating control requests
+ *         were either fulfilled or not supported on the hardware.
+ *       NV_ERR_INVALID_REQUEST
+ *         This value indicates that at least one of the clock-gating control
+ *         requests were invalid given the GF100_PROFILER instance's
+ *         outstanding requests.
+ *       NV_ERR_STATE_IN_USE
+ *         This value indicates that at least one of the clock-gating controls
+ *         has already been locked to a conflicting state by another
+ *         GF100_PROFILER instance or the RM itself.
+ *   statusMask
+ *     This parameter returns the status of the request to set each clock-
+ *     gating control specified by the controlMask parameter. The fields are
+ *     identical to those of the controlMask parameter. For each field for
+ *     which the corresponding field in the controlMask parameter has the
+ *     value NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE, the value is
+ *     undefined. For each field for which the corresponding field in the
+ *     controlMask parameter has the value
+ *     NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST, the value will be
+ *     one of the following:
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FULFILLED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question was enabled or disabled according to the
+ *         controlMask parameter, and the reference count for the feature was
+ *         incremented accordingly.
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question was not set to the expected state according
+ *         to the controlMask parameter because another conflicting request is
+ *         currently outstanding for the clock-gating feature.
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FAILED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question was not set to the expected state according
+ *         to the controlMask parameter because the attempt to do so failed
+ *         with an error other than a conflicting request.
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question is not supported on this GPU. 
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES
+
+typedef NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS NV90CC_CTRL_PROFILER_REQUEST_CG_CONTROLS_PARAMS;
+
+/* valid fields for the controlMask and statusMask parameters */
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG                 1:0
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG                 3:2
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG                 5:4
+
+/* 
+ * The following are temporary fields for the controlMask and statusMask
+ * parameters. They are required to reference count their respective features
+ * until the existing RM controls can be safely updated, and the definitions
+ * for these features will be removed soon after that.
+ */
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG                 7:6
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN        9:8
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT                  11:10
+
+/* valid values for fields in the controlMask parameter */
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE                                   (0x00000000)
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE                                  (0x00000001)
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE                                   (0x00000002)
+
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE                         NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE                        NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE                         NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE                         NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE                        NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE                         NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE                         NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE                        NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE                         NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE                         NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE                        NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE                         NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE                NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE               NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE                NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE                          NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE                         NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE                          NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE
+/* possible values for fields in the statusMask parameter */
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED                        (0x00000000)
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED                         (0x00000001)
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED                    (0x00000002)
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED                           (0x00000003)
+
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FULFILLED              NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_REJECTED               NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_NOT_SUPPORTED          NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FAILED                 NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FULFILLED              NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_REJECTED               NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_NOT_SUPPORTED          NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FAILED                 NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FULFILLED              NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_REJECTED               NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_NOT_SUPPORTED          NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FAILED                 NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FULFILLED              NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_REJECTED               NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_NOT_SUPPORTED          NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FAILED                 NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED     NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED      NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FAILED        NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FULFILLED               NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_REJECTED                NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_NOT_SUPPORTED           NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FAILED                  NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED
+
+/* utility masks for the controlMask parameter for all controls */
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL                             \
+    DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG) |               \
+    DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG) |               \
+    DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG) |               \
+    DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG) |               \
+    DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN) |      \
+    DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT)
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_IGNORE                      \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _IGNORE) |          \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _IGNORE) |          \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _IGNORE) |          \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _IGNORE) |          \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _IGNORE) | \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _IGNORE)
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_DISABLE                     \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _DISABLE) |         \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _DISABLE) |         \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _DISABLE) |         \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _DISABLE) |         \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _DISABLE)| \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _DISABLE)
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_ENABLE                      \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _ENABLE) |          \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _ENABLE) |          \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _ENABLE) |          \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _ENABLE) |          \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _ENABLE) | \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _ENABLE)
+
+/*
+ * NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS
+ *
+ * This command is deprecated; please us
+ * NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES.
+ *
+ * This command releases the GF100_PROFILER's request for the given clock-
+ * gating features that was previously created by the
+ * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS command. If the GF100_PROFILER
+ * object does not have an outstanding request to one or more of the given
+ * clock-gating features, those features will be ignored while the other
+ * feature requests will be released.
+ *
+ * After calling this command, the calling client may not rely on the current
+ * value of any of the released clock-gating features to remain, even if
+ * several identical requests for the given clock-gating features were made
+ * using NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS. The RM only reference-
+ * counts the settings requested by GF100_PROFILER instances - it does not
+ * reference-count multiple identical requests made using the same
+ * GF100_PROFILER instance.
+ *
+ * All outstanding requests made using this GF100_PROFILER object are
+ * implicitly released when the GF100_PROFILER is freed.
+ *
+ *   controlMask
+ *     This parameter indicates which clock-gating features the RM should
+ *     release the GF100_PROFILER's reference to. See
+ *     NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS for valid fields. Valid
+ *     values for each field are:
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE
+ *         This value indicates that the clock-gating feature associated with
+ *         the field should not be released, even if the GF100_PROFILER has an
+ *         outstanding request for it. This will not affect the reference
+ *         count for the feature.
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE
+ *       NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE
+ *         This value indicates that the GF100_PROFILER's outstanding request
+ *         for the clock-gating feature associated with the field should be
+ *         released. This will decrement the reference count for the feature
+ *         if the GF100_PROFILER has an outstanding request for it.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS                             NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES
+
+typedef NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS NV90CC_CTRL_PROFILER_RELEASE_CG_CONTROLS_PARAMS;
+
+/* 
+ * valid values for the controlMask parameter in addition to
+ * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE
+ */
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE                    (0x00000003)
+
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE          NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE          NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE          NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE          NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE           NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE
+
+/* utility mask for the controlMask parameter for all fields */
+#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_RELEASE                     \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _RELEASE) |         \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _RELEASE) |         \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _RELEASE) |         \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _RELEASE) |         \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _RELEASE)| \
+    DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _RELEASE)
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h
new file mode 100644
index 0000000..707ec03
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h
@@ -0,0 +1,54 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl90cc/ctrl90ccbase.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* GF100_PROFILER control commands and parameters */
+
+#define NV90CC_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x90CC, NV90CC_CTRL_##cat, idx)
+
+/* GF100_PROFILER command categories (6 bits) */
+#define NV90CC_CTRL_RESERVED (0x00)
+#define NV90CC_CTRL_HWPM     (0x01)
+
+
+#define NV90CC_CTRL_POWER    (0x03)
+
+/*
+ * NV90CC_CTRL_CMD_NULL
+ *
+ *    This command does nothing.
+ *    This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ */
+#define NV90CC_CTRL_CMD_NULL (0x90cc0000) /* finn: Evaluated from "(FINN_GF100_PROFILER_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* _ctrl90ccbase_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h
new file mode 100644
index 0000000..b1013f2
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h
@@ -0,0 +1,135 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl90cc/ctrl90cchwpm.finn
+//
+
+#include "ctrl/ctrl90cc/ctrl90ccbase.h"
+
+/* GF100_PROFILER HWPM control commands and parameters */
+
+/*
+ * NV90CC_CTRL_CMD_HWPM_RESERVE
+ *
+ * This command attempts to reserve the perfmon for use by the calling client.
+ * If this object was allocated as a child of a subdevice, then the
+ * reservation will be global among all contexts on that subdevice. If this
+ * object was allocated as a child of a channel group or a channel, then the
+ * reservation will only be for the hardware context of that channel group or
+ * channel.
+ *
+ * If the global reservation is held on a subdevice by another client, then
+ * this command will fail, regardless of the parent class.
+ *
+ * If one or more per-context reservations are held by other clients, then
+ * this command will fail if the parent object is a subdevice or another
+ * client already holds the perfmon reservation for the parent context.
+ *
+ * This command will return NV_ERR_STATE_IN_USE for all of the failure
+ * cases described above. A return status of NV_OK guarantees
+ * that the client holds the perfmon reservation of the appropriate scope.
+ *
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_STATE_IN_USE
+ */
+#define NV90CC_CTRL_CMD_HWPM_RESERVE              (0x90cc0101) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | 0x1" */
+
+/*
+ * NV90CC_CTRL_CMD_HWPM_RELEASE
+ *
+ * This command releases an existing reservation of the perfmon for the
+ * calling client. If the calling client does not currently have the perfmon
+ * reservation as acquired by NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM, this
+ * command will return NV_ERR_INVALID_REQUEST.
+ *
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_REQUEST
+ */
+#define NV90CC_CTRL_CMD_HWPM_RELEASE              (0x90cc0102) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | 0x2" */
+
+/*
+ * NV90CC_CTRL_CMD_HWPM_GET_RESERVATION_INFO
+ *
+ * This command returns information about any outstanding perfmon
+ * reservations. If this object was allocated as a child of a subdevice, then
+ * this command will return information about all reservations on the
+ * subdevice (global or per-context). If this object was allocated as a child
+ * of a channel group or channel, then this command will only return
+ * information about the per-context reservation for that context or the
+ * global reservation, if one exists.
+ *
+ *   reservationCount
+ *     This parameter returns the number of outstanding perfmon reservations
+ *     in the applicable scope. If the value of the bGlobal parameter is
+ *     NV_TRUE, then this parameter will have a value of 1. If this object was
+ *     allocated as a child of a channel group or channel, then this parameter
+ *     will have a value of either 0 or 1. If this object was allocated as a
+ *     child of a subdevice and the bGlobal parameter is NV_FALSE, then this
+ *     parameter will return the number of per-context reservations on the
+ *     subdevice.
+ *   pid
+ *     This parameter returns the PID of a process that holds a reservation in
+ *     the applicable scope. If the value of the bGlobal parameter is NV_TRUE,
+ *     then this parameter will be the PID of the process holding the global
+ *     perfmon reservation on the subdevice. Otherwise, if the value of
+ *     reservationCount is greater than 0, the value of this parameter will be
+ *     the PID of one of the process that holds the per-context lock in the
+ *     applicable scope. If the value of the reservationCount parameter is 0,
+ *     the value of this parameter is undefined.
+ *   bGlobal
+ *     This parameter returns whether the outstanding perfmon reservation held
+ *     by any client is global or per-context. If the value of this parameter
+ *     is NV_TRUE, then the value of the reservationCount parameter should be 1
+ *     and the value of the pid parameter should be the pid of the process
+ *     that holds the global perfmon reservation. The value of this parameter
+ *     will be NV_FALSE when there is no global perfmon reservation.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV90CC_CTRL_CMD_HWPM_GET_RESERVATION_INFO (0x90cc0103) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS {
+    NvU32  reservationCount;
+    NvU32  pid;
+    NvBool bGlobal;
+} NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS;
+
+
+
+/* _ctrl90cchwpm_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h
new file mode 100644
index 0000000..aa25ceb
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h
@@ -0,0 +1,403 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl90cc/ctrl90ccpower.finn
+//
+
+#include "ctrl/ctrl90cc/ctrl90ccbase.h"
+
+/* GF100_PROFILER GPU control commands and parameters */
+/*
+ * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES
+ *
+ * This command attempts to enable or disable various clock-gating features of
+ * the GPU on behalf of the profiler. If this command is unable to set the
+ * clock-gating feature state of any of the requested features, this command
+ * will fail and none of the requested features will be modified. If this
+ * command fails because one or more clock-gating feature requests were
+ * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus
+ * parameter and the fields in the statusMask parameter for the features for
+ * which the requests were rejected will have the value
+ * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED.
+ * If a given feature is not supported on the GPU, the field for that clock-
+ * gating feature will have the value
+ * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED in the
+ * statusMask parameter, but this condition by itself will not cause the
+ * command to fail. Even if this command fails, the field for clock-gating
+ * features which would have successfully changed will have the value
+ * NV90CC_CTRL_POWER_FEATURE_MASK_*_FULFILLED in the statusMask
+ * parameter.
+ *
+ * Each of the clock-gating features is reference-counted individually, so
+ * that multiple GF100_PROFILER objects may request and rely on the same
+ * settings for the features simultaneously. Each clock-gating feature is
+ * locked to the requested state until the GF100_PROFILER object is freed or
+ * the NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES command is called for that
+ * feature.
+ *
+ * Currently, only GF100_PROFILER requests for power features using this
+ * command are reference counted. Changes to the power feature settings made
+ * either by other control commands or the RM itself may interfere with the
+ * settings requested by GF100_PROFILER instances.
+ *
+ * This command will always return NV_OK when given valid
+ * parameters. If there is any other failure that prevents the clock-gating
+ * features from being set appropriately, the globalStatus parameter will
+ * indicate this and the statusMask parameter will indicate which clock-gating
+ * feature requests failed and why.
+ *
+ *   controlMask
+ *     This parameter indicates which clock-gating features the request should
+ *     apply to. This parameter has the following fields:
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_ELCG
+ *         The value of this field indicates whether this request should apply
+ *         to engine-level clock-gating of the GR engine. Valid values for
+ *         this field are:
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE
+ *             This value indicates that the GR engine-level clock-gating
+ *             should be ignored. This will not affect the reference count for
+ *             this feature.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE
+ *             This value indicates that the GR engine-level clock-gating
+ *             should be disabled.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE
+ *             This value indicates that the GR engine-level clock-gating
+ *             should be enabled.
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_BLCG
+ *         The value of this field indicates whether this request should apply
+ *         to block-level clock-gating. Valid values for this field are:
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE
+ *             This value indicates that block-level clock-gating should be
+ *             ignored. This will not affect the reference count for this
+ *             feature.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE
+ *             This value indicates that block-level clock-gating should be
+ *             disabled.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE
+ *             This value indicates that block-level clock-gating should be
+ *             enabled.
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_SLCG
+ *         The value of this field indicates whether this request should apply
+ *         to second-level clock-gating. Valid values for this field are:
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE
+ *             This value indicates that second-level clock-gating should be
+ *             ignored. This will not affect the reference count for this
+ *             feature.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE
+ *             This value indicates that second-level clock-gating should be
+ *             disabled.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE
+ *             This value indicates that second-level clock-gating should be
+ *             enabled.
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_ELPG
+ *         The value of this field indicates whether this request should apply
+ *         to GR engine-level power-gating. Valid values for this field are:
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE
+ *             This value indicates that engine-level power-gating should be
+ *             ignored. This will not affect the reference count for this
+ *             feature.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE
+ *             This value indicates that engine-level power-gating should be
+ *             disabled.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE
+ *             This value indicates that engine-level power-gating should be
+ *             enabled.
+ *         Note that this field is only temporary to allow reference counting
+ *         restricted to GF100_PROFILER instances, until the time when the
+ *         existing controls for this power feature can be updated to support
+ *         reference counting across all clients and the RM.
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN
+ *         The value of this field indicates whether this request should apply
+ *         to SM idle slowdown. Valid values for this field are:
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE
+ *             This value indicates that SM idle slowdown should be ignored.
+ *             This will not affect the reference count for this feature.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE
+ *             This value indicates that SM idle slowdown should be disabled.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE
+ *             This value indicates that SM idle slowdown should be enabled.
+ *         Note that this field is only temporary to allow reference counting
+ *         restricted to GF100_PROFILER instances, until the time when the
+ *         existing controls for this power feature can be updated to support
+ *         reference counting across all clients and the RM.
+  *       NV90CC_CTRL_POWER_FEATURE_MASK_VAT
+ *         The value of this field indicates whether this request should apply
+ *         to VAT. Valid values for this field are:
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE
+ *             This value indicates that VAT should be ignored.
+ *             This will not affect the reference count for this feature.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE
+ *             This value indicates that VAT should be disabled.
+ *           NV90CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE
+ *             This value indicates that VAT should be enabled.
+ *         Note that this field is only temporary to allow reference counting
+ *         restricted to GF100_PROFILER instances, until the time when the
+ *         existing controls for this power feature can be updated to support
+ *         reference counting across all clients and the RM.
+ *   globalStatus
+ *     This parameter returns the overall status of the requests for all
+ *     clock-gating controls. If the value of this parameter is not
+ *     NV_OK, none of the clock-gating controls will be set as
+ *     requested. Possible values for this parameter are:
+ *       NV_OK
+ *         This value indicates that all of the clock-gating control requests
+ *         were either fulfilled or not supported on the hardware.
+ *       NV_ERR_INVALID_REQUEST
+ *         This value indicates that at least one of the clock-gating control
+ *         requests were invalid given the GF100_PROFILER instance's
+ *         outstanding requests.
+ *       NV_ERR_STATE_IN_USE
+ *         This value indicates that at least one of the clock-gating controls
+ *         has already been locked to a conflicting state by another
+ *         GF100_PROFILER instance or the RM itself.
+ *   statusMask
+ *     This parameter returns the status of the request to set each clock-
+ *     gating control specified by the controlMask parameter. The fields are
+ *     identical to those of the controlMask parameter. For each field for
+ *     which the corresponding field in the controlMask parameter has the
+ *     value NV90CC_CTRL_POWER_FEATURE_MASK_*_IGNORE, the value is
+ *     undefined. For each field for which the corresponding field in the
+ *     controlMask parameter has the value
+ *     NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST, the value will be
+ *     one of the following:
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FULFILLED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question was enabled or disabled according to the
+ *         controlMask parameter, and the reference count for the feature was
+ *         incremented accordingly.
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question was not set to the expected state according
+ *         to the controlMask parameter because another conflicting request is
+ *         currently outstanding for the clock-gating feature.
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FAILED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question was not set to the expected state according
+ *         to the controlMask parameter because the attempt to do so failed
+ *         with an error other than a conflicting request.
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question is not supported on this GPU. 
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES (0x90cc0301) /* finn: Evaluated from "(FINN_GF100_PROFILER_POWER_INTERFACE_ID << 8) | NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID" */
+
+#define NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS {
+    NvU32 globalStatus;
+    NvU32 controlMask;
+    NvU32 statusMask;
+} NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS;
+
+/* valid fields for the controlMask and statusMask parameters */
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG                                1:0
+#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG                                3:2
+#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG                                5:4
+
+/* 
+ * The following are temporary fields for the controlMask and statusMask
+ * parameters. They are required to reference count their respective features
+ * until the existing RM controls can be safely updated, and the definitions
+ * for these features will be removed soon after that.
+ */
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG                                7:6
+#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN                       9:8
+#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT                               11:10
+
+/* valid values for fields in the controlMask parameter */
+#define NV90CC_CTRL_POWER_FEATURE_IGNORE                                   (0x00000000)
+#define NV90CC_CTRL_POWER_FEATURE_DISABLE                                  (0x00000001)
+#define NV90CC_CTRL_POWER_FEATURE_ENABLE                                   (0x00000002)
+
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE                         NV90CC_CTRL_POWER_FEATURE_IGNORE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE                        NV90CC_CTRL_POWER_FEATURE_DISABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE                         NV90CC_CTRL_POWER_FEATURE_ENABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE                         NV90CC_CTRL_POWER_FEATURE_IGNORE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE                        NV90CC_CTRL_POWER_FEATURE_DISABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE                         NV90CC_CTRL_POWER_FEATURE_ENABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE                         NV90CC_CTRL_POWER_FEATURE_IGNORE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE                        NV90CC_CTRL_POWER_FEATURE_DISABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE                         NV90CC_CTRL_POWER_FEATURE_ENABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE                         NV90CC_CTRL_POWER_FEATURE_IGNORE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE                        NV90CC_CTRL_POWER_FEATURE_DISABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE                         NV90CC_CTRL_POWER_FEATURE_ENABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE                NV90CC_CTRL_POWER_FEATURE_IGNORE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE               NV90CC_CTRL_POWER_FEATURE_DISABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE                NV90CC_CTRL_POWER_FEATURE_ENABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE                          NV90CC_CTRL_POWER_FEATURE_IGNORE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE                         NV90CC_CTRL_POWER_FEATURE_DISABLE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE                          NV90CC_CTRL_POWER_FEATURE_ENABLE
+/* possible values for fields in the statusMask parameter */
+#define NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED                        (0x00000000)
+#define NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED                         (0x00000001)
+#define NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED                    (0x00000002)
+#define NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED                           (0x00000003)
+
+#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED              NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED               NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED          NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED                 NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED              NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED               NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED          NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED                 NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED              NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED               NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED          NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED                 NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED              NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED               NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED          NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED                 NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED     NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED      NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED        NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED               NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED                NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED           NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED                  NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+
+/* utility masks for the controlMask parameter for all controls */
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL                                   \
+    DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_ELCG) |                     \
+    DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_BLCG) |                     \
+    DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_SLCG) |                     \
+    DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_ELPG) |                     \
+    DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN) |            \
+    DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_VAT)
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_IGNORE                            \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _IGNORE) |                \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _IGNORE) |                \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _IGNORE) |                \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _IGNORE) |                \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _IGNORE) |       \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _IGNORE)
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_DISABLE                           \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _DISABLE) |               \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _DISABLE) |               \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _DISABLE) |               \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _DISABLE) |               \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _DISABLE)|       \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _DISABLE)
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_ENABLE                            \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _ENABLE) |                \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _ENABLE) |                \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _ENABLE) |                \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _ENABLE) |                \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _ENABLE) |       \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _ENABLE)
+
+/*
+ * NV90CC_CTRL_CMD_POWER_RELEASE_FEATUERS
+ *
+ * This command releases the GF100_PROFILER's request for the given clock-
+ * gating features that was previously created by the
+ * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES command. If the GF100_PROFILER
+ * object does not have an outstanding request to one or more of the given
+ * clock-gating features, those features will be ignored while the other
+ * feature requests will be released.
+ *
+ * After calling this command, the calling client may not rely on the current
+ * value of any of the released clock-gating features to remain, even if
+ * several identical requests for the given clock-gating features were made
+ * using NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES. The RM only reference-
+ * counts the settings requested by GF100_PROFILER instances - it does not
+ * reference-count multiple identical requests made using the same
+ * GF100_PROFILER instance.
+ *
+ * All outstanding requests made using this GF100_PROFILER object are
+ * implicitly released when the GF100_PROFILER is freed.
+ *
+ *   controlMask
+ *     This parameter indicates which clock-gating features the RM should
+ *     release the GF100_PROFILER's reference to. See
+ *     NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES for valid fields. Valid
+ *     values for each field are:
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE
+ *         This value indicates that the clock-gating feature associated with
+ *         the field should not be released, even if the GF100_PROFILER has an
+ *         outstanding request for it. This will not affect the reference
+ *         count for the feature.
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE
+ *       NV90CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE
+ *         This value indicates that the GF100_PROFILER's outstanding request
+ *         for the clock-gating feature associated with the field should be
+ *         released. This will decrement the reference count for the feature
+ *         if the GF100_PROFILER has an outstanding request for it.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES                             (0x90cc0302) /* finn: Evaluated from "(FINN_GF100_PROFILER_POWER_INTERFACE_ID << 8) | NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID" */
+
+#define NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS {
+    NvU32 controlMask;
+} NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS;
+
+/* 
+ * valid values for the controlMask parameter in addition to
+ * NV90CC_CTRL_POWER_FEATURE_MASK_*_IGNORE
+ */
+#define NV90CC_CTRL_POWER_FEATURE_RELEASE                    (0x00000003)
+
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE          NV90CC_CTRL_POWER_FEATURE_RELEASE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE          NV90CC_CTRL_POWER_FEATURE_RELEASE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE          NV90CC_CTRL_POWER_FEATURE_RELEASE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE          NV90CC_CTRL_POWER_FEATURE_RELEASE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE
+#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE           NV90CC_CTRL_POWER_FEATURE_RELEASE
+
+
+/* _ctrl90ccpower_h_ */
+
+/* utility mask for the controlMask parameter for all fields */
+#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_RELEASE                           \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _RELEASE) |               \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _RELEASE) |               \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _RELEASE) |               \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _RELEASE) |               \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _RELEASE)|       \
+    DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _RELEASE)
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cd.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cd.h
new file mode 100644
index 0000000..29449ab
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cd.h
@@ -0,0 +1,174 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl90cd.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV_EVENT_BUFFER control commands and parameters */
+
+#define NV_EVENT_BUFFER_CTRL_CMD(cat,idx)           NVXXXX_CTRL_CMD(0x90CD, NV90CD_CTRL_##cat, idx)
+
+#define NV90CD_CTRL_RESERVED          (0x00)
+#define NV90CD_CTRL_EVENT             (0x01)
+
+/*
+* NV_EVENT_BUFFER_CTRL_CMD_NULL
+*
+* This command does nothing.
+* This command does not take any parameters.
+*
+* Possible status values returned are:
+*   NV_OK
+*/
+#define NV_EVENT_BUFFER_CTRL_CMD_NULL (0x90cd0000) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+* NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS
+*   This interface enables all the events that are associated to the event buffer
+*/
+#define NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS           (0x90cd0101) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x1" */
+
+#define NV_EVENT_BUFFER_FLAG                                    0:32
+
+/*
+* NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY
+*   This flag defines the kernel behavior when the buffer is full
+*
+*   DEFAULT/DISABLED: By default kernel doesn't assume any policy. To enable events
+*                     an overflow policy has to be set to retain older or newer events
+*
+*   KEEP_OLDEST: kernel would retain older events and drop newer events if the buffer is full
+*
+*   KEEP_NEWEST: kernel would retain newer events and drop older events if the buffer is full
+*
+*/
+#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY                    0:1
+#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DISABLED    0
+#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_KEEP_OLDEST 1
+#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_KEEP_NEWEST 2
+#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DEFAULT     NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DISABLED
+
+/*
+* NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS
+*
+*   enable [IN]
+*       This field is used to enable or disable events
+*
+*   flags[IN]
+*       This field sets NV_EVENT_BUFFER_FLAG parameter used to configure event buffer overflow options
+*
+*   Possible status values returned are:
+*       NV_OK
+*       NV_ERR_INVALID_ARGUMENT
+*/
+typedef struct NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS {
+    NvBool enable;
+    NvU32  flags;
+} NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS;
+
+/*
+* NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET
+*   This interface allows the user to update get pointers.
+*   This call is useful in the KEEP_OLDEST policy to update free space available in the buffer.
+*   In keep oldest policy, kernel adds new entries in the buffer only if there is free space.
+*   The full/empty decision is made as follows:
+*   -   when GET==PUT, the fifo is empty
+*   -   when GET==PUT+1, the fifo is full
+*/
+#define NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET (0x90cd0102) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x2" */
+
+/*
+* NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS
+*
+*   recordBufferGet [IN]
+*       Value to be used to update the get offset of record buffer
+*
+*   varDataBufferGet[IN]
+*       This is the buffer offset up to which user has consumed the vardataBuffer
+*
+*   Possible status values returned are:
+*       NV_OK
+*       NV_ERR_INVALID_ARGUMENT: if any of the get offsets is greater than respective bufferSize.
+*/
+typedef struct NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS {
+    NvU32 recordBufferGet;
+    NvU32 varDataBufferGet;
+} NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS;
+
+/*
+ * Send a test event-buffer notification (verification-only)
+ */
+#define NV_EVENT_BUFFER_CTRL_CMD_VERIF_NOTIFY         (0x90cd0103) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x3" */
+
+/*
+ * Synchronous flush
+ */
+#define NV_EVENT_BUFFER_CTRL_CMD_FLUSH                (0x90cd0104) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x4" */
+
+/*
+ * post event
+ */
+#define NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT (0x90cd0105) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x5" */
+
+ /*
+  *  NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS
+  *
+  * eventType [IN]
+  *     the NvTelemetry event type.
+  * typeVersion [IN]
+  *     the version of the event structure
+  * eventData [IN]
+  *     an array of 256 bytes used to hold the event data.
+  * eventDataSz [IN]
+  *     the amount of valid data in the eventData buffer.
+  * varData [IN]
+  *     an array of 256 bytes used to hold the var data.
+  * varDataSz [IN]
+  *     the amount of valid data in the varData buffer.
+  *
+  *   Possible status values returned are:
+  *       NV_OK
+  *       NV_ERR_INVALID_ARGUMENT
+  */
+typedef struct NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS {
+    NvU32 eventType;
+    NvU16 typeVersion;
+    NvU8  eventData[256];
+    NvU16 eventDataSz;
+    NvU8  varData[256];
+    NvU16 varDataSz;
+} NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS;
+
+/* _ctr l90cd_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90e6.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90e6.h
new file mode 100644
index 0000000..ad1d9fb
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90e6.h
@@ -0,0 +1,137 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl90e6.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#define NV90E6_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0x90E6, NV90E6_CTRL_##cat, idx)
+
+
+/* NV90E6 command categories (6bits) */
+#define NV90E6_CTRL_RESERVED (0x00)
+#define NV90E6_CTRL_MASTER   (0x01)
+
+
+/*
+ * NV90E6_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NV90E6_CTRL_CMD_NULL (0x90e60000) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+ * NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK
+ *
+ * This command is used to query the offset and mask within the object mapping
+ * that can be used to query for ECC and NVLINK interrupts.
+ *
+ * If a read of the given offset+mask is non-zero then it is possible an ECC or
+ * an NVLINK error has been reported and not yet handled. If this is true then
+ * the caller must either wait until the read returns zero or call into the
+ * corresponding count reporting APIs to get updated counts.
+ *
+ * offset
+ *   The offset into a GF100_SUBDEVICE_MASTSER's mapping where the top level
+ *   interrupt register can be found.
+ * mask
+ *   Compatibility field that contains the same bits as eccMask. This field is
+ *   deprecated and will be removed.
+ * eccMask
+ *   The mask to AND with the value found at offset to determine if any ECC
+ *   interrupts are pending.
+ * nvlinkMask
+ *   The mask to AND with the value found at offset to determine if any NVLINK
+ *   interrupts are pending.
+ *
+ *   Possible return status values are
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ *     NV_ERR_NOT_SUPPORTED
+ */
+#define NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK (0x90e60101) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID << 8) | NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS {
+    NvU32 offset;
+    NvU32 mask;     // TODO: remove after all users have switched to use eccMask
+    NvU32 eccMask;
+    NvU32 nvlinkMask;
+} NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS;
+
+// TODO: remove once users of this interface have switched to the new name.
+#define NV90E6_CTRL_CMD_MASTER_GET_ECC_INTR_OFFSET_MASK NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK
+
+typedef NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS NV90E6_CTRL_MASTER_GET_ECC_INTR_OFFSET_MASK_PARAMS;
+
+/*
+ * NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK
+ *
+ * This command is used to query the mask within the fastpath register
+ * (VIRTUAL_FUNCTION_ERR_CONT) that can be used to query for ECC and NVLINK interrupts.
+ *
+ * If a read of the given mask is non-zero then it is possible an ECC or
+ * an NVLINK error has been reported and not yet handled. If this is true then
+ * the caller must either wait until the read returns zero or call into the
+ * corresponding count reporting APIs to get updated counts.
+ *
+ * [out] eccMask
+ *   The mask to AND with the value found at offset to determine if any ECC
+ *   interrupts are possibly pending.
+ * [out] nvlinkMask
+ *   The mask to AND with the value found at offset to determine if any NVLINK
+ *   interrupts are possibly pending.
+ *
+ *   Possible return status values are
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ *     NV_ERR_NOT_SUPPORTED
+ */
+#define NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK (0x90e60102) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID << 8) | NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS {
+    NvU32 eccMask;
+    NvU32 nvlinkMask;
+} NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS;
+
+/* _ctrl90e6_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90ec.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90ec.h
new file mode 100644
index 0000000..00094c1
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90ec.h
@@ -0,0 +1,124 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl90ec.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* GK104 HDACODEC control commands and parameters */
+
+#define NV90EC_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x90EC, NV90EC_CTRL_##cat, idx)
+
+/* NV04_DISPLAY_COMMON command categories (6bits) */
+#define NV90EC_CTRL_RESERVED (0x00)
+#define NV90EC_CTRL_HDACODEC (0x01)
+
+/*
+ * NV90EC_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV90EC_CTRL_CMD_NULL (0x90ec0000) /* finn: Evaluated from "(FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/* 
+ * NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE
+ *
+ * This command sets the CP_READY bit. It basically informs RM whether
+ * the DD has worked upon the HDCP request requested by the Audio driver 
+ * or not. DD asks RM to enable CP_READY bit (by setting CpReadyEnable to NV_TRUE)
+ * once it is done honouring/dishonouring the request.
+ *
+ *   subDeviceInstance
+ *     This parameter specifies the subdevice instance within the
+ *     NV04_DISPLAY_COMMON parent device to which the operation should be 
+ *     directed. This parameter must specify a value between zero and the  
+ *     total number of subdevices within the parent device.  This parameter
+ *     should be set to zero for default behavior.
+ *   displayId
+ *     This parameter specifies the ID of the display for which the cp ready
+ *     bit should be enabled.  The display ID must a dfp display.
+ *     If the displayId is not a dfp, this call will return 
+ *     NV_ERR_INVALID_ARGUMENT.
+ *   CpReadyEnable
+ *     This parameter specifies whether to enable (NV_TRUE) or not. If CpReady
+ *     is enabled then AudioCodec can send more HDCP requests.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ * 
+ * 
+ */
+#define NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE (0x90ec0101) /* finn: Evaluated from "(FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID << 8) | NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS_MESSAGE_ID" */
+
+#define NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS {
+    NvU32  subDeviceInstance;
+    NvU32  displayId;
+    NvBool bCpReadyEnable;
+} NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS;
+
+/* 
+ * NV90EC_CTRL_CMD_HDACODEC_NOTIFY_AUDIO_EVENT
+ *
+ * This command notifies Audio of any events to audio
+ * like notification of PD bit being set.
+ *
+ *   audioEvent
+ *     This parameter specifies the event type.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ * 
+ * 
+ */
+#define NV90EC_CTRL_CMD_HDACODEC_NOTIFY_AUDIO_EVENT (0x90ec0102) /* finn: Evaluated from "(FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID << 8) | NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS_MESSAGE_ID" */
+
+#define NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS {
+    NvU32 audioEvent;
+} NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS;
+
+/*
+ * This command notifies audio driver that PD bit is set by DD, by writing to scratch register
+ */
+#define NV90EC_CTRL_HDACODEC_AUDIOEVENT_PD_BIT_SET (0x00000001)
+
+/* _ctrl90ec_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90f1.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90f1.h
new file mode 100644
index 0000000..20d94dd
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90f1.h
@@ -0,0 +1,309 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrl90f1.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#include "mmu_fmt_types.h"
+
+#define GMMU_FMT_MAX_LEVELS  6U
+
+/* Fermi+ GPU VASpace control commands and parameters */
+#define NV90F1_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0x90F1, NV90F1_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NV90F1_CTRL_RESERVED (0x00U)
+#define NV90F1_CTRL_VASPACE  (0x01U)
+
+/*!
+ * Does nothing.
+ */
+#define NV90F1_CTRL_CMD_NULL (0x90f10000U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*!
+ * Get VAS GPU MMU format.
+ */
+#define NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT (0x90f10101U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID" */
+
+#define NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS {
+    /*!
+     * [in] GPU sub-device handle - this API only supports unicast.
+     *      Pass 0 to use subDeviceId instead.
+     */
+    NvHandle hSubDevice;
+
+    /*!
+     * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
+     */
+    NvU32    subDeviceId;
+
+    /*!
+     * [out] GMMU format struct. This is of RM-internal type "struct GMMU_FMT*"
+     *       which can only be accessed by kernel builds since this is a kernel
+     *       only API.
+     */
+    NV_DECLARE_ALIGNED(NvP64 pFmt, 8);
+} NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS;
+
+/*!
+ * Get VAS page level information.
+ */
+#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x2" */
+
+typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS {
+    /*!
+     * [in] GPU sub-device handle - this API only supports unicast.
+     *      Pass 0 to use subDeviceId instead.
+     */
+    NvHandle hSubDevice;
+
+    /*!
+     * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
+     */
+    NvU32    subDeviceId;
+
+    /*!
+     * [in] GPU virtual address to query.
+     */
+    NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
+
+    /*!
+     * [in] Page size to query.
+     */
+    NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
+
+    /*!
+     * [out] Number of levels populated.
+     */
+    NvU32    numLevels;
+
+    /*!
+     * [out] Per-level information.
+     */
+    struct {
+        /*!
+         * Format of this level.
+         */
+        NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8);
+
+       /*!
+        * Level/Sublevel Formats flattened
+        */
+        NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8);
+        NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8);
+
+        /*!
+         * Physical address of this page level instance.
+         */
+        NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
+
+        /*!
+         * Aperture in which this page level instance resides.
+         */
+        NvU32 aperture;
+
+        /*!
+         * Size in bytes allocated for this level instance.
+         */
+        NV_DECLARE_ALIGNED(NvU64 size, 8);
+    } levels[GMMU_FMT_MAX_LEVELS];
+} NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS;
+
+/*!
+ * Reserve (allocate and bind) page directory/table entries up to
+ * a given level of the MMU format. Also referred to as "lock-down".
+ *
+ * Each range that has been reserved must be released
+ * eventually with @ref NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES.
+ * A particular VA range and level (page size) combination may only be
+ * locked down once at a given time, but each level is independent.
+ */
+#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */
+
+#define NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS {
+    /*!
+     * [in] GPU sub-device handle - this API only supports unicast.
+     *      Pass 0 to use subDeviceId instead.
+     */
+    NvHandle hSubDevice;
+
+    /*!
+     * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
+     */
+    NvU32    subDeviceId;
+
+    /*!
+     * [in] Page size (VA coverage) of the level to reserve.
+     *      This need not be a leaf (page table) page size - it can be
+     *      the coverage of an arbitrary level (including root page directory).
+     */
+    NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
+
+    /*!
+     * [in] First GPU virtual address of the range to reserve.
+     *      This must be aligned to pageSize.
+     */
+    NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8);
+
+    /*!
+     * [in] Last GPU virtual address of the range to reserve.
+     *      This (+1) must be aligned to pageSize.
+     */
+    NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8);
+} NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS;
+
+/*!
+ * Release (unbind and free) page directory/table entries up to
+ * a given level of the MMU format that has been reserved through a call to
+ * @ref NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES. Also referred to as "unlock".
+ */
+#define NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES (0x90f10104U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID" */
+
+#define NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS {
+    /*!
+     * [in] GPU sub-device handle - this API only supports unicast.
+     *      Pass 0 to use subDeviceId instead.
+     */
+    NvHandle hSubDevice;
+
+    /*!
+     * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
+     */
+    NvU32    subDeviceId;
+
+    /*!
+     * [in] Page size (VA coverage) of the level to release.
+     *      This need not be a leaf (page table) page size - it can be
+     *      the coverage of an arbitrary level (including root page directory).
+     */
+    NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
+
+    /*!
+     * [in] First GPU virtual address of the range to release.
+     *      This must be aligned to pageSize.
+     */
+    NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8);
+
+    /*!
+     * [in] Last GPU virtual address of the range to release.
+     *      This (+1) must be aligned to pageSize.
+     */
+    NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8);
+} NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS;
+
+/*!
+ * Get VAS page level information without kernel priviledge. This will internally call
+ * NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO.
+ */
+#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x5" */
+
+/*!
+ * Pin PDEs for a given VA range on the server RM and then mirror the client's page 
+ * directory/tables in the server. 
+ *  
+ * @ref
+ */
+#define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */
+
+#define NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS {
+    /*!
+     * [in] GPU sub-device handle - this API only supports unicast.
+     *      Pass 0 to use subDeviceId instead.
+     */
+    NvHandle hSubDevice;
+
+    /*!
+     * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
+     */
+    NvU32    subDeviceId;
+
+    /*!
+     * [in] Page size (VA coverage) of the level to reserve.
+     *      This need not be a leaf (page table) page size - it can be
+     *      the coverage of an arbitrary level (including root page directory).
+     */
+    NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
+
+    /*!
+     * [in] First GPU virtual address of the range to reserve.
+     *      This must be aligned to pageSize.
+     */
+    NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8);
+
+    /*!
+     * [in] Last GPU virtual address of the range to reserve.
+     *      This (+1) must be aligned to pageSize.
+     */
+    NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8);
+
+    /*! 
+     * [in] Number of PDE levels to copy.
+     */
+    NvU32    numLevelsToCopy;
+
+   /*!
+     * [in] Per-level information.
+     */
+    struct {
+        /*!
+         * Physical address of this page level instance.
+         */
+        NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
+
+        /*!
+         * Size in bytes allocated for this level instance.
+         */
+        NV_DECLARE_ALIGNED(NvU64 size, 8);
+
+        /*!
+         * Aperture in which this page level instance resides.
+         */
+        NvU32 aperture;
+
+        /*!
+         * Page shift corresponding to the level
+         */
+        NvU8  pageShift;
+    } levels[GMMU_FMT_MAX_LEVELS];
+} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS;
+
+/* _ctrl90f1_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06c.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06c.h
new file mode 100644
index 0000000..775ce94
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06c.h
@@ -0,0 +1,421 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla06c.finn
+//
+
+
+
+
+/*
+ * KEPLER_CHANNEL_GROUP_A control commands and parameters
+ *
+ * A channel group is a collection of channels which are executed in a specific
+ * order by hardware.  Hardware will not move from one channel in the group
+ * until it is finished executing all its work or gives up control to the next
+ * channel.
+ *
+ * Channels are added to the group by allocating them as a child of the
+ * KEPLER_CHANNEL_GROUP_A object.
+ *
+ * A channel in a channel group may be restricted with respect to what objects
+ * can be allocated on it and what APIs are allowed to operate on the channel.
+ * For more details on specifics of how groups behave see the Software and
+ * Hardware documetation for the specific architecture in which you are
+ * interested.
+ *
+ */
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrla06f.h"          /* A06C is partially derived from A06F */
+
+#include "ctrl/ctrl2080/ctrl2080internal.h" /* For NV2080_CTRL_INTERNAL_MEMDESC_INFO */
+#include "ctrl/ctrlc36f.h"                  /* For NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES */
+
+#define NVA06C_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0xA06C, NVA06C_CTRL_##cat, idx)
+
+/* KEPLER_CHANNEL_GROUP_A command categories (6bits) */
+#define NVA06C_CTRL_RESERVED (0x00)
+#define NVA06C_CTRL_GPFIFO   (0x01)
+#define NVA06C_CTRL_INTERNAL (0x02)
+
+/*
+ * NVA06C_CTRL_CMD_NULL
+ *
+ * Please see description of NV906D_CTRL_CMD_NULL.
+ *
+ */
+#define NVA06C_CTRL_CMD_NULL (0xa06c0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+ * NVA06C_CTRL_CMD_GPFIFO_SCHEDULE
+ *
+ * This command schedules a channel group in hardware. This command should be
+ * called after objects have been allocated on the channel or a call to
+ * NVA06C_CTRL_CMD_BIND has been made.
+ *
+ * See NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for parameter definitions.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_OPERATION
+ *
+ */
+#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE (0xa06c0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
+typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
+    NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS params;
+} NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
+
+
+
+
+/*
+ * NVA06C_CTRL_CMD_BIND
+ *
+ * This command uses the given engine to configure the group for scheduling.
+ * It alleviates the need to call NVA06C_CTRL_CMD_GPFIFO_SCHEDULE after objects
+ * have been allocated.  However, it requires that the caller know which engine
+ * they want to be able to execute in the group.  Once this has been called
+ * only objects that can be allocated on the specified engine or other engines
+ * allowed to coexist in the group will be allowed.  See
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST to determine which engines can
+ * share a parent.
+ *
+ * See NVA06F_CTRL_CMD_BIND for parameter definitions.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA06C_CTRL_CMD_BIND (0xa06c0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID" */
+
+#define NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID (0x2U)
+
+typedef NVA06F_CTRL_BIND_PARAMS NVA06C_CTRL_BIND_PARAMS;
+
+/*
+ * NVA06C_CTRL_CMD_SET_TIMESLICE
+ *
+ * This command modifies the timeslice for a channel group.  Hardware may not
+ * support all possible values, so the input will be rounded down to a valid
+ * hardware value.
+ *
+ * This takes effect immediately, meaning the channel may be forced off of the
+ * GPU so the change can be made.
+ *
+ * timesliceUs
+ *   This parameter is an input containing the desired timeslice in microseconds
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA06C_CTRL_CMD_SET_TIMESLICE (0xa06c0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */
+
+/*
+ * NVA06C_CTRL_CMD_GET_TIMESLICE
+ *
+ * This command returns the timeslice for a channel group.  If
+ * NVA06C_CTRL_CMD_SET_TIMESLICE has been used this call will return the exact
+ * value passed to that function, which may not be exactly what is programmed
+ * to hardware (see NVA06C_CTRL_CMD_SET_TIMESLICE for more details).
+ *
+ * timesliceUs
+ *   This parameter is an output containing current timeslice in microseconds.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA06C_CTRL_CMD_GET_TIMESLICE (0xa06c0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */
+
+typedef struct NVA06C_CTRL_TIMESLICE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 timesliceUs, 8);
+} NVA06C_CTRL_TIMESLICE_PARAMS;
+
+/*
+ * NVA06C_CTRL_CMD_PREEMPT
+ *
+ * This command preempts a channel group. It optionally waits for the preempt to
+ * complete before returning.
+ *
+ * bWait
+ *   If bWait evaluates to NV_TRUE then this control call waits till the preempt
+ *   completes, else it returns immediately after issuing the preempt.  Calling
+ *   this control call multiple times with bWait = NV_FALSE without waiting for
+ *   the preempt to complete by some other means can lead to undefined results.
+ * bManualTimeout
+ *   If bManualTimer evaluates to NV_TRUE then timeoutUs will be used as the
+ *   timeout value.
+ * timeoutUs
+ *   The desired timeout in microseconds. Only used if bManualTimeout evaluates
+ *   to NV_TRUE. The maximum value of timeoutUs is
+ *   NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ *
+ */
+#define NVA06C_CTRL_CMD_PREEMPT (0xa06c0105) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID" */
+
+#define NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVA06C_CTRL_PREEMPT_PARAMS {
+    NvBool bWait;
+    NvBool bManualTimeout;
+    NvU32  timeoutUs;
+} NVA06C_CTRL_PREEMPT_PARAMS;
+
+#define NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US (1000000) // 1 second
+
+/*
+ * NVA06C_CTRL_CMD_GET_INFO
+ *
+ * This command returns information about the channel group.
+ *
+ * tsgID
+ *   Output parameter containing the hardware TSG ID for this channel group.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_OBJECT
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NVA06C_CTRL_CMD_GET_INFO                      (0xa06c0106) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NVA06C_CTRL_GET_INFO_PARAMS {
+    NvU32 tsgID;
+} NVA06C_CTRL_GET_INFO_PARAMS;
+
+/*
+ * NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL
+ *
+ * Used to change the target TSG's interleave level in the runlist. The
+ * interleave level indicates how often channels in the TSG appear in the
+ * runlist according to the following policy:
+ *
+ *       - LOW:    Appear once
+ *       - MEDIUM: If L > 0, appear L times
+ *                 Else, appear once
+ *       - HIGH:   If L > 0, appear (M + 1) * L times
+ *                 Else if M > 0, appear M times
+ *                 Else, appear once
+ *  where
+ *       - L = # of LOW interleave level TSGs
+ *       - M = # of MEDIUM interleave level TSGs
+ *
+ * For safety reasons, setting this property requires PRIVILEGED user level.
+ *
+ * tsgInterleaveLevel
+ *   Input parameter. One of:
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ */
+#define NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06c0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */
+
+/*
+ * NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL
+ *
+ * Returns the target TSG's interleave level.
+ *
+ * tsgInterleaveLevel
+ *   Output parameter. One of:
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06c0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x8" */
+
+typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS {
+    NvU32 tsgInterleaveLevel;
+} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS;
+
+#define NVA06C_CTRL_INTERLEAVE_LEVEL_LOW       (0x00000000)
+#define NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM    (0x00000001)
+#define NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH      (0x00000002)
+
+/*
+ * NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE
+ * This ctrl call is deprecated in favor of NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE.
+ * @see NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE
+ */
+#define NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE (0xa06c0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID" */
+
+typedef enum NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE {
+    NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0,
+    NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1,
+    NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2,
+} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE;
+
+typedef struct NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD {
+    NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE size;
+} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD;
+
+#define NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS {
+    NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD l1;
+    NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD t1;
+} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS;
+
+/*!
+ * NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS
+ *
+ * This control call is used to
+ * - set the fault method buffer addresses in vGpu host / GSP after the fault
+ *   method buffers are allocated by vGpu guest / GSP_CLIENT during channel
+ *   group allocation
+ * - destroy the method buffer memory descriptors during channel group free
+ *
+ * methodBufferMemdesc [input]
+ *   Details about the memory allocated for method buffer for each runqueue.
+ *   If the size of the memory region is zero, the descriptor will be destroyed.
+ *
+ * bar2Addr [input]
+ *   CPU invisible BAR2 address that the method buffer is mapped to for each
+ *   runqueue
+ *
+ * numValidEntries [input]
+ *   The number of valid entries upto
+ *   NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES actually filled in
+ *   the control call parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS           (0xa06c010a) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8 | NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID)" */
+
+#define NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES (NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES)
+
+#define NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID (0xaU)
+
+typedef struct NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO methodBufferMemdesc[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES], 8);
+    NV_DECLARE_ALIGNED(NvU64 bar2Addr[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES], 8);
+    NvU32 numValidEntries;
+} NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS;
+
+/*
+ * NVA06C_CTRL_CMD_MAKE_REALTIME
+ *
+ * Promote the specified TSG to realtime, or demote to non-realtime,
+ * depending on the given bRealtime parameter. A realtime TSG will have the
+ * highest interleave level when the scheduling policy is CHANNEL_INTERLEAVED,
+ * and will also precede any non-realtime channel/TSG in the order channels are
+ * added to the corresponding runlist.
+ *
+ * Whenever a realtime TSG is added to a runlist, all non-realtime channels/TSGs
+ * are made preemptible by setting a COMPUTE preemption mode to CTA.
+ *
+ * Preemption modes for realtime TSGs remain WFI.
+ *
+ * A client must then issue a NVA06F_CTRL_CMD_RESTART_RUNLIST control call when
+ * kicking off work on a realtime TSG to preempt non-realtime channels and
+ * restart the runlist such that the realtime TSG will start executing next.
+ *
+ *   bRealtime
+ *     Whether the TSG is to be promoted to/demoted from realtime.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAMETER
+ *   NV_ERR_INVALID_OBJECT
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NVA06C_CTRL_CMD_MAKE_REALTIME (0xa06c0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID" */
+
+#define NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NVA06C_CTRL_MAKE_REALTIME_PARAMS {
+    NvBool bRealtime;
+} NVA06C_CTRL_MAKE_REALTIME_PARAMS;
+
+
+
+/*
+ * NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to schedule a channel group in hardware.
+ *
+ * Please see description of NVA06C_CTRL_CMD_GPFIFO_SCHEDULE for more information.
+ *
+ */
+#define NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06c0201) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */
+
+/* 
+ * NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to modify the timeslice for a channel group in hardware.
+ *
+ * Please see description of NVA06C_CTRL_CMD_SET_TIMESLICE for more information.
+ *
+ */
+#define NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE   (0xa06c0202) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */
+
+/* _ctrla06c.h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f.h
new file mode 100644
index 0000000..b768326
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f.h
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla06f.finn
+//
+
+
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrla06f/ctrla06fbase.h"
+#include "ctrl/ctrla06f/ctrla06fgpfifo.h"
+#include "ctrl/ctrla06f/ctrla06fevent.h"
+#include "ctrl/ctrla06f/ctrla06finternal.h"
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h
new file mode 100644
index 0000000..39c977a
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h
@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla06f/ctrla06fbase.finn
+//
+
+
+
+
+/* GK100_GPFIFO control commands and parameters */
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl906f.h"          /* A06F is partially derived from 906F */
+
+#define NVA06F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0xA06F, NVA06F_CTRL_##cat, idx)
+
+/* GK100_GPFIFO command categories (6bits) */
+#define NVA06F_CTRL_RESERVED (0x00)
+#define NVA06F_CTRL_GPFIFO   (0x01)
+#define NVA06F_CTRL_EVENT    (0x02)
+#define NVA06F_CTRL_INTERNAL (0x03)
+
+/*
+ * NVA06F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *
+ */
+#define NVA06F_CTRL_CMD_NULL (0xa06f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* _ctrla06fbase_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h
new file mode 100644
index 0000000..245673b
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla06f/ctrla06fevent.finn
+//
+
+#include "ctrl/ctrla06f/ctrla06fbase.h"
+
+/*
+ * NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * This command sets event notification state for the associated channel.
+ * This command requires that an instance of NV01_EVENT has been previously
+ * bound to the associated channel object.
+ *
+ *   event
+ *     This parameter specifies the type of event to which the specified
+ *     action is to be applied.  This parameter must specify a valid
+ *     NVA06F_NOTIFIERS value (see cla06f.h for more details) and should
+ *     not exceed one less NVA06F_NOTIFIERS_MAXCOUNT.
+ *   action
+ *     This parameter specifies the desired event notification action.
+ *     Valid notification actions include:
+ *       NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_DISABLE
+ *         This action disables event notification for the specified
+ *         event for the associated channel object.
+ *       NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_SINGLE
+ *         This action enables single-shot event notification for the
+ *         specified event for the associated channel object.
+ *       NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_REPEAT
+ *         This action enables repeated event notification for the specified
+ *         event for the associated channel object.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa06f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
+    NvU32 event;
+    NvU32 action;
+} NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
+#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  (0x00000001)
+#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  (0x00000002)
+
+/*
+ * NVA06F_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * This command triggers a software event for the associated channel.
+ * This command accepts no parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVA06F_CTRL_CMD_EVENT_SET_TRIGGER                 (0xa06f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
+
+
+/* _ctrla06fevent_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h
new file mode 100644
index 0000000..699e6c6
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h
@@ -0,0 +1,288 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla06f/ctrla06fgpfifo.finn
+//
+
+#include "ctrl/ctrla06f/ctrla06fbase.h"
+
+/*
+ * NVA06F_CTRL_GET_CLASS_ENGINEID
+ *
+ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
+ *
+ */
+#define NVA06F_CTRL_GET_CLASS_ENGINEID (0xa06f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
+
+typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
+    NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
+} NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
+
+
+
+/*
+ * NVA06F_CTRL_RESET_CHANNEL
+ *
+ * Please see description of NV906F_CTRL_RESET_CHANNEL for more information.
+ */
+#define NVA06F_CTRL_CMD_RESET_CHANNEL (0xa06f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */
+
+typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
+    NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
+} NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
+
+
+
+/*
+ * NVA06F_CTRL_CMD_GPFIFO_SCHEDULE
+ *
+ * This command schedules a channel in hardware. This command should be called
+ * after objects have been allocated on the channel or a call to
+ * NVA06F_CTRL_CMD_BIND has been made.
+ *
+ * bEnable
+ *   This parameter indicates whether or not the channel should be scheduled in hardware.
+ *   When set, the channel will be enabled in addition to being added to the appropriate runlist.
+ *   When not set, the channel will be disabled and removed from runlist.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_OPERATION
+ *
+ */
+#define NVA06F_CTRL_CMD_GPFIFO_SCHEDULE (0xa06f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
+#define NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS {
+    NvBool bEnable;
+    NvBool bSkipSubmit;
+} NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS;
+
+/*
+ * NVA06F_CTRL_CMD_BIND
+ *
+ * This command uses the given engine to configure the channel for scheduling.
+ * It alleviates the need to call NVA06F_CTRL_CMD_GPFIFO_SCHEDULE after objects
+ * have been allocated.  However, it requires that the caller know which engine
+ * they want to be able to execute on the channel.  Once this has been called
+ * only objects that can be allocated on the specified engine or other engines
+ * allowed to coexist on the channel will be allowed.  See
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST to determine which engines can
+ * share a parent.
+ *
+ * engineType
+ *   This parameter specifies an NV2080_ENGINE_TYPE value indicating the
+ *   engine to which this channel should be bound.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA06F_CTRL_CMD_BIND (0xa06f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID" */
+
+#define NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVA06F_CTRL_BIND_PARAMS {
+    NvU32 engineType;
+} NVA06F_CTRL_BIND_PARAMS;
+
+
+
+/*
+ * NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO
+ *
+ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
+ *   
+ */
+#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa06f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */
+
+typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
+} NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
+
+
+
+/*
+ * NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER
+ *
+ * This command sets the channel error notifier of the target channel.
+ *   bNotifyEachChannelInTSG
+ *     When true, the error notifier will be set on every channel in
+ *     the TSG that contains the channel.
+ * 
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER (0xa06f0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS_MESSAGE_ID" */
+
+#define NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS {
+    NvBool bNotifyEachChannelInTSG;
+} NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS;
+
+/*
+ * NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL
+ *
+ * Symmetric to NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL, applied to the individual
+ * target channel.
+ *
+ * When belonging to a TSG, same interleave level will be set to every channel
+ * in the TSG.
+ *
+ * channelInterleaveLevel
+ *   Input parameter. One of:
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ */
+#define NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06f0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x9" */
+
+/*
+ * NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL
+ *
+ * Returns the target channel's interleave level.
+ *
+ * channelInterleaveLevel
+ *   Output parameter. One of:
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM
+ *       - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06f0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */
+
+typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS {
+    NvU32 channelInterleaveLevel;
+} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS;
+
+/*
+ * NVA06F_CTRL_CMD_RESTART_RUNLIST
+ *
+ * This command expires the current timeslice and restarts the runlist the given
+ * channel belongs to. This effectively preempts the current channel on the
+ * corresponding engine.
+ *
+ * This is useful for clients to trigger preemption manually and reduce start
+ * latency for higher priority channels as they are added first to the runlist
+ * if NV0080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED policy is
+ * configured.
+ *
+ * This command interacts with the scheduler and may cause certain low priority
+ * channels to starve under certain circumstances. Therefore, it is only
+ * available to privileged clients.
+ *
+ *   bForceRestart
+ *     Input parameter. If NV_FALSE, the runlist restart will be skipped
+ *     whenever the given channel (or its group) is already running on the
+ *     corresponding engine.
+ *
+ *   bBypassWait
+ *     Input parameter. If NV_TRUE, the command will return immediately after
+ *     issuing the hardware preemption request, without actually waiting for the
+ *     context switch to complete.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA06F_CTRL_CMD_RESTART_RUNLIST (0xa06f0111) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_RESTART_RUNLIST_PARAMS_MESSAGE_ID" */
+
+#define NVA06F_CTRL_RESTART_RUNLIST_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NVA06F_CTRL_RESTART_RUNLIST_PARAMS {
+    NvBool bForceRestart;
+    NvBool bBypassWait;
+} NVA06F_CTRL_RESTART_RUNLIST_PARAMS;
+
+/*
+ * NVA06F_CTRL_CMD_STOP_CHANNEL
+ *
+ * This command is used to stop the channel
+ *
+ * Stopping the channel here means disabling and unbinding the channel and removing it from runlist.
+ * So, if the channel needs to run again, it has to be scheduled, bound and enabled again.
+ * If we fail to preempt channel or remove it from runlist, then we RC the channel.
+ * Also set an error notifier to notify user space that channel is stopped.
+ *
+ *   bImmediate
+ *     Input parameter. If NV_FALSE, we will wait for default RM timeout 
+ *     for channel to idle. If NV_TRUE, we don't wait for channel to idle.
+ *     If channel is not idle, we forcefully preempt it off the runlist.
+ *     If the preempt times out, we will RC the channel.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA06F_CTRL_CMD_STOP_CHANNEL (0xa06f0112) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_STOP_CHANNEL_PARAMS_MESSAGE_ID" */
+
+#define NVA06F_CTRL_STOP_CHANNEL_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NVA06F_CTRL_STOP_CHANNEL_PARAMS {
+    NvBool bImmediate;
+} NVA06F_CTRL_STOP_CHANNEL_PARAMS;
+
+/* _ctrla06fgpfifo_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h
new file mode 100644
index 0000000..7a37815
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h
@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla06f/ctrla06finternal.finn
+//
+
+#include "ctrl/ctrla06f/ctrla06fbase.h"
+#include "ctrl/ctrla06f/ctrla06fgpfifo.h"
+
+/*
+ * NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to stop the channel in hardware
+ *
+ * Please see description of NVA06F_CTRL_CMD_STOP_CHANNEL for more information.
+ *
+ */
+#define NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL    (0xa06f0301) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */
+
+/*
+ * NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to perform the channel reset operations in hardware
+ *
+ * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
+ *
+ */
+#define NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL   (0xa06f0302) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */
+
+/*
+ * NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to schedule the channel in hardware
+ *
+ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
+ *
+ */
+#define NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06f0303) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x3" */
+
+/* ctrla06finternal_h */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla080.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla080.h
new file mode 100644
index 0000000..b956ab9
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla080.h
@@ -0,0 +1,658 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2012-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla080.finn
+//
+
+
+
+
+
+/*
+ * NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES
+ * 
+ * This command sets primary surface properties on a virtual GPU in displayless mode
+ *
+ * Parameters:
+ *   headIndex
+ *      This parameter specifies the head for which surface properties are 
+ *
+ *   isPrimary
+ *      This parameter indicates whether surface information is for primary surface. set to 1 if its a primary surface.
+ *
+ *   hMemory
+ *      Memory handle containing the surface (only for RM-managed heaps)
+ *
+ *   offset
+ *      Offset from base of allocation (hMemory for RM-managed heaps; physical
+ *      memory otherwise)
+ *
+ *   surfaceType
+ *      This parameter indicates whether surface type is block linear or pitch
+ *
+ *   surfaceBlockHeight
+ *      This parameter indicates block height for the surface
+ *
+ *   surfacePitch
+ *      This parameter indicates pitch value for the surface
+ *
+ *   surfaceFormat
+ *      This parameter indicates surface format (A8R8G8B8/A1R5G5B5)
+ *
+ *   surfaceWidth
+ *      This parameter indicates width value for the surface 
+ *
+ *   surfaceHeight
+ *      This parameter indicates height value for the surface
+ *
+ *   surfaceSize
+ *      This parameter indicates size of the surface
+ *
+ *   surfaceKind
+ *      This parameter indicates surface kind (only for externally-managed
+ *      heaps)
+ *
+ *    rectX [unused]
+ *      This parameter indicates X coordinate of the region to be displayed
+ *
+ *    rectY [unused]
+ *      This parameter indicates Y coordinate of the region to be displayed
+ *
+ *    rectWidth
+ *      This parameter indicates width of the region to be displayed
+ *
+ *    rectHeight
+ *      This parameter indicates height of the region to be displayed
+ *
+ *    hHwResDevice
+ *      This parameter indicates the device associated with surface
+ *
+ *    hHwResHandle
+ *      This parameter indicates the handle to hardware resources allocated to surface
+ *
+ *    effectiveFbPageSize 
+ *      This parameter indicates the actual page size used by KMD for the surface
+ *
+ *   Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NVOS_STATUS_NOT_SUPPORTED
+ */
+
+#define NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES (0xa0800103) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID" */
+
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID (0x3U)
+
+typedef struct NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES {
+    NvU32 headIndex;
+    NvU32 isPrimary;
+    NvU32 hMemory;
+    NvU32 offset;
+    NvU32 surfaceType;
+    NvU32 surfaceBlockHeight;
+    NvU32 surfacePitch;
+    NvU32 surfaceFormat;
+    NvU32 surfaceWidth;
+    NvU32 surfaceHeight;
+    NvU32 rectX;
+    NvU32 rectY;
+    NvU32 rectWidth;
+    NvU32 rectHeight;
+    NvU32 surfaceSize;
+    NvU32 surfaceKind;
+    NvU32 hHwResDevice;
+    NvU32 hHwResHandle;
+    NvU32 effectiveFbPageSize;
+} NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES;
+
+/* valid surfaceType values */
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT                      0:0
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_BLOCKLINEAR    0x00000000
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_PITCH          0x00000001
+/* valid surfaceBlockHeight values */
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_ONE_GOB         0x00000000
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_TWO_GOBS        0x00000001
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_FOUR_GOBS       0x00000002
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_EIGHT_GOBS      0x00000003
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_SIXTEEN_GOBS    0x00000004
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_THIRTYTWO_GOBS  0x00000005
+/* valid surfaceFormat values */
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_I8                    0x0000001E
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_RF16_GF16_BF16_AF16   0x000000CA
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8R8G8B8              0x000000CF
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A2B10G10R10           0x000000D1
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_X2BL10GL10RL10_XRBIAS 0x00000022
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8B8G8R8              0x000000D5
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R5G6B5                0x000000E8
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A1R5G5B5              0x000000E9
+#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R16_G16_B16_A16       0x000000C6
+
+/*
+ * NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS
+ * 
+ * This command clears surface information related to head. 
+ * It should be called while shutting down head in displayless mode on virtual GPU
+ *
+ * Parameters:
+ *   headIndex
+ *     This parameter specifies the head for which cleanup is requested.
+ *
+ *   blankingEnabled
+ *     This parameter must be set to 1 to enable blanking.
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ *     NVOS_STATUS_NOT_SUPPORTED
+ */
+#define NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE                                 (0xa0800104) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID" */
+
+#define NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS {
+    NvU32 headIndex;
+    NvU32 blankingEnabled;
+} NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS;
+
+/*
+ * NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS
+ *
+ * This command returns CPU virtual address of the mouse pointer mapping for VGPU.
+ * The address returned by this command is the pointer address for the head 0.
+ * VGPU_POINTER_OFFSET_HEAD(i) should be added to this address to get the address of head i.
+ * VGPU mouse pointer is a 32 bit value, X location of the mouse pointer is stored in
+ * 15:0 and Y location is stored in 31:16 bits. X location value of the mouse pointer is
+ * negative if bit 15 is set. Similarly, Y location value is negative if bit 31 is set.
+ *
+ * Parameters:
+ *   pPointerAddress
+ *     CPU virtual address of the mouse pointer mapping for VGPU
+ * 
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NVOS_STATUS_NOT_SUPPORTED
+ */
+
+#define NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS (0xa0800105) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID" */
+
+#define NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pPointerAddress, 8);
+} NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS;
+
+#define VGPU_POINTER_OFFSET_HEAD0_VALUE 0x00000000
+#define VGPU_POINTER_OFFSET_HEAD0_FLAG  0x00000004
+#define VGPU_POINTER_OFFSET_HEAD1_VALUE 0x00000008
+#define VGPU_POINTER_OFFSET_HEAD1_FLAG  0x0000000c
+#define VGPU_POINTER_OFFSET_HEAD2_VALUE 0x00000010
+#define VGPU_POINTER_OFFSET_HEAD2_FLAG  0x00000014
+#define VGPU_POINTER_OFFSET_HEAD3_VALUE 0x00000018
+#define VGPU_POINTER_OFFSET_HEAD3_FLAG  0x0000001c
+#define VGPU_POINTER_OFFSET_HEAD_VALUE(i)   (i * 8)
+#define VGPU_POINTER_OFFSET_HEAD_FLAG(i)    (4 + i * 8)
+#define VGPU_POINTER_OFFSET_HEAD_SIZE   4
+
+/*
+ * NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE
+ *
+ * This command returns mappable video size to be used by each VM.
+ *
+ * Parameters:
+ *   mappableVideoSize
+ *     This parameter returns mappable video size in bytes.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NVOS_STATUS_NOT_SUPPORTED
+ */
+
+
+#define NV_VGPU_POINTER_X_LOCATION    15:0
+#define NV_VGPU_POINTER_Y_LOCATION    31:16
+#define NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE (0xa0800201) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8);
+} NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS;
+
+/*
+ *  NVA080_CTRL_CMD_MAP_SEMA_MEM
+ *
+ *  This command returns GPU VA for the channel with 'hCtxDma' handle
+ *  where per VM semaphore memory is mapped which is used for tracking
+ *  non-stall interrupt of each VM.
+ *
+ * Parameters:
+ *   hClient [in]
+ *     This parameter specifies the handle to the NV01_ROOT object of
+ *     the client.  This object should be the parent of the object
+ *     specified by hDevice.
+ *   hDevice [in]
+ *     This parameter specifies the handle of the NV01_DEVICE object
+ *     representing the desired GPU.
+ *   hMemory [in]
+ *     This parameter specifies the handle for semaphore memory
+ *   hCtxDma [in]
+ *     This parameter specifies the handle of the NV01_CONTEXT_DMA
+ *     object through which bufferId is written in semaphore memory for
+ *     non-stall interrupt tracking.
+ *   semaAddress [out]
+ *     This parameter returns the GPU virtual address of the semaphore
+ *     memory.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NVOS_STATUS_INVALID_DATA
+ *    NV_ERR_INVALID_CLIENT
+ *    NV_ERR_INVALID_OBJECT_HANDLE
+ *
+ */
+
+#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x2" */
+
+typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS {
+    NvHandle hClient;
+    NvHandle hDevice;
+    NvHandle hMemory;
+    NvHandle hCtxDma;
+    NV_DECLARE_ALIGNED(NvU64 semaAddress, 8);
+} NVA080_CTRL_MAP_SEMA_MEM_PARAMS;
+
+/*
+ *  NVA080_CTRL_CMD_UNMAP_SEMA_MEM
+ *
+ *  This command unmaps per VM semaphore memory from GPU VA space, mapped by
+ *  NVA080_CTRL_CMD_MAP_SEMA_MEM command.
+ *
+ * Parameters:
+ *  Same as NVA080_CTRL_MAP_SEMA_MEM_PARAMS, except semaAddress is input
+ *  parameter here.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NVOS_STATUS_INVALID_DATA
+ *    NV_ERR_INVALID_CLIENT
+ *    NV_ERR_INVALID_OBJECT_HANDLE
+ *
+ */
+
+#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x3" */
+
+/*!
+ * NVA080_CTRL_CMD_SET_FB_USAGE
+ *
+ *  This command sets the current framebuffer usage value in the plugin.
+ *
+ *  Parameters:
+ *   fbUsed [in]
+ *     This parameter holds the current FB usage value in bytes.
+ *
+ *   Possible status values returned are:
+ *      NV_OK
+ */
+#define NVA080_CTRL_CMD_SET_FB_USAGE   (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */
+
+#define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
+} NVA080_CTRL_SET_FB_USAGE_PARAMS;
+
+/*!
+* NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM
+*
+* This command allocates the per engine vGPU semaphore memory and map it to
+* GPU/CPU VA.
+*
+* Calculate engine's semaphore GPU VA =
+*               semaAddress + semaStride * NV2080_ENGINE_TYPE_ of that engine
+*
+* Parameters:
+*    hClient [in]
+*       This parameter specifies the handle to the NV01_ROOT object of
+*       the client.  This object should be the parent of the object
+*       specified by hDevice.
+*   hDevice [in]
+*       This parameter specifies the handle of the NV01_DEVICE object
+*       representing the desired GPU.
+*   hMemory [in]
+*       This parameter specifies the handle for semaphore memory
+*   hCtxDma [in]
+*       This parameter specifies the handle of the NV01_CONTEXT_DMA
+*       object through which bufferId is written in semaphore memory for
+*       non-stall interrupt tracking.
+*   semaAddress [out]
+*       This parameter returns the GPU VA of the per engine semaphore memory.
+*   semaStride [out]
+*       This parameter specifies the stride of each engine's semaphore offset within this memory.
+*
+* Possible status values returned are:
+*   NV_OK
+*/
+
+#define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */
+
+#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS {
+    NvU32    hClient;
+    NvU32    hDevice;
+    NvHandle hMemory;
+    NvU32    hCtxDma;
+    NV_DECLARE_ALIGNED(NvU64 semaAddress, 8);
+    NvU32    semaStride;
+} NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS;
+
+/*!
+* NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM
+*
+* This command unmaps and frees the per engine vGPU semaphore memory.
+*
+* Parameters:
+*   Same as NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS, except semaAddress is input
+*   parameter here.
+*
+*  Possible status values returned are:
+*    NV_OK
+*/
+
+#define NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM (0xa0800206) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */
+
+#define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U)
+
+typedef NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS;
+
+/*
+ *  NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP
+ *
+ *  This command provides the guest RM with PFN information, so that it can
+ *  update the shared memory with the plugin, which keeps track of guest sysmem.
+ *
+ *  Parameters:
+ *   destPhysAddr
+ *     Start address of the segment to be tracked
+ *
+ *   pageCount
+ *     Number of pages in the segment
+ *
+ *   pageSize
+ *     Size of pages in the segment
+ *
+ *   isValid:
+ *     TRUE : Set bits corresponding to PFNs in bitmap and increase segment refcount
+ *     FALSE: Decrease segment refcount and then unset bits if refcount is 0
+ *
+ *   pfnList
+ *     List of PFNs in the segment
+ *
+ *   flags
+ *     FLAGS_DST_PHYS_ADDR_BAR1_OFFSET
+ *       Flag set to TRUE if pteMem is CPU VA pointing to BAR1 and
+ *       dstPhysAddr contains BAR1 offset.
+ *
+ * Possible status values returned are:
+ *   NVOS_STATUS_SUCCESS
+ */
+
+#define NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP                                          (0xa0800207) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID" */
+
+#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET       0:0
+#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_FALSE (0x00000000)
+#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_TRUE  (0x00000001)
+
+#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 destPhysAddr, 8);
+    NvU32  pageCount;
+    NvU32  pageSize;
+    NvBool isValid;
+    NV_DECLARE_ALIGNED(NvP64 pfnList, 8);
+    NvU32  flags;
+} NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS;
+
+/*
+ * Blit semaphore offset location
+ */
+#define VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET            0x200
+#define VGPU_BLIT_RESTORE_SEMA_MEM_ADDR(addr)               (((NvU64)addr) + VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET)
+
+#define VGPU_BLIT_SEMA_MEM_OFFSET                    0x400
+#define VGPU_BLIT_SEMA_MEM_ADDR(addr)                       (((NvU64)addr) + VGPU_BLIT_SEMA_MEM_OFFSET)
+
+#define VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET            0x800
+#define VGPU_FBMEMCE_PUSH_SEMA_MEM_ADDR(addr)               (((NvU64)addr) + VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET)
+
+#define VGPU_FBMEMCE_SEMA_MEM_OFFSET                 0x810
+#define VGPU_FBMEMCE_SEMA_MEM_ADDR(addr)                    (((NvU64)addr) + VGPU_FBMEMCE_SEMA_MEM_OFFSET)
+
+#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET 0x820
+#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_ADDR(addr)    (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET)
+
+#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET 0x824
+
+/*
+ *  NVA080_CTRL_CMD_VGPU_GET_CONFIG
+ *
+ *  This command returns VGPU configuration information for the associated GPU.
+ *
+ *  Parameters:
+ *   frameRateLimiter
+ *     This parameter returns value of frame rate limiter
+ *   swVSyncEnabled
+ *     This parameter returns value of SW VSync flag (zero for disabled,
+ *     non-zero for enabled)
+ *   cudaEnabled
+ *     This parameter returns whether CUDA is enabled or not
+ *   pluginPteBlitEnabled
+ *     This parameter returns whether to use plugin pte blit path
+ *   disableWddm1xPreemption
+ *     This parameter returns whether to disable WDDM 1.x Preemption or not
+ *   debugBuffer
+ *     This parameter specifies a pointer to memory which is filled with
+ *     debugging information.
+ *   debugBufferSize
+ *     This parameter specifies the size of the debugging buffer in bytes.
+ *   guestFbOffset
+ *     This parameter returns FB offset start address for VM
+ *   mappableCpuHostAperture
+ *     This parameter returns mappable CPU host aperture size
+ *   linuxInterruptOptimization
+ *     This parameter returns whether stall interrupts are enabled/disabled for
+ *     Linux VM
+ *   vgpuDeviceCapsBits
+ *      This parameter specifies CAP bits to ON/OFF features from guest OS.
+ *      CAPS_SW_VSYNC_ENABLED
+ *          cap bit to indicate if SW VSync flag enabled/disabled.
+ *          Please note, currently, guest doesn't honour this bit.
+ *      CAPS_CUDA_ENABLED
+ *          cap bit to indicate if CUDA enabled/disabled.
+ *          Please note, currently, guest doesn't honour this bit.
+ *      CAPS_WDDM1_PREEMPTION_DISABLED
+ *          cap bit to indicate if WDDM 1.x Preemption disabled/enabled.
+ *          Please note, currently, guest doesn't honour this bit.
+ *      CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED
+ *          cap bit to indicate if stall interrupts are enabled/disabled for
+ *          Linux VM. Please note, currently, guest doesn't honour this bit.
+ *      CAPS_PTE_BLIT_ENABLED
+ *          cap bit to indicate if PTE blit is enabled/disabled.
+ *          Please note, currently, guest doesn't honour this bit.
+ *      CAPS_PDE_BLIT_ENABLED
+ *          cap bit to indicate if PDE blit is enabled/disabled.
+ *      CAPS_GET_PDE_INFO_CTRL_DISABLED
+ *          cap bit to indicate if GET_PDE_INFO RM Ctrl is disabled/enabled.
+ *      CAPS_GUEST_FB_OFFSET_DISABLED
+ *          cap bit to indicate if FB Offset is exposed to guest or not.
+ *          If set, FB Offset is not exposed to guest.
+ *      CAPS_CILP_DISABLED_ON_WDDM
+ *          cap bit to indicate if CILP on WDDM disabled/enabled.
+ *      CAPS_UPDATE_DOORBELL_TOKEN_ENABLED
+ *          cap bit to indicate if guest needs to use doorbell token value updated
+ *          dynamically by host after migration.
+ *      CAPS_SRIOV_ENABLED
+ *          Cap bit to indicate if the vGPU is running in SRIOV mode or not.
+ *      CAPS_GUEST_MANAGED_VA_ENABLED
+ *          Cap bit to indicate if the Guest is managing the VA.
+ *      CAPS_VGPU_1TO1_COMPTAG_ENABLED
+ *          Cap bit to indicate if the 1to1 comptag enabled. This is always TRUE
+ *          when SR-IOV is enabled.
+ *      CAPS_MBP_ENABLED
+ *          Cap bit to indicate if the Mid Buffer Preemption  enabled.
+ *      CAPS_ASYNC_MBP_ENABLED
+ *          Cap bit to indicate if the asynchronus Mid buffer Preemption enabled.
+ *      CAPS_TLB_INVALIDATE_ENABLED
+ *          Cap bit to indicate if the vGPU supports TLB Invalidation operation or not.
+ *      CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED
+ *          Cap bit to indicate if the vGPU supports PTE blit for page table updates using BAR1
+ *      CAPS_SRIOV_HEAVY_ENABLED
+ *          Cap bit to indicate if vGPU is running in SRIOV Heavy mode or not.
+ *          When set true SRIOV Heavy is enabled.
+ *          When set false and CAPS_SRIOV_ENABLED is set true, SRIOV Standard is enabled.
+ *      CAPS_TIMESLICE_OVERRIDE_ENABLED
+ *          Cap bit to indicate whether TSG timeslice override is enabled or not.
+ *          When set true, TSG timeslice override is enabled.
+ *          When false, TSG timeslice override is disabled.
+ *   uvmEnabledFeatures
+ *      This parameter returns mask of UVM enabled features on vGPU. It comprises of
+ *      UVM managed APIs and replayable faults that are enabled or disabled based on
+ *      vGPU version.
+ *   enableKmdSysmemScratch
+ *      This parameter is used to overwrite guest regkey PreferSystemMemoryScratch.
+ *      Setting vgpu parameter "vgpu_enable_kmd_sysmem_scratch" in plugin will
+ *      set this parameter. If the parameter is set, guest moves shader buffer
+ *      allocation from FB to sysmem.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_ADDR(addr)    (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG                                                                 (0xa0800301) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED                            0:0
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_FALSE                     (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_TRUE                      (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED                                1:1
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_FALSE                         (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_TRUE                          (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED                   2:2
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_FALSE            (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_TRUE             (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED        3:3
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_FALSE (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_TRUE  (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED                            4:4
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_FALSE                     (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_TRUE                      (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED                            5:5
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_FALSE                     (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_TRUE                      (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED                  6:6
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_FALSE           (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_TRUE            (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED                    7:7
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_FALSE             (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_TRUE              (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM                       8:8
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_FALSE                (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_TRUE                 (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED                     9:9
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_FALSE              (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_TRUE               (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED               10:10
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_FALSE        (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_TRUE         (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED                               11:11
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_FALSE                        (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_TRUE                         (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED                    12:12
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_FALSE             (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_TRUE              (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED                   13:13
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_FALSE            (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_TRUE             (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED                                 14:14
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_FALSE                          (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_TRUE                           (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED                           15:15
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_FALSE                    (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_TRUE                     (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED                      16:16
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_FALSE               (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_TRUE                (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED         17:17
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_FALSE  (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_TRUE   (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED                     18:18
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_FALSE              (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_TRUE               (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED                         19:19
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_FALSE                  (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_TRUE                   (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED                  20:20
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_FALSE           (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_TRUE            (0x00000001)
+
+/* UVM supported features */
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED                    0:0
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_FALSE             (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_TRUE              (0x00000001)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED                                  1:1
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_FALSE                           (0x00000000)
+#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_TRUE                            (0x00000001)
+
+#define NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS {
+    NvU32  frameRateLimiter;
+    NvU32  swVSyncEnabled;
+    NvU32  cudaEnabled;
+    NvU32  pluginPteBlitEnabled;
+    NvU32  disableWddm1xPreemption;
+    NvU32  debugBufferSize;
+    NV_DECLARE_ALIGNED(NvP64 debugBuffer, 8);
+    NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 mappableCpuHostAperture, 8);
+    NvU32  linuxInterruptOptimization;
+    NvU32  vgpuDeviceCapsBits;
+    NvU32  maxPixels;
+    NvU32  uvmEnabledFeatures;
+    NvBool enableKmdSysmemScratch;
+} NVA080_CTRL_VGPU_GET_CONFIG_PARAMS;
+
+
+
+/* _ctrla080_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla081.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla081.h
new file mode 100644
index 0000000..35876db
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla081.h
@@ -0,0 +1,716 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla081.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl2080/ctrl2080gpu.h"
+#include "nv_vgpu_types.h"
+/* NVA081_VGPU_CONFIG control commands and parameters */
+
+#define NVA081_CTRL_CMD(cat,idx)             NVXXXX_CTRL_CMD(0xA081, NVA081_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NVA081_CTRL_RESERVED                 (0x00)
+#define NVA081_CTRL_VGPU_CONFIG              (0x01)
+
+#define NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE 0x00
+#define NVA081_MAX_VGPU_TYPES_PER_PGPU       0x40
+#define NVA081_MAX_VGPU_PER_PGPU             32
+#define NVA081_VM_UUID_SIZE                  16
+#define NVA081_VGPU_STRING_BUFFER_SIZE       32
+#define NVA081_VGPU_SIGNATURE_SIZE           128
+#define NVA081_VM_NAME_SIZE                  128
+#define NVA081_PCI_CONFIG_SPACE_SIZE         0x100
+#define NVA081_PGPU_METADATA_STRING_SIZE     256
+#define NVA081_EXTRA_PARAMETERS_SIZE         1024
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO
+ *
+ * This command sets the vGPU config information in RM
+ *
+ * Parameters:
+ *
+ * discardVgpuTypes [IN]
+ *  This parameter specifies if existing vGPU configuration should be
+ *  discarded for given pGPU
+ *
+ * vgpuInfo [IN]
+ *  This parameter specifies virtual GPU type information
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO (0xa0810101) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVA081_CTRL_VGPU_CONFIG_INFO
+ *
+ * This structure represents the per vGPU information
+ *
+ */
+typedef struct NVA081_CTRL_VGPU_INFO {
+    // This structure should be in sync with NVA082_CTRL_CMD_HOST_VGPU_DEVICE_GET_VGPU_TYPE_INFO_PARAMS
+    NvU32 vgpuType;
+    NvU8  vgpuName[NVA081_VGPU_STRING_BUFFER_SIZE];
+    NvU8  vgpuClass[NVA081_VGPU_STRING_BUFFER_SIZE];
+    NvU8  vgpuSignature[NVA081_VGPU_SIGNATURE_SIZE];
+    NvU8  license[NV_GRID_LICENSE_INFO_MAX_LENGTH];
+    NvU32 maxInstance;
+    NvU32 numHeads;
+    NvU32 maxResolutionX;
+    NvU32 maxResolutionY;
+    NvU32 maxPixels;
+    NvU32 frlConfig;
+    NvU32 cudaEnabled;
+    NvU32 eccSupported;
+    NvU32 gpuInstanceSize;
+    NvU32 multiVgpuSupported;
+    NV_DECLARE_ALIGNED(NvU64 vdevId, 8);
+    NV_DECLARE_ALIGNED(NvU64 pdevId, 8);
+    NV_DECLARE_ALIGNED(NvU64 profileSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 fbLength, 8);
+    NV_DECLARE_ALIGNED(NvU64 gspHeapSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 fbReservation, 8);
+    NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8);
+    NvU32 encoderCapacity;
+    NV_DECLARE_ALIGNED(NvU64 bar1Length, 8);
+    NvU32 frlEnable;
+    NvU8  adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH];
+    NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
+    NvU8  shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
+    NvU8  licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH];
+    NvU32 vgpuExtraParams[NVA081_EXTRA_PARAMETERS_SIZE];
+    NvU32 ftraceEnable;
+    NvU32 gpuDirectSupported;
+    NvU32 nvlinkP2PSupported;
+    NvU32 multiVgpuExclusive;
+    NvU32 exclusiveType;
+    NvU32 exclusiveSize;
+    // used only by NVML
+    NvU32 gpuInstanceProfileId;
+} NVA081_CTRL_VGPU_INFO;
+
+/*
+ * NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS
+ *
+ * This structure represents the vGPU configuration information
+ *
+ */
+#define NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS {
+    NvBool discardVgpuTypes;
+    NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo, 8);
+    NvU32  vgpuConfigState;
+} NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS;
+
+/* VGPU Config state values */
+#define NVA081_CTRL_VGPU_CONFIG_STATE_UNINITIALIZED         0
+#define NVA081_CTRL_VGPU_CONFIG_STATE_IN_PROGRESS           1
+#define NVA081_CTRL_VGPU_CONFIG_STATE_READY                 2
+
+/*
+ * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU
+ *
+ * This command enumerates list of vGPU guest instances per pGpu
+ *
+ * Parameters:
+ *
+ * vgpuType [OUT]
+ *  This parameter specifies the virtual GPU type for this physical GPU
+ *
+ * numVgpu [OUT]
+ *  This parameter specifies the number of virtual GPUs created on this physical GPU
+ *
+ * guestInstanceInfo [OUT]
+ *  This parameter specifies an array containing guest instance's information for
+ *  all instances created on this physical GPU
+ *
+ * guestVgpuInfo [OUT]
+ *  This parameter specifies an array containing guest vgpu's information for
+ *  all vGPUs created on this physical GPU
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU (0xa0810102) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVA081_GUEST_VM_INFO
+ *
+ * This structure represents vGPU guest's (VM's) information
+ *
+ * vmPid [OUT]
+ *  This param specifies the vGPU plugin process ID
+ * vmIdType [OUT]
+ *  This param specifies the VM ID type, i.e. DOMAIN_ID or UUID
+ * guestOs [OUT]
+ *  This param specifies the vGPU guest OS type
+ * migrationProhibited [OUT]
+ *  This flag indicates whether migration is prohibited for VM or not
+ * guestNegotiatedVgpuVersion [OUT]
+ *  This param specifies the vGPU version of guest driver after negotiation
+ * frameRateLimit [OUT]
+ *  This param specifies the current value of FRL set for guest
+ * licensed [OUT]
+ *  This param specifies whether the VM is Unlicensed/Licensed
+ * licenseState [OUT]
+ *  This param specifies the current state of the GRID license state machine
+ * licenseExpiryTimestamp [OUT]
+ *  License expiry time in seconds since UNIX epoch
+ * licenseExpiryStatus [OUT]
+ *  License expiry status
+ * guestDriverVersion [OUT]
+ *  This param specifies the driver version of the driver installed on the VM
+ * guestDriverBranch [OUT]
+ *  This param specifies the driver branch of the driver installed on the VM
+ * vmName [OUT]
+ *  This param stores the name assigned to VM (KVM only)
+ * guestVmInfoState [OUT]
+ *  This param stores the current state of guest dependent fields
+ *
+ */
+typedef struct NVA081_GUEST_VM_INFO {
+    NvU32               vmPid;
+    VM_ID_TYPE          vmIdType;
+    NvU32               guestOs;
+    NvU32               migrationProhibited;
+    NvU32               guestNegotiatedVgpuVersion;
+    NvU32               frameRateLimit;
+    NvBool              licensed;
+    NvU32               licenseState;
+    NvU32               licenseExpiryTimestamp;
+    NvU8                licenseExpiryStatus;
+    NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
+    NvU8                guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE];
+    NvU8                guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE];
+    NvU8                vmName[NVA081_VM_NAME_SIZE];
+    GUEST_VM_INFO_STATE guestVmInfoState;
+} NVA081_GUEST_VM_INFO;
+
+/*
+ * NVA081_GUEST_VGPU_DEVICE
+ *
+ * This structure represents host vgpu device's (assigned to VM) information
+ *
+ * eccState [OUT]
+ *  This parameter specifies the ECC state of the virtual GPU.
+ *  One of NVA081_CTRL_ECC_STATE_xxx values.
+ * bDriverLoaded [OUT]
+ *  This parameter specifies whether driver is loaded on this particular vGPU.
+ * swizzId [OUT]
+ *  This param specifies the GPU Instance ID or Swizz ID
+ *
+ */
+typedef struct NVA081_HOST_VGPU_DEVICE {
+    NvU32  vgpuType;
+    NvU32  vgpuDeviceInstanceId;
+    NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8);
+    NvU8   vgpuUuid[VM_UUID_SIZE];
+    NvU8   mdevUuid[VM_UUID_SIZE];
+    NvU32  encoderCapacity;
+    NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
+    NvU32  eccState;
+    NvBool bDriverLoaded;
+    NvU32  swizzId;
+} NVA081_HOST_VGPU_DEVICE;
+
+/* ECC state values */
+#define NVA081_CTRL_ECC_STATE_UNKNOWN       0
+#define NVA081_CTRL_ECC_STATE_NOT_SUPPORTED 1
+#define NVA081_CTRL_ECC_STATE_DISABLED      2
+#define NVA081_CTRL_ECC_STATE_ENABLED       3
+
+/*
+ * NVA081_VGPU_GUEST
+ *
+ * This structure represents a vGPU guest
+ *
+ */
+typedef struct NVA081_VGPU_GUEST {
+    NV_DECLARE_ALIGNED(NVA081_GUEST_VM_INFO guestVmInfo, 8);
+    NV_DECLARE_ALIGNED(NVA081_HOST_VGPU_DEVICE vgpuDevice, 8);
+} NVA081_VGPU_GUEST;
+
+/*
+ * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS
+ *
+ * This structure represents the information of vGPU guest instances per pGpu
+ *
+ */
+#define NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS {
+    NvU32 vgpuType;
+    NvU32 numVgpu;
+    NV_DECLARE_ALIGNED(NVA081_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8);
+} NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS;
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO
+ *
+ * This command fetches vGPU type info from RM.
+ *
+ * Parameters:
+ *
+ * vgpuType [IN]
+ *  This parameter specifies the virtual GPU type for which vGPU info should be returned.
+ *
+ * vgpuTypeInfo [OUT]
+ *  This parameter returns NVA081_CTRL_VGPU_INFO data for the vGPU type specified by vgpuType.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+
+#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO (0xa0810103) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS
+ *
+ */
+#define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS {
+    NvU32 vgpuType;
+    NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuTypeInfo, 8);
+} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS;
+
+/*
+ * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS
+ *      This structure represents supported/creatable vGPU types on a pGPU
+ */
+typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS {
+    /*
+     * [OUT] vGPU config state on a pGPU
+     */
+    NvU32 vgpuConfigState;
+
+    /*
+     * [OUT] Count of supported/creatable vGPU types on a pGPU
+     */
+    NvU32 numVgpuTypes;
+
+    /*
+     * [OUT] - Array of vGPU type ids supported/creatable on a pGPU
+     */
+    NvU32 vgpuTypes[NVA081_MAX_VGPU_TYPES_PER_PGPU];
+} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS;
+
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES
+ *
+ * This command fetches count and list of vGPU types supported on a pGpu from RM
+ *
+ * Parameters:
+ *
+ * numVgpuTypes [OUT]
+ *  This parameter returns the number of vGPU types supported on this pGPU
+ *
+ * vgpuTypes [OUT]
+ *  This parameter returns list of supported vGPUs types on this pGPU
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x4" */
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES
+ *
+ * This command fetches count and list of vGPU types creatable on a pGpu from RM
+ *
+ * Parameters:
+ *
+ * numVgpuTypes [OUT]
+ *  This parameter returns the number of vGPU types creatable on this pGPU
+ *
+ * vgpuTypes [OUT]
+ *  This parameter returns list of creatable vGPUs types on this pGPU
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x5" */
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION
+ *
+ * This command sets event notification state for the associated subdevice/pGPU.
+ * This command requires that an instance of NV01_EVENT has been previously
+ * bound to the associated subdevice object.
+ *
+ *   event
+ *     This parameter specifies the type of event to which the specified
+ *     action is to be applied.  This parameter must specify a valid
+ *     NVA081_NOTIFIERS value (see cla081.h for more details) and should
+ *     not exceed one less NVA081_NOTIFIERS_MAXCOUNT.
+ *   action
+ *     This parameter specifies the desired event notification action.
+ *     Valid notification actions include:
+ *       NVA081_CTRL_SET_EVENT_NOTIFICATION_DISABLE
+ *         This action disables event notification for the specified
+ *         event for the associated subdevice object.
+ *       NVA081_CTRL_SET_EVENT_NOTIFICATION_SINGLE
+ *         This action enables single-shot event notification for the
+ *         specified event for the associated subdevice object.
+ *       NVA081_CTRL_SET_EVENT_NOTIFICATION_REPEAT
+ *         This action enables repeated event notification for the specified
+ *         event for the associated system controller object.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION   (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS {
+    NvU32 event;
+    NvU32 action;
+} NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS;
+
+
+/* valid event action values */
+#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
+#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  (0x00000001)
+#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  (0x00000002)
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_NOTIFY_START
+ *
+ * This command notifies the nvidia-vgpu-vfio module with start status.
+ * It notifies whether start has been successful or not.
+ *
+ *   mdevUuid
+ *     This parameter specifies the uuid of the mdev device for which start has
+ *     been called.
+ *   vmUuid
+ *     The UUID of VM for which vGPU has been created.
+ *   vmName
+ *     The name of VM for which vGPU has been created.
+ *   returnStatus
+ *     This parameter species whether the vGPU plugin is initialized or not.
+ *     it specifies the error code in case plugin initialization has failed
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_NOTIFY_START          (0xa0810107) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS
+ * This structure represents information of plugin init status.
+ */
+#define NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS {
+    NvU8  mdevUuid[VM_UUID_SIZE];
+    NvU8  vmUuid[VM_UUID_SIZE];
+    NvU8  vmName[NVA081_VM_NAME_SIZE];
+    NvU32 returnStatus;
+} NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS;
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER
+ *
+ * This command register the GPU to Linux kernel's mdev module for vGPU on KVM.
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER                      (0xa0810109) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x9" */
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY
+ *
+ * This command is used to set vGPU instance's (represented by vgpuUuid) encoder Capacity.
+ *
+ *   vgpuUuid
+ *     This parameter specifies the uuid of vGPU assigned to VM.
+ *   encoderCapacity
+ *     Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance
+ *     may be minimal for this GPU and software should fall back to CPU-based encode.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY (0xa0810110) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS
+ *
+ * This structure represents  encoder capacity for vgpu instance.
+ */
+#define NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS {
+    NvU8  vgpuUuid[VM_UUID_SIZE];
+    NvU32 encoderCapacity;
+} NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS;
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE
+ *
+ * This command is used to get the FB usage of all vGPU instances running on a GPU.
+ *
+ *  vgpuCount
+ *      This field specifies the number of vGPU devices for which FB usage is returned.
+ *  vgpuFbUsage
+ *      This is an array of type NVA081_VGPU_FB_USAGE, which contains a list of vGPUs
+ *      and their corresponding FB usage in bytes;
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE (0xa0810111) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */
+
+typedef struct NVA081_VGPU_FB_USAGE {
+    NvU8 vgpuUuid[VM_UUID_SIZE];
+    NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
+} NVA081_VGPU_FB_USAGE;
+
+/*
+ * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS
+ *
+ * This structure represents the FB usage information of vGPU instances running on a GPU.
+ */
+#define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS {
+    NvU32 vgpuCount;
+    NV_DECLARE_ALIGNED(NVA081_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8);
+} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS;
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP
+ *
+ * This command is used to query whether pGPU is live migration capable or not.
+ *
+ *  bMigrationCap
+ *      Set to NV_TRUE if pGPU is migration capable.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_REQUEST
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP (0xa0810112) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS {
+    NvBool bMigrationCap;
+} NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS;
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION
+ *
+ * This command is used to get the host FB requirements
+ *
+ *  hostReservedFb [OUT]
+ *      Amount of FB reserved for the host
+ *  eccAndPrReservedFb [OUT]
+ *      Amount of FB reserved for the ecc and page retirement
+ *  totalReservedFb [OUT]
+ *      Total FB reservation
+ *  vgpuTypeId [IN]
+ *      The Type ID for VGPU profile
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION (0xa0810113) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID" */
+
+#define NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8);
+    NV_DECLARE_ALIGNED(NvU64 eccAndPrReservedFb, 8);
+    NV_DECLARE_ALIGNED(NvU64 totalReservedFb, 8);
+    NvU32 vgpuTypeId;
+} NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS;
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING
+ *
+ * This command is used to get the pGpu metadata string.
+ *
+ * pGpuString
+ *     String holding pGpu Metadata
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_REQUEST
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING (0xa0810114) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID" */
+
+#define NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS {
+    NvU8 pGpuString[NVA081_PGPU_METADATA_STRING_SIZE];
+} NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS;
+
+#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT (0xa0810115) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID" */
+
+#define NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS {
+    NvBool doorbellEmulationEnabled;
+} NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS;
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID
+ *
+ * This command is used to get free swizzid from RM
+ *
+ * gpuPciId [IN]
+ *  This param specifies the PCI device ID of VF on which VM is running
+ *
+ * vgpuTypeId [IN]
+ *  This param specifies the Type ID for VGPU profile
+ *
+ * swizzId [OUT]
+ *  This param specifies the GPU Instance ID or Swizz ID
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_REQUEST
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID (0xa0810116) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID" */
+
+#define NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS {
+    NvU32 gpuPciId;
+    NvU32 vgpuTypeId;
+    NvU32 swizzId;
+} NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS;
+
+/*
+ * NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO
+ *
+ * This command is used to get multi vGPU related info for the physical GPU.
+ *
+ * fractionalmultiVgpuSupported [OUT]
+ *  This param specifies whether fractional multi-vGPU is supported
+ *
+ * heterogeneousTimesliceProfilesSupported [OUT]
+ *  This param specifies whether concurrent execution of timesliced vGPU profiles of differing types is supported
+ *
+ * heterogeneousTimesliceSizesSupported [OUT]
+ *  This param specifies whether concurrent execution of timesliced vGPU profiles of differing framebuffer sizes is supported
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_REQUEST
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO (0xa0810117) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID" */
+
+#define NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID (0x17U)
+
+typedef struct NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS {
+    NvU32 fractionalmultiVgpuSupported;
+    NvU32 heterogeneousTimesliceProfilesSupported;
+    NvU32 heterogeneousTimesliceSizesSupported;
+} NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS;
+
+/*
+ * NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS
+ *
+ * This command is used to get vGPU driver capabilities.
+ *
+ * heterogeneousMultiVgpuSupported [OUT]
+ *  This param specifies whether heterogeneous multi-vGPU is supported
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_REQUEST
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS (0xa0810118) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS {
+    NvU32 heterogeneousMultiVgpuSupported;
+} NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS;
+
+/*
+ * NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO
+ *
+ * This command is to set pgpu info
+ *
+ * fractionalMultiVgpu [IN]
+ *  This param specifies the fractional multivgpu is enabled or disabled on GPU
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+
+#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO (0xa0810119) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID" */
+
+#define NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS {
+    NvU32 fractionalMultiVgpu;
+} NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS;
+
+/* _ctrlA081vgpuconfig_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla084.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla084.h
new file mode 100644
index 0000000..f5a5146
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla084.h
@@ -0,0 +1,302 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla084.finn
+//
+
+#include "nv_vgpu_types.h"
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_GPU_MAX_GID_LENGTH
+#include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES
+
+/* NVA084_KERNEL_HOST_VGPU_DEVICE control commands and parameters */
+#define NVA084_CTRL_CMD(cat,idx)             NVXXXX_CTRL_CMD(0xA084U, NVA084_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NVA084_CTRL_RESERVED                                         (0x00)
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE                          (0x01)
+
+/*
+ * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO
+ *
+ * This command sets the guest vgpu device's information
+ *
+ * Parameter:
+ *
+ * vgpuUuid [IN]
+ *  This parameter specifies the universaly unique identifier of the guest vGPU device
+ *
+ * vgpuDeviceInstanceId [IN]
+ *  This parameter specifies the vGPU device instance
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO (0xa0840101) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS {
+    NvU8  vgpuUuid[NV2080_GPU_MAX_GID_LENGTH];
+    NvU32 vgpuDeviceInstanceId;
+} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS;
+
+/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE
+ *
+ * This command triggers the notifier for vGPU guest.
+ *
+ * Parameters:
+ *
+ * vmLifeCycleState[IN]
+ * The life cycle event of the vGPU guest. This can be:
+ *   NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED
+ *   NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE (0xa0840102) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS_MESSAGE_ID" */
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS {
+    NvU32 vmLifeCycleState;
+} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS;
+
+/*
+ * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO
+ *
+ * This command is used to copy offlined page mapping info from plugin to host vgpu device
+ *
+ *   guestFbSegmentPageSize [in]
+ *     Guest FB segment page size
+ *
+ *   offlinedPageCount [in]
+ *     Offlined page count in the guest FB range
+ *
+ *   gpa [in]
+ *     This array represents guest page address list of offlined page
+ *
+ *   hMemory [in]
+ *     This array represents memory handle list of good page
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO (0xa0840103) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS_MESSAGE_ID" */
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS {
+    NvU32    guestFbSegmentPageSize;
+    NvU32    offlinedPageCount;
+    NV_DECLARE_ALIGNED(NvU64 gpa[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8);
+    NvHandle hMemory[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES];
+} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS;
+
+/*
+ * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS
+ *
+ * Config space access for the virtual function
+ *
+ * Parameters:
+ * 
+ * offset [IN]
+ *   Offset within the config space
+ *
+ * numBytes [IN]
+ *   Number of bytes to be read/written: 1/2/4
+ *
+ * accessType [IN]
+ *   To indicate whether it is a read operation or a write operation
+ *
+ * value [INOUT]
+ *   Value to be read or written
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS (0xa0840104) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS_MESSAGE_ID" */
+
+#define NVA084_CTRL_VF_CONFIG_SPACE_ACCESS_TYPE_READ                   0x1
+#define NVA084_CTRL_VF_CONFIG_SPACE_ACCESS_TYPE_WRITE                  0x2
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS {
+    NvU16 offset;
+    NvU8  numBytes;
+    NvU8  accessType;
+    NvU32 value;
+} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS;
+
+/*
+ * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF
+ *
+ * This command is used to create a bind-point on a host system
+ * for the collection of guest VM FECS events
+ *
+ *  hEventBufferClient[IN]
+ *      The client of the event buffer to bind to
+ *
+ *  hEventBufferSubdevice[IN]
+ *      The subdevice of the event buffer to bind to
+ *
+ *  hEventBuffer[IN]
+ *      The event buffer to bind to
+ *
+ *  reasonCode[OUT]
+ *      The reason for failure (if any); see NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF (0xa0840105) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS_MESSAGE_ID" */
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS {
+    NvHandle hEventBufferClient;
+    NvHandle hEventBufferSubdevice;
+    NvHandle hEventBuffer;
+    NvU32    reasonCode;
+} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS;
+
+/*
+ * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL
+ *
+ * The command will trigger the specified interrupt on the host from CPU Plugin.
+ *
+ *   handle[IN]
+ *      - An opaque handle that will be passed in along with the interrupt
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL (0xa0840106) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS_MESSAGE_ID" */
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS {
+    NvU32 handle;
+} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS;
+
+/* valid action values */
+#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
+#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  (0x00000001)
+#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  (0x00000002)
+
+/*
+ * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION
+ *
+ * This command sets event notification state for the associated host vgpu device.
+ * This command requires that an instance of NV01_EVENT has been previously
+ * bound to the associated host vgpu device object.
+ */
+#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION (0xa0840107) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS {
+    //
+    // @todo: We will define the actual event values later based on the use case.
+    // These event values are only for Test purpose.
+    //
+    NvU32  event;
+    NvU32  action;
+    NvBool bNotifyState;
+} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE
+ *
+ * This command is used to set SRIOV state parameters in RM.
+ *
+ * Parameters:
+ *
+ * numPluginChannels [IN]
+ *   Number of channels required by plugin
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE                 (0xa0840108) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID" */
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_MAX_PLUGIN_CHANNELS 5
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS {
+    NvU32 numPluginChannels;
+} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS;
+
+/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID
+ *
+ * This command is used to set/unset VM ID parameters in host vgpu device in RM.
+ *
+ * Parameters:
+ *
+ * action
+ *   This parameter specifies the desired set guest id action.
+ *   Valid set guest id actions include:
+ *     NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_SET
+ *       This action sets the VM ID information in host vgpu device.
+ *     NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_UNSET
+ *       This action unsets the VM ID information in host vgpu device.
+ * vmPid [IN]
+ *   VM process ID
+ * vmIdType[IN]
+ *   VM ID type whether it's UUID or DOMAIN_ID
+ * guestVmId[IN]
+ *   VM ID
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID (0xa0840109) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID" */
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS {
+    NvU8       action;
+    NvU32      vmPid;
+    VM_ID_TYPE vmIdType;
+    NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
+} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS;
+
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_SET   (0x00000000)
+#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_UNSET (0x00000001)
+
+/* _ctrla084_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla16f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla16f.h
new file mode 100644
index 0000000..7cf7069
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla16f.h
@@ -0,0 +1,200 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla16f.finn
+//
+
+
+
+
+/* GK100_GPFIFO control commands and parameters */
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrla06f.h"          /* A16F is partially derived from A06F */
+#include "ctrl/ctrl906f.h"          /* A16F is partially derived from 906F */
+#define NVA16F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0xA16F, NVA16F_CTRL_##cat, idx)
+
+/* GK100_GPFIFO command categories (6bits) */
+#define NVA16F_CTRL_RESERVED (0x00)
+#define NVA16F_CTRL_GPFIFO   (0x01)
+#define NVA16F_CTRL_EVENT    (0x02)
+
+/*
+ * NVA16F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVA16F_CTRL_CMD_NULL (0xa16f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+ * NVA16F_CTRL_GET_CLASS_ENGINEID
+ *
+ * Please see description of NVA06F_CTRL_GET_CLASS_ENGINEID for more information.
+ *   
+ */
+#define NVA16F_CTRL_GET_CLASS_ENGINEID (0xa16f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x1" */
+
+typedef NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
+    NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
+} NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
+
+
+
+/*
+ * NVA16F_CTRL_RESET_CHANNEL
+ *
+ * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. 
+ *   
+ */
+#define NVA16F_CTRL_CMD_RESET_CHANNEL (0xa16f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x2" */
+typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
+    NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
+} NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
+
+
+
+/*
+ * NVA16F_CTRL_CMD_GPFIFO_SCHEDULE
+ *
+ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
+ *
+ */
+#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE (0xa16f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x3" */
+typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
+    NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS params;
+} NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
+
+
+
+/*
+ * NVA16F_CTRL_CMD_BIND
+ *
+ * Please see description of NVA06F_CTRL_CMD_BIND for more information.
+ */
+#define NVA16F_CTRL_CMD_BIND (0xa16f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x4" */
+
+typedef NVA06F_CTRL_BIND_PARAMS NVA16F_CTRL_BIND_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA16F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVA16F_CTRL_CMD_BIND_FINN_PARAMS {
+    NVA16F_CTRL_BIND_PARAMS params;
+} NVA16F_CTRL_CMD_BIND_FINN_PARAMS;
+
+
+
+/*
+ * NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
+*/
+#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x5" */
+
+typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
+    NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params;
+} NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS;
+
+
+
+/* valid action values */
+#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
+#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
+#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
+
+/*
+ * NVA16F_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
+ */
+#define NVA16F_CTRL_CMD_EVENT_SET_TRIGGER                 (0xa16f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x6" */
+
+
+
+
+
+/*
+ * NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO
+ *
+ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
+ *   
+ */
+#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa16f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x7" */
+
+typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
+} NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
+
+
+
+/* _ctrla16f.h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla26f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla26f.h
new file mode 100644
index 0000000..6dcf930
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla26f.h
@@ -0,0 +1,200 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrla26f.finn
+//
+
+
+
+
+/* GK20A_GPFIFO control commands and parameters */
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrla06f.h"          /* A26F is partially derived from A06F */
+#include "ctrl/ctrl906f.h"          /* A26F is partially derived from 906F */
+#define NVA26F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0xA26F, NVA26F_CTRL_##cat, idx)
+
+/* GK20A_GPFIFO command categories (6bits) */
+#define NVA26F_CTRL_RESERVED (0x00)
+#define NVA26F_CTRL_GPFIFO   (0x01)
+#define NVA26F_CTRL_EVENT    (0x02)
+
+/*
+ * NVA26F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVA26F_CTRL_CMD_NULL (0xa26f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+ * NVA26F_CTRL_GET_CLASS_ENGINEID
+ *
+ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
+ *   
+ */
+#define NVA26F_CTRL_GET_CLASS_ENGINEID (0xa26f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x1" */
+
+typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
+    NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
+} NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
+
+
+
+/*
+ * NVA26F_CTRL_RESET_CHANNEL
+ *
+ * Please see description of NVA06F_CTRL_CMD_RESET_CHANNEL for more information. 
+ *
+ */
+#define NVA26F_CTRL_CMD_RESET_CHANNEL (0xa26f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x2" */
+typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
+    NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
+} NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
+
+
+
+/*
+ * NVA26F_CTRL_CMD_GPFIFO_SCHEDULE
+ *
+ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
+ *
+ */
+#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE (0xa26f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x3" */
+typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
+    NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS params;
+} NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
+
+
+
+/*
+ * NVA26F_CTRL_CMD_BIND
+ *
+ * Please see description of NVA06F_CTRL_CMD_BIND for more information.
+ */
+#define NVA26F_CTRL_CMD_BIND (0xa26f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x4" */
+
+typedef NVA06F_CTRL_BIND_PARAMS NVA26F_CTRL_BIND_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA26F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVA26F_CTRL_CMD_BIND_FINN_PARAMS {
+    NVA26F_CTRL_BIND_PARAMS params;
+} NVA26F_CTRL_CMD_BIND_FINN_PARAMS;
+
+
+
+/*
+ * NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
+*/
+#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x5" */
+
+typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
+    NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params;
+} NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS;
+
+
+
+/* valid action values */
+#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
+#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
+#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
+
+/*
+ * NVA26F_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
+ */
+#define NVA26F_CTRL_CMD_EVENT_SET_TRIGGER                 (0xa26f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x6" */
+
+
+
+
+
+/*
+ * NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO
+ *
+ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
+ *   
+ */
+#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa26f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x7" */
+
+typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
+} NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
+
+
+
+/* _ctrla26f.h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb069.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb069.h
new file mode 100644
index 0000000..66eb26d
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb069.h
@@ -0,0 +1,180 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlb069.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* MAXWELL_FAULT_BUFFER_A control commands and parameters */
+
+#define NVB069_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0xB069, NVB069_CTRL_##cat, idx)
+
+/* MAXWELL_FAULT_BUFFER_A command categories (6bits) */
+#define NVB069_CTRL_RESERVED    (0x00)
+#define NVB069_CTRL_FAULTBUFFER (0x01)
+
+/*
+ * NVB069_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVB069_CTRL_CMD_NULL    (0xb0690000) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+
+/*
+ * NVB069_CTRL_CMD_FAULTBUFFER_READ_GET
+ *
+ * This command returns the current HW GET pointer for the requested type fault buffer
+ *
+ *    faultBufferGetOffset
+ *      Value of current HW GET pointer
+ *    faultBufferType
+ *      Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE
+ */
+#define NVB069_CTRL_CMD_FAULTBUFFER_READ_GET (0xb0690101) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS_MESSAGE_ID" */
+
+#define NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS {
+    NvU32 faultBufferGetOffset;
+    NvU32 faultBufferType;
+} NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS;
+
+//
+// Valid Fault buffer Types
+// NON_REPLAYABLE is only supported in Volta+ GPUs.
+//
+#define NVB069_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000)
+#define NVB069_CTRL_FAULT_BUFFER_REPLAYABLE     (0x00000001)
+
+/*
+ * NVB069_CTRL_CMD_FAULTBUFFER_WRITE_GET
+ *
+ * This command writes the HW GET pointer for the requested type of fault buffer
+ *
+ * NOTE: The caller must issue a write barrier before this function to
+ * ensure modifications to the current buffer entry are committed before
+ * the GET pointer is updated.
+ * 
+ *    faultBufferGetOffset
+ *      Value to be written to HW GET pointer
+ *    faultBufferType
+ *      Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE
+ */
+#define NVB069_CTRL_CMD_FAULTBUFFER_WRITE_GET   (0xb0690102) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS_MESSAGE_ID" */
+
+#define NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS {
+    NvU32 faultBufferGetOffset;
+    NvU32 faultBufferType;
+} NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS;
+
+/*
+ * NVB069_CTRL_CMD_FAULTBUFFER_READ_PUT
+ *
+ * This command returns the current HW PUT pointer for the requested type fault buffer
+ *
+ *    faultBufferGetOffset
+ *      Value of current HW PUT pointer
+ *    faultBufferType
+ *      Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE
+ */
+#define NVB069_CTRL_CMD_FAULTBUFFER_READ_PUT (0xb0690103) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS_MESSAGE_ID" */
+
+#define NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS {
+    NvU32 faultBufferPutOffset;
+    NvU32 faultBufferType;
+} NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS;
+
+#define NVB069_CTRL_CMD_FAULTBUFFER_ENABLE_NOTIFICATION (0xb0690104) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS {
+    NvBool Enable;
+} NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS;
+
+#define NVB069_CTRL_CMD_FAULTBUFFER_GET_SIZE (0xb0690105) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS {
+    NvU32 faultBufferSize;
+} NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS;
+
+
+/*
+ * NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS
+ *
+ * This command provides kernel mapping to a few registers.
+ * These mappings are needed by UVM driver to handle non fatal gpu faults
+ *
+ *    pFaultBufferGet
+ *      Mapping for fault buffer's get pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_GET)
+ *    pFaultBufferPut
+ *      Mapping for fault buffer's put pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_PUT)
+ *    pFaultBufferInfo
+ *      Mapping for fault buffer's Info pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_INFO)
+ *      Note: this variable is deprecated since buffer overflow is not a seperate register from Volta
+ *    pPmcIntr
+ *      Mapping for PMC intr register (NV_PMC_INTR(0))
+ *    pPmcIntrEnSet
+ *      Mapping for PMC intr set register - used to enable an intr (NV_PMC_INTR_EN_SET(0))
+ *    pPmcIntrEnClear
+ *      Mapping for PMC intr clear register - used to disable an intr (NV_PMC_INTR_EN_CLEAR(0))
+ *    replayableFaultMask
+ *      Mask for the replayable fault bit(NV_PMC_INTR_REPLAYABLE_FAULT)
+ */
+#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS (0xb0690106) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */
+
+#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pFaultBufferGet, 8);
+    NV_DECLARE_ALIGNED(NvP64 pFaultBufferPut, 8);
+    NV_DECLARE_ALIGNED(NvP64 pFaultBufferInfo, 8);
+    NV_DECLARE_ALIGNED(NvP64 pPmcIntr, 8);
+    NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnSet, 8);
+    NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnClear, 8);
+    NvU32 replayableFaultMask;
+    NV_DECLARE_ALIGNED(NvP64 pPrefetchCtrl, 8);
+} NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS;
+
+/* _ctrlb069_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb06f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb06f.h
new file mode 100644
index 0000000..14a6199
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb06f.h
@@ -0,0 +1,527 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlb06f.finn
+//
+
+
+
+
+/* MAXWELL_CHANNEL_GPFIFO_A control commands and parameters */
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrla06f.h"          /* B06F is partially derived from A06F */
+#include "ctrl/ctrl906f.h"          /* B06F is partially derived from 906F */
+#define NVB06F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0xB06F, NVB06F_CTRL_##cat, idx)
+
+/* MAXWELL_CHANNEL_GPFIFO_A command categories (6bits) */
+#define NVB06F_CTRL_RESERVED (0x00)
+#define NVB06F_CTRL_GPFIFO   (0x01)
+#define NVB06F_CTRL_EVENT    (0x02)
+
+/*
+ * NVB06F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVB06F_CTRL_CMD_NULL (0xb06f0000) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+ * NVB06F_CTRL_GET_CLASS_ENGINEID
+ *
+ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
+ *
+ */
+#define NVB06F_CTRL_GET_CLASS_ENGINEID (0xb06f0101) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
+
+typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
+    NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
+} NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
+
+
+
+/*
+ * NVB06F_CTRL_RESET_CHANNEL
+ *
+ * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information.
+ *
+ */
+#define NVB06F_CTRL_CMD_RESET_CHANNEL (0xb06f0102) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */
+
+typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
+    NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
+} NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
+
+
+
+/*
+ * NVB06F_CTRL_CMD_GPFIFO_SCHEDULE
+ *
+ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
+ *
+ */
+#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE (0xb06f0103) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */
+
+typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
+    NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS params;
+} NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
+
+
+
+/*
+ * NVB06F_CTRL_CMD_BIND
+ *
+ * Please see description of NVA06F_CTRL_CMD_BIND for more information.
+ */
+#define NVB06F_CTRL_CMD_BIND (0xb06f0104) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */
+
+typedef NVA06F_CTRL_BIND_PARAMS NVB06F_CTRL_BIND_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVB06F_CTRL_CMD_BIND_FINN_PARAMS {
+    NVB06F_CTRL_BIND_PARAMS params;
+} NVB06F_CTRL_CMD_BIND_FINN_PARAMS;
+
+
+
+/*
+ * NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
+*/
+#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
+
+typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
+    NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params;
+} NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS;
+
+
+
+/* valid action values */
+#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
+#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
+#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
+
+/*
+ * NVB06F_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
+ */
+#define NVB06F_CTRL_CMD_EVENT_SET_TRIGGER                 (0xb06f0206) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
+
+
+
+
+
+/*
+ * NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO
+ *
+ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
+ *
+ */
+#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xb06f0107) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */
+
+typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
+} NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
+
+
+
+/*
+ * NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE
+ *
+ * This command returns the size of the engine context.
+ *
+ * engineID
+ *   This parameter specifies the engine context size to be retrieved.
+ *
+ *   See the description of the NV2080_ENGINE_TYPE values in cl2080.h for more
+ *   information
+ *
+ * size
+ *   This parameter returns the size of the engine context
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE (0xb06f010b) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS {
+    NvU32 engineID;
+    NvU32 size;
+} NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS;
+
+/*
+ * NVB06F_CTRL_CMD_GET_ENGINE_CTX_DATA
+ *
+ * This command returns the context buffer data for the given engine for vGPU motion.
+ *
+ * engineID
+ *   This parameter specifies the engine context to be retrieved.
+ *
+ *   See the description of the NV2080_ENGINE_TYPE values in cl2080.h for
+ *   more information
+ *
+ * size
+ *   This parameter specifies the size of the context buffer.
+ *
+ * pEngineCtxBuff
+ *   This parameter specifies the context buffer for motion operation to be filled in.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+
+#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_DATA (0xb06f010c) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */
+
+typedef struct SW_OBJECT_ENGINE_CTX {
+    NvU32 hObject;
+    NvU32 subCh;
+} SW_OBJECT_ENGINE_CTX;
+
+#define NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS {
+    NvU32 engineID;
+    NvU32 size;
+    NV_DECLARE_ALIGNED(NvP64 pEngineCtxBuff, 8);
+} NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS;
+
+/*
+ * NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA
+ *
+ * This command restores the context buffer for the given engine for vGPU motion.
+ *
+ * engineID
+ *   This parameter specifies the engine context to be restored.
+ *
+ *   See the description of the NV2080_ENGINE_TYPE values in cl2080.h for
+ *   more information
+ *
+ * size
+ *   This parameter specifies the size of the context buffer.
+ *
+ * pEngineCtxBuff
+ *   This parameter specifies the context buffer for motion operation restore.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+
+#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA (0xb06f010d) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */
+
+typedef NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS params, 8);
+} NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS;
+
+
+
+/*
+ * NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE
+ *
+ * This command returns the context buffer state of the given engine for vGPU motion.
+ *
+ * engineID
+ *   This input parameter specifies the engine context to be restored.
+ *
+ *   See the description of the NV2080_ENGINE_TYPE values in cl2080.h for
+ *   more information
+ *
+ * hObject
+ *   This parameter specifies the channel object that is running on the SW engine.
+ *
+ * engineCtxState
+ *   This parameter specifies the engine context state. For SW engine, the only meaningful
+ *   field is INVALID, INITIALIZED and the subch.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+
+#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE (0xb06f010e) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS_MESSAGE_ID" */
+
+#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS {
+    NvU32 engineID;
+    NvU32 hObject;
+    NvU32 engineCtxState;
+} NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS;
+
+#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT              0:0
+#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT_DISABLED (0x00000000)
+#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT_ENABLED  (0x00000001)
+#define NVB06F_CTRL_GET_ENGINE_CTX_STATE                        2:1
+#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_INVALID            (0x00000000)
+#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_INITIALIZED        (0x00000001)
+#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_PROMOTED           (0x00000002)
+#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_EVICTED            (0x00000003)
+#define NVB06F_CTRL_GET_ENGINE_CTX_SUBCH                        6:4
+
+/*
+ * NVB06F_CTRL_CMD_GET_CHANNEL_HW_STATE
+ *
+ * This command returns the channel HW state.
+ *
+ * state
+ *   This parameter stores single bit-fields corresponding to the following
+ *   channel HW states:
+ *      NEXT
+ *          A value of NV_TRUE indicates that this channel should be scheduled
+ *          first when GPU Host chooses this TSG to run next on the runlist.
+ *
+ *      CTX_RELOAD
+ *          A value of NV_TRUE indicates that this channel's context was
+ *          preempted and needs to be reloaded.
+ *
+ *      PENDING
+ *          A value of NV_TRUE indicates that this channel is not loaded on the
+ *          PBDMA but methods still remain. This includes the completion of
+ *          semaphores acquires and WFI methods. This field is deprecated
+ *          from Volta onwards, and can be ignored.
+ *
+ *      ENG_FAULTED
+ *          A value of NV_TRUE indicates that the channel's engine has faulted,
+ *          and the channel will not be rescheduled until the fault has been
+ *          cleared. This bit should only be set as part of migration, and will
+ *          not necessarily cause the channel to be prevented from being
+ *          scheduled.
+ *
+ *      PBDMA_FAULTED
+ *          A value of NV_TRUE indicates that the channel's PBDMA has faulted,
+ *          and the channel will not be rescheduled until the fault has been
+ *          cleared. This bit should only be set as part of migration, and will
+ *          not necessarily cause the channel to be prevented from being
+ *          scheduled.
+ *
+ *      ACQUIRE_FAIL
+ *          A value of NV_TRUE indicates that the engine scheduler failed to
+ *          acquire a semaphore for this channel. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVB06F_CTRL_CMD_GET_CHANNEL_HW_STATE                (0xb06f010f) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID" */
+
+#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_NEXT               0:0
+#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_CTX_RELOAD         1:1
+#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PENDING            2:2
+#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ENG_FAULTED        3:3
+#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PBDMA_FAULTED      4:4
+#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ACQUIRE_FAIL       5:5
+
+#define NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS {
+    NvU32 state;
+} NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS;
+
+/*
+ * NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE
+ *
+ * This command restores the channel HW state.
+ *
+ * state
+ *   This parameter stores single bit-fields corresponding to the following
+ *   channel HW states:
+ *      NEXT
+ *          A value of NV_TRUE indicates that this channel should be scheduled
+ *          first when GPU Host chooses this TSG to run next on the runlist.
+ *
+ *      CTX_RELOAD
+ *          A value of NV_TRUE indicates that this channel's context was
+ *          preempted and needs to be reloaded.
+ *
+ *      PENDING
+ *          A value of NV_TRUE indicates that this channel is not loaded on the
+ *          PBDMA but methods still remain. This includes the completion of
+ *          semaphores acquires and WFI methods. This field is deprecated
+ *          from Volta onwards, and can be ignored.
+ *
+ *      ENG_FAULTED
+ *          A value of NV_TRUE indicates that the channel's engine has faulted,
+ *          and the channel will not be rescheduled until the fault has been
+ *          cleared. This bit should only be set as part of migration, and will
+ *          not necessarily cause the channel to be prevented from being
+ *          scheduled.
+ *
+ *      PBDMA_FAULTED
+ *          A value of NV_TRUE indicates that the channel's PBDMA has faulted,
+ *          and the channel will not be rescheduled until the fault has been
+ *          cleared. This bit should only be set as part of migration, and will
+ *          not necessarily cause the channel to be prevented from being
+ *          scheduled.
+ *
+ *      ACQUIRE_FAIL
+ *          A value of NV_TRUE indicates that the engine scheduler failed to
+ *          acquire a semaphore for this channel. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE (0xb06f0110) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */
+
+typedef NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS {
+    NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS params;
+} NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS;
+
+/*
+ * NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA
+ *
+ * This command returns the context buffer data for the given engine for vGPU migration.
+ *
+ * engineID
+ *   This parameter specifies the engine context to be retrieved.
+ *
+ *   See the description of the NV2080_ENGINE_TYPE values in cl2080.h for
+ *   more information
+ *
+ * size
+ *   This parameter specifies the size of the context buffer. The maximum size
+ *   of engine context buffer is choosen to support only RAMFC and instance
+ *   memory block. To use this RmCtrl for a higher sized buffer, like the GR
+ *   context, the max size would have to be increased.
+ *
+ * engineCtxBuff
+ *   This parameter specifies the context buffer data.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+
+#define NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA   (0xb06f0111) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */
+
+#define NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX 4096
+
+#define NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS {
+    NvU32 engineID;
+    NvU32 size;
+    NvU8  engineCtxBuff[NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX];
+} NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS;
+
+/*
+ * NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA
+ *
+ * This command restores the context buffer for the given engine for vGPU migration.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+
+#define NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA (0xb06f0112) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */
+
+typedef NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS {
+    NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS params;
+} NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS;
+
+
+
+/* _ctrlb06f.h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc.h
new file mode 100644
index 0000000..decc79a
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc.h
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlb0cc.finn
+//
+
+
+
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl2080/ctrl2080gpu.h"  // NV2080_CTRL_GPU_REG_OP
+#include "ctrlb0cc/ctrlb0ccprofiler.h"
+#include "ctrlb0cc/ctrlb0ccinternal.h"
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h
new file mode 100644
index 0000000..a6d2929
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h
@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlb0cc/ctrlb0ccbase.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl2080/ctrl2080gpu.h"  // NV2080_CTRL_GPU_REG_OP
+#define NVB0CC_CTRL_CMD(cat,idx)                     NVXXXX_CTRL_CMD(0xB0CC, NVB0CC_CTRL_##cat, idx)
+
+/* MAXWELL_PROFILER command categories (6 bits) */
+#define NVB0CC_CTRL_RESERVED (0x00)
+#define NVB0CC_CTRL_PROFILER (0x01)
+#define NVB0CC_CTRL_INTERNAL (0x02)
+
+/*!
+ * NVB0CC_CTRL_CMD_NULL
+ *
+ *    This command does nothing.
+ *    This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ */
+#define NVB0CC_CTRL_CMD_NULL (0xb0cc0000) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+/* _ctrlb0ccbase_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h
new file mode 100644
index 0000000..54e2dbd
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h
@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlb0cc/ctrlb0ccinternal.finn
+//
+
+#include "ctrl/ctrlb0cc/ctrlb0ccbase.h"
+
+#include "ctrl/ctrlb0cc/ctrlb0ccprofiler.h"        /* Some controls derivative of b0ccprofiler */
+/*!
+ * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0200) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID" */
+
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID (0x0U)
+
+typedef struct NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS params, 8);
+} NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS;
+
+
+
+/*!
+ * NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT
+ *
+ * This command is used to convey the client permissions for appropriate
+ * profiling capability initialization
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT (0xb0cc0203) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS {
+    /*!
+     * [in] Is Admin profiling permitted
+     */
+    NvBool bAdminProfilingPermitted;
+    /*!
+     * [in] Is Device profiling permitted
+     */
+    NvBool bDevProfilingPermitted;
+
+    /*!
+     * [in] Is Memory profiling permitted
+     */
+    NvBool bMemoryProfilingPermitted;
+} NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS;
+
+/* _ctrlb0ccinternal_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
new file mode 100644
index 0000000..d456c63
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
@@ -0,0 +1,479 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlb0cc/ctrlb0ccprofiler.finn
+//
+
+#include "ctrl/ctrlb0cc/ctrlb0ccbase.h"
+
+
+/*!
+ * NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY
+ *
+ * Reserves the HWPM legacy PM system for use by the calling client.
+ * This PM system will only be accessible if this reservation is
+ * taken.
+ *
+ * If a device level reservation is held by another client, then this command
+ * will fail regardless of reservation scope.
+ *
+ * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY.
+ *
+ */
+
+
+#define NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY (0xb0cc0101) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS {
+    /*!
+     * [in] Enable ctxsw for HWPM.
+     */
+    NvBool ctxsw;
+} NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY
+ *
+ * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY.
+ *
+ * This command does not take any parameters.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY  (0xb0cc0102) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x2" */
+
+/*!
+ * NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC
+ *
+ * Reserves the SMPC PM system for use by the calling client.
+ * This PM system will only be accessible if this reservation is
+ * taken.
+ *
+ * Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY.
+ *
+ * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC (0xb0cc0103) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS {
+    /*!
+     * [in] Enable ctxsw for SMPC.
+     */
+    NvBool ctxsw;
+} NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC
+ *
+ * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC.
+ *
+ * This command does not take any parameters.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC (0xb0cc0104) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x4" */
+
+/*!
+ * NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM
+ *
+ * Allocates PMA VA and map it to the buffers for streaming records and for
+ * for streaming the updated bytes available in the buffer.
+ *
+ */
+#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM     (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x5" */
+
+/*!
+ * Defines the maximum size of PMA buffer for streamout. It can be up to 4GB minus one page
+ * reserved for streaming mem_bytes (see @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE).
+ */
+#define NVB0CC_PMA_BUFFER_SIZE_MAX           (0xffe00000ULL) /* finn: Evaluated from "(4 * 1024 * 1024 * 1024 - 2 * 1024 * 1024)" */
+#define NVB0CC_PMA_BYTES_AVAILABLE_SIZE      (0x1000) /* finn: Evaluated from "(4 * 1024)" */
+
+typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS {
+    /*!
+     * [in] Memory handle (RW memory) for streaming records.
+     * Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize.
+     */
+    NvHandle hMemPmaBuffer;
+
+    /*!
+     * [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer).
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8);
+
+    /*!
+     * [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX.
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8);
+
+    /*!
+     * [in] Memory handle (RO memory) for streaming number of bytes available.
+     * Size of this must be of at least @ref pmaBytesAvailableOffset +
+     * @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE.
+     */
+    NvHandle hMemPmaBytesAvailable;
+
+    /*!
+     * [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable).
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8);
+
+    /*!
+     * [in] Enable ctxsw for PMA stream.
+     */
+    NvBool   ctxsw;
+
+    /*!
+     * [out] The PMA Channel Index associated with a given PMA stream.
+     */
+    NvU32    pmaChannelIdx;
+
+    /*!
+     * [out] PMA buffer VA. Note that this is a HWPM Virtual address.
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8);
+} NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_FREE_PMA_STREAM
+ *
+ * Releases (unmap and free) PMA stream allocated through
+ * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM.
+ *
+ */
+#define NVB0CC_CTRL_CMD_FREE_PMA_STREAM (0xb0cc0106) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS {
+    /*!
+     * [in] The PMA channel index associated with a given PMA stream.
+     */
+    NvU32 pmaChannelIdx;
+} NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_BIND_PM_RESOURCES
+ *
+ * Binds all PM resources reserved through @ref NVB0CC_CTRL_CMD_RESERVE_*
+ * and with @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM with PMA engine.
+ * After this call, interface is ready for programming a collection
+ * of counters.
+ * @Note: Any new PM resource reservation via NVB0CC_CTRL_CMD_RESERVE_* or
+ * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM request after this call will fail,
+ * clients need to unbind (see @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES) to
+ * reserve more resources.
+ *
+ * This can be unbound with @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES.
+ *
+ */
+#define NVB0CC_CTRL_CMD_BIND_PM_RESOURCES         (0xb0cc0107) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x7" */
+
+/*!
+ * NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES
+ *
+ * Unbinds PM resources that were bound with @ref NVB0CC_CTRL_CMD_BIND_PM_RESOURCES
+ *
+ */
+#define NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES       (0xb0cc0108) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x8" */
+
+/*!
+ * NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT
+ *
+ * This command updates bytes consumed by the SW and optionally gets the
+ * current available bytes in the buffer.
+ *
+ */
+#define NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT (0xb0cc0109) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE      0xFFFFFFFF
+#define NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS {
+    /*!
+     * [in] Total bytes consumed by SW since last update.
+     */
+    NV_DECLARE_ALIGNED(NvU64 bytesConsumed, 8);
+
+    /*!
+     * [in] Initiate streaming of the bytes available (see @ref hMemPmaBytesAvailable).
+     * RM will set the memory for streaming (see @ref hMemPmaBytesAvailable) to NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE and
+     * client can optionally wait (see @ref bWait) for it to change from this value.
+     */
+    NvBool bUpdateAvailableBytes;
+
+    /*!
+     * [in] Waits for available bytes to get updated
+     */
+    NvBool bWait;
+
+    /*!
+     * [out] Bytes available in the PMA buffer (see @ref hMemPmaBuffer) for SW to consume.
+     * This will only be populated if both bUpdateAvailableBytes and bWait are set
+     * to TRUE.
+     */
+    NV_DECLARE_ALIGNED(NvU64 bytesAvailable, 8);
+
+    /*!
+     * [in] If set to TRUE, current put pointer will be returned in @ref putPtr.
+     */
+    NvBool bReturnPut;
+
+    /*!
+     * [out] Current PUT pointer (MEM_HEAD).
+     * This will only be populated if bReturnPut is set to TRUE.
+     */
+    NV_DECLARE_ALIGNED(NvU64 putPtr, 8);
+
+    /*!
+     * [in] The PMA Channel Index associated with a given PMA stream.
+     */
+    NvU32  pmaChannelIdx;
+} NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS;
+
+/*!
+ * Maximum number of register operations allowed in a single request.
+ * @NOTE: @ref NVB0CC_REGOPS_MAX_COUNT is chosen to keep struct size
+ * of @ref NVB0CC_CTRL_EXEC_REG_OPS_PARAMS under 4KB.
+ */
+#define NVB0CC_REGOPS_MAX_COUNT      (124)
+
+/*!
+ * NVB0CC_CTRL_CMD_EXEC_REG_OPS
+ *
+ * This command is used to submit an array containing one or more
+ * register operations for processing.  Each entry in the
+ * array specifies a single read or write operation. Each entry is
+ * checked for validity in the initial pass: Only registers from PM area
+ * are allowed using this interface and only register from PM systems for
+ * which user has a valid reservation are allowed (see @ref NVB0CC_CTRL_CMD_RESERVE_*).
+ * Operation type (@ref  NV2080_CTRL_GPU_REG_OP_TYPE_*) is not required to be passed in.
+ */
+#define NVB0CC_CTRL_CMD_EXEC_REG_OPS (0xb0cc010a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Structure definition for register operation. See @ref NV2080_CTRL_GPU_REG_OP.
+ */
+typedef NV2080_CTRL_GPU_REG_OP NVB0CC_GPU_REG_OP;
+
+/*!
+ * Enumeration of different REG_OPS modes. This mode determines how a failure
+ * of a regop is handled in a batch of regops.
+ */
+typedef enum NVB0CC_REGOPS_MODE {
+
+    /*!
+     * Either all regops will be executed or none of them will be executed.
+     * Failing regop will have the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus).
+     */
+    NVB0CC_REGOPS_MODE_ALL_OR_NONE = 0,
+    /*!
+     * All regops will be attempted and the ones that failed will have the
+     * the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus).
+     */
+    NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR = 1,
+} NVB0CC_REGOPS_MODE;
+
+#define NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS {
+    /*!
+     * [in] Number of valid entries in the regOps array. This value cannot
+     * exceed NVB0CC_REGOPS_MAX_COUNT.
+     */
+    NvU32              regOpCount;
+
+    /*!
+     * [in] Specifies the mode for the entire operation see @ref NVB0CC_REGOPS_MODE.
+     */
+    NVB0CC_REGOPS_MODE mode;
+
+    /*!
+     * [out] Provides status for the entire operation. This is only valid for
+     * mode @ref NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR.
+     */
+    NvBool             bPassed;
+
+    /*!
+     * [out] This is currently not populated.
+     */
+    NvBool             bDirect;
+
+    /*!
+     * [in/out] An array (of fixed size NVB0CC_REGOPS_MAX_COUNT) of register read or write
+     * operations (see @ref NVB0CC_GPU_REG_OP)
+     *
+     */
+    NVB0CC_GPU_REG_OP  regOps[NVB0CC_REGOPS_MAX_COUNT];
+} NVB0CC_CTRL_EXEC_REG_OPS_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER
+ *
+ * Reserves the PC sampler system for use by the calling client.
+ *
+ * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER.
+ *
+ * This command does not take any parameters.
+ *
+ * PC sampler is always context switched with a GR context, so reservation scope is
+ * always context. This requires that profiler object is instantiated with a valid GR
+ * context. See @ref NVB2CC_ALLOC_PARAMETERS.
+ */
+
+#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER (0xb0cc010b) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xB" */
+
+/*!
+ * NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER
+ *
+ * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER.
+ *
+ * This command does not take any parameters.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER (0xb0cc010c) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xC" */
+
+/*!
+ * NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS
+ *
+ * Gets the total high speed streaming credits available for the client.
+ *
+ * This command can only be performed after a bind using NVB0CC_CTRL_CMD_BIND_PM_RESOURCES.
+ *
+ */
+#define NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS       (0xb0cc010d) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS {
+    NvU32 numCredits;
+} NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_SET_HS_CREDITS_CHIPLET
+ *
+ * Sets per chiplet (pmm router) credits for high speed streaming for a pma channel.
+ *
+ * @note: This command resets the current credits to 0 before setting the new values also
+ *        if programming fails, it will reset credits to 0 for all the chiplets.
+ *
+ */
+#define NVB0CC_CTRL_CMD_SET_HS_CREDITS (0xb0cc010e) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID" */
+
+typedef enum NVB0CC_CHIPLET_TYPE {
+    NVB0CC_CHIPLET_TYPE_INVALID = 0,
+    NVB0CC_CHIPLET_TYPE_FBP = 1,
+    NVB0CC_CHIPLET_TYPE_GPC = 2,
+    NVB0CC_CHIPLET_TYPE_SYS = 3,
+} NVB0CC_CHIPLET_TYPE;
+
+typedef enum NVB0CC_HS_CREDITS_CMD_STATUS {
+    NVB0CC_HS_CREDITS_CMD_STATUS_OK = 0,
+    /*!
+     * More credits are requested than the total credits. Total credits can be queried using @ref NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS
+     */
+    NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CREDITS = 1,
+    /*!
+     * Chiplet index is invalid.
+     */
+    NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET = 2,
+} NVB0CC_HS_CREDITS_CMD_STATUS;
+
+typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO {
+    /*!
+     * Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE.
+     */
+    NvU8  chipletType;
+
+    /*!
+     * Specifies the logical index of the chiplet.
+     */
+    NvU8  chipletIndex;
+
+    /*!
+     * Specifies the number of credits for the chiplet.
+     */
+    NvU16 numCredits;
+} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO;
+
+typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS {
+    /*!
+     * Status for the command @ref NVB0CC_HS_CREDITS_CMD_STATUS.
+     */
+    NvU8 status;
+
+    /*!
+     * Index of the failing @ref NVB0CC_CTRL_SET_HS_CREDITS_PARAMS::creditInfo entry. This
+     * is only relevant if status is NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET.
+     */
+    NvU8 entryIndex;
+} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS;
+
+#define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63)
+
+#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS {
+    /*!
+     * [in] The PMA Channel Index associated with a given PMA stream.
+     */
+    NvU8                                     pmaChannelIdx;
+
+    /*!
+     * [in] Number of valid entries in creditInfo.
+     */
+    NvU8                                     numEntries;
+
+    /*!
+     * [out] Provides status for the entire operation.
+     */
+    NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS statusInfo;
+
+    /*!
+     * [in] Credit programming per chiplet
+     */
+    NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO   creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES];
+} NVB0CC_CTRL_SET_HS_CREDITS_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_GET_HS_CREDITS
+ *
+ * Gets per chiplet (pmm router) high speed streaming credits for a pma channel.
+ *
+ */
+#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xF" */
+
+typedef NVB0CC_CTRL_SET_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS;
+
+
+
+/* _ctrlb0ccprofiler_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc06f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc06f.h
new file mode 100644
index 0000000..1b493c7
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc06f.h
@@ -0,0 +1,200 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc06f.finn
+//
+
+
+
+
+/* PASCAL_CHANNEL_GPFIFO_A control commands and parameters */
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrla06f.h"          /* C06F is partially derived from A06F */
+#include "ctrl/ctrl906f.h"          /* C06F is partially derived from 906F */
+#define NVC06F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0xC06F, NVC06F_CTRL_##cat, idx)
+
+/* PASCAL_CHANNEL_GPFIFO_B command categories (6bits) */
+#define NVC06F_CTRL_RESERVED (0x00)
+#define NVC06F_CTRL_GPFIFO   (0x01)
+#define NVC06F_CTRL_EVENT    (0x02)
+
+/*
+ * NVC06F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVC06F_CTRL_CMD_NULL (0xc06f0000) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+/*
+ * NVC06F_CTRL_GET_CLASS_ENGINEID
+ *
+ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
+ *   
+ */
+#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
+
+typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
+    NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
+} NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
+
+
+
+/*
+ * NVC06F_CTRL_RESET_CHANNEL
+ *
+ * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. 
+ *   
+ */
+#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */
+typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
+    NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
+} NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
+
+
+
+/*
+ * NVC06F_CTRL_CMD_GPFIFO_SCHEDULE
+ *
+ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
+ *
+ */
+#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */
+typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
+    NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS params;
+} NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
+
+
+
+/*
+ * NVC06F_CTRL_CMD_BIND
+ *
+ * Please see description of NVA06F_CTRL_CMD_BIND for more information.
+ */
+#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */
+
+typedef NVA06F_CTRL_BIND_PARAMS NVC06F_CTRL_BIND_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVC06F_CTRL_CMD_BIND_FINN_PARAMS {
+    NVC06F_CTRL_BIND_PARAMS params;
+} NVC06F_CTRL_CMD_BIND_FINN_PARAMS;
+
+
+
+/*
+ * NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
+*/
+#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
+
+typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
+    NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params;
+} NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS;
+
+
+
+/* valid action values */
+#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
+#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
+#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
+
+/*
+ * NVC06F_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
+ */
+#define NVC06F_CTRL_CMD_EVENT_SET_TRIGGER                 (0xc06f0206) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
+
+
+
+
+
+/*
+ * NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO
+ *
+ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
+ *   
+ */
+#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */
+
+typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
+} NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
+
+
+
+/* _ctrlc06f.h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc365.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc365.h
new file mode 100644
index 0000000..fc23e13
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc365.h
@@ -0,0 +1,331 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc365.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#define NVC365_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0xC365, NVC365_CTRL_##cat, idx)
+
+
+#define NVC365_CTRL_RESERVED           (0x00)
+#define NVC365_CTRL_ACCESS_CNTR_BUFFER (0x01)
+
+
+/*
+ * NVC365_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVC365_CTRL_CMD_NULL           (0xc3650000) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+
+/*
+ * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_GET
+ *
+ * This command provides the value of the GET register 
+ *
+ *    accessCntrBufferGetOffset [OUT]
+ *       This parameter returns the value of the GET register
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_GET (0xc3650101) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS_MESSAGE_ID" */
+
+#define NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS {
+    NvU32 accessCntrBufferGetOffset;
+} NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS;
+
+
+/*
+ * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_WRITE_GET
+ *
+ * This command writes a value into the GET register 
+ *
+ *    accessCntrBufferGetValue [IN]
+ *       This parameter specifies the new value of the GET register
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_WRITE_GET (0xc3650102) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS_MESSAGE_ID" */
+
+#define NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS {
+    NvU32 accessCntrBufferGetValue;
+} NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS;
+
+
+/*
+ * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_PUT
+ *
+ * This command provides the value of the PUT register 
+ *
+ *    accessCntrBufferPutOffset [OUT]
+ *       This parameter returns the value of the PUT register
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_PUT (0xc3650103) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS_MESSAGE_ID" */
+
+#define NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS {
+    NvU32 accessCntrBufferPutOffset;
+} NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS;
+
+
+/*
+ * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE
+ *
+ * This command enables/disables the access counters 
+ * It also sets up RM to either service or ignore the Access Counter interrupts.
+ *
+ *    intrOwnership [IN]
+ *       This parameter specifies whether RM should own the interrupt upon return
+ *    enable [IN]
+ *       NV_TRUE  = Access counters will be enabled
+ *       NV_FALSE = Access counters will be disabled
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE (0xc3650104) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS_MESSAGE_ID" */
+
+#define NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS {
+    NvU32  intrOwnership;
+    NvBool enable;
+} NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS;
+
+#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_NO_CHANGE (0x0)
+#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_RM        (0x1)
+#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_NOT_RM    (0x2)
+
+/*
+ * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_SIZE
+ *
+ * This command provides the size of the notification buffer
+ *
+ *    accessCntrBufferSize [OUT]
+ *       This parameter returns the size of the notification buffer
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_SIZE              (0xc3650105) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS {
+    NvU32 accessCntrBufferSize;
+} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS;
+
+
+/*
+ * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS
+ *
+ * This command provides the access counter register mappings
+ *
+ *    pAccessCntrBufferGet [OUT]
+ *       This parameter returns the pointer to the GET register
+ *    pAccessCntrBufferPut [OUT]
+ *       This parameter returns the pointer to the PUT register
+ *    pAccessCntrlBufferFull [OUT]
+ *       This parameter returns the pointer to the FULL register 
+ *    pHubIntr [OUT]
+ *       This parameter returns the pointer to the hub interrupt register
+ *    pHubIntrEnSet [OUT]
+ *       This parameter returns the pointer to the set register
+ *    pHubIntrEnClear [OUT]
+ *       This parameter returns the pointer to the clear register
+ *    accessCntrMask [OUT]
+ *       This parameter returns the interrupt mask
+ * 
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS (0xc3650106) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */
+
+#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferGet, 8);
+    NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferPut, 8);
+    NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferFull, 8);
+    NV_DECLARE_ALIGNED(NvP64 pHubIntr, 8);
+    NV_DECLARE_ALIGNED(NvP64 pHubIntrEnSet, 8);
+    NV_DECLARE_ALIGNED(NvP64 pHubIntrEnClear, 8);
+    NvU32 accessCntrMask;
+} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS;
+
+
+/*
+ * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_FULL_INFO
+ *
+ * This command gives information whether the buffer is full
+ *
+ *    fullFlag [OUT]
+ *       This parameter specifies whether the buffer is full
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_FULL_INFO (0xc3650107) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS {
+    NvBool fullFlag;
+} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS;
+
+
+/*
+ * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_RESET_COUNTERS
+ *
+ * This command resets access counters of specified type
+ *
+ *    resetFlag [OUT]
+ *       This parameter specifies that counters have been reset
+ *    counterType [IN]
+ *       This parameter specifies the type of counters that should be reset (MIMC, MOMC or ALL)  
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_RESET_COUNTERS (0xc3650108) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS {
+    NvBool resetFlag;
+    NvU32  counterType;
+} NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS;
+
+#define NVC365_CTRL_ACCESS_COUNTER_TYPE_MIMC   (0x0)
+#define NVC365_CTRL_ACCESS_COUNTER_TYPE_MOMC   (0x1)
+#define NVC365_CTRL_ACCESS_COUNTER_TYPE_ALL    (0x2)
+
+/*
+ * NVC365_CTRL_CMD_ACCESS_CNTR_SET_CONFIG
+ *
+ * This command configures the access counters
+ *
+ *    mimcGranularity [IN]
+ *       This parameter specifies the desired granularity for mimc (64K, 2M, 16M, 16G)
+ *    momcGranularity [IN]
+ *       This parameter specifies the desired granularity for momc (64K, 2M, 16M, 16G)
+ *    mimcLimit [IN]
+ *       This parameter specifies mimc limit (none, qtr, half, full)
+ *    momcLimit [IN]
+ *       This parameter specifies momc limit (none, qtr, half, full)
+ *    threshold [IN]
+ *       This parameter specifies the threshold
+ *    flag [IN]
+ *       This parameter is a bitmask denoting what configurations should be made
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NVC365_CTRL_CMD_ACCESS_CNTR_SET_CONFIG (0xc3650109) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS {
+    NvU32 mimcGranularity;
+    NvU32 momcGranularity;
+    NvU32 mimcLimit;
+    NvU32 momcLimit;
+    NvU32 threshold;
+    NvU32 cmd;
+} NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS;
+
+#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_64K      (0x0)
+#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_2M       (0x1)
+#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16M      (0x2)
+#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16G      (0x3)
+
+#define NVC365_CTRL_ACCESS_COUNTER_MIMC_LIMIT           (0x0)
+#define NVC365_CTRL_ACCESS_COUNTER_MOMC_LIMIT           (0x1)
+
+#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_NONE       (0x0)
+#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_QTR        (0x1)
+#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_HALF       (0x2)
+#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_FULL       (0x3)
+
+#define NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_GRANULARITY (0x1)
+#define NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_GRANULARITY (0x2)
+#define NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_LIMIT       (0x4)
+#define NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_LIMIT       (0x8)
+#define NVC365_CTRL_ACCESS_COUNTER_SET_THRESHOLD        (0x10)
+
+/*
+ * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE_INTR
+ *
+ * This command enables the access counters interrupts 
+ *
+ *    enable [OUT]
+ *       This parameter specifies that the access counters interrupts are enabled
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE_INTR  (0xc365010b) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS_MESSAGE_ID" */
+
+#define NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS {
+    NvBool enable;
+} NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS;
+/* _ctrlc365_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc369.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc369.h
new file mode 100644
index 0000000..135de33
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc369.h
@@ -0,0 +1,109 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc369.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* MMU_FAULT_BUFFER control commands and parameters */
+
+#define NVC369_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0xC369, NVC369_CTRL_##cat, idx)
+
+/* MMU_FAULT_BUFFER command categories (6bits) */
+#define NVC369_CTRL_RESERVED         (0x00)
+#define NVC369_CTRL_MMU_FAULT_BUFFER (0x01)
+
+/*
+ * NVC369_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVC369_CTRL_CMD_NULL         (0xc3690000) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+
+/*
+ * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUFFER
+ *
+ * This call creates and registers a client buffer for the non replayable faults
+ *
+ *    pShadowBuffer [OUT]
+ *       This parameter represents the pointer to the shadow buffer
+ *
+ *    pShadowBufferContext [OUT]
+ *       Execution context for pShadowBuffer queue
+ *
+ *    bufferSize [OUT]
+ *       Size in bytes of the shadow buffer for non replayable faults
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF (0xc3690101) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID" */
+
+#define NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8);
+    NV_DECLARE_ALIGNED(NvP64 pShadowBufferContext, 8);
+    NvU32 bufferSize;
+} NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS;
+
+
+/*
+ * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUFFER
+ *
+ * This call unregisters and destroys a client buffer for the non replayable
+ * faults
+ * 
+ *    pShadowBuffer [IN]
+ *       This parameter represents the pointer to the shadow buffer
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF (0xc3690102) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID" */
+
+#define NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8);
+} NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS;
+
+/* _ctrlc369_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc36f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc36f.h
new file mode 100644
index 0000000..ddfce20
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc36f.h
@@ -0,0 +1,275 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc36f.finn
+//
+
+
+
+
+/* VOLTA_CHANNEL_GPFIFO_A control commands and parameters */
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl906f.h"          /* C36F is partially derived from 906F */
+#include "ctrl/ctrla06f.h"          /* C36F is partially derived from a06F */
+#define NVC36F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0xC36F, NVC36F_CTRL_##cat, idx)
+
+/* VOLTA_CHANNEL_GPFIFO_A command categories (6bits) */
+#define NVC36F_CTRL_RESERVED (0x00)
+#define NVC36F_CTRL_GPFIFO   (0x01)
+#define NVC36F_CTRL_EVENT    (0x02)
+
+/*
+ * NVC36F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned is: NV_OK
+*/
+#define NVC36F_CTRL_CMD_NULL (0xc36f0000) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+
+
+
+/*
+ * NVC36F_CTRL_GET_CLASS_ENGINEID
+ *
+ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
+ *
+ */
+#define NVC36F_CTRL_GET_CLASS_ENGINEID (0xc36f0101) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
+
+typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
+    NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
+} NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
+
+
+
+/*
+ * NVC36F_CTRL_RESET_CHANNEL
+ *
+ * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
+ *
+ */
+#define NVC36F_CTRL_CMD_RESET_CHANNEL (0xc36f0102) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */
+
+typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
+    NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
+} NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
+
+
+
+/*
+ * NVC36F_CTRL_CMD_GPFIFO_SCHEDULE
+ *
+ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
+ *
+ */
+#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE (0xc36f0103) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */
+
+typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
+    NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS params;
+} NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
+
+
+
+/*
+ * NVC36F_CTRL_CMD_BIND
+ *
+ * Please see description of NVA06F_CTRL_CMD_BIND for more information.
+ */
+#define NVC36F_CTRL_CMD_BIND (0xc36f0104) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */
+
+typedef NVA06F_CTRL_BIND_PARAMS NVC36F_CTRL_BIND_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC36F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVC36F_CTRL_CMD_BIND_FINN_PARAMS {
+    NVC36F_CTRL_BIND_PARAMS params;
+} NVC36F_CTRL_CMD_BIND_FINN_PARAMS;
+
+
+
+/*
+ * NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
+*/
+#define NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc36f0205) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
+
+typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC36F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
+#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
+#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
+
+/*
+ * NVC36F_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
+ */
+#define NVC36F_CTRL_CMD_EVENT_SET_TRIGGER                 (0xc36f0206) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
+
+
+
+
+
+/*
+ * NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO
+ *
+ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
+ *
+ */
+#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc36f0107) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */
+
+typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
+} NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
+
+
+
+/*
+ * NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN
+ *
+ *    This command returns an opaque work submit token to the caller which
+ *    can be used to write to doorbell register to finish submitting work. If
+ *    the client has provided an error context handle during channel allocation,
+ *    and the error context is large enough to write the doorbell token, a
+ *    notification at index NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN
+ *    will be sent with the work submit token value. This index may be modified
+ *    by NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX.
+ *
+ *    workSubmitToken       The 32-bit work submit token
+ *
+ *    Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_OBJECT_HANDLE
+ *     NV_ERR_INVALID_ARGUMENT
+ *
+ */
+
+#define NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (0xc36f0108) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID" */
+
+#define NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS {
+    NvU32 workSubmitToken;
+} NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS;
+
+/**
+ * NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER
+ *
+ *    This command updates the HOST CE Fault method buffer
+ *    data structure of Virtual channel created for SR-IOV guest. It will also
+ *    update the fault method buffer address in the instance block of the channel
+ *
+ *    bar2Addr[]
+ *           Array contains the Virtual BAR2 address mapped by the Guest during channel
+ *           creation.
+ *    Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_INSUFFICIENT_RESOURCES
+ *
+ */
+#define NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES 0x2
+#define NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER        (0xc36f0109) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID" */
+
+#define NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 bar2Addr[NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES], 8);
+} NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS;
+
+/*
+ * NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX
+ *
+ *    This command updates the notifier index within the error context notifier
+ *    to write the doorbell token to. This interface cannot be used to cause the
+ *    token to overwrite the RC notification slot. The notification slot
+ *    referred to by the passed index must be within the bounds of the error
+ *    context notifier object. In the case that multiple channels share the same
+ *    error context, it is not illegal for the client to set the same index for
+ *    multiple channels (however it is not recommended).
+ *
+ *    [IN] index
+ *      Notification slot to write the doorbell token. The initial value of this
+ *      index is NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN.
+ *
+ *    Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_OBJECT_HANDLE
+ *     NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX (0xc36f010a) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID" */
+
+#define NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS {
+    NvU32 index;
+} NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS;
+
+/* _ctrlc36f.h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h
new file mode 100644
index 0000000..c132cc0
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h
@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc370/ctrlc370base.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NVC370_DISPLAY control commands and parameters */
+
+#define NVC370_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0XC370, NVC370_CTRL_##cat, idx)
+
+/* NVC370_DISPLAY command categories (6bits) */
+#define NVC370_CTRL_RESERVED (0x00)
+#define NVC370_CTRL_CHNCTL   (0x01)
+#define NVC370_CTRL_RG       (0x02)
+#define NVC370_CTRL_SEQ      (0x03)
+#define NVC370_CTRL_OR       (0x04)
+#define NVC370_CTRL_INST     (0x05)
+#define NVC370_CTRL_VERIF    (0x06)
+#define NVC370_CTRL_SYSTEM   (0x07)
+#define NVC370_CTRL_EVENT    (0x09)
+
+// This struct must be the first member of all C370 control calls
+typedef struct NVC370_CTRL_CMD_BASE_PARAMS {
+    NvU32 subdeviceIndex;
+} NVC370_CTRL_CMD_BASE_PARAMS;
+
+
+/*
+ * NVC370_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVC370_CTRL_CMD_NULL (0xc3700000) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+/* _ctrlc370base_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h
new file mode 100644
index 0000000..a231232
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h
@@ -0,0 +1,300 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc370/ctrlc370chnc.finn
+//
+
+#include "ctrl/ctrlc370/ctrlc370base.h"
+/* C370 is partially derived from 5070 */
+#include "ctrl/ctrl5070/ctrl5070chnc.h"
+
+
+
+
+#define NVC370_CTRL_CMD_CHANNEL_STATE_IDLE                              NVBIT(0)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT1                        NVBIT(2)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT2                        NVBIT(3)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_BUSY                              NVBIT(6)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC                           NVBIT(7)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO                     NVBIT(8)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT1                         NVBIT(11)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT2                         NVBIT(12)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_OPERATION                     NVBIT(13)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT1                       NVBIT(14)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT2                       NVBIT(15)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_OPERATION                   NVBIT(16)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_UNCONNECTED                       NVBIT(17)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_INIT1                             NVBIT(18)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_INIT2                             NVBIT(19)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1                         NVBIT(20)
+#define NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2                         NVBIT(21)
+
+#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE        1
+#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW      32
+#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM  32
+#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK   8
+#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR      8
+
+/*
+ * NVC370_CTRL_CMD_IDLE_CHANNEL
+ *
+ * This command tries to wait or forces the desired channel state.
+ *
+ *      channelClass
+ *          This field indicates the hw class number (0xC378 - 0xC37E).
+ *          It's defined in the h/w header (i.e. clc37d.h, etc.).
+ *
+ *      channelInstance
+ *          This field indicates which instance of the channelClass the cmd is
+ *          meant for. (zero-based)
+ *
+ *      desiredChannelStateMask
+ *          This field indicates the desired channel states. When more than
+ *          one bit is set, RM will return whenever it finds hardware on one
+ *          of the states in the bistmask.
+ *          Normal options are IDLE, QUIESCENT1 and QUIESCENT2.
+ *          Verif only option includes BUSY as well.
+ *          Note:
+ *              (1) When QUIESCENT1 or QUIESCENT2 is chosen only one bit should
+ *                  be set in the bitmask. RM will ignore any other state.
+ *              (2) Accelerators should not be required for QUIESCENT states as
+ *                  RM tries to ensure QUIESCENT forcibly on it's own.
+ *
+ *      accelerators
+ *          What accelerator bits should be used if RM timesout trying to
+ *          wait for the desired state. This is not yet implemented since it
+ *          should normally not be required to use these. Usage of accelerators
+ *          should be restricted and be done very carefully as they may have
+ *          undesirable effects.
+ *          NOTE: accelerators should not be used directly in production code.
+ *
+ *      timeout
+ *          Timeout to use when waiting for the desired state. This is also for
+ *          future expansion and not yet implemented.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_TIMEOUT
+ */
+#define NVC370_CTRL_CMD_IDLE_CHANNEL                     (0xc3700101) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID" */
+
+#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_CORE       NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE
+#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WINDOW     NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW
+#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM
+#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WRITEBACK  NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK
+#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_CURSOR     NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR
+
+#define NVC370_CTRL_IDLE_CHANNEL_STATE_IDLE                 NVC370_CTRL_CMD_CHANNEL_STATE_IDLE
+#define NVC370_CTRL_IDLE_CHANNEL_STATE_QUIESCENT1           NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT1
+#define NVC370_CTRL_IDLE_CHANNEL_STATE_QUIESCENT2           NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT2
+
+#define NVC370_CTRL_IDLE_CHANNEL_STATE_BUSY                 NVC370_CTRL_CMD_CHANNEL_STATE_BUSY
+
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_NONE               (0x00000000)
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI             (NVBIT(0))
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF            (NVBIT(1))
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA             (NVBIT(2))
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK      (NVBIT(3))
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK       (NVBIT(4))
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY            (NVBIT(5))
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT       (NVBIT(6))
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT        (NVBIT(7))
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP      (NVBIT(8))
+#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI            (NVBIT(9))
+
+#define NVC370_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVC370_CTRL_IDLE_CHANNEL_PARAMS {
+    NVC370_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       channelClass;
+    NvU32                       channelInstance;
+    NvU32                       desiredChannelStateMask;
+    NvU32                       accelerators;        // For future expansion. Not yet implemented
+    NvU32                       timeout;             // For future expansion. Not yet implemented
+    NvBool                      restoreDebugMode;
+} NVC370_CTRL_IDLE_CHANNEL_PARAMS;
+
+/*
+ * NVC370_CTRL_CMD_SET_ACCL
+ *
+ *   This command turns accelerators on and off. The use of this command
+ *   should be restricted as it may have undesirable effects. It's
+ *   purpose is to provide a mechanism for clients to use the
+ *   accelerator bits to get into states that are either not detectable
+ *   by the RM or may take longer to reach than we think is reasonable
+ *   to wait in the RM.
+ *
+ * NVC370_CTRL_CMD_GET_ACCL
+ *
+ *   This command queries the current state of the accelerators.
+ *
+ *      channelClass
+ *          This field indicates the hw class number (0xC378 - 0xC37E).
+ *          It's defined in the h/w header (i.e. clc37d.h, etc.).
+ *
+ *      channelInstance
+ *          This field indicates which instance of the channelClass the cmd is
+ *          meant for. (zero-based)
+ *
+ *      accelerators
+ *          Accelerators to be set in the SET_ACCEL command. Returns the
+ *          currently set accelerators on the GET_ACCEL command.
+ */
+
+
+/*
+ *
+ *      accelMask
+ *          A mask to specify which accelerators to change with the
+ *          SET_ACCEL command. This field does nothing in the GET_ACCEL
+ *          command.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_CHANNEL
+ *      NV_ERR_INVALID_OWNER
+ *      NV_ERR_GENERIC
+ *
+ */
+
+#define NVC370_CTRL_CMD_SET_ACCL                 (0xc3700102) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */
+
+#define NVC370_CTRL_CMD_GET_ACCL                 (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | 0x3" */
+
+#define NVC370_CTRL_ACCL_MAX_INSTANCE_CORE       NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE
+#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW     NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW
+#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM
+#define NVC370_CTRL_ACCL_MAX_INSTANCE_WRITEBACK  NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK
+#define NVC370_CTRL_ACCL_MAX_INSTANCE_CURSOR     NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR
+
+#define NVC370_CTRL_ACCL_NONE                    NVC370_CTRL_IDLE_CHANNEL_ACCL_NONE
+#define NVC370_CTRL_ACCL_IGNORE_PI                  NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI
+#define NVC370_CTRL_ACCL_SKIP_NOTIF                 NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF
+#define NVC370_CTRL_ACCL_SKIP_SEMA                  NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA
+#define NVC370_CTRL_ACCL_IGNORE_INTERLOCK           NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK
+#define NVC370_CTRL_ACCL_IGNORE_FLIPLOCK            NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK
+#define NVC370_CTRL_ACCL_TRASH_ONLY                 NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY
+#define NVC370_CTRL_ACCL_TRASH_AND_ABORT            NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT
+#define NVC370_CTRL_ACCL_SKIP_SYNCPOINT             NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT
+#define NVC370_CTRL_ACCL_IGNORE_TIMESTAMP           NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP
+#define NVC370_CTRL_ACCL_IGNORE_MGI                 NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI
+#define NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVC370_CTRL_SET_ACCL_PARAMS {
+    NVC370_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       channelClass;
+    NvU32                       channelInstance;
+    NvU32                       accelerators;
+    NvU32                       accelMask;
+} NVC370_CTRL_SET_ACCL_PARAMS;
+typedef NVC370_CTRL_SET_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS;
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS {
+    NVC370_CTRL_GET_ACCL_PARAMS params;
+} NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS;
+
+
+
+
+/*
+ * NVC370_CTRL_CMD_GET_CHANNEL_INFO
+ *
+ * This command returns the current channel state.
+ *
+ *      channelClass
+ *          This field indicates the hw class number (0xC378 - 0xC37E).
+ *          It's defined in the h/w header (i.e. clc37d.h, etc.).
+ *
+ *      channelInstance
+ *          This field indicates which instance of the channelClass the cmd is
+ *          meant for. (zero-based)
+ *
+ *      channelState
+ *          This field indicates the desired channel state in a mask form that
+ *          is compatible with NVC370_CTRL_CMD_IDLE_CHANNEL. A mask format
+ *          allows clients to check for one from a group of states.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_GENERIC
+ *
+ * Display driver uses this call to ensure that all it's methods have
+ * propagated through hardware's internal fifo
+ * (NVC370_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING) before it calls
+ * RM to check whether or not the mode it set up in Assembly State Cache will
+ * be possible. Note that display driver can not use completion notifier in
+ * this case because completion notifier is associated with Update and Update
+ * will propagate the state from Assembly to Armed and when checking the
+ * possibility of a mode, display driver wouldn't want Armed state to be
+ * affected.
+ */
+
+
+
+#define NVC370_CTRL_CMD_GET_CHANNEL_INFO                     (0xc3700104) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_CORE       NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE
+#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WINDOW     NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW
+#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM
+#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WRITEBACK  NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK
+#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_CURSOR     NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR
+
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE                 NVC370_CTRL_CMD_CHANNEL_STATE_IDLE
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_BUSY                 NVC370_CTRL_CMD_CHANNEL_STATE_BUSY
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC              NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC_LIMBO        NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_INIT1            NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT1
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_INIT2            NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT2
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_OPERATION        NVC370_CTRL_CMD_CHANNEL_STATE_EFI_OPERATION
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_INIT1          NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT1
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_INIT2          NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT2
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_OPERATION      NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_OPERATION
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_UNCONNECTED          NVC370_CTRL_CMD_CHANNEL_STATE_UNCONNECTED
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_INIT1                NVC370_CTRL_CMD_CHANNEL_STATE_INIT1
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_INIT2                NVC370_CTRL_CMD_CHANNEL_STATE_INIT2
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN1            NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN2            NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2
+#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING    NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE
+#define NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS {
+    NVC370_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       channelClass;
+    NvU32                       channelInstance;
+    NvBool                      IsChannelInDebugMode;
+    NvU32                       channelState;
+} NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS;
+
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h
new file mode 100644
index 0000000..ef18c7d
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h
@@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc370/ctrlc370event.finn
+//
+
+#include "ctrl/ctrlc370/ctrlc370base.h"
+/* C370 is partially derived from 5070 */
+#include "ctrl/ctrl5070/ctrl5070event.h"
+
+
+
+
+
+/* valid action values */
+#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
+#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
+#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
+
+/* _ctrlc370event_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h
new file mode 100644
index 0000000..2a49284
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h
@@ -0,0 +1,123 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc370/ctrlc370rg.finn
+//
+
+#include "ctrl/ctrlc370/ctrlc370base.h"
+/* C370 is partially derived from 5070 */
+#include "ctrl/ctrl5070/ctrl5070rg.h"
+
+
+
+
+/*
+ * NVC370_CTRL_CMD_GET_LOCKPINS_CAPS
+ *
+ * This command returns lockpins for the specified pinset,
+ * as well as lockpins' HW capabilities.
+ *
+ *   pinset [in]
+ *     This parameter takes the pinset whose corresponding
+ *     lockpin numbers need to be determined. This only affects
+ *     the return value for the RaterLock and FlipLock pins.
+ *
+ *   frameLockPin [out]
+ *     This parameter returns the FrameLock pin index.
+ *
+ *   rasterLockPin [out]
+ *     This parameter returns the RasterLock pin index.
+ *
+ *   flipLockPin [out]
+ *     This parameter returns the FlipLock pin index.
+ *
+ *   stereoPin [out]
+ *     This parameter returns the Stereo pin index.
+ *
+ *   numScanLockPins [out]
+ *     This parameter returns the HW capability of ScanLock pins.
+ *
+ *   numFlipLockPins [out]
+ *     This parameter returns the HW capability of FlipLock pins.
+ *
+ *   numStereoPins [out]
+ *     This parameter returns the HW capability of Stereo pins.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NVC370_CTRL_CMD_GET_LOCKPINS_CAPS                  (0xc3700201) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RG_INTERFACE_ID << 8) | NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NVC370_CTRL_GET_LOCKPINS_CAPS_FRAME_LOCK_PIN_NONE  (0xffffffff)
+#define NVC370_CTRL_GET_LOCKPINS_CAPS_RASTER_LOCK_PIN_NONE (0xffffffff)
+#define NVC370_CTRL_GET_LOCKPINS_CAPS_FLIP_LOCK_PIN_NONE   (0xffffffff)
+#define NVC370_CTRL_GET_LOCKPINS_CAPS_STEREO_PIN_NONE      (0xffffffff)
+#define NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS {
+    NVC370_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       pinset;
+    NvU32                       frameLockPin;
+    NvU32                       rasterLockPin;
+    NvU32                       flipLockPin;
+    NvU32                       stereoPin;
+    NvU32                       numScanLockPins;
+    NvU32                       numFlipLockPins;
+    NvU32                       numStereoPins;
+} NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS;
+
+/*
+ * NVC370_CTRL_CMD_SET_SWAPRDY_GPIO_WAR
+ *
+ * This command switches SWAP_READY_OUT GPIO between SW
+ * and HW control to WAR bug 200374184
+ *
+ *   bEnable [in]:
+ *     This parameter indicates enable/disable external fliplock
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_GENERIC
+ */
+
+#define NVC370_CTRL_CMD_SET_SWAPRDY_GPIO_WAR (0xc3700202) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RG_INTERFACE_ID << 8) | NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS_MESSAGE_ID" */
+
+#define NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS {
+    NVC370_CTRL_CMD_BASE_PARAMS base;
+    NvBool                      bEnable;
+} NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS;
+
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h
new file mode 100644
index 0000000..d891974
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h
@@ -0,0 +1,133 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc370/ctrlc370verif.finn
+//
+
+#include "ctrl/ctrlc370/ctrlc370base.h"
+/* C370 is partially derived from 5070 */
+#include "ctrl/ctrl5070/ctrl5070verif.h"
+
+
+
+
+#define NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES (0xc3700601) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID << 8) | NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID" */
+
+#define NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS {
+    NVC370_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       headInstance;
+    NvU32                       modesetValue;
+} NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS;
+
+/*
+ * NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES
+ *
+ * This command sets modeswitch flags, prior to a modeset.  The flags will be
+ * automatically cleared at the end of each modeset, so this function must be
+ * called for each modeset where overrides are desired.
+ *
+ *      headInstance
+ *          this field specifies the head for which modeswitch flags will be overridden
+ *
+ *      modesetMaskValid
+ *          this field specifies the maskset at which modeswitch flags will be overridden
+ *
+ *      modesetValue
+ *          this field specifies the override value
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES (0xc3700602) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID << 8) | NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID" */
+
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS {
+    NVC370_CTRL_CMD_BASE_PARAMS base;
+    NvU32                       headInstance;
+    NvU32                       modesetMaskValid;
+    NvU32                       modesetValue;
+} NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS;
+
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK                       0:0
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK_VALID              0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK_INVALID            0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK                     1:1
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_VALID            0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_INVALID          0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN                    2:2
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN_VALID           0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN_INVALID         0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN                  3:3
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN_VALID         0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN_INVALID       0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL                 4:4
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL_VALID        0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL_INVALID      0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL               5:5
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL_VALID      0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL_INVALID    0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP              6:6
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP_VALID     0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP_INVALID   0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN            7:7
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN_VALID   0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN_INVALID 0x00000000
+
+
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK                            0:0
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK_YES                     0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK_NO                      0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK                          1:1
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_YES                   0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_NO                    0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN                         2:2
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN_YES                  0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN_NO                   0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN                       3:3
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN_YES                0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN_NO                 0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL                      4:4
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL_YES               0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL_NO                0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL                    5:5
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL_YES             0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL_NO              0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP                   6:6
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP_YES            0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP_NO             0x00000000
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN                 7:7
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN_YES          0x00000001
+#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN_NO           0x00000000
+
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h
new file mode 100644
index 0000000..2d4aea5
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h
@@ -0,0 +1,61 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc372/ctrlc372base.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NVC372_DISPLAY_SW control commands and parameters */
+
+#define NVC372_CTRL_CMD(cat,idx)          NVXXXX_CTRL_CMD(0XC372, NVC372_CTRL_##cat, idx)
+
+/* NVC372_DISPLAY_SW command categories (6 bits) */
+#define NVC372_CTRL_RESERVED (0x00)
+#define NVC372_CTRL_CHNCTL   (0x01)
+#define NVC372_CTRL_VERIF    (0x02)
+
+/*
+ * NVC372_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVC372_CTRL_CMD_NULL (0xc3720000) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+// This struct must be the first member of all
+// C372 control calls
+typedef struct NVC372_CTRL_CMD_BASE_PARAMS {
+    NvU32 subdeviceIndex;
+} NVC372_CTRL_CMD_BASE_PARAMS;
+
+/* _ctrlc372base_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h
new file mode 100644
index 0000000..743663c
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h
@@ -0,0 +1,721 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc372/ctrlc372chnc.finn
+//
+
+#include "nvdisptypes.h"
+#include "ctrl/ctrlc372/ctrlc372base.h"
+
+#define NVC372_CTRL_MAX_POSSIBLE_HEADS   8
+#define NVC372_CTRL_MAX_POSSIBLE_WINDOWS 32
+
+#define NVC372_CTRL_CMD_IS_MODE_POSSIBLE (0xc3720101) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVC372_CTRL_CMD_IS_MODE_POSSIBLE
+ *
+ * This command tells whether or not the specified display config is possible.
+ * A config might not be possible if the display requirements exceed the GPU
+ * capabilities.  Display requirements will be higher with more display
+ * surfaces, higher resolutions, higher downscaling factors, etc.  GPU
+ * capabilities are determined by clock frequencies, the width of data pipes,
+ * amount of mempool available, number of thread groups available, etc.
+ *
+ * Inputs:
+ *   head.headIndex
+ *     This is the hardware index number for the head.  Only active heads
+ *     should be included in the input structure.
+ *
+ *   head.maxPixelClkKHz
+ *     This parameter specifies the pixel scanout rate (in KHz).
+ *
+ *   head.rasterSize
+ *     This structure specifies the total width and height of the raster that
+ *     is sent to the display.  (The width and height are also referred to as
+ *     HTotal and VTotal, respectively.)
+ *
+ *   head.rasterBlankStart
+ *     X specifies the pixel column where horizontal blanking begins;
+ *     Y specifies the pixel row where vertical blanking begins.
+ *
+ *   head.rasterBlankEnd
+ *     X specifies the pixel column where horizontal blanking ends;
+ *     Y specifies the pixel row where vertical blanking ends.
+ *
+ *   head.rasterVertBlank2
+ *     X and Y specify the pixel column/row where horizontal/vertical blanking
+ *     ends on the second field of every pair for an interlaced raster.  This
+ *     field is not used when the raster is progressive.
+ *
+ *   head.control.masterLockMode
+ *   head.control.masterLockPin
+ *   head.control.slaveLockMode
+ *   head.control.slaveLockPin
+ *     Heads that are raster locked or frame locked together will have
+ *     synchronized timing.  For example, vblank will occur at the same time on
+ *     all of the heads that are locked together.
+ *
+ *     "LockMode" tells if a head is raster locked, frame locked, or not locked.
+ *
+ *     "LockPin" tells which heads are in a group of locked heads.  There
+ *     should be one master per group, and all slave heads that are locked to
+ *     that master should have the same slaveLockPin number as the master's
+ *     masterLockPin number.
+ *
+ *     Note: The LockModes and LockPins are used only if the min v-pstate is
+ *     required (i.e., if NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE
+ *     is set).
+ * 
+ *   head.maxDownscaleFactorH
+ *   head.maxDownscaleFactorV
+ *     maxDownscaleFactorH and maxDownscaleFactorV represent the maximum amount
+ *     by which the the composited image can be reduced in size, horizontally
+ *     and vertically, respectively, multiplied by 0x400.  For example, if the
+ *     scaler input width is 1024, and the scaler output width is 2048, the
+ *     downscale factor would be 1024 / 2048 = 0.5, and multiplying by 0x400
+ *     would give 512.
+ *
+ *   head.outputScalerVerticalTaps
+ *     scalerVerticalTaps indicates the maximum number of vertical taps 
+ *     allowed in the output scaler.
+ * 
+ *     Note that there are no #defines for tap values; the parameter is simply
+ *     the number of taps (e.g., "2" for 2 taps).
+ *
+ *   head.bUpscalingAllowedV
+ *     bUpscalingAllowed indicates whether or not the composited image can be
+ *     increased in size, vertically.
+ * 
+ *   head.bOverfetchEnabled
+ *     bOverfetchEnabled indicates whether or not the vertical overfetch is 
+ *     enabled in postcomp scaler.
+ *
+ *   head.minFrameIdle.leadingRasterLines
+ *     leadingRasterLines defines the number of lines between the start of the
+ *     frame (vsync) and the start of the active region.  This includes Vsync,
+ *     Vertical Back Porch, and the top part of the overscan border.  The
+ *     minimum value is 2 because vsync and VBP must be at least 1 line each.
+ *
+ *   head.minFrameIdle.trailingRasterLines
+ *     trailingRasterLines defines the number of lines between the end of the
+ *     active region and the end of the frame.  This includes the bottom part
+ *     of the overscan border and the Vertical Front Porch.
+ *
+ *   head.lut
+ *     This parameter specifies whether or not the output LUT is enabled, and
+ *     the size of the LUT.  The parameter should be an
+ *     NVC372_CTRL_IMP_LUT_USAGE_xxx value.
+ *
+ *   head.cursorSize32p
+ *     This parameter specifies the width of the cursor, in units of 32 pixels.
+ *     So, for example, "8" would mean 8 * 32 = 256, for a 256x256 cursor.  Zero
+ *     means the cursor is disabled.
+ *
+ *   head.bEnableDsc
+ *     bEnableDsc indicates whether or not DSC is enabled
+ *
+ *   head.bYUV420Format
+ *     This parameter indicates output format is YUV420.
+ *     Refer to NVD_YUV420_Output_Functional_Description.docx for more details.
+ *
+ *   head.bIs2Head1Or
+ *     This parameter specifies if the head operates in 2Head1Or mode.
+ *     Refer to NVD_2_Heads_Driving_1_OR_Functional_Description.docx for more details.
+ * 
+ *   head.bGetOSLDOutput
+ *     This parameter specifies if the client requires output for the OSLD 
+ *     (One Shot Mode with Stall Lock Disabled) mode along with legacy outputs.
+ * 
+ *   head.bDisableMidFrameAndDWCFWatermark
+ *     WAR for bug 200508242. 
+ *     In linux it is possible that there will be no fullscreen window visible 
+ *     for a head. For these cases we would not hit dwcf or midframe watermarks 
+ *     leading to fbflcn timing out waiting on ok_to_switch and forcing mclk 
+ *     switch. This could lead to underflows. So if that scenario is caught (by
+ *     Display Driver) bDisableMidFrameAndDWCFWatermark will be set to true and 
+ *     IMP will exclude dwcf and midframe contribution from the "is mclk switch 
+ *     guaranteed" calculation for the bandwidth clients of that head.
+ *
+ *   window.windowIndex
+ *     This is the hardware index number for the window.  Only active windows
+ *     should be included in the input structure.
+ *
+ *   window.owningHead
+ *     This is the hardware index of the head that will receive the window's
+ *     output.
+ * 
+ *   window.formatUsageBound
+ *     This parameter is a bitmask of all possible non-rotated mode data
+ *     formats (NVC372_CTRL_FORMAT_xxx values).
+ *
+ *   window.rotatedFormatUsageBound
+ *     This parameter is a bitmask of all possible rotated mode data formats
+ *     (NVC372_CTRL_FORMAT_xxx values).
+ *
+ *   window.maxPixelsFetchedPerLine
+ *     This parameter defines the maximum number of pixels that may need to be
+ *     fetched in a single line for this window.  Often, this can be set to the
+ *     viewportSizeIn.Width.  But if the window is known to be clipped, such
+ *     that an entire line will never be fetched, then this parameter can be
+ *     set to the clipped size (to improve the chances of the mode being
+ *     possible, or possible at a lower v-pstate).
+ * 
+ *     In some cases, the value of this parameter must be increased by a few
+ *     pixels in order to account for scaling overfetch, input chroma overfetch
+ *     (420/422->444), and/or chroma output low pass filter overfetch
+ *     (444->422/420).  This value is chip dependent; refer to the
+ *     MaxPixelsFetchedPerLine parameter in nvdClass_01.mfs for the exact
+ *     value.  In no case does the maxPixelsFetchedPerLine value need to exceed
+ *     the surface width.
+ *
+ *   window.maxDownscaleFactorH
+ *   window.maxDownscaleFactorV
+ *     maxDownscaleFactorH and maxDownscaleFactorV represent the maximum amount
+ *     by which the the window image can be reduced in size, horizontally and
+ *     vertically, respectively, multiplied by 
+ *     NVC372_CTRL_SCALING_FACTOR_MULTIPLIER. For example,
+ *     if the scaler input width is 1024, and the scaler output width is 2048,
+ *     the downscale factor would be 1024 / 2048 = 0.5, and multiplying by 
+ *     NVC372_CTRL_SCALING_FACTOR_MULTIPLIER if 0x400 would give 512.
+ *
+ *   window.inputScalerVerticalTaps
+ *     scalerVerticalTaps indicates the maximum number of vertical taps 
+ *     allowed in the input scaler.
+ *
+ *     Note that there are no #defines for tap values; the parameter is simply
+ *     the number of taps (e.g., "2" for 2 taps).
+ *
+ *   window.bUpscalingAllowedV
+ *     bUpscalingAllowed indicates whether or not the composited image can be
+ *     increased in size, vertically.
+ *
+ *   window.bOverfetchEnabled
+ *     bOverfetchEnabled indicates whether or not the vertical overfetch is 
+ *     enabled in precomp scaler.
+ *
+ *   window.lut
+ *     This parameter specifies whether or not the input LUT is enabled, and
+ *     the size of the LUT.  The parameter should be an
+ *     NVC372_CTRL_IMP_LUT_USAGE_xxx value.
+ *
+ *   window.tmoLut
+ *     This parameter specifies whether or not the tmo LUT is enabled, and
+ *     the size of the LUT. This lut is used for HDR.  The parameter should be
+ *     an NVC372_CTRL_IMP_LUT_USAGE_xxx value.
+ *
+ *   numHeads
+ *     This is the number of heads in the "head" array of the
+ *     NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS struct.  Only active heads should be
+ *     included in the struct.
+ *
+ *   numWindows
+ *     This is the number of windows in the "window" array of the
+ *     NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS struct.  Only active windows should
+ *     be included in the struct.
+ *
+ *   options
+ *     This parameter specifies a bitmask for options.
+ *
+ *       NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN
+ *         tells IMP to calculate worstCaseMargin and worstCaseDomain.
+ *       NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE
+ *         tells IMP to calculate and report the minimum v-pstate at which the
+ *         mode is possible.
+ *
+ *   bUseCachedPerfState
+ *     Indicates that RM should use cached values for the fastest
+ *     available perf level (v-pstate for PStates 3.0 or pstate for
+ *     PStates 2.0) and dispclk.  This feature allows the query call to
+ *     execute faster, and is intended to be used, for example, during
+ *     mode enumeration, when many IMP query calls are made in close
+ *     succession, and perf conditions are not expected to change between
+ *     query calls.  When IMP has not been queried recently, it is
+ *     recommended to NOT use cached values, in case perf conditions have
+ *     changed and the cached values no longer reflect the current
+ *     conditions.
+ *
+ *   testMclkFreqKHz
+ *     This is the mclk frequency specified by the client, in KHz.  RM will 
+ *     use this value to compare with the minimum dramclk required by the 
+ *     given mode.  The parameter will have value 0 if the client doesn't want 
+ *     IMP query to consider this. This input is valid only on Tegra and only
+ *     for verification purposes on internal builds.
+ *     For this input to work, client must set 
+ *     NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE in the
+ *     "options" field.
+ *
+ * Outputs:
+ *   bIsPossible
+ *     This output tells if the specified mode can be supported.  To know if 
+ *     the mode is possible with OSLD, the bIsOSLDPossible result must 
+ *     be checked.
+ *
+ *   bIsOSLDPossible
+ *     This output is returned for each head and suggests to the clients
+ *     if the mode will be possible or not on that head when OSLD is enabled. 
+ *     The output is only valid if bGetOSLDOutput is set in the head input.
+ *     Note that with OSLD output, RM will also return the legacy output
+ *     values.
+ *    
+ *   minImpVPState
+ *     minImpVPState returns the minimum v-pstate at which the mode is possible
+ *     (assuming bIsPossible is TRUE).  This output is valid only on dGPU, and
+ *     only if NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in
+ *     the "options" field.
+ *
+ *     If the minimum v-pstate is required for a multi-head config, then
+ *     masterLockMode, masterLockPin, slaveLockMode, and slaveLockPin must all
+ *     be initialized.
+ *   minPState
+ *     minPState returns the pstate value corresponding to minImpVPState.  It
+ *     is returned as the numeric value of the pstate (P0 -> 0, P1 -> 1, etc.).
+ *     This output is valid only on dGPU, and only if
+ *     NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set
+ *     in the "options" field.
+ *
+ *     Note that the pstate returned by minPstateForGlitchless is not
+ *     necessarily sufficient to meet IMP requirements.  The pstate corresponds
+ *     to the vpstate returned by minImpVPState, and this vpstate represents
+ *     clocks that are sufficient for IMP requirements, but the pstate
+ *     typically covers a range of frequencies (depending on the clock), and it
+ *     is possible that only part of the range is sufficient for IMP.
+ *
+ *   minRequiredBandwidthKBPS
+ *     minRequiredBandwidthKBPS returns the minimum bandwidth that must be
+ *     allocated to display in order to make the mode possible (assuming
+ *     bIsPossible is TRUE).  This output is valid only on Tegra, and only if
+ *     NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the
+ *     "options" field.
+ * 
+ *   floorBandwidthKBPS
+ *     floorBandwidthKBPS returns the minimum mclk frequency that can support
+ *     the mode, and allow glitchless mclk switch, multiplied by the width of
+ *     the data pipe.  (This is an approximation of the bandwidth that can be
+ *     provided by the min required mclk frequency, ignoring overhead.)  If the
+ *     mode is possible, but glitchless mclk switch is not, floorBandwidthKBPS
+ *     will be calculated based on the maximum possible mclk frequency.  This
+ *     output is valid only on Tegra, and only if
+ *     NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the
+ *     "options" field.
+ *
+ *   minRequiredHubclkKHz
+ *     minRequiredHubclkKHz returns the minimum hubclk frequency that can 
+ *     support the mode.  This output is valid only on Tegra, and only if 
+ *     NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the
+ *     "options" field.
+ *
+ *   vblankIncreaseInLinesForOSLDMode
+ *     vblankIncreaseInLinesForOSLDMode returns the amount, in lines, by 
+ *     which vblank needs to be extended to achieve optimized MSCG when OSLD 
+ *     Mode is enabled (assuming bIsPossible is TRUE). Features like Panel
+ *     Replay and Panel Self Refresh enable OSLD mode. This value is 0 if 
+ *     the vblank is large enough to accommodate spool up and MSCG latencies.
+ *     This output is valid only if 
+ *     NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the
+ *     "options" field and bGetOSLDOutput was specified in the head input.
+ *
+ *   wakeUpRgLineForOSLDMode
+ *     wakeUpRgLineForOSLDMode returns the rg line in the vblank region at which 
+ *     the clients will be required to send a timestamped update to achieve
+ *     optimized MSCG when OSLD Mode is enabled (assuming bIsPossible is 
+ *     is TRUE).  Features like Panel Replay and Panel Self Refresh enable 
+ *     OSLD mode. This output is valid only if 
+ *     NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the
+ *     "options" field and bGetOSLDOutput was specified in the head input.
+ * 
+ *   worstCaseMargin
+ *     worstCaseMargin returns the ratio of available bandwidth to required
+ *     bandwidth, multiplied by NV5070_CTRL_IMP_MARGIN_MULTIPLIER.  Available
+ *     bandwidth is calculated in the worst case bandwidth domain, i.e., the
+ *     domain with the least available margin.  Bandwidth domains include the
+ *     IMP-relevant clock domains, and possibly other virtual bandwidth
+ *     domains such as AWP.
+ *
+ *     Note that IMP checks additional parameters besides the bandwidth margins
+ *     but only the bandwidth margin is reported here, so it is possible for a
+ *     mode to have a more restrictive domain that is not reflected in the
+ *     reported margin result.
+ *
+ *     This result is not guaranteed to be valid if the mode is not possible.
+ *
+ *     Note also that the result is generally calculated for the highest
+ *     v-pstate possible (usually P0).  But if the _NEED_MIN_VPSTATE is
+ *     specified, the result will be calculated for the min possible v-pstate
+ *     (or the highest possible v-pstate, if the mode is not possible).
+ * 
+ *     The result is valid only if
+ *     NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN is set in "options".
+ *
+ *   dispClkKHz
+ *     This is the dispclk frequency selected by IMP for this mode. For dGPU,
+ *     it will be one of the fixed frequencies from the list of frequencies 
+ *     supported by the vbios.
+ *
+ *   worstCaseDomain
+ *     Returns a short text string naming the domain for the margin returned in
+ *     "worstCaseMargin".  See "worstCaseMargin" for more information.
+ *
+ * Possible status values returned are:
+ *     NVOS_STATUS_SUCCESS
+ *     NVOS_STATUS_ERROR_GENERIC
+ */
+#define NVC372_CTRL_IMP_LUT_USAGE_NONE   0
+#define NVC372_CTRL_IMP_LUT_USAGE_257    1
+#define NVC372_CTRL_IMP_LUT_USAGE_1025   2
+
+typedef struct NVC372_CTRL_IMP_HEAD {
+    NvU8  headIndex;
+
+    NvU32 maxPixelClkKHz;
+
+    struct {
+        NvU32 width;
+        NvU32 height;
+    } rasterSize;
+
+    struct {
+        NvU32 X;
+        NvU32 Y;
+    } rasterBlankStart;
+
+    struct {
+        NvU32 X;
+        NvU32 Y;
+    } rasterBlankEnd;
+
+    struct {
+        NvU32 yStart;
+        NvU32 yEnd;
+    } rasterVertBlank2;
+
+    struct {
+        NV_DISP_LOCK_MODE masterLockMode;
+        NV_DISP_LOCK_PIN  masterLockPin;
+        NV_DISP_LOCK_MODE slaveLockMode;
+        NV_DISP_LOCK_PIN  slaveLockPin;
+    } control;
+
+    NvU32  maxDownscaleFactorH;
+    NvU32  maxDownscaleFactorV;
+    NvU8   outputScalerVerticalTaps;
+    NvBool bUpscalingAllowedV;
+    NvBool bOverfetchEnabled;
+
+    struct {
+        NvU16 leadingRasterLines;
+        NvU16 trailingRasterLines;
+    } minFrameIdle;
+
+    NvU8   lut;
+    NvU8   cursorSize32p;
+
+    NvBool bEnableDsc;
+
+    NvBool bYUV420Format;
+
+    NvBool bIs2Head1Or;
+
+    NvBool bGetOSLDOutput;
+
+    NvBool bDisableMidFrameAndDWCFWatermark;
+} NVC372_CTRL_IMP_HEAD;
+typedef struct NVC372_CTRL_IMP_HEAD *PNVC372_CTRL_IMP_HEAD;
+
+typedef struct NVC372_CTRL_IMP_WINDOW {
+    NvU32  windowIndex;
+    NvU32  owningHead;
+    NvU32  formatUsageBound;
+    NvU32  rotatedFormatUsageBound;
+    NvU32  maxPixelsFetchedPerLine;
+    NvU32  maxDownscaleFactorH;
+    NvU32  maxDownscaleFactorV;
+    NvU8   inputScalerVerticalTaps;
+    NvBool bUpscalingAllowedV;
+    NvBool bOverfetchEnabled;
+    NvU8   lut;
+    NvU8   tmoLut;
+} NVC372_CTRL_IMP_WINDOW;
+typedef struct NVC372_CTRL_IMP_WINDOW *PNVC372_CTRL_IMP_WINDOW;
+
+#define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN       (0x00000001)
+#define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE (0x00000002)
+
+#define NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS {
+    NVC372_CTRL_CMD_BASE_PARAMS base;
+
+    NvU8                        numHeads;
+    NvU8                        numWindows;
+
+    NVC372_CTRL_IMP_HEAD        head[NVC372_CTRL_MAX_POSSIBLE_HEADS];
+
+    // C form: NVC372_CTRL_IMP_WINDOW window[NVC372_CTRL_MAX_POSSIBLE_WINDOWS];
+    NVC372_CTRL_IMP_WINDOW      window[NVC372_CTRL_MAX_POSSIBLE_WINDOWS];
+
+    NvU32                       options;
+
+    NvU32                       testMclkFreqKHz;
+
+    NvBool                      bIsPossible;
+
+    NvBool                      bIsOSLDPossible[NVC372_CTRL_MAX_POSSIBLE_HEADS];
+
+    NvU32                       minImpVPState;
+
+    NvU32                       minPState;
+
+    NvU32                       minRequiredBandwidthKBPS;
+
+    NvU32                       floorBandwidthKBPS;
+
+    NvU32                       minRequiredHubclkKHz;
+
+    NvU32                       vblankIncreaseInLinesForOSLDMode[NVC372_CTRL_MAX_POSSIBLE_HEADS];
+
+    NvU32                       wakeUpRgLineForOSLDMode[NVC372_CTRL_MAX_POSSIBLE_HEADS];
+
+    NvU32                       worstCaseMargin;
+
+    NvU32                       dispClkKHz;
+
+    char                        worstCaseDomain[8];
+
+    NvBool                      bUseCachedPerfState;
+} NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS;
+typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS *PNVC372_CTRL_IS_MODE_POSSIBLE_PARAMS;
+
+/* valid format values */
+#define NVC372_CTRL_FORMAT_RGB_PACKED_1_BPP                           (0x00000001)
+#define NVC372_CTRL_FORMAT_RGB_PACKED_2_BPP                           (0x00000002)
+#define NVC372_CTRL_FORMAT_RGB_PACKED_4_BPP                           (0x00000004)
+#define NVC372_CTRL_FORMAT_RGB_PACKED_8_BPP                           (0x00000008)
+#define NVC372_CTRL_FORMAT_YUV_PACKED_422                             (0x00000010)
+#define NVC372_CTRL_FORMAT_YUV_PLANAR_420                             (0x00000020)
+#define NVC372_CTRL_FORMAT_YUV_PLANAR_444                             (0x00000040)
+#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_420                        (0x00000080)
+#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_422                        (0x00000100)
+#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_422R                       (0x00000200)
+#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_444                        (0x00000400)
+#define NVC372_CTRL_FORMAT_EXT_YUV_PLANAR_420                         (0x00000800)
+#define NVC372_CTRL_FORMAT_EXT_YUV_PLANAR_444                         (0x00001000)
+#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_420                    (0x00002000)
+#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_422                    (0x00004000)
+#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_422R                   (0x00008000)
+#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_444                    (0x00010000)
+
+/* valid impResult values */
+#define NVC372_CTRL_IMP_MODE_POSSIBLE                                 0
+#define NVC372_CTRL_IMP_NOT_ENOUGH_MEMPOOL                            1
+#define NVC372_CTRL_IMP_REQ_LIMIT_TOO_HIGH                            2
+#define NVC372_CTRL_IMP_VBLANK_TOO_SMALL                              3
+#define NVC372_CTRL_IMP_HUBCLK_TOO_LOW                                4
+#define NVC372_CTRL_IMP_INSUFFICIENT_BANDWIDTH                        5
+#define NVC372_CTRL_IMP_DISPCLK_TOO_LOW                               6
+#define NVC372_CTRL_IMP_ELV_START_TOO_HIGH                            7
+#define NVC372_CTRL_IMP_OSLD_ELV_START_TOO_HIGH                       8
+#define NVC372_CTRL_IMP_INSUFFICIENT_THREAD_GROUPS                    9
+#define NVC372_CTRL_IMP_INVALID_PARAMETER                             10
+#define NVC372_CTRL_IMP_UNRECOGNIZED_FORMAT                           11
+#define NVC372_CTRL_IMP_UNSPECIFIED                                   12
+
+/*
+ * The calculated margin is multiplied by a constant, so that it can be
+ * represented as an integer with reasonable precision.  "0x400" was chosen
+ * because it is a power of two, which might allow some compilers/CPUs to
+ * simplify the calculation by doing a shift instead of a multiply/divide.
+ * (And 0x400 is 1024, which is close to 1000, so that may simplify visual
+ * interpretation of the raw margin value.)
+ */
+#define NVC372_CTRL_IMP_MARGIN_MULTIPLIER                             (0x00000400)
+
+/* scaling factor */
+#define NVC372_CTRL_SCALING_FACTOR_MULTIPLIER                         (0x00000400)
+
+#define NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD                2
+#define NVC372_CTRL_CMD_MAX_SORS                                      4
+
+#define NVC372_CTRL_CMD_IS_MODE_POSSIBLE_OR_SETTINGS                  (0xc3720102) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS_MESSAGE_ID" */
+
+/* 
+ * NVC372_CTRL_CMD_IS_MODE_POSSIBLE_OR_SETTINGS
+ *
+ * This command tells us if output resource pixel clocks requested by client
+ * is possible or not. Note that this will not be used for displayport sor as 
+ * it will be handled by displayport library.
+ * 
+ * Inputs: 
+ *   numHeads
+ *     This is the number of heads in the "head" array of the
+ *     NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS struct.  Only active heads 
+ *     should be included in the struct.
+ *
+ *   head.headIndex
+ *     This is the hardware index number for the head.  Only an active head
+ *     should be included in the input structure.
+ *
+ *   head.maxPixelClkKHz
+ *     This parameter specifies the pixel scanout rate (in KHz).
+ *
+ *   head.displayId
+ *     Array of displayId's associated with the head. This is limited by
+ *     NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD.
+ *
+ *   sor.ownerMask
+ *     Consists of a mask of all heads that drive this sor.
+ *
+ *   sor.protocol
+ *     Defines the protocol of the sor in question.
+ *
+ *   sor.pixelReplicateMode
+ *     Defines which pixel replication mode is requested. This can be off
+ *     or X2 or X4 mode.
+ *
+ * Outputs:
+ *   bIsPossible
+ *     This tells us that the requested pixel clock can be supported.
+ */
+
+
+#define NVC372_CTRL_IS_MODE_POSSIBLE_DISPLAY_ID_SKIP_IMP_OUTPUT_CHECK (0xAAAAAAAA)
+
+typedef struct NVC372_CTRL_IMP_OR_SETTINGS_HEAD {
+    NvU8                               headIndex;
+    NvU32                              maxPixelClkKhz;
+
+    NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP outputResourcePixelDepthBPP;
+
+    NvU32                              displayId[NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD];
+} NVC372_CTRL_IMP_OR_SETTINGS_HEAD;
+typedef struct NVC372_CTRL_IMP_OR_SETTINGS_HEAD *PNVC372_CTRL_IMP_OR_SETTINGS_HEAD;
+
+#define NVC372_CTRL_CMD_SOR_OWNER_MASK_NONE                   (0x00000000)
+#define NVC372_CTRL_CMD_SOR_OWNER_MASK_HEAD(i)                          (1 << i)
+
+#define NVC372_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_A            (0x00000000)
+#define NVC372_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_B            (0x00000001)
+#define NVC372_CTRL_CMD_SOR_PROTOCOL_DUAL_TMDS                (0x00000002)
+#define NVC372_CTRL_CMD_SOR_PROTOCOL_SUPPORTED                (0xFFFFFFFF)
+
+#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_OFF (0x00000000)
+#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X2  (0x00000001)
+#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X4  (0x00000002)
+
+typedef struct NVC372_CTRL_IMP_OR_SETTINGS_SOR {
+    NvU32 ownerMask;
+    NvU32 protocol;
+    NvU32 pixelReplicateMode;
+} NVC372_CTRL_IMP_OR_SETTINGS_SOR;
+typedef struct NVC372_CTRL_IMP_OR_SETTINGS_SOR *PNVC372_CTRL_IMP_OR_SETTINGS_SOR;
+
+#define NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS {
+    NVC372_CTRL_CMD_BASE_PARAMS      base;
+
+    NvU32                            numHeads;
+
+    NVC372_CTRL_IMP_OR_SETTINGS_HEAD head[NVC372_CTRL_MAX_POSSIBLE_HEADS];
+
+    NVC372_CTRL_IMP_OR_SETTINGS_SOR  sor[NVC372_CTRL_CMD_MAX_SORS];
+
+    NvBool                           bIsPossible;
+} NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS;
+typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS *PNVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS;
+
+#define NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE (0xc3720103) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE
+ *
+ * This control call is used by clients to inform RM about video adaptive refresh rate enable/disable.
+ * Based on the state, RM will enable/disable supported low power features.
+ *
+ * Inputs:
+ *   displayID
+ *      displayId of panel on which video adaptive refresh rate is enabled/disabled.
+ *
+ *   bEnable
+ *      NV_TRUE to enable video adaptive refresh rate mode.
+ *      NV_FALSE to disable video adaptive refresh rate mode.
+ *
+ * Outputs:
+ *   Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_NOT_SUPPORTED
+ */
+
+#define NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS {
+    NvU32  displayID;
+    NvBool bEnable;
+} NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS;
+typedef struct NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS *PNVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS;
+
+
+#define NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN (0xc3720104) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN
+ *
+ * This control call is used by clients to query the active viewport for the
+ * provided window precalculated at the beginning of each frame.
+ *
+ * Inputs:
+ *   windowIndex
+ *      Index of the window to be queried.  Must be connected to an active head.
+ *
+ * Outputs:
+ *   activeViewportPointIn
+ *      X and Y coordinates of the active viewport on the provided window for
+ *      the most recent frame.
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT if the window index is invalid
+ *      NV_ERR_INVALID_STATE if the window index isn't connected to a head
+ *      NV_ERR_NOT_SUPPORTED
+ */
+#define NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS {
+    NVC372_CTRL_CMD_BASE_PARAMS base;
+
+    NvU32                       windowIndex;
+
+    struct {
+        NvU32 x;
+        NvU32 y;
+    } activeViewportPointIn;
+} NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS;
+typedef struct NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS *PNVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS;
+
+/* _ctrlc372chnc_h_ */
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc46f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc46f.h
new file mode 100644
index 0000000..c53e217
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc46f.h
@@ -0,0 +1,162 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc46f.finn
+//
+
+
+
+
+/* TURING_CHANNEL_GPFIFO_A control commands and parameters */
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl906f.h"          /* C36F is partially derived from 906F */
+#include "ctrl/ctrla06f.h"          /* C36F is partially derived from a06F */
+#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
+
+#define NVC46F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0xC36F, NVC46F_CTRL_##cat, idx)
+
+/* TURING_CHANNEL_GPFIFO_A command categories (6bits) */
+#define NVC46F_CTRL_RESERVED (0x00)
+#define NVC46F_CTRL_GPFIFO   (0x01)
+#define NVC46F_CTRL_EVENT    (0x02)
+
+/*
+ * NVC46F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned is: NV_OK
+*/
+#define NVC46F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)
+
+
+
+
+
+
+/*
+ * NVC46F_CTRL_GET_CLASS_ENGINEID
+ *
+ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
+ *
+ */
+#define NVC46F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID)
+
+typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC46F_CTRL_GET_CLASS_ENGINEID_PARAMS;
+
+/*
+ * NVC46F_CTRL_RESET_CHANNEL
+ *
+ * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
+ *
+ */
+#define NVC46F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL)
+
+typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC46F_CTRL_CMD_RESET_CHANNEL_PARAMS;
+
+/*
+ * NVC46F_CTRL_CMD_GPFIFO_SCHEDULE
+ *
+ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
+ *
+ */
+#define NVC46F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE)
+
+typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC46F_CTRL_GPFIFO_SCHEDULE_PARAMS;
+
+/*
+ * NVC46F_CTRL_CMD_BIND
+ *
+ * Please see description of NVA06F_CTRL_CMD_BIND for more information.
+ */
+#define NVC46F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND)
+
+typedef NVA06F_CTRL_BIND_PARAMS NVC46F_CTRL_BIND_PARAMS;
+
+/*
+ * NVC46F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
+*/
+#define NVC46F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION)
+
+typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC46F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
+#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
+#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
+
+/*
+ * NVC46F_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
+ */
+#define NVC46F_CTRL_CMD_EVENT_SET_TRIGGER                 (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER)
+
+
+
+
+
+/*
+ * NVC46F_CTRL_CMD_GET_MMU_FAULT_INFO
+ *
+ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
+ *
+ */
+#define NVC46F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO)
+
+typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC46F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
+
+/*
+ * NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN
+ *
+ *    This command returns an opaque work submit token to the caller which
+ *    can be used to write to doorbell register to finish submitting work.
+ *
+ *    workSubmitToken       The 32-bit work submit token
+ *
+ *    Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_OBJECT_HANDLE
+ *     NV_ERR_INVALID_ARGUMENT
+ *
+ */
+
+#define NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN)
+
+typedef struct NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS {
+    NvU32 workSubmitToken;
+} NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS;
+
+/* _ctrlc46f.h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc56f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc56f.h
new file mode 100644
index 0000000..a781b1a
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc56f.h
@@ -0,0 +1,166 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc56f.finn
+//
+
+
+
+
+/* AMPERE_CHANNEL_GPFIFO_A control commands and parameters */
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl906f.h"          /* C36F is partially derived from 906F */
+#include "ctrl/ctrla06f.h"          /* C36F is partially derived from a06F */
+#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
+
+
+
+#define NVC56F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0xC36F, NVC56F_CTRL_##cat, idx)
+
+/* AMPERE_CHANNEL_GPFIFO_A command categories (6bits) */
+#define NVC56F_CTRL_RESERVED (0x00)
+#define NVC56F_CTRL_GPFIFO   (0x01)
+#define NVC56F_CTRL_EVENT    (0x02)
+
+/*
+ * NVC56F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned is: NV_OK
+*/
+#define NVC56F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)
+
+
+
+
+
+
+/*
+ * NVC56F_CTRL_GET_CLASS_ENGINEID
+ *
+ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
+ *
+ */
+#define NVC56F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID)
+
+typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC56F_CTRL_GET_CLASS_ENGINEID_PARAMS;
+
+/*
+ * NVC56F_CTRL_RESET_CHANNEL
+ *
+ * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
+ *
+ */
+#define NVC56F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL)
+
+typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC56F_CTRL_CMD_RESET_CHANNEL_PARAMS;
+
+/*
+ * NVC56F_CTRL_CMD_GPFIFO_SCHEDULE
+ *
+ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
+ *
+ */
+#define NVC56F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE)
+
+typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC56F_CTRL_GPFIFO_SCHEDULE_PARAMS;
+
+/*
+ * NVC56F_CTRL_CMD_BIND
+ *
+ * Please see description of NVA06F_CTRL_CMD_BIND for more information.
+ */
+#define NVC56F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND)
+
+typedef NVA06F_CTRL_BIND_PARAMS NVC56F_CTRL_BIND_PARAMS;
+
+/*
+ * NVC56F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
+*/
+#define NVC56F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION)
+
+typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC56F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
+#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
+#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
+
+/*
+ * NVC56F_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
+ */
+#define NVC56F_CTRL_CMD_EVENT_SET_TRIGGER                 (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER)
+
+
+
+
+
+/*
+ * NVC56F_CTRL_CMD_GET_MMU_FAULT_INFO
+ *
+ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
+ *
+ */
+#define NVC56F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO)
+
+typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC56F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
+
+/*
+ * NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN
+ *
+ *    This command returns an opaque work submit token to the caller which
+ *    can be used to write to doorbell register to finish submitting work.
+ *
+ *    workSubmitToken       The 32-bit work submit token
+ *
+ *    Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_OBJECT_HANDLE
+ *     NV_ERR_INVALID_ARGUMENT
+ *
+ */
+
+#define NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN)
+
+typedef struct NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS {
+    NvU32 workSubmitToken;
+} NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS;
+
+
+
+/* _ctrlc56f.h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc637.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc637.h
new file mode 100644
index 0000000..155d639
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc637.h
@@ -0,0 +1,392 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc637.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* AMPERE_SMC_PARTITION_REF commands and parameters */
+
+#define NVC637_CTRL_CMD(cat,idx)             NVXXXX_CTRL_CMD(0xC637, NVC637_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NVC637_CTRL_RESERVED        (0x00)
+#define NVC637_CTRL_EXEC_PARTITIONS (0x01)
+
+
+/*!
+ * NVC637_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVC637_CTRL_CMD_NULL        (0xc6370000) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/*!
+ * NVC637_CTRL_EXEC_PARTITIONS_INFO
+ *
+ * This structure specifies resources in an execution partition
+ *
+ *  gpcCount[IN/OUT]
+ *      - Total Number of GPCs in this partition (including GFX Supported GPCs)
+ *
+ *  gfxGpcCount[IN/OUT]
+ *      - Number of GFX GPCs in this partition. This should be a subset of gpcs inlcuded in gpcCount
+ *
+ *  VeidCount[OUT]
+ *      - Number of VEIDs available in this partition.
+ *
+ *  ceCount[IN/OUT]
+ *      - Copy Engines in this partition
+ *
+ *  nvEncCount[IN/OUT]
+ *      - Encoder Engines in this partition
+ *
+ *  nvDecCount[IN/OUT]
+ *      - Decoder Engines in this partition
+ *
+ *  nvJpgCount[IN/OUT]
+ *      - Jpg Engines in this partition
+ *
+ *  nvOfaCount[IN/OUT]
+ *      - Ofa engines in this partition
+ *
+ *  sharedEngFlags[IN/OUT]
+ *      - Flags determining whether above engines are shared with other execution partitions
+ *
+ *  veidStartOffset[OUT]
+ *      - VEID start offset within GPU partition
+ *
+ *  smCount[IN/OUT]
+ *      - Number of active SMs in this partition
+ *
+ *  spanStart[IN/OUT]
+ *      - First slot in the span for an execution partition placement
+ *
+ *  computeSize[IN/OUT]
+ *      - Flag corresponding to the compute profile used 
+ *        
+ */
+typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO {
+    NvU32 gpcCount;
+    NvU32 gfxGpcCount;
+    NvU32 veidCount;
+    NvU32 ceCount;
+    NvU32 nvEncCount;
+    NvU32 nvDecCount;
+    NvU32 nvJpgCount;
+    NvU32 ofaCount;
+    NvU32 sharedEngFlag;
+    NvU32 veidStartOffset;
+    NvU32 smCount;
+    NvU32 spanStart;
+    NvU32 computeSize;
+} NVC637_CTRL_EXEC_PARTITIONS_INFO;
+
+#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG         31:0
+#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NONE                      0x0
+#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_CE      NVBIT(0)
+#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVDEC   NVBIT(1)
+#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVENC   NVBIT(2)
+#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA     NVBIT(3)
+#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVJPG   NVBIT(4)
+
+#define NVC637_CTRL_MAX_EXEC_PARTITIONS                                   8
+#define NVC637_CTRL_EXEC_PARTITIONS_ID_INVALID                            0xFFFFFFFF
+
+/*!
+ * NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS
+ *
+ * This command will create requested execution partitions under the subscribed
+ * memory partition. The memory partition is expected to be configured before
+ * execution partition creation.
+ *
+ * bQuery[IN]
+ *      - If NV_TRUE, execution partitions will not be created, but return
+ *      status of NV_OK will indicate that the request is valid and can
+ *      currently be fulfilled
+ * flag [IN]
+ *      REQUEST_WITH_PART_ID
+ *      - If set, RM will try to assign execution partition id requested by clients.
+ *      This flag is only supported on vGPU enabled RM build and will be removed
+ *      when vgpu plugin implements virtualized execution partition ID support.
+ *      (bug 2938187)
+ *
+ *      REQUEST_AT_SPAN
+ *      - If set, RM will try to assign execution partition resources at the specified span.
+ *      This flag currently is only useful for chips in which CTS IDs are mandatory in RM,
+ *      as it allows the requester to position compute instances without using RM best fit
+ *      allocation.
+ *
+ * execPartCount[IN]
+ *      - Number of execution partitions requested
+ *
+ * execPartInfo[IN]
+ *      - Requested execution partition resources for each requested partition
+ *
+ * execPartId[OUT]
+ *      - ID of each requested execution partition
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID                   0:0
+#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID_FALSE (0x00000000)
+#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID_TRUE  (0x00000001)
+#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN                        1:1
+#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN_FALSE      (0x00000000)
+#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN_TRUE       (0x00000001)
+
+#define NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE (0xc6370101) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS
+ *
+ * This command will delete requested execution partitions.
+ *
+ * execPartCount[IN]
+ *      - Number of execution partitions to delete.
+ *
+ * execPartId[IN]
+ *      - Execution partition IDs to delete
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS {
+    NvBool                           bQuery;
+    NvU32                            flags;
+    NvU32                            execPartCount;
+    // C form: NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS];
+    NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS];
+    // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS];
+    NvU32                            execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS];
+} NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS;
+#define NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS {
+    NvU32 execPartCount;
+    NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS];
+} NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS;
+
+#define NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE (0xc6370102) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS
+ *
+ * This command will return information about execution partitions which
+ * currently exist within the subscribed memory partition.
+ *
+ * execPartCount[OUT]
+ *      - Number of existing execution partitions
+ *
+ * execPartId[OUT]
+ *      - ID of existing execution partitions
+ *
+ * execPartInfo[OUT]
+ *      - Resources within each existing execution partition
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS {
+    NvU32                            execPartCount;
+    // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS];
+    NvU32                            execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS];
+    // C form: NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS];
+    NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS];
+} NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS;
+
+#define NVC637_CTRL_CMD_EXEC_PARTITIONS_GET (0xc6370103) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS
+ *
+ * This command will return IDs of all active execution partitions in a memory
+ * partition
+ *
+ * execPartCount[OUT]
+ *      - Number of existing execution partitions
+ *
+ * execPartId[OUT]
+ *      - ID of existing execution partitions
+ *
+ * execPartUuid[OUT]
+ *      - ASCII UUID string of existing execution partitions
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+/* 'M' 'I' 'G' '-'(x5), '\0x0', extra = 9 */
+#define NVC637_UUID_LEN                     16
+#define NVC637_UUID_STR_LEN                 (0x29) /* finn: Evaluated from "((NVC637_UUID_LEN << 1) + 9)" */
+
+typedef struct NVC637_EXEC_PARTITION_UUID {
+    // C form: char str[NVC638_UUID_STR_LEN];
+    char str[NVC637_UUID_STR_LEN];
+} NVC637_EXEC_PARTITION_UUID;
+
+#define NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS {
+    NvU32                      execPartCount;
+
+    // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS];
+    NvU32                      execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS];
+
+    // C form: NVC637_EXEC_PARTITION_UUID execPartUuid[NVC637_CTRL_MAX_EXEC_PARTITIONS];
+    NVC637_EXEC_PARTITION_UUID execPartUuid[NVC637_CTRL_MAX_EXEC_PARTITIONS];
+} NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS;
+
+#define NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS               (0xc6370104) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT
+ *
+ * Export the resource and placement information about an exec partition such
+ * that a similar partition can be recreated from scratch in the same position.
+ */
+#define NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT                   (0xc6370105) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | 0x5" */
+
+/*
+ * NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT
+ *
+ * Create an exec partition resembling the exported partition info. The imported
+ * partition should behave identically with respect to fragmentation.
+ */
+#define NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT                   (0xc6370106) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | 0x6" */
+
+#define NVC637_CTRL_EXEC_PARTITIONS_EXPORT_MAX_ENGINES_MASK_SIZE 4
+typedef struct NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO {
+    NV_DECLARE_ALIGNED(NvU64 enginesMask[NVC637_CTRL_EXEC_PARTITIONS_EXPORT_MAX_ENGINES_MASK_SIZE], 8);
+    NvU8  uuid[NVC637_UUID_LEN];
+    NvU32 sharedEngFlags;
+    NvU32 gpcMask;
+    NvU32 veidOffset;
+    NvU32 veidCount;
+    NvU32 smCount;
+    NvU32 spanStart;
+    NvU32 computeSize;
+} NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO;
+
+typedef struct NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS {
+    NvU32 id;
+    NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO info, 8);
+} NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS;
+
+/*
+ * NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN
+ *
+ * This struct represents the span of a compute instance, which represents the
+ * resource slots a given partition occupies (or may occupy) within a fixed range which
+ * is defined per-chip. A partition containing more resources will cover more
+ * resource slots and therefore cover a larger span.
+ *
+ *   lo
+ *      - The starting unit of this span, inclusive
+ *
+ *   hi
+ *      - The ending unit of this span, inclusive
+ *
+ */
+typedef struct NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN {
+    NV_DECLARE_ALIGNED(NvU64 lo, 8);
+    NV_DECLARE_ALIGNED(NvU64 hi, 8);
+} NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN;
+
+/*
+ * NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY
+ *
+ * This command returns the count of compute instances which can be created 
+ * of the given commpute profile size (represented by the computeSize field
+ * within a profile) which can be requested via NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES
+ * Note that this API does not "reserve" any partitions, and there is no
+ * guarantee that the reported count of available partitions of a given size
+ * will remain consistent following creation of partitions of different size
+ * through NV2080_CTRL_GPU_SET_PARTITIONS.
+ * Note that this API is unsupported if SMC is feature-disabled.
+ * Note that the caller of this CTRL must be subscribed to a valid GPU instance
+ *
+ *   computeSize[IN]
+ *      - Partition flag indicating size of requested profile
+ *
+ *   profileCount[OUT]
+ *      - Available number of profiles of the given size which can currently be created.
+ *
+ *   availableSpans[OUT]
+ *      - For each profile able to be created of the specified size, the span
+ *        it could occupy.
+ *
+ *   availableSpansCount[OUT]
+ *      - Number of valid entries in availableSpans.
+ *
+ *   totalProfileCount[OUT]
+ *      - Total number of profiles of the given size which can be created.
+ *
+ *   totalSpans[OUT]
+ *      - List of spans which can possibly be occupied by profiles of the
+ *        given type.
+ *
+ *   totalSpansCount[OUT]
+ *      - Number of valid entries in totalSpans.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NVC637_CTRL_CMD_EXEC_PARTITIONS_GET_PROFILE_CAPACITY (0xc63701a9U) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS_MESSAGE_ID" */
+
+#define NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS_MESSAGE_ID (0xA9U)
+
+typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS {
+    NvU32 computeSize;
+    NvU32 profileCount;
+    NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN availableSpans[NVC637_CTRL_MAX_EXEC_PARTITIONS], 8);
+    NvU32 availableSpansCount;
+    NvU32 totalProfileCount;
+    NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN totalSpans[NVC637_CTRL_MAX_EXEC_PARTITIONS], 8);
+    NvU32 totalSpansCount;
+} NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS;
+
+//  _ctrlc637_h_
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc638.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc638.h
new file mode 100644
index 0000000..f9cf5fb
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc638.h
@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc638.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* AMPERE_SMC_EXEC_PARTITION_REF commands and parameters */
+
+#define NVC638_CTRL_CMD(cat,idx)             NVXXXX_CTRL_CMD(0xC638, NVC638_CTRL_##cat, idx)
+
+/* Command categories (6bits) */
+#define NVC638_CTRL_RESERVED       (0x00)
+#define NVC638_CTRL_EXEC_PARTITION (0x01)
+
+/*!
+ * NVC638_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVC638_CTRL_CMD_NULL       (0xc6380000) /* finn: Evaluated from "(FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/*!
+ * NVC638_CTRL_CMD_GET_UUID
+ *
+ * This command returns SHA1 ASCII UUID string as well as the binary UUID for
+ * the execution partition. The ASCII string format is,
+ * "MIG-%16x-%08x-%08x-%08x-%024x" (the canonical format of a UUID)
+ *
+ * uuid[OUT]
+ *      - Raw UUID bytes
+ *
+ * uuidStr[OUT]
+ *      - ASCII UUID string
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ */
+
+#define NVC638_UUID_LEN            16
+
+/* 'M' 'I' 'G' '-'(x5), '\0x0', extra = 9 */
+#define NVC638_UUID_STR_LEN        (0x29) /* finn: Evaluated from "((NVC638_UUID_LEN << 1) + 9)" */
+
+
+
+#define NVC638_CTRL_CMD_GET_UUID (0xc6380101) /* finn: Evaluated from "(FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID << 8) | NVC638_CTRL_GET_UUID_PARAMS_MESSAGE_ID" */
+
+
+
+#define NVC638_CTRL_GET_UUID_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVC638_CTRL_GET_UUID_PARAMS {
+    // C form: NvU8 uuid[NVC638_UUID_LEN];
+    NvU8 uuid[NVC638_UUID_LEN];
+
+    // C form: char uuidStr[NVC638_UUID_STR_LEN];
+    char uuidStr[NVC638_UUID_STR_LEN];
+} NVC638_CTRL_GET_UUID_PARAMS;//  _ctrlc638_h_
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc86f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc86f.h
new file mode 100644
index 0000000..eeb8923
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc86f.h
@@ -0,0 +1,165 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+*/
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlc86f.finn
+//
+
+
+
+#include "nvcfg_sdk.h"
+
+
+
+/* HOPPER_CHANNEL_GPFIFO_A control commands and parameters */
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl906f.h"          /* C36F is partially derived from 906F */
+#include "ctrl/ctrla06f.h"          /* C36F is partially derived from a06F */
+#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
+
+#define NVC86F_CTRL_CMD(cat,idx)  \
+    NVXXXX_CTRL_CMD(0xC36F, NVC86F_CTRL_##cat, idx)
+
+/* HOPPER_CHANNEL_GPFIFO_A command categories (6bits) */
+#define NVC86F_CTRL_RESERVED (0x00)
+#define NVC86F_CTRL_GPFIFO   (0x01)
+#define NVC86F_CTRL_EVENT    (0x02)
+
+/*
+ * NVC86F_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned is: NV_OK
+*/
+#define NVC86F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)
+
+
+
+
+
+
+/*
+ * NVC86F_CTRL_GET_CLASS_ENGINEID
+ *
+ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
+ *
+ */
+#define NVC86F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID)
+
+typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC86F_CTRL_GET_CLASS_ENGINEID_PARAMS;
+
+/*
+ * NVC86F_CTRL_RESET_CHANNEL
+ *
+ * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
+ *
+ */
+#define NVC86F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL)
+
+typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC86F_CTRL_CMD_RESET_CHANNEL_PARAMS;
+
+/*
+ * NVC86F_CTRL_CMD_GPFIFO_SCHEDULE
+ *
+ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
+ *
+ */
+#define NVC86F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE)
+
+typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC86F_CTRL_GPFIFO_SCHEDULE_PARAMS;
+
+/*
+ * NVC86F_CTRL_CMD_BIND
+ *
+ * Please see description of NVA06F_CTRL_CMD_BIND for more information.
+ */
+#define NVC86F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND)
+
+typedef NVA06F_CTRL_BIND_PARAMS NVC86F_CTRL_BIND_PARAMS;
+
+/*
+ * NVC86F_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
+*/
+#define NVC86F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION)
+
+typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC86F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
+#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
+#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
+
+/*
+ * NVC86F_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
+ */
+#define NVC86F_CTRL_CMD_EVENT_SET_TRIGGER                 (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER)
+
+
+
+
+
+/*
+ * NVC86F_CTRL_CMD_GET_MMU_FAULT_INFO
+ *
+ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
+ *
+ */
+#define NVC86F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO)
+
+typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC86F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
+
+/*
+ * NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN
+ *
+ *    This command returns an opaque work submit token to the caller which
+ *    can be used to write to doorbell register to finish submitting work.
+ *
+ *    workSubmitToken       The 32-bit work submit token
+ *
+ *    Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_OBJECT_HANDLE
+ *     NV_ERR_INVALID_ARGUMENT
+ *
+ */
+
+#define NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN)
+
+typedef struct NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS {
+    NvU32 workSubmitToken;
+} NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS;
+
+/* _ctrlC86F.h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlcbca.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlcbca.h
new file mode 100644
index 0000000..1e47dec
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlcbca.h
@@ -0,0 +1,120 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the 
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlcbca.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV_COUNTER_COLLECTION_UNIT control commands and parameters */
+
+#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD(cat,idx)                   NVXXXX_CTRL_CMD(0xCBCA, NVCBCA_CTRL_##cat, idx)
+
+#define NVCBCA_CTRL_RESERVED                     (0x00)
+#define NVCBCA_CTRL_COUNTER_COLLECTION_UNIT      (0x01)
+
+/*
+ * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible return values:
+ *   NV_OK
+ */
+#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_NULL (0xcbca0000) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+
+/*
+ * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SUBSCRIBE
+ *
+ * This command is used to subscribe performance counter data
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SUBSCRIBE (0xcbca0101) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS_MESSAGE_ID" */
+
+#define NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 bufferSize, 8);
+    NvU32 counterBlockSize;
+} NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS;
+
+/*
+ * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE
+ *
+ * This command is used to unsubscribe performance counter data
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE      (0xcbca0102) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x2" */
+
+/*
+ * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SET_STREAM_STATE
+ *
+ * This command is used to set the counter collection unit stream state
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SET_STREAM_STATE (0xcbca0103) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS {
+    NvBool bStreamState;
+} NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS;
+
+/*
+ * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_GET_STREAM_STATE
+ *
+ * This command is used to get the counter collection unit stream state
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_GET_STREAM_STATE (0xcbca0104) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x4" */
+
+/* _ctrlcbca_h_ */
+
diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlxxxx.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlxxxx.h
new file mode 100644
index 0000000..efe0c58
--- /dev/null
+++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlxxxx.h
@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2008,2013,2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file: ctrl/ctrlxxxx.finn
+//
+
+
+
+#include "nvtypes.h"
+
+/* definitions shared by all CTRL interfaces */
+
+/* Basic command format:
+*   cmd_class       [31:16],
+*   cmd_reserved    [15:15],
+*   cmd_reserved    [14:14],
+*   cmd_category    [13:8],
+*   cmd_index       [7:0]
+*/
+
+#define NVXXXX_CTRL_CMD_CLASS                                             31:16
+
+#define NVXXXX_CTRL_CMD_CATEGORY                                           13:8
+#define NVXXXX_CTRL_CMD_INDEX                                               7:0
+
+/* don't use DRF_NUM - not always available */
+#  define NVXXXX_CTRL_CMD(cls,cat,idx)     \
+                               (((cls) << 16) | ((0) << 15) | ((0) << 14) \
+                               | ((cat) << 8) | ((idx) & 0xFF))
+/*
+ * NVXXXX_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ * This command is valid for all classes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NVXXXX_CTRL_CMD_NULL              (0x00000000)
+
+#define NVxxxx_CTRL_LEGACY_PRIVILEGED     (0xC0)
+#define NVxxxx_CTRL_LEGACY_NON_PRIVILEGED (0x80)