Initial commit: Open-IOV vGPU-IO complete stack

- Firmware decompilation: GSP 570.144W (28.5MB ELF, RV64IMAC), 132 decompiled C files
- Kernel modules: nvidia.ko (34MB, OpenRM), open-iov-vfio.ko (2.8MB, VFIO mdev), gsp-vgpu.ko (1.8MB, guest driver)
- Userspace: libiov.so/libvgpu.so (76KB), example_vgpu (28KB), rpc_emulator.c
- PCI config space emulation (256B with PM, MSI, MSI-X, PCIe caps)
- 12 RPC types fully mapped from firmware decompilation
- BAR trap, WPR, scheduling, notification, migration emulation
- Helper scripts: load_vgpu_stack, create_mdev, launch_qemu_vgpu, test_vgpu_stack, setup_guest_driver, unload_vgpu_stack
- Architecture documentation
- Wiki: 10 technical documents
- Git LFS for large binaries (.ko, .bin, .iso, .img, .o, ghidra repos)
- nvidia-open-gpu-kernel-modules as submodule

28 files changed, 5622 insertions, 0 deletions

diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-caps.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-caps.h
new file mode 100644
index 0000000..35bbf7c
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-caps.h
@@ -0,0 +1,94 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _NV_CAPS_H_
+#define _NV_CAPS_H_
+
+#include <nv-kernel-interface-api.h>
+
+/*
+ * Opaque OS-specific struct; on Linux, this has member
+ * 'struct proc_dir_entry'.
+ */
+typedef struct nv_cap nv_cap_t;
+
+/*
+ * Creates directory named "capabilities" under the provided path.
+ *
+ * @param[in]   path        Absolute path
+ *
+ * Returns a valid nv_cap_t upon success. Otherwise, returns NULL.
+ */
+nv_cap_t* NV_API_CALL nv_cap_init(const char *path);
+
+/*
+ * Creates capability directory entry
+ *
+ * @param[in]   parent_cap     Parent capability directory
+ * @param[in]   name           Capability directory's name
+ * @param[in]   mode           Capability directory's access mode
+ *
+ * Returns a valid nv_cap_t upon success. Otherwise, returns NULL.
+ */
+nv_cap_t* NV_API_CALL nv_cap_create_dir_entry(nv_cap_t *parent_cap, const char *name, int mode);
+
+/*
+ * Creates capability file entry
+ *
+ * @param[in]   parent_cap     Parent capability directory
+ * @param[in]   name           Capability file's name
+ * @param[in]   mode           Capability file's access mode
+ *
+ * Returns a valid nv_cap_t upon success. Otherwise, returns NULL.
+ */
+nv_cap_t* NV_API_CALL nv_cap_create_file_entry(nv_cap_t *parent_cap, const char *name, int mode);
+
+/*
+ * Destroys capability entry
+ *
+ * @param[in]   cap              Capability entry
+ */
+void NV_API_CALL nv_cap_destroy_entry(nv_cap_t *cap);
+
+/*
+ * Validates and duplicates the provided file descriptor
+ *
+ * @param[in]   cap         Capability entry
+ * @param[in]   fd          File descriptor to be validated
+ *
+ * Returns duplicate fd upon success. Otherwise, returns -1.
+ */
+int NV_API_CALL nv_cap_validate_and_dup_fd(const nv_cap_t *cap, int fd);
+
+/*
+ * Closes file descriptor
+ *
+ * This function should be used to close duplicate file descriptors
+ * returned by nv_cap_validate_and_dup_fd.
+ *
+ * @param[in]   fd          File descriptor to be validated
+ *
+ */
+void NV_API_CALL nv_cap_close_fd(int fd);
+
+#endif  /* _NV_CAPS_H_ */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-chardev-numbers.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-chardev-numbers.h
new file mode 100644
index 0000000..54ca547
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-chardev-numbers.h
@@ -0,0 +1,43 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _NV_CHARDEV_NUMBERS_H_
+#define _NV_CHARDEV_NUMBERS_H_
+
+// NVIDIA's reserved major character device number (Linux).
+#define NV_MAJOR_DEVICE_NUMBER  195
+
+// Minor numbers 0 to 247 reserved for regular devices
+#define NV_MINOR_DEVICE_NUMBER_REGULAR_MAX         247
+
+// Minor numbers 248 to 253 currently unused
+
+// Minor number 254 reserved for the modeset device (provided by NVKMS)
+#define NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE      254
+
+// Minor number 255 reserved for the control device
+#define NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE      255
+
+#endif  // _NV_CHARDEV_NUMBERS_H_
+
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-gpu-info.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-gpu-info.h
new file mode 100644
index 0000000..1b79320
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-gpu-info.h
@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _NV_GPU_INFO_H_
+#define _NV_GPU_INFO_H_
+
+typedef struct {
+    NvU32 gpu_id;
+
+    struct {
+        NvU32 domain;
+        NvU8  bus, slot, function;
+    } pci_info;
+
+    NvBool needs_numa_setup;
+    NvBool is_soc_disp;
+
+    /*
+     * opaque OS-specific pointer; on Linux, this is a pointer to the
+     * 'struct device' for the GPU.
+     */
+    void *os_device_ptr;
+} nv_gpu_info_t;
+
+#define NV_MAX_GPUS 32
+
+#endif /* _NV_GPU_INFO_H_ */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-lockless-diag.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-lockless-diag.h
new file mode 100644
index 0000000..84e3fa7
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-lockless-diag.h
@@ -0,0 +1,43 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#if !defined(NV_IOCTL_LOCKLESS_DIAG)
+#define NV_IOCTL_LOCKLESS_DIAG
+
+#include <nvtypes.h>
+#include "ctrl/ctrl0000/ctrl0000nvd.h"
+
+typedef struct
+{
+    NvU32 cmd; // in
+    NvU32 status; // out
+    union // in/out
+    {
+        NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS getNvlogInfo;
+        NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS getNvlogBufferInfo;
+        NV0000_CTRL_NVD_GET_NVLOG_PARAMS getNvlog;
+    } params;
+} NV_LOCKLESS_DIAGNOSTIC_PARAMS;
+
+#endif
+
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numa.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numa.h
new file mode 100644
index 0000000..0af5267
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numa.h
@@ -0,0 +1,81 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef NV_IOCTL_NUMA_H
+#define NV_IOCTL_NUMA_H
+
+#include <nv-ioctl-numbers.h>
+
+#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX)
+#include <linux/types.h>
+#elif defined (NV_KERNEL_INTERFACE_LAYER) && defined(NV_BSD)
+#include <sys/stdint.h>
+#else
+
+#include <stdint.h>
+
+#if !defined(__aligned)
+#define __aligned(n) __attribute__((aligned(n)))
+#endif
+
+#endif
+
+#define NV_ESC_NUMA_INFO         (NV_IOCTL_BASE + 15)
+#define NV_ESC_SET_NUMA_STATUS   (NV_IOCTL_BASE + 16)
+
+#define NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64
+typedef struct offline_addresses
+{
+    uint64_t addresses[NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES] __aligned(8);
+    uint32_t numEntries;
+} nv_offline_addresses_t;
+
+
+/* per-device NUMA memory info as assigned by the system */
+typedef struct nv_ioctl_numa_info
+{
+    int32_t  nid;
+    int32_t  status;
+    uint64_t memblock_size __aligned(8);
+    uint64_t numa_mem_addr __aligned(8);
+    uint64_t numa_mem_size __aligned(8);
+    uint8_t  use_auto_online;
+    nv_offline_addresses_t offline_addresses __aligned(8);
+} nv_ioctl_numa_info_t;
+
+/* set the status of the device NUMA memory */
+typedef struct nv_ioctl_set_numa_status
+{
+    int32_t status;
+} nv_ioctl_set_numa_status_t;
+
+#define NV_IOCTL_NUMA_STATUS_DISABLED               0
+#define NV_IOCTL_NUMA_STATUS_OFFLINE                1
+#define NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS     2
+#define NV_IOCTL_NUMA_STATUS_ONLINE                 3
+#define NV_IOCTL_NUMA_STATUS_ONLINE_FAILED          4
+#define NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS    5
+#define NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED         6
+
+#endif
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numbers.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numbers.h
new file mode 100644
index 0000000..e266368
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numbers.h
@@ -0,0 +1,48 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef NV_IOCTL_NUMBERS_H
+#define NV_IOCTL_NUMBERS_H
+
+/* NOTE: using an ioctl() number > 55 will overflow! */
+/* 
+ * NOTE: Any new ioctls added here should also be added to nv_validate_ioctls() in nv.c or
+ * rm_validate_ioctls() in osapi.c
+ */
+#define NV_IOCTL_MAGIC      'F'
+#define NV_IOCTL_BASE       200
+#define NV_ESC_CARD_INFO             (NV_IOCTL_BASE + 0)
+#define NV_ESC_REGISTER_FD           (NV_IOCTL_BASE + 1)
+#define NV_ESC_ALLOC_OS_EVENT        (NV_IOCTL_BASE + 6)
+#define NV_ESC_FREE_OS_EVENT         (NV_IOCTL_BASE + 7)
+#define NV_ESC_STATUS_CODE           (NV_IOCTL_BASE + 9)
+#define NV_ESC_CHECK_VERSION_STR     (NV_IOCTL_BASE + 10)
+#define NV_ESC_IOCTL_XFER_CMD        (NV_IOCTL_BASE + 11)
+#define NV_ESC_ATTACH_GPUS_TO_FD     (NV_IOCTL_BASE + 12)
+#define NV_ESC_QUERY_DEVICE_INTR     (NV_IOCTL_BASE + 13)
+#define NV_ESC_SYS_PARAMS            (NV_IOCTL_BASE + 14)
+#define NV_ESC_EXPORT_TO_DMABUF_FD   (NV_IOCTL_BASE + 17)
+#define NV_ESC_WAIT_OPEN_COMPLETE    (NV_IOCTL_BASE + 18)
+
+#endif
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl.h
new file mode 100644
index 0000000..8ca1642
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl.h
@@ -0,0 +1,158 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef NV_IOCTL_H
+#define NV_IOCTL_H
+
+#include <nv-ioctl-numbers.h>
+#include <nv-ioctl-numa.h>
+#include <nvtypes.h>
+
+
+typedef struct {
+    NvU32    domain;        /* PCI domain number   */
+    NvU8     bus;           /* PCI bus number      */
+    NvU8     slot;          /* PCI slot number     */
+    NvU8     function;      /* PCI function number */
+    NvU16    vendor_id;     /* PCI vendor ID       */
+    NvU16    device_id;     /* PCI device ID       */
+} nv_pci_info_t;
+
+/*
+ * ioctl()'s with parameter structures too large for the
+ * _IOC cmd layout use the nv_ioctl_xfer_t structure
+ * and the NV_ESC_IOCTL_XFER_CMD ioctl() to pass the actual
+ * size and user argument pointer into the RM, which
+ * will then copy it to/from kernel space in separate steps.
+ */
+typedef struct nv_ioctl_xfer
+{
+    NvU32   cmd;
+    NvU32   size;
+    NvP64   ptr  NV_ALIGN_BYTES(8);
+} nv_ioctl_xfer_t;
+
+typedef struct nv_ioctl_card_info
+{
+    NvBool        valid;
+    nv_pci_info_t pci_info;            /* PCI config information      */
+    NvU32         gpu_id;
+    NvU16         interrupt_line;
+    NvU64         reg_address    NV_ALIGN_BYTES(8);
+    NvU64         reg_size       NV_ALIGN_BYTES(8);
+    NvU64         fb_address     NV_ALIGN_BYTES(8);
+    NvU64         fb_size        NV_ALIGN_BYTES(8);
+    NvU32         minor_number;
+    NvU8          dev_name[10];  /* device names such as vmgfx[0-32] for vmkernel */
+} nv_ioctl_card_info_t;
+
+/* alloc event */
+typedef struct nv_ioctl_alloc_os_event
+{
+    NvHandle hClient;
+    NvHandle hDevice;
+    NvU32    fd;
+    NvU32    Status;
+} nv_ioctl_alloc_os_event_t;
+
+/* free event */
+typedef struct nv_ioctl_free_os_event
+{
+    NvHandle hClient;
+    NvHandle hDevice;
+    NvU32    fd;
+    NvU32    Status;
+} nv_ioctl_free_os_event_t;
+
+/* status code */
+typedef struct nv_ioctl_status_code
+{
+    NvU32 domain;
+    NvU8  bus;
+    NvU8  slot;
+    NvU32 status;
+} nv_ioctl_status_code_t;
+
+/* check version string */
+#define NV_RM_API_VERSION_STRING_LENGTH 64
+
+typedef struct nv_ioctl_rm_api_version
+{
+    NvU32 cmd;
+    NvU32 reply;
+    char versionString[NV_RM_API_VERSION_STRING_LENGTH];
+} nv_ioctl_rm_api_version_t;
+
+#define NV_RM_API_VERSION_CMD_STRICT         0
+#define NV_RM_API_VERSION_CMD_RELAXED       '1'
+#define NV_RM_API_VERSION_CMD_QUERY         '2'
+
+#define NV_RM_API_VERSION_REPLY_UNRECOGNIZED 0
+#define NV_RM_API_VERSION_REPLY_RECOGNIZED   1
+
+typedef struct nv_ioctl_query_device_intr
+{
+    NvU32 intrStatus NV_ALIGN_BYTES(4);
+    NvU32 status;
+} nv_ioctl_query_device_intr_t;
+
+/* system parameters that the kernel driver may use for configuration */
+typedef struct nv_ioctl_sys_params
+{
+    NvU64 memblock_size NV_ALIGN_BYTES(8);
+} nv_ioctl_sys_params_t;
+
+typedef struct nv_ioctl_register_fd
+{
+    int ctl_fd;
+} nv_ioctl_register_fd_t;
+
+#define NV_DMABUF_EXPORT_MAX_HANDLES 128
+
+#define NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT        0
+#define NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE     1
+
+typedef struct nv_ioctl_export_to_dma_buf_fd
+{
+    int         fd;
+    NvHandle    hClient;
+    NvU32       totalObjects;
+    NvU32       numObjects;
+    NvU32       index;
+    NvU64       totalSize NV_ALIGN_BYTES(8);
+    NvU8        mappingType;
+    NvBool      bAllowMmap;
+    NvHandle    handles[NV_DMABUF_EXPORT_MAX_HANDLES];
+    NvU64       offsets[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8);
+    NvU64       sizes[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8);
+    NvU32       status;
+} nv_ioctl_export_to_dma_buf_fd_t;
+
+typedef struct nv_ioctl_wait_open_complete
+{
+    int rc;
+    NvU32 adapterStatus;
+} nv_ioctl_wait_open_complete_t;
+
+#endif
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-kernel-rmapi-ops.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-kernel-rmapi-ops.h
new file mode 100644
index 0000000..d50a1e4
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-kernel-rmapi-ops.h
@@ -0,0 +1,61 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _NV_KERNEL_RMAPI_OPS_H_
+#define _NV_KERNEL_RMAPI_OPS_H_
+
+/*
+ * Define the RMAPI provided to kernel-level RM clients.
+ *
+ * Kernel-level RM clients should populate nvidia_kernel_rmapi_ops_t
+ * by assigning nvidia_kernel_rmapi_ops_t::op and the corresponding
+ * parameter structure in nvidia_kernel_rmapi_ops_t's params union.
+ * Then, pass a pointer to the nvidia_kernel_rmapi_ops_t to
+ * rm_kernel_rmapi_op().
+ */
+
+#include "nvtypes.h"
+#include "nvos.h"
+
+typedef struct {
+    NvU32 op; /* One of the NV0[14]_XXXX operations listed below. */
+
+    union {
+        NVOS00_PARAMETERS free;                /* NV01_FREE */
+        NVOS02_PARAMETERS allocMemory64;       /* NV01_ALLOC_MEMORY */
+        NVOS64_PARAMETERS alloc;               /* NV04_ALLOC */
+        NVOS32_PARAMETERS *pVidHeapControl;    /* NV04_VID_HEAP_CONTROL */
+        NVOS33_PARAMETERS mapMemory;           /* NV04_MAP_MEMORY */
+        NVOS34_PARAMETERS unmapMemory;         /* NV04_UNMAP_MEMORY */
+        NVOS39_PARAMETERS allocContextDma2;    /* NV04_ALLOC_CONTEXT_DMA */
+        NVOS46_PARAMETERS mapMemoryDma;        /* NV04_MAP_MEMORY_DMA */
+        NVOS47_PARAMETERS unmapMemoryDma;      /* NV04_UNMAP_MEMORY_DMA */
+        NVOS49_PARAMETERS bindContextDma;      /* NV04_BIND_CONTEXT_DMA */
+        NVOS54_PARAMETERS control;             /* NV04_CONTROL*/
+        NVOS55_PARAMETERS dupObject;           /* NV04_DUP_OBJECT */
+        NVOS57_PARAMETERS share;               /* NV04_SHARE */
+        NVOS61_PARAMETERS addVblankCallback;   /* NV04_ADD_VBLANK_CALLBACK */
+    } params;
+} nvidia_kernel_rmapi_ops_t;
+
+#endif /* _NV_KERNEL_RMAPI_OPS_H_ */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-nb-regs.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-nb-regs.h
new file mode 100644
index 0000000..6282b35
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-nb-regs.h
@@ -0,0 +1,65 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _NV_NB_REGS_H_
+#define _NV_NB_REGS_H_
+
+#include "nvdevid.h"
+
+typedef struct
+{
+    NvU32 subsystem_vendor_id;
+    NvU32 subsystem_device_id;
+    NvU16 gpu_device_id;
+} nv_nb_id_t;
+
+typedef struct
+{
+    NvU32       vendor_id;
+    const char *name;
+    NvU32       data;
+} nv_nb_reg_t;
+
+/*
+ * nb_id_table contains the OEM vendor ID, the subsystem ID and the
+ * GPU device ID of the notebooks for which we need to enable
+ * vendor specific registry keys. nb_reg_table contains the vendor
+ * specific registry key values. The initVendorSpecificRegistry()
+ * function compares the present notebooks OEM subsystem ID and the
+ * GPU device ID with the values present in id_tables. If a match
+ * is found, initVendorSpecificRegistry() extracts the vendor
+ * ID and sets any associated registry key listed in nb_reg_table.
+ */
+
+static nv_nb_id_t nb_id_table[] = {
+    { PCI_VENDOR_ID_PC_PARTNER, 0x0620, 0x1284 }, // Acer GT 630
+    { PCI_VENDOR_ID_PC_PARTNER, 0x0620, 0x124b }, // Acer GT 640
+    { 0,                      0,      0      }
+};
+
+static nv_nb_reg_t nb_reg_table[] = {
+    { PCI_VENDOR_ID_PC_PARTNER, "RmOverrideSupportChipsetAspm", 2   },
+    { 0,                      NULL,                      0   }
+};
+
+#endif //_NV_NB_REGS_H_
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-priv.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-priv.h
new file mode 100644
index 0000000..a3dcebf
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-priv.h
@@ -0,0 +1,357 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _NV_PRIV_H_
+#define _NV_PRIV_H_
+
+#include <nv.h>
+#include <os/os.h>
+#include <ctrl/ctrl402c.h>
+#include <gpu/disp/kern_disp_max.h>
+#include <gpu/disp/kern_disp_type.h>
+
+#define NV_PRIV_REG_WR08(b,o,d)   (*((volatile NvV8*)&(b)->Reg008[(o)/1])=(NvV8)(d))
+#define NV_PRIV_REG_WR16(b,o,d)   (*((volatile NvV16*)&(b)->Reg016[(o)/2])=(NvV16)(d))
+#define NV_PRIV_REG_WR32(b,o,d)   (*((volatile NvV32*)&(b)->Reg032[(o)/4])=(NvV32)(d))
+
+#define NV_PRIV_REG_RD08(b,o)     ((b)->Reg008[(o)/1])
+#define NV_PRIV_REG_RD16(b,o)     ((b)->Reg016[(o)/2])
+#define NV_PRIV_REG_RD32(b,o)     ((b)->Reg032[(o)/4])
+
+struct OBJGPU;
+
+typedef struct
+{
+    NvBool              baseValid;
+    VGAADDRDESC         base;
+    NvBool              workspaceBaseValid;
+    VGAADDRDESC         workspaceBase;
+    NvU32               vesaMode;
+} nv_vga_t;
+
+/*
+* device state during Power Management
+*/
+typedef struct nv_pm_state_s
+{
+    NvU32  IntrEn;
+    NvBool InHibernate;
+} nv_pm_state_t;
+
+/*
+* data structure for the UNIX workqueues
+*/
+typedef struct nv_work_item_s
+{
+    OsQueueWorkItemFlags flags;
+    NvU32   gpuInstance;
+    union
+    {
+        OSWorkItemFunction *pGpuFunction;
+        OSSystemWorkItemFunction *pSystemFunction;
+    } func;
+    void *pData;
+} nv_work_item_t;
+
+#define INVALID_DISP_ID 0xFFFFFFFF
+#define MAX_DISP_ID_PER_ADAPTER 0x2
+
+typedef struct nv_i2c_adapter_entry_s
+{
+    void  *pOsAdapter;
+    NvU32  port;
+    NvU32  displayId[MAX_DISP_ID_PER_ADAPTER];
+} nv_i2c_adapter_entry_t;
+
+#define NV_INIT_FLAG_HAL                  0x0001
+#define NV_INIT_FLAG_HAL_COMPONENTS       0x0002
+#define NV_INIT_FLAG_GPU_STATE            0x0004
+#define NV_INIT_FLAG_GPU_STATE_LOAD       0x0008
+#define NV_INIT_FLAG_FIFO_WATCHDOG        0x0010
+#define NV_INIT_FLAG_CORE_LOGIC           0x0020
+#define NV_INIT_FLAG_GPUMGR_ATTACH        0x0040
+#define NV_INIT_FLAG_PUBLIC_I2C           0x0080
+#define NV_INIT_FLAG_SCALABILITY          0x0100
+#define NV_INIT_FLAG_DMA                  0x0200
+
+#define MAX_I2C_ADAPTERS    NV402C_CTRL_NUM_I2C_PORTS
+
+/*
+ * GPU dynamic power state machine.
+ *
+ * The GPU is in exactly one of these states at at time.  Only certain state
+ * transitions are valid, as documented by the DAGs below.
+ *
+ * When in "instant idle" or COARSE mode:
+ *
+ *                   +----------------------+
+ *                   v                      |
+ * +---------+     +----------------+     +--------+
+ * | UNKNOWN | --> | IDLE_INDICATED | --> | IN_USE |
+ * +---------+     +----------------+     +--------+
+ *
+ * The transition from UNKNOWN to IDLE_INDICATED happens in
+ * rm_init_dynamic_power_management().
+ *
+ * Thereafter, transitions from IDLE_INDICATED to IN_USE happen when
+ * os_ref_dynamic_power() is called and the refcount transitions from 0 to 1;
+ * transitions from IN_USE to IDLE_INDICATED happen when
+ * os_unref_dynamic_power() is called and the refcount transitions from 1 to 0.
+ * Note that only calls to os_(un)ref_dynamic_power() with the mode == COARSE
+ * are considered in this mode; calls with mode == FINE are ignored.  Since
+ * COARSE calls are placed only in rm_init_adapter/rm_shutdown_adapter, the GPU
+ * effectively stays in the IN_USE state any time any client has initialized
+ * it.
+ *
+ *
+ * When in "deferred idle" or FINE mode:
+ *
+ *  +----------------------------------------------------------------+
+ *  |                                                                |
+ *  |                                                                |
+ *  |                    +-------------------------------------------+----------------------+
+ *  |                    |                                           |                      v
+ *  |  +---------+     +----------------+     +--------------+     +----------------+     +--------+
+ *  |  | UNKNOWN | --> | IDLE_INDICATED | --> |              | --> | IDLE_SUSTAINED | --> | IN_USE | -+
+ *  |  +---------+     +----------------+     |              |     +----------------+     +--------+  |
+ *  |                    ^                    |              |       |                      ^         |
+ *  +--------------------+                    | IDLE_INSTANT | ------+----------------------+         |
+ *                                            |              |       |                                |
+ *                                            |              |       |                                |
+ *                                            |              | <-----+                                |
+ *                                            +--------------+                                        |
+ *                                              ^                                                     |
+ *                                              +-----------------------------------------------------+
+ *
+ * As before, the transition from UNKNOWN to IDLE_INDICATED happens in
+ * rm_init_dynamic_power_management().  This is not ideal: it means the GPU may
+ * be powered down immediately upon loading the RM module, even if
+ * rm_init_adapter() is going to be called soon thereafter.  However, we can't
+ * rely on deferred idle callbacks yet, since those currently rely on core RM
+ * being initialized.
+ *
+ * At the beginning of rm_init_adapter(), the GPU transitions to the IN_USE
+ * state; during the rm_init_adapter() sequence,
+ * RmInitDeferredDynamicPowerManagement() will be called which will schedule
+ * timer callbacks and set the "deferred_idle_enabled" boolean.
+ *
+ * While in "deferred idle" mode, one of the callbacks
+ * timerCallbackForIdlePreConditions(), timerCallbackToIndicateIdle(), or
+ * RmIndicateIdle() should be scheduled when in the states:
+ * - IN_USE
+ * - IDLE_INSTANT
+ * - IDLE_SUSTAINED
+ * Note that since we may transition from IN_USE to IDLE_INSTANT rapidly (e.g.,
+ * for a series of RM calls), we don't attempt to schedule the callbacks and
+ * cancel them on each of these transitions.  The
+ * timerCallbackForIdlePreConditions() callback will simply exit early if in
+ * the IN_USE state.
+ *
+ * As before, the GPU will remain in the IN_USE state until
+ * os_unref_dynamic_power() is called and the count transitions from 1 to 0
+ * (calls with mode == FINE are honored, in this mode, and these transitions
+ * can happen frequently).  When the refcount reaches 0, rather than going
+ * directly to the IDLE_INDICATED state, it transitions to the IDLE_INSTANT
+ * state.
+ *
+ * Then, when the next timerCallbackForIdlePreConditions() callback executes,
+ * if all preconditions are met, the state will transition to IDLE_SUSTAINED.
+ *
+ * If, when in the IDLE_SUSTAINED state, os_ref_dynamic_power() is called, the
+ * GPU will transition back to the IN_USE state and return to the IDLE_INSTANT
+ * state.  This ensures that there is a suitable delay between any activity
+ * that requires bumping the refcount and indicating idleness.
+ *
+ * If the timerCallbackForIdlePreConditions() callback executes again and the
+ * GPU is still in the IDLE_SUSTAINED state, userspace mappings will be revoked
+ * and the timerCallbackToIndicateIdle() callback will be scheduled.
+ *
+ * If, before the timerCallbackToIndicateIdle() callback executes, either
+ * os_ref_dynamic_power() is called or a mapping which has been revoked is
+ * accessed (which triggers the RmForceGpuNotIdle() callback), the GPU will
+ * transition back to the IN_USE or IDLE_INSTANT state, respectively.
+ *
+ * Then, when the timerCallbackToIndicateIdle() callback executes, if all
+ * mappings are still revoked, and the GPU is still in the IDLE_SUSTAINED
+ * state, and all GPU idleness preconditions remain satisfied, the
+ * RmIndicateIdle() work item will be enqueued.  (Else, the GPU will transition
+ * back to the IDLE_INSTANT state and the callback for preconditions is
+ * scheduled again.)
+ *
+ * Finally, once the RmIndicateIdle() work item is called, if all of the same
+ * conditions still hold, the state will transition to IDLE_INDICATED.  No
+ * callbacks will be scheduled from here; the callbacks for preconditions
+ * should be re-scheduled when transitioning out of the IDLE_INDICATED state.
+ *
+ * Once in the IDLE_INDICATED state, the kernel is free to call the RM to
+ * perform the GC6 entry sequence then turn off power to the GPU (although it
+ * may not, if the audio function is being used for example).
+ *
+ * There are two paths to exit the IDLE_INDICATED state:
+ * (a) If os_ref_dynamic_power() is called, in which case it transitions
+ *     directly to the IN_USE state;
+ * (b) If RmForceGpuNotIdle() is called, in which case it transitions back to
+ *     the IDLE_INSTANT state.
+ */
+typedef enum
+{
+    NV_DYNAMIC_POWER_STATE_UNKNOWN = 0,
+
+    NV_DYNAMIC_POWER_STATE_IN_USE,
+
+    NV_DYNAMIC_POWER_STATE_IDLE_INSTANT,
+    NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED,
+    NV_DYNAMIC_POWER_STATE_IDLE_INDICATED,
+} nv_dynamic_power_state_t;
+
+typedef struct nv_dynamic_power_s
+{
+    /*
+     * mode is read without the mutex -- should be read-only outside of
+     * rm_init_dynamic_power_management, called during probe only.
+     */
+    nv_dynamic_power_mode_t mode;
+    /*
+     * Whether to indicate idle immediately when the refcount reaches 0, or
+     * only go to the IDLE_INSTANT state, and expect timer callbacks to
+     * transition through IDLE_SUSTAINED -> IDLE_INDICATED.
+     */
+    NvBool deferred_idle_enabled;
+
+    PORT_ATOMIC nv_dynamic_power_state_t state;
+    NvS32 refcount;
+
+    /*
+     * A word on lock ordering.  These locks must be taken in the order:
+     *
+     *      RM API lock > this dynamic_power mutex > RM GPUs lock
+     *
+     * Skipping any of those locks is fine (if they aren't required to protect
+     * whatever state is being accessed or modified), so long as the order is
+     * not violated.
+     */
+    PORT_MUTEX *mutex;
+
+    /*
+     * callback handles for deferred dynamic power management.
+     */
+    NvP64 idle_precondition_check_event;
+    NvP64 indicate_idle_event;
+    NvBool idle_precondition_check_callback_scheduled;
+
+    /*
+     * callback handle for kernel initiated gc6 entry/exit.
+     * these will be protected by the gpu lock.
+     */
+    NvP64 remove_idle_holdoff;
+    NvBool b_idle_holdoff;
+
+    /*
+     * flag set if the platform does not support fine grain dynamic power
+     * management.
+     */
+    NvBool b_fine_not_supported;
+
+    /*
+     * This flag is used to check if a workitem is queued for 
+     * RmQueueIdleSustainedWorkitem().
+     */
+    NvBool b_idle_sustained_workitem_queued;
+
+    /*
+     * Counter to track clients disallowing GCOFF.
+     */
+    NvU32 clients_gcoff_disallow_refcount;
+
+    /*
+     * Maximum FB allocation size which can be saved in system memory
+     * while doing GCOFF based dynamic PM.
+     */
+    NvU64 gcoff_max_fb_size;
+
+    /*
+     * NVreg_DynamicPowerManagement regkey value set by the user
+     */
+    NvU32 dynamic_power_regkey;
+} nv_dynamic_power_t;
+
+typedef struct
+{
+    OBJGPU *pGpu;
+
+    NvU32 pmc_boot_0;
+
+    nv_vga_t vga;
+
+    NvU32 flags;
+    NvU32 status;
+
+    nv_i2c_adapter_entry_t i2c_adapters[MAX_I2C_ADAPTERS];
+
+    void *pVbiosCopy;
+    NvU32 vbiosSize;
+
+    nv_pm_state_t pm_state;
+
+    nv_reg_entry_t *pRegistry;
+
+    nv_dynamic_power_t dynamic_power;
+
+    /* Flag to check if GPU mobile config is enabled */
+    NvBool b_mobile_config_enabled;
+
+    /* Flag to check if S0ix-based power management is enabled. */
+    NvBool s0ix_pm_enabled;
+
+    /* Variable to track Dynamic Boost support */
+    int db_supported;
+
+    /*
+     * Maximum FB allocation size which can be saved in system memory
+     * during system supened with S0ix-based power management.
+     */
+    NvU64 s0ix_gcoff_max_fb_size;
+
+    NvU32 pmc_boot_1;
+    NvU32 pmc_boot_42;
+
+    /*
+     * This flag is set if the upstream port has been configured ("D3cold Aux Power Limit" and
+     * "PERST# Assertion Delay") for GC6. This configuration is needed only for desktops.
+     */
+    NvBool gc6_upstream_port_configured;
+
+    /* This flag is set if _PR3 ACPI method is available to support RTD3. */
+    NvBool pr3_acpi_method_present;
+} nv_priv_t;
+
+#define NV_SET_NV_PRIV(nv,p) ((nv)->priv = (p))
+#define NV_GET_NV_PRIV(nv)   ((nv) ? (nv)->priv : NULL)
+
+/*
+ * Make sure that your stack has taken API Lock before using this macro.
+ */
+#define NV_GET_NV_PRIV_PGPU(nv) \
+    (NV_GET_NV_PRIV(nv) ? ((nv_priv_t *)NV_GET_NV_PRIV(nv))->pGpu : NULL)
+
+#endif // _NV_PRIV_H_
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-reg.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-reg.h
new file mode 100644
index 0000000..93999d4
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-reg.h
@@ -0,0 +1,1137 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+//
+// This file holds Unix-specific NVIDIA driver options
+//
+
+#ifndef _RM_REG_H_
+#define _RM_REG_H_
+
+#include "nvtypes.h"
+#include "nv-firmware-registry.h"
+
+/*
+ * use NV_REG_STRING to stringify a registry key when using that registry key
+ */
+
+#define __NV_REG_STRING(regkey)  #regkey
+#define NV_REG_STRING(regkey)  __NV_REG_STRING(regkey)
+
+/*
+ * use NV_DEFINE_REG_ENTRY and NV_DEFINE_PARAMS_TABLE_ENTRY to simplify definition
+ * of registry keys in the kernel module source code.
+ */
+
+#define __NV_REG_VAR(regkey)  NVreg_##regkey
+
+#if defined(NV_MODULE_PARAMETER)
+#define NV_DEFINE_REG_ENTRY(regkey, default_value)        \
+    static NvU32 __NV_REG_VAR(regkey) = (default_value);  \
+    NV_MODULE_PARAMETER(__NV_REG_VAR(regkey))
+#define NV_DEFINE_REG_ENTRY_GLOBAL(regkey, default_value) \
+    NvU32 __NV_REG_VAR(regkey) = (default_value);         \
+    NV_MODULE_PARAMETER(__NV_REG_VAR(regkey))
+#else
+#define NV_DEFINE_REG_ENTRY(regkey, default_value)        \
+    static NvU32 __NV_REG_VAR(regkey) = (default_value)
+#define NV_DEFINE_REG_ENTRY_GLOBAL(regkey, default_value) \
+    NvU32 __NV_REG_VAR(regkey) = (default_value)
+#endif
+
+#if defined(NV_MODULE_STRING_PARAMETER)
+#define NV_DEFINE_REG_STRING_ENTRY(regkey, default_value) \
+    char *__NV_REG_VAR(regkey) = (default_value);         \
+    NV_MODULE_STRING_PARAMETER(__NV_REG_VAR(regkey))
+#else
+#define NV_DEFINE_REG_STRING_ENTRY(regkey, default_value) \
+    char *__NV_REG_VAR(regkey) = (default_value)
+#endif
+
+#define NV_DEFINE_PARAMS_TABLE_ENTRY(regkey) \
+    { NV_REG_STRING(regkey), &__NV_REG_VAR(regkey) }
+
+/*
+ * Like NV_DEFINE_PARMS_TABLE_ENTRY, but allows a mismatch between the name of
+ * the regkey and the name of the module parameter. When using this macro, the
+ * name of the parameter is passed to the extra "parameter" argument, and it is
+ * this name that must be used in the NV_DEFINE_REG_ENTRY() macro.
+ */
+
+#define NV_DEFINE_PARAMS_TABLE_ENTRY_CUSTOM_NAME(regkey, parameter) \
+    { NV_REG_STRING(regkey), &__NV_REG_VAR(parameter)}
+
+/*
+ *----------------- registry key definitions--------------------------
+ */
+
+/*
+ * Option: ModifyDeviceFiles
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA driver will verify the validity
+ * of the NVIDIA device files in /dev and attempt to dynamically modify
+ * and/or (re-)create them, if necessary. If you don't wish for the NVIDIA
+ * driver to touch the device files, you can use this registry key.
+ *
+ * This module parameter is only honored by the NVIDIA GPU driver and NVIDIA
+ * capability driver. Furthermore, the NVIDIA capability driver provides
+ * modifiable /proc file entry (DeviceFileModify=0/1) to alter the behavior of
+ * this module parameter per device file.
+ *
+ * Possible Values:
+ *  0 = disable dynamic device file management
+ *  1 = enable  dynamic device file management (default)
+ */
+
+#define __NV_MODIFY_DEVICE_FILES ModifyDeviceFiles
+#define NV_REG_MODIFY_DEVICE_FILES NV_REG_STRING(__NV_MODIFY_DEVICE_FILES)
+
+/*
+ * Option: DeviceFileUID
+ *
+ * Description:
+ *
+ * This registry key specifies the UID assigned to the NVIDIA device files
+ * created and/or modified by the NVIDIA driver when dynamic device file
+ * management is enabled.
+ *
+ * This module parameter is only honored by the NVIDIA GPU driver.
+ *
+ * The default UID is 0 ('root').
+ */
+
+#define __NV_DEVICE_FILE_UID DeviceFileUID
+#define NV_REG_DEVICE_FILE_UID NV_REG_STRING(__NV_DEVICE_FILE_UID)
+
+/*
+ * Option: DeviceFileGID
+ *
+ * Description:
+ *
+ * This registry key specifies the GID assigned to the NVIDIA device files
+ * created and/or modified by the NVIDIA driver when dynamic device file
+ * management is enabled.
+ *
+ * This module parameter is only honored by the NVIDIA GPU driver.
+ *
+ * The default GID is 0 ('root').
+ */
+
+#define __NV_DEVICE_FILE_GID DeviceFileGID
+#define NV_REG_DEVICE_FILE_GID NV_REG_STRING(__NV_DEVICE_FILE_GID)
+
+/*
+ * Option: DeviceFileMode
+ *
+ * Description:
+ *
+ * This registry key specifies the device file mode assigned to the NVIDIA
+ * device files created and/or modified by the NVIDIA driver when dynamic
+ * device file management is enabled.
+ *
+ * This module parameter is only honored by the NVIDIA GPU driver.
+ *
+ * The default mode is 0666 (octal, rw-rw-rw-).
+ */
+
+#define __NV_DEVICE_FILE_MODE DeviceFileMode
+#define NV_REG_DEVICE_FILE_MODE NV_REG_STRING(__NV_DEVICE_FILE_MODE)
+
+/*
+ * Option: ResmanDebugLevel
+ *
+ * Default value: ~0
+ */
+
+#define __NV_RESMAN_DEBUG_LEVEL ResmanDebugLevel
+#define NV_REG_RESMAN_DEBUG_LEVEL NV_REG_STRING(__NV_RESMAN_DEBUG_LEVEL)
+
+/*
+ * Option: RmLogonRC
+ *
+ * Default value: 1
+ */
+
+#define __NV_RM_LOGON_RC RmLogonRC
+#define NV_REG_RM_LOGON_RC NV_REG_STRING(__NV_RM_LOGON_RC)
+
+/*
+ * Option: InitializeSystemMemoryAllocations
+ *
+ * Description:
+ *
+ * The NVIDIA Linux driver normally clears system memory it allocates
+ * for use with GPUs or within the driver stack. This is to ensure
+ * that potentially sensitive data is not rendered accessible by
+ * arbitrary user applications.
+ *
+ * Owners of single-user systems or similar trusted configurations may
+ * choose to disable the aforementioned clears using this option and
+ * potentially improve performance.
+ *
+ * Possible values:
+ *
+ *  1 = zero out system memory allocations (default)
+ *  0 = do not perform memory clears
+ */
+
+#define __NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS \
+    InitializeSystemMemoryAllocations
+#define NV_REG_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS \
+    NV_REG_STRING(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS)
+
+/*
+ * Option: RegistryDwords
+ *
+ * Description:
+ *
+ * This option accepts a semicolon-separated list of key=value pairs. Each
+ * key name is checked against the table of static options; if a match is
+ * found, the static option value is overridden, but invalid options remain
+ * invalid. Pairs that do not match an entry in the static option table
+ * are passed on to the RM directly.
+ *
+ * Format:
+ *
+ *  NVreg_RegistryDwords="<key=value>;<key=value>;..."
+ */
+
+#define __NV_REGISTRY_DWORDS RegistryDwords
+#define NV_REG_REGISTRY_DWORDS NV_REG_STRING(__NV_REGISTRY_DWORDS)
+
+/*
+ * Option: RegistryDwordsPerDevice
+ *
+ * Description:
+ *
+ * This option allows to specify registry keys per GPU device. It helps to
+ * control registry at GPU level of granularity. It accepts a semicolon
+ * separated list of key=value pairs. The first key value pair MUST be
+ * "pci=DDDD:BB:DD.F;" where DDDD is Domain, BB is Bus Id, DD is device slot
+ * number and F is the Function. This PCI BDF is used to identify which GPU to
+ * assign the registry keys that follows next.
+ * If a GPU corresponding to the value specified in "pci=DDDD:BB:DD.F;" is NOT
+ * found, then all the registry keys that follows are skipped, until we find next
+ * valid pci identified "pci=DDDD:BB:DD.F;". Following are the valid formats for
+ * the value of the "pci" string:
+ * 1)  bus:slot                 : Domain and function defaults to 0.
+ * 2)  domain:bus:slot          : Function defaults to 0.
+ * 3)  domain:bus:slot.func     : Complete PCI dev id string.
+ *
+ * For each of the registry keys that follows, key name is checked against the
+ * table of static options; if a match is found, the static option value is
+ * overridden, but invalid options remain invalid. Pairs that do not match an
+ * entry in the static option table are passed on to the RM directly.
+ *
+ * Format:
+ *
+ *  NVreg_RegistryDwordsPerDevice="pci=DDDD:BB:DD.F;<key=value>;<key=value>;..; \
+ *               pci=DDDD:BB:DD.F;<key=value>;..;"
+ */
+
+#define __NV_REGISTRY_DWORDS_PER_DEVICE RegistryDwordsPerDevice
+#define NV_REG_REGISTRY_DWORDS_PER_DEVICE NV_REG_STRING(__NV_REGISTRY_DWORDS_PER_DEVICE)
+
+#define __NV_RM_MSG RmMsg
+#define NV_RM_MSG NV_REG_STRING(__NV_RM_MSG)
+
+/*
+ * Option: EnableMSI
+ *
+ * Description:
+ *
+ * When this option is enabled and the host kernel supports the MSI feature,
+ * the NVIDIA driver will enable the PCI-E MSI capability of GPUs with the
+ * support for this feature instead of using PCI-E wired interrupt.
+ *
+ * Possible Values:
+ *
+ *  0 = disable MSI interrupt
+ *  1 = enable MSI interrupt (default)
+ *
+ */
+
+#define __NV_ENABLE_MSI EnableMSI
+#define NV_REG_ENABLE_MSI NV_REG_STRING(__NV_ENABLE_MSI)
+
+/*
+ * Option: EnablePCIeGen3
+ *
+ * Description:
+ *
+ * Due to interoperability problems seen with Kepler PCIe Gen3 capable GPUs
+ * when configured on SandyBridge E desktop platforms, NVIDIA feels that
+ * delivering a reliable, high-quality experience is not currently possible in
+ * PCIe Gen3 mode on all PCIe Gen3 platforms. Therefore, Quadro, Tesla and
+ * NVS Kepler products operate in PCIe Gen2 mode by default. You may use this
+ * option to enable PCIe Gen3 support.
+ *
+ * This is completely unsupported!
+ *
+ * Possible Values:
+ *
+ *  0: disable PCIe Gen3 support (default)
+ *  1: enable PCIe Gen3 support
+ */
+
+#define __NV_ENABLE_PCIE_GEN3 EnablePCIeGen3
+#define NV_REG_ENABLE_PCIE_GEN3 NV_REG_STRING(__NV_ENABLE_PCIE_GEN3)
+
+/*
+ * Option: MemoryPoolSize
+ *
+ * Description:
+ *
+ * When set to a non-zero value, this option specifies the size of the
+ * memory pool, given as a multiple of 1 GB, created on VMware ESXi to
+ * satisfy any system memory allocations requested by the NVIDIA kernel
+ * module.
+ */
+
+#define __NV_MEMORY_POOL_SIZE MemoryPoolSize
+#define NV_REG_MEMORY_POOL_SIZE NV_REG_STRING(__NV_MEMORY_POOL_SIZE)
+
+/*
+ * Option: KMallocHeapMaxSize
+ *
+ * Description:
+ *
+ * When set to a non-zero value, this option specifies the maximum size of the
+ * heap memory space reserved for kmalloc operations. Given as a
+ * multiple of 1 MB created on VMware ESXi to satisfy any system memory
+ * allocations requested by the NVIDIA kernel module.
+ */
+
+#define __NV_KMALLOC_HEAP_MAX_SIZE KMallocHeapMaxSize
+#define NV_KMALLOC_HEAP_MAX_SIZE NV_REG_STRING(__NV_KMALLOC_HEAP_MAX_SIZE)
+
+/*
+ * Option: VMallocHeapMaxSize
+ *
+ * Description:
+ *
+ * When set to a non-zero value, this option specifies the maximum size of the
+ * heap memory space reserved for vmalloc operations. Given as a
+ * multiple of 1 MB created on VMware ESXi to satisfy any system memory
+ * allocations requested by the NVIDIA kernel module.
+ */
+
+#define __NV_VMALLOC_HEAP_MAX_SIZE VMallocHeapMaxSize
+#define NV_VMALLOC_HEAP_MAX_SIZE NV_REG_STRING(__NV_VMALLOC_HEAP_MAX_SIZE)
+
+/*
+ * Option: IgnoreMMIOCheck
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA kernel module will ignore
+ * MMIO limit check during device probe on VMWare ESXi kernel. This is
+ * typically necessary when VMware ESXi MMIO limit differs between any
+ * base version and its updates. Customer using updates can set regkey
+ * to avoid probe failure.
+ */
+
+#define __NV_IGNORE_MMIO_CHECK IgnoreMMIOCheck
+#define NV_REG_IGNORE_MMIO_CHECK NV_REG_STRING(__NV_IGNORE_MMIO_CHECK)
+
+/*
+ * Option: pci
+ *
+ * Description:
+ *
+ * On Unix platforms, per GPU based registry key can be specified as:
+ * NVreg_RegistryDwordsPerDevice="pci=DDDD:BB:DD.F,<per-gpu registry keys>".
+ * where DDDD:BB:DD.F refers to Domain:Bus:Device.Function.
+ * We need this key "pci" to identify what follows next is a PCI BDF identifier,
+ * for which the registry keys are to be applied.
+ *
+ * This define is not used on non-UNIX platforms.
+ *
+ * Possible Formats for value:
+ *
+ * 1)  bus:slot                 : Domain and function defaults to 0.
+ * 2)  domain:bus:slot          : Function defaults to 0.
+ * 3)  domain:bus:slot.func     : Complete PCI BDF identifier string.
+ */
+#define __NV_PCI_DEVICE_BDF pci
+#define NV_REG_PCI_DEVICE_BDF NV_REG_STRING(__NV_PCI_DEVICE_BDF)
+
+/*
+ * Option: EnableStreamMemOPs
+ *
+ * Description:
+ *
+ * When this option is enabled, the CUDA driver will enable support for
+ * CUDA Stream Memory Operations in user-mode applications, which are so
+ * far required to be disabled by default due to limited support in
+ * devtools.
+ *
+ * Note: this is treated as a hint. MemOPs may still be left disabled by CUDA
+ * driver for other reasons.
+ *
+ * Possible Values:
+ *
+ *  0 = disable feature (default)
+ *  1 = enable feature
+ */
+#define __NV_ENABLE_STREAM_MEMOPS EnableStreamMemOPs
+#define NV_REG_ENABLE_STREAM_MEMOPS NV_REG_STRING(__NV_ENABLE_STREAM_MEMOPS)
+
+/*
+ * Option: EnableUserNUMAManagement
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA kernel module will require the
+ * user-mode NVIDIA Persistence daemon to manage the onlining and offlining
+ * of its NUMA device memory.
+ *
+ * This option has no effect on platforms that do not support onlining
+ * device memory to a NUMA node (this feature is only supported on certain
+ * POWER9 systems).
+ *
+ * Possible Values:
+ *
+ *  0: disable user-mode NUMA management
+ *  1: enable user-mode NUMA management (default)
+ */
+#define __NV_ENABLE_USER_NUMA_MANAGEMENT EnableUserNUMAManagement
+#define NV_REG_ENABLE_USER_NUMA_MANAGEMENT NV_REG_STRING(__NV_ENABLE_USER_NUMA_MANAGEMENT)
+
+/*
+ * Option: CoherentGPUMemoryMode
+ *
+ * Description:
+ *
+ * This option can be set to control how GPU Memory is accessed through
+ * the coherent link. 
+ *
+ * This option has no effect on platforms that do not support onlining
+ * device memory to a NUMA node.
+ *
+ * Possible string values:
+ *
+ *  "driver" : disable onlining coherent memory to the OS as a NUMA node. The driver
+ *             will manage it in this case
+ *  "numa" (or unset) : enable onlining coherent memory to the OS as a NUMA node (default)
+ */
+#define __NV_COHERENT_GPU_MEMORY_MODE CoherentGPUMemoryMode
+#define NV_REG_COHERENT_GPU_MEMORY_MODE NV_REG_STRING(__NV_COHERENT_GPU_MEMORY_MODE)
+
+/*
+ * Option: GpuBlacklist
+ *
+ * Description:
+ *
+ * This option accepts a list of blacklisted GPUs, separated by commas, that
+ * cannot be attached or used. Each blacklisted GPU is identified by a UUID in
+ * the ASCII format with leading "GPU-". An exact match is required; no partial
+ * UUIDs. This regkey is deprecated and will be removed in the future. Use
+ * NV_REG_EXCLUDED_GPUS instead.
+ */
+#define __NV_GPU_BLACKLIST GpuBlacklist
+#define NV_REG_GPU_BLACKLIST NV_REG_STRING(__NV_GPU_BLACKLIST)
+
+/*
+ * Option: ExcludedGpus
+ *
+ * Description:
+ *
+ * This option accepts a list of excluded GPUs, separated by commas, that
+ * cannot be attached or used. Each excluded GPU is identified by a UUID in
+ * the ASCII format with leading "GPU-". An exact match is required; no partial
+ * UUIDs.
+ */
+#define __NV_EXCLUDED_GPUS ExcludedGpus
+#define NV_REG_EXCLUDED_GPUS NV_REG_STRING(__NV_EXCLUDED_GPUS)
+
+/*
+ * Option: NVreg_ExcludeAllGpus
+ *
+ * Description:
+ *
+ * This option allows the user to exclude all GPUs. If used in conjunction with
+ * UUID based GPU exclusion, all GPUs will be excluded
+ *
+ * Possible values:
+ * 1 - Excludes all GPUs from being attached or used
+ * 0 - No effect (default)
+ */
+ #define __NV_EXCLUDE_ALL_GPUS ExcludeAllGpus
+ #define NV_EXCLUDE_ALL_GPUS NV_REG_STRING(__NV_EXCLUDE_ALL_GPUS)
+ #define NV_EXCLUDE_ALL_GPUS_DEFAULT 0
+
+/*
+ * Option: NvLinkDisable
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA kernel module will not attempt to
+ * initialize or train NVLink connections for any GPUs. System reboot is required
+ * for changes to take affect.
+ *
+ * This option has no effect if no GPUs support NVLink.
+ *
+ * Possible Values:
+ *
+ *  0: Do not disable NVLink (default)
+ *  1: Disable NVLink
+ */
+#define __NV_NVLINK_DISABLE NvLinkDisable
+#define NV_REG_NVLINK_DISABLE NV_REG_STRING(__NV_NVLINK_DISABLE)
+
+/*
+ * Option: RestrictProfilingToAdminUsers
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA kernel module will prevent users
+ * without administrative access (i.e., the CAP_SYS_ADMIN capability) from
+ * using GPU performance counters.
+ *
+ * Possible Values:
+ *
+ * 0: Do not restrict GPU counters (default)
+ * 1: Restrict GPU counters to system administrators only
+ */
+
+#define __NV_RM_PROFILING_ADMIN_ONLY RmProfilingAdminOnly
+#define __NV_RM_PROFILING_ADMIN_ONLY_PARAMETER RestrictProfilingToAdminUsers
+#define NV_REG_RM_PROFILING_ADMIN_ONLY NV_REG_STRING(__NV_RM_PROFILING_ADMIN_ONLY)
+
+
+/*
+* Option: EnableDebuggerInterface
+* 
+* Description:
+*
+* When this option is enabled, the NVIDIA kernel module will allow non-administrator users to 
+* create a non-preemptable debugger session for non-CILP contexts.
+*
+* Possible Values:
+*
+*  0: Do not allow non-administrator users to create non-preemptable debugger sessions (default)
+*  1: Allow non-administrator users to create non-preemptable debugger sessions
+*/
+#define __NV_ENABLE_NON_PREEMTABLE_DEBUGGER_SESSION EnableDebuggerInterface
+#define NV_REG_ENABLE_NON_PREEMTABLE_DEBUGGER_SESSION NV_REG_STRING(__NV_ENABLE_NON_PREEMTABLE_DEBUGGER_SESSION)
+
+/*
+ * Option: TemporaryFilePath
+ *
+ * Description:
+ *
+ * When specified, this option changes the location in which the
+ * NVIDIA kernel module will create unnamed temporary files (e.g. to
+ * save the contents of video memory in).  The indicated file must
+ * be a directory.  By default, temporary files are created in /tmp.
+ */
+#define __NV_TEMPORARY_FILE_PATH TemporaryFilePath
+#define NV_REG_TEMPORARY_FILE_PATH NV_REG_STRING(__NV_TEMPORARY_FILE_PATH)
+
+/*
+ * Option: PreserveVideoMemoryAllocations
+ *
+ * If enabled, this option prompts the NVIDIA kernel module to save and
+ * restore all video memory allocations across system power management
+ * cycles, i.e. suspend/resume and hibernate/restore.  Otherwise,
+ * only select allocations are preserved.
+ *
+ * Possible Values:
+ *
+ *  0: Preserve only select video memory allocations
+ *  1: Preserve all video memory allocations
+ *  2: Automatically enable video memory allocations when
+ *     NVreg_UseKernelSuspendNotifiers is enabled (default)
+ */
+#define __NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS PreserveVideoMemoryAllocations
+#define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS \
+    NV_REG_STRING(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS)
+
+#define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS_DISABLED    0
+#define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS_ENABLED     1
+#define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS_AUTO        2
+
+/*
+ * Option: UseKernelSuspendNotifiers
+ *
+ * If enabled, this option prompts the NVIDIA kernel module to register a
+ * notifier that saves and restores all video memory allocations across system
+ * power management cycles if PreserveVideoMemoryAllocations is enabled.
+ *
+ * Possible Values:
+ *
+ *  0: Suspend notifiers are not used (default)
+ *  1: Suspend notifiers are used when available
+ */
+
+#define __NV_USE_KERNEL_SUSPEND_NOTIFIERS UseKernelSuspendNotifiers
+#define NV_REG_USE_KERNEL_SUSPEND_NOTIFIERS \
+    NV_REG_STRING(__NV_USE_KERNEL_SUSPEND_NOTIFIERS)
+
+/*
+ * Option: EnableS0ixPowerManagement
+ *
+ * When this option is enabled, the NVIDIA driver will use S0ix-based
+ * power management for system suspend/resume, if both the platform and
+ * the GPU support S0ix.
+ *
+ * During system suspend, if S0ix is enabled and
+ * video memory usage is above the threshold configured by
+ * 'S0ixPowerManagementVideoMemoryThreshold', video memory will be kept
+ * in self-refresh mode while the rest of the GPU is powered down.
+ *
+ * Otherwise, the driver will copy video memory contents to system memory
+ * and power off the video memory along with the GPU.
+ *
+ * Possible Values:
+ *
+ *  0: Disable S0ix based power management (default)
+ *  1: Enable S0ix based power management
+ */
+
+#define __NV_ENABLE_S0IX_POWER_MANAGEMENT EnableS0ixPowerManagement
+#define NV_REG_ENABLE_S0IX_POWER_MANAGEMENT \
+    NV_REG_STRING(__NV_ENABLE_S0IX_POWER_MANAGEMENT)
+
+/*
+ * Option: S0ixPowerManagementVideoMemoryThreshold
+ *
+ * This option controls the threshold that the NVIDIA driver will use during
+ * S0ix-based system power management.
+ *
+ * When S0ix is enabled and the system is suspended, the driver will
+ * compare the amount of video memory in use with this threshold,
+ * to decide whether to keep video memory in self-refresh or copy video
+ * memory content to system memory.
+ *
+ * See the 'EnableS0ixPowerManagement' option.
+ *
+ * Values are expressed in Megabytes (1048576 bytes).
+ *
+ * Default value for this option is 256MB.
+ *
+ */
+#define __NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \
+    S0ixPowerManagementVideoMemoryThreshold
+#define NV_REG_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \
+    NV_REG_STRING(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD)
+
+/*
+ * Option: DynamicPowerManagement
+ *
+ * This option controls how aggressively the NVIDIA kernel module will manage
+ * GPU power through kernel interfaces.
+ *
+ * Possible Values:
+ *
+ *  0: Never allow the GPU to be powered down (default).
+ *  1: Power down the GPU when it is not initialized.
+ *  2: Power down the GPU after it has been inactive for some time.
+ *  3: (Default) Power down the GPU after a period of inactivity (i.e.,
+ *     mode 2) on Ampere or later notebooks.  Otherwise, do not power down
+ *     the GPU.
+ */
+#define __NV_DYNAMIC_POWER_MANAGEMENT DynamicPowerManagement
+#define NV_REG_DYNAMIC_POWER_MANAGEMENT \
+    NV_REG_STRING(__NV_DYNAMIC_POWER_MANAGEMENT)
+
+#define NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER   0
+#define NV_REG_DYNAMIC_POWER_MANAGEMENT_COARSE  1
+#define NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE    2
+#define NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT 3
+
+/*
+ * Option: DynamicPowerManagementVideoMemoryThreshold
+ *
+ * This option controls the threshold that the NVIDIA driver will use
+ * when selecting the dynamic power management scheme.
+ *
+ * When the driver detects that the GPU is idle, it will compare the amount
+ * of video memory in use with this threshold.
+ *
+ * If the current video memory usage is less than the threshold, the
+ * driver may preserve video memory contents in system memory and power off
+ * the video memory along with the GPU itself, if supported.  Otherwise,
+ * the video memory will be kept in self-refresh mode while powering down
+ * the rest of the GPU, if supported.
+ *
+ * Values are expressed in Megabytes (1048576 bytes).
+ *
+ * If the requested value is greater than 200MB (the default), then it
+ * will be capped to 200MB.
+ */
+#define __NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \
+    DynamicPowerManagementVideoMemoryThreshold
+#define NV_REG_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \
+    NV_REG_STRING(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD)
+
+/*
+ * Option: TegraGpuPgMask
+ *
+ * This option controls the TPC/GPC/FBP power-gating mask for Tegra iGPU.
+ *
+ */
+#define __NV_TEGRA_GPU_PG_MASK TegraGpuPgMask
+#define NV_REG_TEGRA_GPU_PG_MASK \
+    NV_REG_STRING(__NV_TEGRA_GPU_PG_MASK)
+
+/*
+ * Option: RegisterPCIDriver
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA driver will register with
+ * PCI subsystem.
+ *
+ * Possible values:
+ *
+ *  1 - register as PCI driver (default)
+ *  0 - do not register as PCI driver
+ */
+
+#define __NV_REGISTER_PCI_DRIVER  RegisterPCIDriver
+#define NV_REG_REGISTER_PCI_DRIVER NV_REG_STRING(__NV_REGISTER_PCI_DRIVER)
+
+/*
+ * Option: RegisterPlatformDeviceDriver
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA driver will register with
+ * platform subsystem.
+ *
+ * Possible values:
+ *
+ *  1 - register as platform driver (default)
+ *  0 - do not register as platform driver
+ */
+
+#define __NV_REGISTER_PLATFORM_DEVICE_DRIVER  RegisterPlatformDeviceDriver
+#define NV_REG_REGISTER_PLATFORM_DEVICE_DRIVER NV_REG_STRING(__NV_REGISTER_PLATFORM_DEVICE_DRIVER)
+
+/*
+ * Option: EnablePCIERelaxedOrderingMode
+ *
+ * Description:
+ *
+ * When this option is enabled, the registry key RmSetPCIERelaxedOrdering will
+ * be set to NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_FORCE_ENABLE, causing
+ * every device to set the relaxed ordering bit to 1 in all outbound MWr
+ * transaction-layer packets. This is equivalent to setting the regkey to
+ * FORCE_ENABLE as a non-per-device registry key.
+ *
+ * Possible values:
+ *  0 - Do not enable PCIe TLP relaxed ordering bit-setting (default)
+ *  1 - Enable PCIe TLP relaxed ordering bit-setting
+ */
+#define  __NV_ENABLE_PCIE_RELAXED_ORDERING_MODE EnablePCIERelaxedOrderingMode
+#define NV_REG_ENABLE_PCIE_RELAXED_ORDERING_MODE \
+    NV_REG_STRING(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE)
+
+/*
+ * Option: EnableResizableBar
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA driver will attempt to resize
+ * BAR1 to match framebuffer size, or the next largest available size on
+ * supported machines. This is currently only implemented for Linux.
+ *
+ * Possible values:
+ *  0 - Do not enable PCI BAR resizing
+ *  1 - Enable PCI BAR resizing
+ */
+#define __NV_ENABLE_RESIZABLE_BAR EnableResizableBar
+#define NV_REG_ENABLE_RESIZABLE_BAR NV_REG_STRING(__NV_ENABLE_RESIZABLE_BAR)
+
+/*
+ * Option: EnableGpuFirmware
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA driver will enable use of GPU
+ * firmware.
+ *
+ * If this key is set globally to the system, the driver may still attempt
+ * to apply some policies to maintain uniform firmware modes across all
+ * GPUS.  This may result in the driver failing initialization on some GPUs
+ * to maintain such a policy.
+ *
+ * If this key is set using NVreg_RegistryDwordsPerDevice, then the driver 
+ * will attempt to honor whatever configuration is specified without applying
+ * additional policies.  This may also result in failed GPU initialzations if
+ * the configuration is not possible (for example if the firmware is missing 
+ * from the filesystem, or the GPU is not capable).
+ *
+ * NOTE: More details for this regkey can be found in nv-firmware-registry.h
+ */
+#define __NV_ENABLE_GPU_FIRMWARE  EnableGpuFirmware
+#define NV_REG_ENABLE_GPU_FIRMWARE NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE)
+
+/*
+ * Option: EnableGpuFirmwareLogs
+ *
+ * When this option is enabled, the NVIDIA driver will send GPU firmware logs
+ * to the system log, when possible.
+ *
+ * NOTE: More details for this regkey can be found in nv-firmware-registry.h
+ */
+#define __NV_ENABLE_GPU_FIRMWARE_LOGS  EnableGpuFirmwareLogs
+#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE_LOGS)
+
+/*
+ * Option: EnableDbgBreakpoint
+ *
+ * When this option is set to a non-zero value, and the kernel is configured
+ * appropriately, assertions within resman will trigger a CPU breakpoint (e.g.,
+ * INT3 on x86_64), assumed to be caught by an attached debugger.
+ *
+ * When this option is set to the value zero (the default), assertions within
+ * resman will print to the system log, but no CPU breakpoint will be triggered.
+ */
+#define __NV_ENABLE_DBG_BREAKPOINT EnableDbgBreakpoint
+
+
+/*
+ * Option: OpenRmEnableUnsupportedGpus
+ *
+ * This option to require opt in for use of Open RM on non-Data Center
+ * GPUs is deprecated and no longer required. The kernel module parameter
+ * is left here, though ignored, for backwards compatibility.
+ */
+#define __NV_OPENRM_ENABLE_UNSUPPORTED_GPUS OpenRmEnableUnsupportedGpus
+
+/*
+ * Option: NVreg_DmaRemapPeerMmio
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA driver will use device driver
+ * APIs provided by the Linux kernel for DMA-remapping part of a device's
+ * MMIO region to another device, creating e.g., IOMMU mappings as necessary.
+ * When this option is disabled, the NVIDIA driver will instead only apply a
+ * fixed offset, which may be zero, to CPU physical addresses to produce the
+ * DMA address for the peer's MMIO region, and no IOMMU mappings will be
+ * created.
+ *
+ * This option only affects peer MMIO DMA mappings, and not system memory
+ * mappings.
+ *
+ * Possible Values:
+ *  0 = disable dynamic DMA remapping of peer MMIO regions
+ *  1 = enable dynamic DMA remapping of peer MMIO regions (default)
+ */
+#define __NV_DMA_REMAP_PEER_MMIO DmaRemapPeerMmio
+#define NV_DMA_REMAP_PEER_MMIO NV_REG_STRING(__NV_DMA_REMAP_PEER_MMIO)
+#define NV_DMA_REMAP_PEER_MMIO_DISABLE  0x00000000
+#define NV_DMA_REMAP_PEER_MMIO_ENABLE   0x00000001
+
+/*
+ * Option: NVreg_RmNvlinkBandwidthLinkCount
+ *
+ * Description:
+ *
+ * This option allows user to reduce the GPU nvlink bandwidth to save power.
+ *
+ * This option is only for Blackwell+ GPU with NVLINK version 5.0.
+ */
+#define __NV_RM_NVLINK_BW_LINK_COUNT RmNvlinkBandwidthLinkCount
+#define NV_RM_NVLINK_BW_LINK_COUNT NV_REG_STRING(__NV_RM_NVLINK_BW_LINK_COUNT)
+
+/*
+ * Option: NVreg_RmNvlinkBandwidth
+ *
+ * Description:
+ *
+ * This option allows user to reduce the NVLINK P2P bandwidth to save power.
+ * The option is in the string format.
+ *
+ * Possible string values:
+ *   OFF:      0% bandwidth
+ *   MIN:      15%-25% bandwidth depending on the system's NVLink topology
+ *   HALF:     50% bandwidth
+ *   3QUARTER: 75% bandwidth
+ *   FULL:     100% bandwidth (default)
+ *
+ * This option is only for Hopper+ GPU with NVLINK version 4.0.
+ */
+#define __NV_RM_NVLINK_BW RmNvlinkBandwidth
+#define NV_RM_NVLINK_BW NV_REG_STRING(__NV_RM_NVLINK_BW)
+
+/*
+ * Option: NVreg_EnableNonblockingOpen
+ *
+ * Description:
+ *
+ * When this option is enabled, the NVIDIA driver will try to perform any
+ * required device initialization in the background when /dev/nvidiaN devices
+ * are opened with the flag O_NONBLOCK.
+ *
+ * Possible Values:
+ *  0 = O_NONBLOCK flag when opening devices is ignored
+ *  1 = O_NONBLOCK flag when opening devices results in background device
+ *      initialization (default)
+ */
+#define __NV_ENABLE_NONBLOCKING_OPEN EnableNonblockingOpen
+#define NV_ENABLE_NONBLOCKING_OPEN NV_REG_STRING(__NV_ENABLE_NONBLOCKING_OPEN)
+
+/*
+ * Option: NVreg_ImexChannelCount
+ *
+ * Description:
+ *
+ * This option allows users to specify the number of IMEX (import/export)
+ * channels. Within an IMEX domain, the channels allow sharing memory
+ * securely in a multi-user environment using the CUDA driver's fabric handle
+ * based APIs.
+ *
+ * An IMEX domain is either an OS instance or a group of securely
+ * connected OS instances using the NVIDIA IMEX daemon. The option must
+ * be set to the same value on each OS instance within the IMEX domain.
+ *
+ * An IMEX channel is a logical entity that is represented by a /dev node.
+ * The IMEX channels are global resources within the IMEX domain. When
+ * exporter and importer CUDA processes have been granted access to the
+ * same IMEX channel, they can securely share memory.
+ *
+ * Note that the NVIDIA driver will not attempt to create the /dev nodes. Thus,
+ * the related CUDA APIs will fail with an insufficient permission error until
+ * the /dev nodes are set up. The creation of these /dev nodes,
+ * /dev/nvidia-caps-imex-channels/channelN, must be handled by the
+ * administrator, where N is the minor number. The major number can be
+ * queried from /proc/devices.
+ *
+ * nvidia-modprobe CLI support is available to set up the /dev nodes.
+ * NVreg_ModifyDeviceFiles, NVreg_DeviceFileGID, NVreg_DeviceFileUID
+ * and NVreg_DeviceFileMode will be honored by nvidia-modprobe.
+ *
+ * Also, refer to the NVreg_CreateImexChannel0 option.
+ *
+ * Possible values:
+ *  0 - Disable IMEX using CUDA driver's fabric handles.
+ *  N - N IMEX channels will be enabled in the driver to facilitate N
+ *      concurrent users. Default value is 2048 channels, and the current
+ *      maximum value is 20-bit, same as Linux dev_t's minor number limit.
+ */
+#define __NV_IMEX_CHANNEL_COUNT ImexChannelCount
+#define NV_REG_IMEX_CHANNEL_COUNT NV_REG_STRING(__NV_IMEX_CHANNEL_COUNT)
+
+/*
+ * Option: NVreg_CreateImexChannel0
+ *
+ * Description:
+ *
+ * This option allows users to specify whether the NVIDIA driver must create
+ * the IMEX channel 0 by default. The channel will be created automatically
+ * when the NVIDIA open GPU kernel module is loaded.
+ *
+ * Note that users are advised to enable this option only in trusted
+ * environments where it is acceptable for applications to share the same
+ * IMEX channel.
+ *
+ * For more details on IMEX channels, refer to the NVreg_ImexChannelCount
+ * option.
+ *
+ * Possible values:
+ *  0 - Do not create IMEX channel 0 (default).
+ *  1 - Create IMEX channel 0.
+ */
+#define __NV_CREATE_IMEX_CHANNEL_0 CreateImexChannel0
+#define NV_CREATE_IMEX_CHANNEL_0 NV_REG_STRING(__CREATE_IMEX_CHANNEL_0)
+
+/*
+ * Option: NVreg_EnableSystemMemoryPools
+ *
+ * Description:
+ *
+ * This option controls system memory page pools creation for different page sizes
+ * Pool for pageSize is enabled by setting bit (pageSize >> NV_ENABLE_SYSTEM_MEMORY_POOLS_SHIFT)
+ * The pools keep memory cached once freed to speed-up reallocation
+ * Pools are shared by all adapters
+ *
+ * This feature is only supported by OpenRM driver
+ *
+ * By default 4K, 64K, 2M page size pools are enabled
+ */
+#define __NV_ENABLE_SYSTEM_MEMORY_POOLS EnableSystemMemoryPools
+#define NV_ENABLE_SYSTEM_MEMORY_POOLS NV_REG_STRING(__NV_ENABLE_SYSTEM_MEMORY_POOLS)
+#define NV_ENABLE_SYSTEM_MEMORY_POOLS_DEFAULT 0x00000211
+#define NV_ENABLE_SYSTEM_MEMORY_POOLS_SHIFT 12
+
+/*
+ * Option: NVreg_OsEnableCxlSupport
+ *
+ * Description:
+ *
+ * When this option is enabled, the driver will enable support for
+ * CXL at the OS layer.
+ *
+ * This option has no effect on platforms that do not support CXL or on
+ * GPUs without CXL capability.
+ *
+ * Possible Values:
+ *
+ *  0: disable CXL support
+ *  1: enable CXL support (default)
+ */
+#define __NV_OS_ENABLE_CXL_SUPPORT OsEnableCxlSupport
+#define NV_REG_OS_ENABLE_CXL_SUPPORT NV_REG_STRING(__NV_OS_ENABLE_CXL_SUPPORT)
+
+/*
+ * Option: NVreg_GpuInitOnProbe
+ *
+ * Description:
+ *
+ * This option allows the user to control initialization of the GPU at PCI probe time
+ *
+ * Possible values:
+ * 0 - Disable initializing the GPUs on PCI probe
+ * 1 - Initialize GPUs on PCI probe
+ */
+ #define __NV_GPU_INIT_ON_PROBE GpuInitOnProbe
+ #define NV_GPU_INIT_ON_PROBE NV_REG_STRING(__NV_GPU_INIT_ON_PROBE)
+ #define NV_GPU_INIT_ON_PROBE_DEFAULT 0
+
+#if defined(NV_DEFINE_REGISTRY_KEY_TABLE)
+
+/*
+ *---------registry key parameter declarations--------------
+ */
+
+NV_DEFINE_REG_ENTRY(__NV_RESMAN_DEBUG_LEVEL, ~0);
+NV_DEFINE_REG_ENTRY(__NV_RM_LOGON_RC, 1);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MODIFY_DEVICE_FILES, 1);
+NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_UID, 0);
+NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_GID, 0);
+NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_MODE, 0666);
+NV_DEFINE_REG_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, 1);
+NV_DEFINE_REG_ENTRY(__NV_ENABLE_PCIE_GEN3, 0);
+NV_DEFINE_REG_ENTRY(__NV_ENABLE_MSI, 1);
+NV_DEFINE_REG_ENTRY(__NV_ENABLE_STREAM_MEMOPS, 0);
+NV_DEFINE_REG_ENTRY(__NV_RM_PROFILING_ADMIN_ONLY_PARAMETER, 1);
+NV_DEFINE_REG_ENTRY(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS,
+                    NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS_AUTO);
+NV_DEFINE_REG_ENTRY(__NV_ENABLE_S0IX_POWER_MANAGEMENT, 0);
+NV_DEFINE_REG_ENTRY(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 256);
+NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT, 3);
+NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 200);
+NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE, NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE);
+NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS, NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG);
+NV_DEFINE_REG_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS, 1);
+
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_USER_NUMA_MANAGEMENT, 1);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MEMORY_POOL_SIZE, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_KMALLOC_HEAP_MAX_SIZE, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_VMALLOC_HEAP_MAX_SIZE, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_IGNORE_MMIO_CHECK, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_NVLINK_DISABLE, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PCI_DRIVER, 1);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PLATFORM_DEVICE_DRIVER, 1);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_RESIZABLE_BAR, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_DBG_BREAKPOINT, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_TEGRA_GPU_PG_MASK, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_NONBLOCKING_OPEN, 1);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_EXCLUDE_ALL_GPUS, NV_EXCLUDE_ALL_GPUS_DEFAULT);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_GPU_INIT_ON_PROBE, NV_GPU_INIT_ON_PROBE_DEFAULT);
+
+NV_DEFINE_REG_STRING_ENTRY(__NV_COHERENT_GPU_MEMORY_MODE, NULL);
+NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL);
+NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS_PER_DEVICE, NULL);
+NV_DEFINE_REG_STRING_ENTRY(__NV_RM_MSG, NULL);
+NV_DEFINE_REG_STRING_ENTRY(__NV_GPU_BLACKLIST, NULL);
+NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL);
+NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL);
+NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE);
+NV_DEFINE_REG_STRING_ENTRY(__NV_RM_NVLINK_BW, NULL);
+NV_DEFINE_REG_ENTRY(__NV_RM_NVLINK_BW_LINK_COUNT, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_IMEX_CHANNEL_COUNT, 2048);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_CREATE_IMEX_CHANNEL_0, 0);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_SYSTEM_MEMORY_POOLS, NV_ENABLE_SYSTEM_MEMORY_POOLS_DEFAULT);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_OS_ENABLE_CXL_SUPPORT, 1);
+NV_DEFINE_REG_ENTRY_GLOBAL(__NV_USE_KERNEL_SUSPEND_NOTIFIERS, 0);
+NV_DEFINE_REG_ENTRY(__NV_ENABLE_NON_PREEMTABLE_DEBUGGER_SESSION, 0);
+/*
+ *----------------registry database definition----------------------
+ */
+
+/*
+ * You can enable any of the registry options disabled by default by
+ * editing their respective entries in the table below. The last field
+ * determines if the option is considered valid - in order for the
+ * changes to take effect, you need to recompile and reload the NVIDIA
+ * kernel module.
+ */
+nv_parm_t nv_parms[] = {
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RESMAN_DEBUG_LEVEL),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RM_LOGON_RC),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MODIFY_DEVICE_FILES),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_UID),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_GID),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_MODE),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_MSI),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_GEN3),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MEMORY_POOL_SIZE),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_KMALLOC_HEAP_MAX_SIZE),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_VMALLOC_HEAP_MAX_SIZE),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_IGNORE_MMIO_CHECK),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_STREAM_MEMOPS),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_USER_NUMA_MANAGEMENT),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_NVLINK_DISABLE),
+    NV_DEFINE_PARAMS_TABLE_ENTRY_CUSTOM_NAME(__NV_RM_PROFILING_ADMIN_ONLY,
+        __NV_RM_PROFILING_ADMIN_ONLY_PARAMETER),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_KERNEL_SUSPEND_NOTIFIERS),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_S0IX_POWER_MANAGEMENT),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_TEGRA_GPU_PG_MASK),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_PCI_DRIVER),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_RESIZABLE_BAR),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RM_NVLINK_BW_LINK_COUNT),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DMA_REMAP_PEER_MMIO),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_IMEX_CHANNEL_COUNT),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_CREATE_IMEX_CHANNEL_0),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_SYSTEM_MEMORY_POOLS),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_OS_ENABLE_CXL_SUPPORT),
+    NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_NON_PREEMTABLE_DEBUGGER_SESSION),
+    {NULL, NULL}
+};
+
+#elif defined(NVRM)
+
+extern nv_parm_t nv_parms[];
+
+#endif /* NV_DEFINE_REGISTRY_KEY_TABLE */
+
+#endif /* _RM_REG_H_ */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h
new file mode 100644
index 0000000..02b0156
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h
@@ -0,0 +1,49 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _NV_UNIX_NVOS_PARAMS_WRAPPERS_H_
+#define _NV_UNIX_NVOS_PARAMS_WRAPPERS_H_
+
+#include <nvos.h>
+
+/*
+ * This is a wrapper for NVOS02_PARAMETERS with file descriptor
+ */
+
+typedef struct
+{
+    NVOS02_PARAMETERS params;
+    int fd;
+} nv_ioctl_nvos02_parameters_with_fd;
+
+/*
+ * This is a wrapper for NVOS33_PARAMETERS with file descriptor
+ */
+typedef struct
+{
+    NVOS33_PARAMETERS params;
+    int fd;
+} nv_ioctl_nvos33_parameters_with_fd;
+
+#endif // _NV_UNIX_NVOS_PARAMS_WRAPPERS_H_
+
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv.h b/userspace/sdks/nv570/nvalloc/unix/include/nv.h
new file mode 100644
index 0000000..d8db166
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv.h
@@ -0,0 +1,1367 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _NV_H_
+#define _NV_H_
+
+
+
+#include <nvlimits.h>
+
+#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(__FreeBSD__)
+  #include <sys/stddef.h>   // NULL
+#elif defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX)
+  #include <linux/stddef.h> // NULL
+#else
+  #include <stddef.h>       // NULL
+#endif
+
+#include <nvstatus.h>
+#include "nv_stdarg.h"
+#include <nv-caps.h>
+#include <nv-firmware.h>
+#include <nv-ioctl.h>
+#include <nv-ioctl-numa.h>
+#include <nvmisc.h>
+#include <os/nv_memory_area.h>
+
+#if !defined(NV_KERNEL_INTERFACE_LAYER) && defined(NVRM) && !defined(NV_DRM_FREEBSD_LKPI)
+#include <nvport/nvport.h>
+#else
+#define PORT_ATOMIC
+#endif
+
+extern nv_cap_t *nvidia_caps_root;
+
+extern const NvBool nv_is_rm_firmware_supported_os;
+
+#include <nvi2c.h>
+#include <nvimpshared.h>
+
+#include <nv-kernel-interface-api.h>
+
+#define GPU_UUID_LEN    (16)
+
+/*
+ * Buffer size for an ASCII UUID: We need 2 digits per byte, plus space
+ * for "GPU", 5 dashes, and '\0' termination:
+ */
+#define GPU_UUID_ASCII_LEN  (GPU_UUID_LEN * 2 + 9)
+
+/*
+ * #define an absolute maximum used as a sanity check for the
+ * NV_ESC_IOCTL_XFER_CMD ioctl() size argument.
+ */
+#define NV_ABSOLUTE_MAX_IOCTL_SIZE  16384
+
+/*
+ * Solaris provides no more than 8 bits for the argument size in
+ * the ioctl() command encoding; make sure we don't exceed this
+ * limit.
+ */
+#define __NV_IOWR_ASSERT(type) ((sizeof(type) <= NV_PLATFORM_MAX_IOCTL_SIZE) ? 1 : -1)
+#define __NV_IOWR(nr, type) ({                                        \
+    typedef char __NV_IOWR_TYPE_SIZE_ASSERT[__NV_IOWR_ASSERT(type)];  \
+    _IOWR(NV_IOCTL_MAGIC, (nr), type);                                \
+})
+
+#define NV_PCI_DEV_FMT          "%04x:%02x:%02x.%x"
+#define NV_PCI_DEV_FMT_ARGS(nv) (nv)->pci_info.domain, (nv)->pci_info.bus, \
+                                (nv)->pci_info.slot, (nv)->pci_info.function
+
+#define NV_RM_DEVICE_INTR_ADDRESS 0x100
+
+#define NV_TEGRA_PCI_IGPU_PG_MASK_DEFAULT 0xFFFFFFFF
+
+/*
+ * Clock domain identifier, which is used for fetching the engine
+ * load backed by the specified clock domain for Tegra platforms
+ * conforming linux devfreq framework to realize dynamic frequency
+ * scaling.
+ */
+typedef enum _TEGRASOC_DEVFREQ_CLK
+{
+    TEGRASOC_DEVFREQ_CLK_GPC,
+    TEGRASOC_DEVFREQ_CLK_NVD,
+} TEGRASOC_DEVFREQ_CLK;
+
+/*!
+ * @brief The order of the display clocks in the below defined enum
+ * should be synced with below mapping array and macro.
+ * All four should be updated simultaneously in case
+ * of removal or addition of clocks in below order.
+ * Also, TEGRASOC_WHICH_CLK_MAX is used in various places
+ * in below mentioned files.
+ * arch/nvalloc/unix/Linux/nv-linux.h
+ *
+ * arch/nvalloc/unix/src/os.c
+ * dispClkMapRmToOsArr[] = {...};
+ *
+ * arch/nvalloc/unix/Linux/nv-clk.c
+ * osMapClk[] = {...};
+ *
+ */
+typedef enum _TEGRASOC_WHICH_CLK
+{
+    TEGRASOC_WHICH_CLK_NVDISPLAYHUB,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_DISP,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P0,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P1,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P2,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P3,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P4,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P5,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P6,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P7,
+    TEGRASOC_WHICH_CLK_DPAUX0,
+    TEGRASOC_WHICH_CLK_FUSE,
+    TEGRASOC_WHICH_CLK_DSIPLL_VCO,
+    TEGRASOC_WHICH_CLK_DSIPLL_CLKOUTPN,
+    TEGRASOC_WHICH_CLK_DSIPLL_CLKOUTA,
+    TEGRASOC_WHICH_CLK_SPPLL0_VCO,
+    TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTA,
+    TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTB,
+    TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTPN,
+    TEGRASOC_WHICH_CLK_SPPLL1_CLKOUTPN,
+    TEGRASOC_WHICH_CLK_SPPLL0_DIV27,
+    TEGRASOC_WHICH_CLK_SPPLL1_DIV27,
+    TEGRASOC_WHICH_CLK_SPPLL0_DIV10,
+    TEGRASOC_WHICH_CLK_SPPLL0_DIV25,
+    TEGRASOC_WHICH_CLK_SPPLL1_VCO,
+    TEGRASOC_WHICH_CLK_VPLL0_REF,
+    TEGRASOC_WHICH_CLK_VPLL0,
+    TEGRASOC_WHICH_CLK_VPLL1,
+    TEGRASOC_WHICH_CLK_VPLL2,
+    TEGRASOC_WHICH_CLK_VPLL3,
+    TEGRASOC_WHICH_CLK_VPLL4,
+    TEGRASOC_WHICH_CLK_VPLL5,
+    TEGRASOC_WHICH_CLK_VPLL6,
+    TEGRASOC_WHICH_CLK_VPLL7,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P0_REF,
+    TEGRASOC_WHICH_CLK_RG0,
+    TEGRASOC_WHICH_CLK_RG1,
+    TEGRASOC_WHICH_CLK_RG2,
+    TEGRASOC_WHICH_CLK_RG3,
+    TEGRASOC_WHICH_CLK_RG4,
+    TEGRASOC_WHICH_CLK_RG5,
+    TEGRASOC_WHICH_CLK_RG6,
+    TEGRASOC_WHICH_CLK_RG7,
+    TEGRASOC_WHICH_CLK_DISPPLL,
+    TEGRASOC_WHICH_CLK_DISPHUBPLL,
+    TEGRASOC_WHICH_CLK_DSI_LP,
+    TEGRASOC_WHICH_CLK_DSI_CORE,
+    TEGRASOC_WHICH_CLK_DSI_PIXEL,
+    TEGRASOC_WHICH_CLK_PRE_SOR0,
+    TEGRASOC_WHICH_CLK_PRE_SOR1,
+    TEGRASOC_WHICH_CLK_PRE_SOR2,
+    TEGRASOC_WHICH_CLK_PRE_SOR3,
+    TEGRASOC_WHICH_CLK_DP_LINKA_REF,
+    TEGRASOC_WHICH_CLK_DP_LINKB_REF,
+    TEGRASOC_WHICH_CLK_DP_LINKC_REF,
+    TEGRASOC_WHICH_CLK_DP_LINKD_REF,
+    TEGRASOC_WHICH_CLK_SOR_LINKA_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_LINKB_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_LINKC_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_LINKD_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO,
+    TEGRASOC_WHICH_CLK_SOR_LINKB_AFIFO,
+    TEGRASOC_WHICH_CLK_SOR_LINKC_AFIFO,
+    TEGRASOC_WHICH_CLK_SOR_LINKD_AFIFO,
+    TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO_M,
+    TEGRASOC_WHICH_CLK_RG0_M,
+    TEGRASOC_WHICH_CLK_RG1_M,
+    TEGRASOC_WHICH_CLK_SOR0_M,
+    TEGRASOC_WHICH_CLK_SOR1_M,
+    TEGRASOC_WHICH_CLK_PLLHUB,
+    TEGRASOC_WHICH_CLK_SOR0,
+    TEGRASOC_WHICH_CLK_SOR1,
+    TEGRASOC_WHICH_CLK_SOR2,
+    TEGRASOC_WHICH_CLK_SOR3,
+    TEGRASOC_WHICH_CLK_SOR_PADA_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_PADB_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_PADC_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_PADD_INPUT,
+    TEGRASOC_WHICH_CLK_SOR0_PAD,
+    TEGRASOC_WHICH_CLK_SOR1_PAD,
+    TEGRASOC_WHICH_CLK_SOR2_PAD,
+    TEGRASOC_WHICH_CLK_SOR3_PAD,
+    TEGRASOC_WHICH_CLK_PRE_SF0,
+    TEGRASOC_WHICH_CLK_SF0,
+    TEGRASOC_WHICH_CLK_SF1,
+    TEGRASOC_WHICH_CLK_SF2,
+    TEGRASOC_WHICH_CLK_SF3,
+    TEGRASOC_WHICH_CLK_SF4,
+    TEGRASOC_WHICH_CLK_SF5,
+    TEGRASOC_WHICH_CLK_SF6,
+    TEGRASOC_WHICH_CLK_SF7,
+    TEGRASOC_WHICH_CLK_DSI_PAD_INPUT,
+    TEGRASOC_WHICH_CLK_PRE_SOR0_REF,
+    TEGRASOC_WHICH_CLK_PRE_SOR1_REF,
+    TEGRASOC_WHICH_CLK_SOR0_PLL_REF,
+    TEGRASOC_WHICH_CLK_SOR1_PLL_REF,
+    TEGRASOC_WHICH_CLK_SOR2_PLL_REF,
+    TEGRASOC_WHICH_CLK_SOR3_PLL_REF,
+    TEGRASOC_WHICH_CLK_SOR0_REF,
+    TEGRASOC_WHICH_CLK_SOR1_REF,
+    TEGRASOC_WHICH_CLK_SOR2_REF,
+    TEGRASOC_WHICH_CLK_SOR3_REF,
+    TEGRASOC_WHICH_CLK_OSC,
+    TEGRASOC_WHICH_CLK_DSC,
+    TEGRASOC_WHICH_CLK_MAUD,
+    TEGRASOC_WHICH_CLK_AZA_2XBIT,
+    TEGRASOC_WHICH_CLK_AZA_BIT,
+    TEGRASOC_WHICH_CLK_MIPI_CAL,
+    TEGRASOC_WHICH_CLK_UART_FST_MIPI_CAL,
+    TEGRASOC_WHICH_CLK_SOR0_DIV,
+    TEGRASOC_WHICH_CLK_DISP_ROOT,
+    TEGRASOC_WHICH_CLK_HUB_ROOT,
+    TEGRASOC_WHICH_CLK_PLLA_DISP,
+    TEGRASOC_WHICH_CLK_PLLA_DISPHUB,
+    TEGRASOC_WHICH_CLK_PLLA,
+    TEGRASOC_WHICH_CLK_VPLLX_SOR0_MUXED,
+    TEGRASOC_WHICH_CLK_VPLLX_SOR1_MUXED,
+    TEGRASOC_WHICH_CLK_VPLLX_SOR2_MUXED,
+    TEGRASOC_WHICH_CLK_VPLLX_SOR3_MUXED,
+    TEGRASOC_WHICH_CLK_SF0_SOR,
+    TEGRASOC_WHICH_CLK_SF1_SOR,
+    TEGRASOC_WHICH_CLK_SF2_SOR,
+    TEGRASOC_WHICH_CLK_SF3_SOR,
+    TEGRASOC_WHICH_CLK_SF4_SOR,
+    TEGRASOC_WHICH_CLK_SF5_SOR,
+    TEGRASOC_WHICH_CLK_SF6_SOR,
+    TEGRASOC_WHICH_CLK_SF7_SOR,
+    TEGRASOC_WHICH_CLK_EMC,
+    TEGRASOC_WHICH_CLK_GPU_FIRST,
+    TEGRASOC_WHICH_CLK_GPU_SYS = TEGRASOC_WHICH_CLK_GPU_FIRST,
+    TEGRASOC_WHICH_CLK_GPU_NVD,
+    TEGRASOC_WHICH_CLK_GPU_UPROC,
+    TEGRASOC_WHICH_CLK_GPU_GPC0,
+    TEGRASOC_WHICH_CLK_GPU_GPC1,
+    TEGRASOC_WHICH_CLK_GPU_GPC2,
+    TEGRASOC_WHICH_CLK_GPU_LAST = TEGRASOC_WHICH_CLK_GPU_GPC2,
+    TEGRASOC_WHICH_CLK_MAX, // TEGRASOC_WHICH_CLK_MAX is defined for boundary checks only.
+} TEGRASOC_WHICH_CLK;
+
+#ifdef NVRM
+
+extern const char *pNVRM_ID;
+
+/*
+ * ptr arithmetic convenience
+ */
+
+typedef union
+{
+    volatile NvV8 Reg008[1];
+    volatile NvV16 Reg016[1];
+    volatile NvV32 Reg032[1];
+} nv_hwreg_t, * nv_phwreg_t;
+
+
+#define NVRM_PCICFG_NUM_BARS            6
+#define NVRM_PCICFG_BAR_OFFSET(i)       (0x10 + (i) * 4)
+#define NVRM_PCICFG_BAR_REQTYPE_MASK    0x00000001
+#define NVRM_PCICFG_BAR_REQTYPE_MEMORY  0x00000000
+#define NVRM_PCICFG_BAR_MEMTYPE_MASK    0x00000006
+#define NVRM_PCICFG_BAR_MEMTYPE_64BIT   0x00000004
+#define NVRM_PCICFG_BAR_ADDR_MASK       0xfffffff0
+
+#define NVRM_PCICFG_NUM_DWORDS          16
+
+#define NV_GPU_NUM_BARS                 3
+#define NV_GPU_BAR_INDEX_REGS           0
+#define NV_GPU_BAR_INDEX_FB             1
+#define NV_GPU_BAR_INDEX_IMEM           2
+
+typedef struct
+{
+    NvU64 cpu_address;
+    NvU64 size;
+    NvU32 offset;
+    NvU32 *map;
+    nv_phwreg_t map_u;
+} nv_aperture_t;
+
+typedef struct
+{
+    char *name;
+    NvU32 *data;
+} nv_parm_t;
+
+#define NV_RM_PAGE_SHIFT    12
+#define NV_RM_PAGE_SIZE     (1 << NV_RM_PAGE_SHIFT)
+#define NV_RM_PAGE_MASK     (NV_RM_PAGE_SIZE - 1)
+
+#define NV_RM_TO_OS_PAGE_SHIFT      (os_page_shift - NV_RM_PAGE_SHIFT)
+#define NV_RM_PAGES_TO_OS_PAGES(count) \
+    ((((NvUPtr)(count)) >> NV_RM_TO_OS_PAGE_SHIFT) + \
+     ((((count) & ((1 << NV_RM_TO_OS_PAGE_SHIFT) - 1)) != 0) ? 1 : 0))
+
+// for dynamic granularity page array feature.
+// Notice: dst_granu should be larger than src_granu.
+#define NV_SRC_TO_DST_PAGE_SHIFT(src_granu, dst_granu)      (GET_PAGE_SHIFT(dst_granu) - GET_PAGE_SHIFT(src_granu))
+#define NV_SRC_TO_DST_PAGE_COUNT(src_page_count,src_granu, dst_granu) \
+    ((((NvUPtr)(src_page_count)) >> NV_SRC_TO_DST_PAGE_SHIFT(src_granu, dst_granu)) + \
+     ((((src_page_count) & ((1 << NV_SRC_TO_DST_PAGE_SHIFT(src_granu, dst_granu)) - 1)) != 0) ? 1 : 0))
+
+#if defined(NVCPU_X86_64)
+#define NV_STACK_SIZE (NV_RM_PAGE_SIZE * 3)
+#else
+#define NV_STACK_SIZE (NV_RM_PAGE_SIZE * 2)
+#endif
+
+typedef struct nvidia_stack_s
+{
+    NvU32 size;
+    void *top;
+    NvU8  stack[NV_STACK_SIZE-16] __attribute__ ((aligned(16)));
+} nvidia_stack_t;
+
+/*
+ * TODO: Remove once all UNIX layers have been converted to use nvidia_stack_t
+ */
+typedef nvidia_stack_t nv_stack_t;
+
+typedef struct nv_file_private_t nv_file_private_t;
+
+/*
+ * this is a wrapper for unix events
+ * unlike the events that will be returned to clients, this includes
+ * kernel-specific data, such as file pointer, etc..
+ */
+typedef struct nv_event_s
+{
+    NvHandle            hParent;
+    NvHandle            hObject;
+    NvU32               index;
+    NvU32               info32;
+    NvU16               info16;
+    nv_file_private_t  *nvfp;  /* per file-descriptor data pointer */
+    NvU32               fd;
+    PORT_ATOMIC NvS32   active; /* whether the event should be signaled */
+    NvU32               refcount; /* count of associated RM events */
+    struct nv_event_s  *next;
+} nv_event_t;
+
+typedef struct nv_kern_mapping_s
+{
+    void  *addr;
+    NvU64 size;
+    NvU32 modeFlag;
+    struct nv_kern_mapping_s *next;
+} nv_kern_mapping_t;
+
+typedef struct nv_usermap_access_params_s
+{
+    NvU64    addr;
+    NvU64    size;
+    NvU64    offset;
+    NvU64   *page_array;
+    NvU64    num_pages;
+    MemoryArea memArea;
+    NvU64    access_start;
+    NvU64    access_size;
+    NvBool   contig;
+    NvU32    caching;
+} nv_usermap_access_params_t;
+
+/*
+ * It stores mapping context per mapping
+ */
+typedef struct nv_alloc_mapping_context_s {
+    void  *alloc;
+    NvU64  page_index;
+    NvU64 *page_array;
+    NvU64  num_pages;
+    MemoryArea memArea;
+    NvU64  access_start;
+    NvU64  access_size;
+    NvU32  prot;
+    NvBool valid;
+    NvU32  caching;
+} nv_alloc_mapping_context_t;
+
+struct nv_alloc_mapping_list_node_s;
+
+typedef struct nv_alloc_mapping_list_node_s {
+    nv_alloc_mapping_context_t context;
+    MemoryRange fileRange;
+    struct nv_alloc_mapping_list_node_s *pNext;
+    struct nv_alloc_mapping_list_node_s *pPrev;
+} nv_alloc_mapping_list_node_t;
+
+typedef enum
+{
+    NV_SOC_IRQ_DISPLAY_TYPE = 0x1,
+    NV_SOC_IRQ_DPAUX_TYPE,
+    NV_SOC_IRQ_GPIO_TYPE,
+    NV_SOC_IRQ_HDACODEC_TYPE,
+    NV_SOC_IRQ_TCPC2DISP_TYPE,
+    NV_SOC_IRQ_INVALID_TYPE
+} nv_soc_irq_type_t;
+
+/*
+ * It stores interrupt numbers and interrupt type and private data
+ */
+typedef struct nv_soc_irq_info_s {
+    NvU32 irq_num;
+    nv_soc_irq_type_t irq_type;
+    NvBool bh_pending;
+    union {
+        NvU32 gpio_num;
+        NvU32 dpaux_instance;
+    } irq_data;
+    NvS32 ref_count;
+} nv_soc_irq_info_t;
+
+#define NV_MAX_SOC_IRQS              10
+#define NV_MAX_DPAUX_NUM_DEVICES     4
+#define NV_MAX_DPAUX_DEV_NAME_SIZE   10
+
+#define NV_MAX_SOC_DPAUX_NUM_DEVICES 4
+
+/*
+ * per device state
+ */
+
+/* DMA-capable device data, defined by kernel interface layer */
+typedef struct nv_dma_device nv_dma_device_t;
+
+typedef struct nv_phys_addr_range
+{
+    NvU64 addr;
+    NvU64 len;
+} nv_phys_addr_range_t;
+
+typedef struct
+{
+    char vbios_version[15];
+    char firmware_version[64];
+} nv_cached_gpu_info_t;
+
+typedef struct nv_state_t
+{
+    void  *priv;                    /* private data */
+    void  *os_state;                /* os-specific device state */
+
+    int    flags;
+
+    /* PCI config info */
+    nv_pci_info_t pci_info;
+    NvU16 subsystem_id;
+    NvU16 subsystem_vendor;
+    NvU32 gpu_id;
+    NvU32 iovaspace_id;
+    struct
+    {
+        NvBool         valid;
+        NvU8           uuid[GPU_UUID_LEN];
+        NvBool         pci_uuid_read_attempted;
+        NV_STATUS      pci_uuid_status;
+    } nv_uuid_cache;
+    void *handle;
+
+    NvU32 pci_cfg_space[NVRM_PCICFG_NUM_DWORDS];
+
+    /* physical characteristics */
+    nv_aperture_t bars[NV_GPU_NUM_BARS];
+    nv_aperture_t *regs;
+    nv_aperture_t *dpaux[NV_MAX_DPAUX_NUM_DEVICES];
+    nv_aperture_t *hdacodec_regs;
+    nv_aperture_t *mipical_regs;
+    nv_aperture_t *fb, ud;
+    nv_aperture_t *simregs;
+
+    NvU32  num_dpaux_instance;
+    NvU32  interrupt_line;
+    NvU32  dpaux_irqs[NV_MAX_DPAUX_NUM_DEVICES];
+    char   dpaux_devname[NV_MAX_DPAUX_NUM_DEVICES][NV_MAX_DPAUX_DEV_NAME_SIZE];
+    nv_soc_irq_info_t soc_irq_info[NV_MAX_SOC_IRQS];
+    NvS32 current_soc_irq;
+    NvU32 num_soc_irqs;
+    NvU32 hdacodec_irq;
+    NvU32 tcpc2disp_irq;
+    NvU8 *soc_dcb_blob;
+    NvU32 soc_dcb_size;
+    NvU32 disp_sw_soc_chip_id;
+    NvBool soc_is_dpalt_mode_supported;
+    NvBool soc_is_hfrp_supported;
+    NvBool soc_is_external_phy_supported;
+    NvU64 dma_mask;
+
+    NvBool is_tegra_pci_igpu;
+    NvBool supports_tegra_igpu_rg;
+    NvBool is_tegra_pci_igpu_rg_enabled;
+    NvU32 tegra_pci_igpu_pg_mask;
+
+    NvBool primary_vga;
+
+    NvU32 sim_env;
+
+    NvU32 rc_timer_enabled;
+
+    /* list of events allocated for this device */
+    nv_event_t *event_list;
+
+    /* lock to protect event_list */
+    void *event_spinlock;
+
+    nv_kern_mapping_t *kern_mappings;
+
+    /* Kernel interface DMA device data */
+    nv_dma_device_t *dma_dev;
+    nv_dma_device_t *niso_dma_dev;
+
+    /*
+     * Per-GPU queue.  The actual queue object is usually allocated in the
+     * arch-specific parent structure (e.g. nv_linux_state_t), and this
+     * pointer just points to it.
+     */
+    struct os_work_queue *queue;
+
+    /* For loading RM as a firmware (DCE or GSP) client */
+    NvBool request_firmware;                /* request firmware from the OS */
+    NvBool request_fw_client_rm;            /* attempt to init RM as FW a client */
+    NvBool allow_fallback_to_monolithic_rm; /* allow fallback to monolithic RM if FW client RM doesn't work out */
+    NvBool enable_firmware_logs;            /* attempt to enable firmware log decoding/printing */
+
+    /* Variable to track, if nvidia_remove is called */
+    NvBool removed;
+
+    NvBool console_device;
+
+    /* Variable to track, if GPU is external GPU */
+    NvBool is_external_gpu;
+
+    /* Variable to track, if regkey PreserveVideoMemoryAllocations is set */
+    NvBool preserve_vidmem_allocations;
+
+    /* Variable to force allocation of 32-bit addressable memory */
+    NvBool force_dma32_alloc;
+
+    /* PCI power state should be D0 during system suspend */
+    NvBool d0_state_in_suspend;
+
+    /* Current cyclestats client and context */
+    NvU32 profiler_owner;
+    void *profiler_context;
+
+    /*
+     * RMAPI objects to use in the OS layer to talk to core RM.
+     *
+     * Note that we only need to store one subdevice handle: in SLI, we will
+     * have a separate nv_state_t per physical GPU.
+     */
+    struct {
+        NvHandle hClient;
+        NvHandle hDevice;
+        NvHandle hSubDevice;
+        NvHandle hI2C;
+        NvHandle hDisp;
+    } rmapi;
+
+    /* Bool to check if dma-buf is supported */
+    NvBool dma_buf_supported;
+
+    /* Bool to check if the device received a shutdown notification */
+    NvBool is_shutdown;
+
+    /* Bool to check if the GPU has a coherent sysmem link */
+    NvBool coherent;
+
+    /*
+     * Bool to check if GPU memory is backed by struct page.
+     * False for non-coherent platforms. May also be false
+     * on coherent platforms if GPU memory is not onlined to the kernel.
+     */
+    NvBool mem_has_struct_page;
+
+    /*
+     * Coherent GPU Memory Mode, one of:
+     *   NV_COHERENT_GPU_MEM_MODE_NONE
+     *   NV_COHERENT_GPU_MEM_MODE_NUMA
+     *   NV_COHERENT_GPU_MEM_MODE_DRIVER
+     */
+    NvBool coherent_gpu_mem_mode;
+
+    /* OS detected GPU has ATS capability */
+    NvBool ats_support;
+    /*
+     * NUMA node ID of the CPU to which the GPU is attached.
+     * Holds NUMA_NO_NODE on platforms that don't support NUMA configuration.
+     */
+    NvS32 cpu_numa_node_id;
+
+    struct {
+        /* Bool to check if ISO iommu enabled */
+        NvBool iso_iommu_present;
+        /* Bool to check if NISO iommu enabled */
+        NvBool niso_iommu_present;
+        /* Display SMMU Stream IDs */
+        NvU32 dispIsoStreamId;
+        NvU32 dispNisoStreamId;
+    } iommus;
+
+    struct {
+        NvU32 max_dispclk_rate_using_disppllkhz;
+        NvU32 max_dispclk_rate_using_sppll0clkoutakhz;
+        NvU32 max_hubclk_rate_using_sppll0clkoutbkhz;
+    } clocks;
+
+    /* Console is managed by drm drivers or NVKMS */
+    NvBool client_managed_console;
+
+    /* Console is mapped to sysmem instead of GPU PCIe BAR1 or BAR2 */
+    NvBool sysmem_mapped_console;
+
+    /* Struct to cache the gpu info details */
+    nv_cached_gpu_info_t cached_gpu_info;
+
+    /* Bool to check if power management is supported */
+    NvBool is_pm_unsupported;
+
+    /* Bool to check if the GPU is a CXL device */
+    NvBool is_cxl_dev;
+} nv_state_t;
+
+#define NVFP_TYPE_NONE       ((NvU32)0x0)
+#define NVFP_TYPE_REFCOUNTED ((NvU32)0x1)
+#define NVFP_TYPE_REGISTERED ((NvU32)0x2)
+
+struct nv_file_private_t
+{
+    NvHandle *handles;
+    NvU16 maxHandles;
+    NvU32 deviceInstance;
+    NvU32 gpuInstanceId;
+    NvU8 metadata[64];
+
+    nv_file_private_t * PORT_ATOMIC ctl_nvfp;
+    void *ctl_nvfp_priv;
+    PORT_ATOMIC NvU32 register_or_refcount;
+    // In-flight nv_post_event() calls using this file private.
+    PORT_ATOMIC NvS32 event_posting_refcount;
+
+    //
+    // True if a client or an event was ever allocated on this fd.
+    // If false, RMAPI cleanup is skipped.
+    //
+    NvBool bCleanupRmapi;
+};
+
+static inline NvS32 nv_event_posting_refcount_read(nv_file_private_t *nvfp)
+{
+    return *((volatile NvS32 *)&nvfp->event_posting_refcount);
+}
+
+// Forward define the gpu ops structures
+typedef struct gpuSession                           *nvgpuSessionHandle_t;
+typedef struct gpuDevice                            *nvgpuDeviceHandle_t;
+typedef struct gpuAddressSpace                      *nvgpuAddressSpaceHandle_t;
+typedef struct gpuTsg                               *nvgpuTsgHandle_t;
+typedef struct UvmGpuTsgAllocParams_tag              nvgpuTsgAllocParams_t;
+typedef struct gpuChannel                           *nvgpuChannelHandle_t;
+typedef struct UvmGpuChannelInfo_tag                *nvgpuChannelInfo_t;
+typedef struct UvmGpuChannelAllocParams_tag          nvgpuChannelAllocParams_t;
+typedef struct UvmGpuCaps_tag                       *nvgpuCaps_t;
+typedef struct UvmGpuCopyEnginesCaps_tag            *nvgpuCesCaps_t;
+typedef struct UvmGpuAddressSpaceInfo_tag           *nvgpuAddressSpaceInfo_t;
+typedef struct UvmGpuAllocInfo_tag                  *nvgpuAllocInfo_t;
+typedef struct UvmGpuP2PCapsParams_tag              *nvgpuP2PCapsParams_t;
+typedef struct UvmGpuFbInfo_tag                     *nvgpuFbInfo_t;
+typedef struct UvmGpuNvlinkInfo_tag                 *nvgpuNvlinkInfo_t;
+typedef struct UvmGpuEccInfo_tag                    *nvgpuEccInfo_t;
+typedef struct UvmGpuFaultInfo_tag                  *nvgpuFaultInfo_t;
+typedef struct UvmGpuAccessCntrInfo_tag             *nvgpuAccessCntrInfo_t;
+typedef struct UvmGpuAccessCntrConfig_tag            nvgpuAccessCntrConfig_t;
+typedef struct UvmGpuInfo_tag                        nvgpuInfo_t;
+typedef struct UvmGpuClientInfo_tag                  nvgpuClientInfo_t;
+typedef struct UvmPmaAllocationOptions_tag          *nvgpuPmaAllocationOptions_t;
+typedef struct UvmPmaStatistics_tag                 *nvgpuPmaStatistics_t;
+typedef struct UvmGpuMemoryInfo_tag                 *nvgpuMemoryInfo_t;
+typedef struct UvmGpuExternalMappingInfo_tag        *nvgpuExternalMappingInfo_t;
+typedef struct UvmGpuExternalPhysAddrInfo_tag       *nvgpuExternalPhysAddrInfo_t;
+typedef struct UvmGpuChannelResourceInfo_tag        *nvgpuChannelResourceInfo_t;
+typedef struct UvmGpuChannelInstanceInfo_tag        *nvgpuChannelInstanceInfo_t;
+typedef struct UvmGpuChannelResourceBindParams_tag  *nvgpuChannelResourceBindParams_t;
+typedef struct UvmGpuPagingChannelAllocParams_tag    nvgpuPagingChannelAllocParams_t;
+typedef struct UvmGpuPagingChannel_tag              *nvgpuPagingChannelHandle_t;
+typedef struct UvmGpuPagingChannelInfo_tag          *nvgpuPagingChannelInfo_t;
+typedef enum   UvmPmaGpuMemoryType_tag               nvgpuGpuMemoryType_t;
+typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU64, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t);
+typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemoryType_t);
+typedef struct UvmGpuAccessBitsBufferAlloc_tag      *nvgpuAccessBitBufferAlloc_t;
+/*
+ * flags
+ */
+
+#define NV_FLAG_INITIALIZED                     0x0001
+#define NV_FLAG_EXCLUDE                         0x0002
+#define NV_FLAG_CONTROL                         0x0004
+#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET     0x0008
+#define NV_FLAG_SOC_DISPLAY                     0x0010
+#define NV_FLAG_USES_MSI                        0x0020
+#define NV_FLAG_USES_MSIX                       0x0040
+#define NV_FLAG_PASSTHRU                        0x0080
+#define NV_FLAG_SUSPENDED                       0x0100
+#define NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT  0x0200
+/* To be set when an FLR needs to be triggered after device shut down. */
+#define NV_FLAG_TRIGGER_FLR                     0x0400
+#define NV_FLAG_PERSISTENT_SW_STATE             0x0800
+#define NV_FLAG_IN_RECOVERY                     0x1000
+// Unused                                       0x2000
+#define NV_FLAG_UNBIND_LOCK                     0x4000
+/* To be set when GPU is not present on the bus, to help device teardown */
+#define NV_FLAG_IN_SURPRISE_REMOVAL             0x8000
+
+typedef enum
+{
+    NV_PM_ACTION_HIBERNATE,
+    NV_PM_ACTION_STANDBY,
+    NV_PM_ACTION_RESUME
+} nv_pm_action_t;
+
+typedef enum
+{
+    NV_PM_ACTION_DEPTH_DEFAULT,
+    NV_PM_ACTION_DEPTH_MODESET,
+    NV_PM_ACTION_DEPTH_UVM
+} nv_pm_action_depth_t;
+
+typedef enum
+{
+    NV_DYNAMIC_PM_NEVER,
+    NV_DYNAMIC_PM_COARSE,
+    NV_DYNAMIC_PM_FINE
+} nv_dynamic_power_mode_t;
+
+typedef enum
+{
+    NV_POWER_STATE_IN_HIBERNATE,
+    NV_POWER_STATE_IN_STANDBY,
+    NV_POWER_STATE_RUNNING
+} nv_power_state_t;
+
+typedef struct
+{
+    const char *vidmem_power_status;
+    const char *dynamic_power_status;
+    const char *gc6_support;
+    const char *gcoff_support;
+    const char *s0ix_status;
+    const char *db_support;
+} nv_power_info_t;
+
+typedef enum
+{
+    NV_MEMORY_TYPE_SYSTEM,      /* Memory mapped for ROM, SBIOS and physical RAM. */
+    NV_MEMORY_TYPE_REGISTERS,
+    NV_MEMORY_TYPE_FRAMEBUFFER,
+    NV_MEMORY_TYPE_DEVICE_MMIO, /* All kinds of MMIO referred by NVRM e.g. BARs and MCFG of device */
+} nv_memory_type_t;
+
+#define NV_PRIMARY_VGA(nv)      ((nv)->primary_vga)
+
+#define NV_IS_CTL_DEVICE(nv)    ((nv)->flags & NV_FLAG_CONTROL)
+#define NV_IS_SOC_DISPLAY_DEVICE(nv)    \
+        ((nv)->flags & NV_FLAG_SOC_DISPLAY)
+
+#define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv)    \
+        (((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0)
+
+#define NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv)    \
+        (((nv)->flags & NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT) != 0)
+
+/*
+ * For console setup by EFI GOP, the base address is BAR1.
+ * For console setup by VBIOS, the base address is BAR2 + 16MB.
+ */
+#define NV_IS_CONSOLE_MAPPED(nv, addr)  \
+        (((addr) == (nv)->bars[NV_GPU_BAR_INDEX_FB].cpu_address) || \
+         ((addr) == ((nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000)))
+
+#define NV_SOC_IS_ISO_IOMMU_PRESENT(nv)     \
+        ((nv)->iommus.iso_iommu_present)
+
+#define NV_SOC_IS_NISO_IOMMU_PRESENT(nv)     \
+        ((nv)->iommus.niso_iommu_present)
+/*
+ * GPU add/remove events
+ */
+#define NV_SYSTEM_GPU_ADD_EVENT             0x9001
+#define NV_SYSTEM_GPU_REMOVE_EVENT          0x9002
+
+/*
+ * NVIDIA ACPI sub-event IDs (event types) to be passed into
+ * to core NVIDIA driver for ACPI events.
+ */
+#define NV_SYSTEM_ACPI_EVENT_VALUE_DISPLAY_SWITCH_DEFAULT    0
+#define NV_SYSTEM_ACPI_EVENT_VALUE_DOCK_EVENT_UNDOCKED       0
+#define NV_SYSTEM_ACPI_EVENT_VALUE_DOCK_EVENT_DOCKED         1
+
+#define NV_ACPI_NVIF_HANDLE_PRESENT 0x01
+#define NV_ACPI_DSM_HANDLE_PRESENT  0x02
+#define NV_ACPI_WMMX_HANDLE_PRESENT 0x04
+
+#define NV_EVAL_ACPI_METHOD_NVIF     0x01
+#define NV_EVAL_ACPI_METHOD_WMMX     0x02
+
+/*
+ * Coherent GPU Memory Mode
+ */
+#define NV_COHERENT_GPU_MEM_MODE_NONE   0
+#define NV_COHERENT_GPU_MEM_MODE_NUMA   1
+#define NV_COHERENT_GPU_MEM_MODE_DRIVER 2
+
+typedef enum {
+    NV_I2C_CMD_READ = 1,
+    NV_I2C_CMD_WRITE,
+    NV_I2C_CMD_SMBUS_READ,
+    NV_I2C_CMD_SMBUS_WRITE,
+    NV_I2C_CMD_SMBUS_QUICK_WRITE,
+    NV_I2C_CMD_SMBUS_QUICK_READ,
+    NV_I2C_CMD_SMBUS_BLOCK_READ,
+    NV_I2C_CMD_SMBUS_BLOCK_WRITE,
+    NV_I2C_CMD_BLOCK_READ,
+    NV_I2C_CMD_BLOCK_WRITE
+} nv_i2c_cmd_t;
+
+// Flags needed by osAllocPagesNode / os_alloc_pages_node
+#define NV_ALLOC_PAGES_NODE_NONE                0x0
+#define NV_ALLOC_PAGES_NODE_SKIP_RECLAIM        0x1
+
+/*
+** where we hide our nv_state_t * ...
+*/
+#define NV_SET_NV_STATE(pgpu,p) ((pgpu)->pOsGpuInfo = (p))
+#define NV_GET_NV_STATE(pGpu) \
+    (nv_state_t *)((pGpu) ? (pGpu)->pOsGpuInfo : NULL)
+
+static inline NvBool IS_REG_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)
+{
+    return ((offset >= nv->regs->cpu_address) &&
+            ((offset + (length - 1)) >= offset) &&
+            ((offset + (length - 1)) <= (nv->regs->cpu_address + (nv->regs->size - 1))));
+}
+
+static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)
+{
+    return  ((nv->fb) && (nv->fb->size != 0) &&
+             (offset >= nv->fb->cpu_address) &&
+             ((offset + (length - 1)) >= offset) &&
+             ((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1))));
+}
+
+static inline NvBool IS_UD_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)
+{
+    return ((nv->ud.cpu_address != 0) && (nv->ud.size != 0) &&
+            (offset >= nv->ud.cpu_address) &&
+            ((offset + (length - 1)) >= offset) &&
+            ((offset + (length - 1)) <= (nv->ud.cpu_address + (nv->ud.size - 1))));
+}
+
+static inline NvBool IS_IMEM_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)
+{
+    return ((nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address != 0) &&
+            (nv->bars[NV_GPU_BAR_INDEX_IMEM].size != 0) &&
+            (offset >= nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address) &&
+            ((offset + (length - 1)) >= offset) &&
+            ((offset + (length - 1)) <= (nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address +
+                                         (nv->bars[NV_GPU_BAR_INDEX_IMEM].size - 1))));
+}
+
+#define NV_RM_MAX_MSIX_LINES  8
+
+#define NV_MAX_ISR_DELAY_US           20000
+#define NV_MAX_ISR_DELAY_MS           (NV_MAX_ISR_DELAY_US / 1000)
+
+#define NV_TIMERCMP(a, b, CMP)                                              \
+    (((a)->tv_sec == (b)->tv_sec) ?                                         \
+        ((a)->tv_usec CMP (b)->tv_usec) : ((a)->tv_sec CMP (b)->tv_sec))
+
+#define NV_TIMERADD(a, b, result)                                           \
+    {                                                                       \
+        (result)->tv_sec = (a)->tv_sec + (b)->tv_sec;                       \
+        (result)->tv_usec = (a)->tv_usec + (b)->tv_usec;                    \
+        if ((result)->tv_usec >= 1000000)                                   \
+        {                                                                   \
+            ++(result)->tv_sec;                                             \
+            (result)->tv_usec -= 1000000;                                   \
+        }                                                                   \
+    }
+
+#define NV_TIMERSUB(a, b, result)                                           \
+    {                                                                       \
+        (result)->tv_sec = (a)->tv_sec - (b)->tv_sec;                       \
+        (result)->tv_usec = (a)->tv_usec - (b)->tv_usec;                    \
+        if ((result)->tv_usec < 0)                                          \
+        {                                                                   \
+          --(result)->tv_sec;                                               \
+          (result)->tv_usec += 1000000;                                     \
+        }                                                                   \
+    }
+
+#define NV_TIMEVAL_TO_US(tv)    ((NvU64)(tv).tv_sec * 1000000 + (tv).tv_usec)
+
+#ifndef NV_ALIGN_UP
+#define NV_ALIGN_UP(v,g) (((v) + ((g) - 1)) & ~((g) - 1))
+#endif
+#ifndef NV_ALIGN_DOWN
+#define NV_ALIGN_DOWN(v,g) ((v) & ~((g) - 1))
+#endif
+
+
+/*
+ * driver internal interfaces
+ */
+
+/*
+ * ---------------------------------------------------------------------------
+ *
+ * Function prototypes for UNIX specific OS interface.
+ *
+ * ---------------------------------------------------------------------------
+ */
+
+NvU32      NV_API_CALL  nv_get_dev_minor         (nv_state_t *);
+void*      NV_API_CALL  nv_alloc_kernel_mapping  (nv_state_t *, void *, NvU64, NvU32, NvU64, void **);
+void       NV_API_CALL  nv_free_kernel_mapping   (nv_state_t *, void *, void *, void *);
+NV_STATUS  NV_API_CALL  nv_alloc_user_mapping    (nv_state_t *, void *, NvU64, NvU32, NvU64, NvU32, NvU64 *, void **);
+void       NV_API_CALL  nv_free_user_mapping     (nv_state_t *, void *, NvU64, void *);
+NV_STATUS  NV_API_CALL  nv_add_mapping_context_to_file (nv_state_t *, nv_usermap_access_params_t*, NvU32, void *, NvU64, NvU32);
+
+NvU64  NV_API_CALL  nv_get_kern_phys_address     (NvU64);
+NvU64  NV_API_CALL  nv_get_user_phys_address     (NvU64);
+nv_state_t*  NV_API_CALL  nv_get_adapter_state   (NvU32, NvU8, NvU8);
+nv_state_t*  NV_API_CALL  nv_get_ctl_state       (void);
+
+void   NV_API_CALL  nv_set_dma_address_size      (nv_state_t *, NvU32 );
+
+NV_STATUS  NV_API_CALL  nv_alias_pages           (nv_state_t *, NvU32, NvU64, NvU32, NvU32, NvU64, NvU64 *, NvBool, void **);
+NV_STATUS  NV_API_CALL  nv_alloc_pages           (nv_state_t *, NvU32, NvU64, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **);
+NV_STATUS  NV_API_CALL  nv_free_pages            (nv_state_t *, NvU32, NvBool, NvU32, void *);
+
+NV_STATUS  NV_API_CALL  nv_register_user_pages   (nv_state_t *, NvU64, NvU64 *, void *, void **, NvBool);
+void       NV_API_CALL  nv_unregister_user_pages (nv_state_t *, NvU64, void **, void **);
+
+NV_STATUS NV_API_CALL   nv_register_peer_io_mem  (nv_state_t *, NvU64 *, NvU64, void **);
+void      NV_API_CALL   nv_unregister_peer_io_mem(nv_state_t *, void *);
+
+struct sg_table;
+
+NV_STATUS NV_API_CALL   nv_register_sgt          (nv_state_t *, NvU64 *, NvU64, NvU32, void **,
+                                                  struct sg_table *, void *, NvBool);
+void      NV_API_CALL   nv_unregister_sgt        (nv_state_t *, struct sg_table **, void **, void *);
+NV_STATUS NV_API_CALL   nv_register_phys_pages   (nv_state_t *, NvU64 *, NvU64, NvU32, void **);
+void      NV_API_CALL   nv_unregister_phys_pages (nv_state_t *, void *);
+
+NV_STATUS  NV_API_CALL  nv_dma_map_sgt           (nv_dma_device_t *, NvU64, NvU64 *, NvU32, NvBool, void **);
+
+NV_STATUS  NV_API_CALL  nv_dma_map_alloc         (nv_dma_device_t *, NvU64, NvU64 *, NvBool, NvBool, void **);
+NV_STATUS  NV_API_CALL  nv_dma_unmap_alloc       (nv_dma_device_t *, NvU64, NvU64 *, void **);
+
+NV_STATUS  NV_API_CALL  nv_dma_map_peer          (nv_dma_device_t *, nv_dma_device_t *, NvU8, NvU64, NvU64 *);
+void       NV_API_CALL  nv_dma_unmap_peer        (nv_dma_device_t *, NvU64, NvU64);
+
+NV_STATUS  NV_API_CALL  nv_dma_map_mmio          (nv_dma_device_t *, NvU64, NvU64 *);
+void       NV_API_CALL  nv_dma_unmap_mmio        (nv_dma_device_t *, NvU64, NvU64);
+
+void       NV_API_CALL  nv_dma_cache_invalidate  (nv_dma_device_t *, void *);
+void*      NV_API_CALL  nv_dma_get_dev_pagemap   (NvU64);
+void       NV_API_CALL  nv_dma_put_dev_pagemap   (void *);
+NvBool     NV_API_CALL  nv_grdma_pci_topology_supported(nv_state_t *, nv_dma_device_t *);
+
+NvS32  NV_API_CALL  nv_start_rc_timer            (nv_state_t *);
+NvS32  NV_API_CALL  nv_stop_rc_timer             (nv_state_t *);
+
+void   NV_API_CALL  nv_post_event                (nv_event_t *, NvHandle, NvU32, NvU32, NvU16, NvBool);
+NvS32  NV_API_CALL  nv_get_event                 (nv_file_private_t *, nv_event_t *, NvU32 *);
+
+void*  NV_API_CALL  nv_i2c_add_adapter           (nv_state_t *, NvU32);
+void   NV_API_CALL  nv_i2c_del_adapter           (nv_state_t *, void *);
+
+void   NV_API_CALL  nv_acpi_methods_init         (NvU32 *);
+void   NV_API_CALL  nv_acpi_methods_uninit       (void);
+
+NV_STATUS  NV_API_CALL  nv_acpi_method           (NvU32, NvU32, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *);
+NV_STATUS  NV_API_CALL  nv_acpi_d3cold_dsm_for_upstream_port (nv_state_t *, NvU8 *, NvU32, NvU32, NvU32 *);
+NV_STATUS  NV_API_CALL  nv_acpi_dsm_method       (nv_state_t *, NvU8 *, NvU32, NvBool, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *);
+NV_STATUS  NV_API_CALL  nv_acpi_ddc_method       (nv_state_t *, void *, NvU32 *, NvBool);
+NV_STATUS  NV_API_CALL  nv_acpi_dod_method       (nv_state_t *, NvU32 *, NvU32 *);
+NV_STATUS  NV_API_CALL  nv_acpi_rom_method       (nv_state_t *, NvU32 *, NvU32 *);
+NV_STATUS  NV_API_CALL  nv_acpi_get_powersource  (NvU32 *);
+NvBool     NV_API_CALL  nv_acpi_is_battery_present(void);
+
+NV_STATUS  NV_API_CALL  nv_acpi_mux_method       (nv_state_t *, NvU32 *, NvU32, const char *);
+
+NV_STATUS  NV_API_CALL  nv_log_error             (nv_state_t *, NvU32, const char *, va_list);
+
+NvBool     NV_API_CALL  nv_requires_dma_remap    (nv_state_t *);
+
+NvBool     NV_API_CALL  nv_is_rm_firmware_active(nv_state_t *);
+const void*NV_API_CALL  nv_get_firmware(nv_state_t *, nv_firmware_type_t, nv_firmware_chip_family_t, const void **, NvU32 *);
+void       NV_API_CALL  nv_put_firmware(const void *);
+
+nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **);
+void               NV_API_CALL nv_put_file_private(void *);
+
+NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU32 *, NvS32 *);
+NV_STATUS NV_API_CALL nv_get_egm_info(nv_state_t *, NvU64 *, NvU64 *, NvS32 *);
+
+void      NV_API_CALL nv_p2p_free_platform_data(void *data);
+
+NV_STATUS NV_API_CALL nv_revoke_gpu_mappings     (nv_state_t *);
+void      NV_API_CALL nv_acquire_mmap_lock       (nv_state_t *);
+void      NV_API_CALL nv_release_mmap_lock       (nv_state_t *);
+NvBool    NV_API_CALL nv_get_all_mappings_revoked_locked (nv_state_t *);
+void      NV_API_CALL nv_set_safe_to_mmap_locked (nv_state_t *, NvBool);
+
+nv_alloc_mapping_list_node_t** NV_API_CALL nv_acquire_file_va(nv_file_private_t *, NvBool);
+void      NV_API_CALL nv_release_file_va(nv_file_private_t *, NvBool);
+
+NV_STATUS NV_API_CALL nv_indicate_idle           (nv_state_t *);
+NV_STATUS NV_API_CALL nv_indicate_not_idle       (nv_state_t *);
+void      NV_API_CALL nv_idle_holdoff            (nv_state_t *);
+
+NvBool    NV_API_CALL nv_dynamic_power_available (nv_state_t *);
+void      NV_API_CALL nv_audio_dynamic_power     (nv_state_t *);
+
+void      NV_API_CALL nv_control_soc_irqs        (nv_state_t *, NvBool bEnable);
+NV_STATUS NV_API_CALL nv_get_current_irq_priv_data(nv_state_t *, NvU32 *);
+
+NV_STATUS NV_API_CALL nv_acquire_fabric_mgmt_cap (int, int*);
+int       NV_API_CALL nv_cap_drv_init(void);
+void      NV_API_CALL nv_cap_drv_exit(void);
+NvBool    NV_API_CALL nv_is_gpu_accessible(nv_state_t *);
+NvBool    NV_API_CALL nv_match_gpu_os_info(nv_state_t *, void *);
+
+void      NV_API_CALL nv_get_updated_emu_seg(NvU32 *start, NvU32 *end);
+void      NV_API_CALL nv_get_screen_info(nv_state_t *, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64 *);
+void      NV_API_CALL nv_set_gpu_pg_mask(nv_state_t *);
+
+struct dma_buf;
+typedef struct nv_dma_buf nv_dma_buf_t;
+struct drm_gem_object;
+
+NV_STATUS NV_API_CALL nv_dma_import_sgt  (nv_dma_device_t *, struct sg_table *, struct drm_gem_object *);
+void NV_API_CALL nv_dma_release_sgt(struct sg_table *, struct drm_gem_object *);
+NV_STATUS NV_API_CALL nv_dma_import_dma_buf      (nv_dma_device_t *, struct dma_buf *, NvBool, NvU32 *, struct sg_table **, nv_dma_buf_t **);
+NV_STATUS NV_API_CALL nv_dma_import_from_fd      (nv_dma_device_t *, NvS32, NvBool, NvU32 *, struct sg_table **, nv_dma_buf_t **);
+void      NV_API_CALL nv_dma_release_dma_buf     (nv_dma_buf_t *);
+
+void      NV_API_CALL nv_schedule_uvm_isr        (nv_state_t *);
+
+NV_STATUS NV_API_CALL nv_schedule_uvm_drain_p2p  (NvU8 *);
+void      NV_API_CALL nv_schedule_uvm_resume_p2p (NvU8 *);
+
+NvBool    NV_API_CALL nv_platform_supports_s0ix  (void);
+NvBool    NV_API_CALL nv_s2idle_pm_configured    (void);
+
+NvBool    NV_API_CALL nv_pci_tegra_register_power_domain    (nv_state_t *, NvBool);
+NvBool    NV_API_CALL nv_pci_tegra_pm_init        (nv_state_t *);
+void      NV_API_CALL nv_pci_tegra_pm_deinit      (nv_state_t *);
+
+NvBool    NV_API_CALL nv_is_chassis_notebook      (void);
+void      NV_API_CALL nv_allow_runtime_suspend    (nv_state_t *nv);
+void      NV_API_CALL nv_disallow_runtime_suspend (nv_state_t *nv);
+
+typedef void (*nvTegraDceClientIpcCallback)(NvU32, NvU32, NvU32, void *, void *);
+
+NV_STATUS NV_API_CALL nv_get_num_phys_pages      (void *, NvU32 *);
+NV_STATUS NV_API_CALL nv_get_phys_pages          (void *, void *, NvU32 *);
+void      NV_API_CALL nv_get_disp_smmu_stream_ids (nv_state_t *, NvU32 *, NvU32 *);
+
+typedef struct TEGRA_IMP_IMPORT_DATA TEGRA_IMP_IMPORT_DATA;
+typedef struct nv_i2c_msg_s nv_i2c_msg_t;
+
+NV_STATUS NV_API_CALL nv_bpmp_send_mrq           (nv_state_t *, NvU32, const void *, NvU32, void *, NvU32, NvS32 *, NvS32 *);
+NV_STATUS NV_API_CALL nv_i2c_transfer(nv_state_t *, NvU32, NvU8, nv_i2c_msg_t *, int);
+void      NV_API_CALL nv_i2c_unregister_clients(nv_state_t *);
+NV_STATUS NV_API_CALL nv_i2c_bus_status(nv_state_t *, NvU32, NvS32 *, NvS32 *);
+NV_STATUS NV_API_CALL nv_imp_get_import_data     (TEGRA_IMP_IMPORT_DATA *);
+NV_STATUS NV_API_CALL nv_imp_get_uefi_data       (nv_state_t *nv, NvU32 *iso_bw_kbps, NvU32 *floor_bw_kbps);
+NV_STATUS NV_API_CALL nv_imp_enable_disable_rfl  (nv_state_t *nv, NvBool bEnable);
+NV_STATUS NV_API_CALL nv_imp_icc_set_bw          (nv_state_t *nv, NvU32 avg_bw_kbps, NvU32 floor_bw_kbps);
+NV_STATUS NV_API_CALL nv_get_num_dpaux_instances(nv_state_t *nv, NvU32 *num_instances);
+NV_STATUS NV_API_CALL nv_get_tegra_brightness_level(nv_state_t *, NvU32 *);
+NV_STATUS NV_API_CALL nv_set_tegra_brightness_level(nv_state_t *, NvU32);
+
+NV_STATUS NV_API_CALL nv_soc_device_reset        (nv_state_t *);
+NV_STATUS NV_API_CALL nv_soc_pm_powergate        (nv_state_t *);
+NV_STATUS NV_API_CALL nv_soc_pm_unpowergate      (nv_state_t *);
+NV_STATUS NV_API_CALL nv_gpio_get_pin_state(nv_state_t *, NvU32, NvU32 *);
+void      NV_API_CALL nv_gpio_set_pin_state(nv_state_t *, NvU32, NvU32);
+NV_STATUS NV_API_CALL nv_gpio_set_pin_direction(nv_state_t *, NvU32, NvU32);
+NV_STATUS NV_API_CALL nv_gpio_get_pin_direction(nv_state_t *, NvU32, NvU32 *);
+NV_STATUS NV_API_CALL nv_gpio_get_pin_number(nv_state_t *, NvU32, NvU32 *);
+NvBool    NV_API_CALL nv_gpio_get_pin_interrupt_status(nv_state_t *, NvU32, NvU32);
+NV_STATUS NV_API_CALL nv_gpio_set_pin_interrupt(nv_state_t *, NvU32, NvU32);
+NvU32     NV_API_CALL nv_tegra_get_rm_interface_type(NvU32);
+NV_STATUS NV_API_CALL nv_tegra_dce_register_ipc_client(NvU32, void *, nvTegraDceClientIpcCallback, NvU32 *);
+NV_STATUS NV_API_CALL nv_tegra_dce_client_ipc_send_recv(NvU32, void *, NvU32);
+NV_STATUS NV_API_CALL nv_tegra_dce_unregister_ipc_client(NvU32);
+NV_STATUS NV_API_CALL nv_dsi_parse_panel_props(nv_state_t *, void *);
+NvBool    NV_API_CALL nv_dsi_is_panel_connected(nv_state_t *);
+NV_STATUS NV_API_CALL nv_dsi_panel_enable(nv_state_t *, void *);
+NV_STATUS NV_API_CALL nv_dsi_panel_reset(nv_state_t *, void *);
+void      NV_API_CALL nv_dsi_panel_disable(nv_state_t *, void *);
+void      NV_API_CALL nv_dsi_panel_cleanup(nv_state_t *, void *);
+NV_STATUS NV_API_CALL nv_soc_mipi_cal_reset(nv_state_t *);
+NvU32     NV_API_CALL nv_soc_fuse_register_read (NvU32 addr);
+NvBool    NV_API_CALL nv_get_hdcp_enabled(nv_state_t *nv);
+NV_STATUS NV_API_CALL nv_get_valid_window_head_mask(nv_state_t *nv, NvU64 *);
+NV_STATUS NV_API_CALL nv_dp_uphy_pll_init(nv_state_t *, NvU32, NvU32);
+NV_STATUS NV_API_CALL nv_dp_uphy_pll_deinit(nv_state_t *);
+NV_STATUS NV_API_CALL nv_soc_i2c_hsp_semaphore_acquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout);
+typedef void (*nv_soc_tsec_cb_func_t)(void*, void*);
+NvU32     NV_API_CALL nv_soc_tsec_send_cmd(void* cmd, nv_soc_tsec_cb_func_t cb_func, void* cb_context);
+NvU32     NV_API_CALL nv_soc_tsec_event_register(nv_soc_tsec_cb_func_t cb_func, void* cb_context, NvBool is_init_event);
+NvU32     NV_API_CALL nv_soc_tsec_event_unregister(NvBool is_init_event);
+void*     NV_API_CALL nv_soc_tsec_alloc_mem_desc(NvU32 num_bytes, NvU32 *flcn_addr);
+void      NV_API_CALL nv_soc_tsec_free_mem_desc(void *mem_desc);
+NvBool    NV_API_CALL nv_is_clk_enabled          (nv_state_t *, TEGRASOC_WHICH_CLK);
+NV_STATUS NV_API_CALL nv_set_parent              (nv_state_t *, TEGRASOC_WHICH_CLK, TEGRASOC_WHICH_CLK);
+NV_STATUS NV_API_CALL nv_get_parent              (nv_state_t *, TEGRASOC_WHICH_CLK, TEGRASOC_WHICH_CLK*);
+NV_STATUS NV_API_CALL nv_clk_get_handles         (nv_state_t *);
+void      NV_API_CALL nv_clk_clear_handles       (nv_state_t *);
+NV_STATUS NV_API_CALL nv_enable_clk              (nv_state_t *, TEGRASOC_WHICH_CLK);
+void      NV_API_CALL nv_disable_clk             (nv_state_t *, TEGRASOC_WHICH_CLK);
+NV_STATUS NV_API_CALL nv_get_curr_freq           (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
+NV_STATUS NV_API_CALL nv_get_max_freq            (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
+NV_STATUS NV_API_CALL nv_get_min_freq            (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
+NV_STATUS NV_API_CALL nv_set_freq                (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32);
+
+void      NV_API_CALL nv_pci_cxl_set_caching(nv_state_t *, NvBool);
+
+/*
+ * ---------------------------------------------------------------------------
+ *
+ * Function prototypes for Resource Manager interface.
+ *
+ * ---------------------------------------------------------------------------
+ */
+
+NvBool     NV_API_CALL  rm_init_rm               (nvidia_stack_t *);
+void       NV_API_CALL  rm_shutdown_rm           (nvidia_stack_t *);
+NvBool     NV_API_CALL  rm_init_private_state    (nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL  rm_free_private_state    (nvidia_stack_t *, nv_state_t *);
+NvBool     NV_API_CALL  rm_init_adapter          (nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL  rm_disable_adapter       (nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL  rm_shutdown_adapter      (nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL  rm_exclude_adapter       (nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL  rm_acquire_api_lock      (nvidia_stack_t *);
+NV_STATUS  NV_API_CALL  rm_release_api_lock      (nvidia_stack_t *);
+NV_STATUS  NV_API_CALL  rm_acquire_gpu_lock      (nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL  rm_release_gpu_lock      (nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL  rm_acquire_all_gpus_lock (nvidia_stack_t *);
+NV_STATUS  NV_API_CALL  rm_release_all_gpus_lock (nvidia_stack_t *);
+NV_STATUS  NV_API_CALL  rm_ioctl                 (nvidia_stack_t *, nv_state_t *, nv_file_private_t *, NvU32, void *, NvU32);
+NV_STATUS  NV_API_CALL  rm_validate_ioctls       (NvU32, NvU32);
+NvBool     NV_API_CALL  rm_isr                   (nvidia_stack_t *, nv_state_t *, NvU32 *);
+void       NV_API_CALL  rm_isr_bh                (nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL  rm_isr_bh_unlocked       (nvidia_stack_t *, nv_state_t *);
+NvBool     NV_API_CALL  rm_is_msix_allowed       (nvidia_stack_t *, nv_state_t *);
+NvBool     NV_API_CALL  rm_wait_for_bar_firewall (nvidia_stack_t *, NvU32 domain, NvU8 bus, NvU8 device, NvU8 function, NvU16 devId, NvU16 subsystemId);
+NV_STATUS  NV_API_CALL  rm_pmu_perfmon_get_load  (nvidia_stack_t *, nv_state_t *, NvU32 *, TEGRASOC_DEVFREQ_CLK);
+NV_STATUS  NV_API_CALL  rm_power_management      (nvidia_stack_t *, nv_state_t *, nv_pm_action_t);
+NV_STATUS  NV_API_CALL  rm_stop_user_channels    (nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL  rm_restart_user_channels (nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL  rm_save_low_res_mode     (nvidia_stack_t *, nv_state_t *);
+char*      NV_API_CALL  rm_get_gpu_uuid          (nvidia_stack_t *, nv_state_t *);
+const NvU8* NV_API_CALL rm_get_gpu_uuid_raw      (nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL  rm_set_rm_firmware_requested(nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL  rm_cleanup_file_private  (nvidia_stack_t *, nv_state_t *, nv_file_private_t *);
+void       NV_API_CALL  rm_unbind_lock           (nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL  rm_read_registry_dword   (nvidia_stack_t *, nv_state_t *, const char *, NvU32 *);
+NV_STATUS  NV_API_CALL  rm_write_registry_dword  (nvidia_stack_t *, nv_state_t *, const char *, NvU32);
+NV_STATUS  NV_API_CALL  rm_write_registry_binary (nvidia_stack_t *, nv_state_t *, const char *, NvU8 *, NvU32);
+NV_STATUS  NV_API_CALL  rm_write_registry_string (nvidia_stack_t *, nv_state_t *, const char *, const char *, NvU32);
+void       NV_API_CALL  rm_parse_option_string   (nvidia_stack_t *, const char *);
+char*      NV_API_CALL  rm_remove_spaces         (const char *);
+char*      NV_API_CALL  rm_string_token          (char **, const char);
+void       NV_API_CALL  rm_vgpu_vfio_set_driver_vm(nvidia_stack_t *, NvBool);
+NV_STATUS  NV_API_CALL  rm_get_adapter_status_external(nvidia_stack_t *, nv_state_t *);
+
+NV_STATUS  NV_API_CALL  rm_run_rc_callback       (nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL  rm_execute_work_item     (nvidia_stack_t *, void *);
+const char* NV_API_CALL rm_get_device_name       (NvU16, NvU16, NvU16);
+
+NV_STATUS  NV_API_CALL  rm_is_supported_device   (nvidia_stack_t *, nv_state_t *);
+NvBool     NV_API_CALL  rm_is_supported_pci_device(NvU8   pci_class,
+                                                   NvU8   pci_subclass,
+                                                   NvU16  vendor,
+                                                   NvU16  device,
+                                                   NvU16  subsystem_vendor,
+                                                   NvU16  subsystem_device,
+                                                   NvBool print_legacy_warning);
+
+void       NV_API_CALL  rm_i2c_remove_adapters    (nvidia_stack_t *, nv_state_t *);
+NvBool     NV_API_CALL  rm_i2c_is_smbus_capable   (nvidia_stack_t *, nv_state_t *, void *);
+NV_STATUS  NV_API_CALL  rm_i2c_transfer           (nvidia_stack_t *, nv_state_t *, void *, nv_i2c_cmd_t, NvU8, NvU8, NvU32, NvU8 *);
+
+NV_STATUS  NV_API_CALL  rm_perform_version_check  (nvidia_stack_t *, void *, NvU32);
+
+void       NV_API_CALL  rm_power_source_change_event        (nvidia_stack_t *, NvU32);
+
+void       NV_API_CALL  rm_request_dnotifier_state          (nvidia_stack_t *, nv_state_t *);
+
+void       NV_API_CALL  rm_disable_gpu_state_persistence    (nvidia_stack_t *sp, nv_state_t *);
+NV_STATUS  NV_API_CALL  rm_p2p_init_mapping       (nvidia_stack_t *, NvU64, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU64, NvU64, NvU64, NvU64, void (*)(void *), void *);
+NV_STATUS  NV_API_CALL  rm_p2p_destroy_mapping    (nvidia_stack_t *, NvU64);
+NV_STATUS  NV_API_CALL  rm_p2p_get_pages          (nvidia_stack_t *, NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU8 **, void *, NvBool *);
+NV_STATUS  NV_API_CALL  rm_p2p_get_gpu_info       (nvidia_stack_t *, NvU64, NvU64, NvU8 **, void **);
+NV_STATUS  NV_API_CALL  rm_p2p_get_pages_persistent (nvidia_stack_t *,  NvU64, NvU64, void **, NvU64 *, NvU32 *, NvBool, void *, void *, void **, NvBool *);
+NV_STATUS  NV_API_CALL  rm_p2p_register_callback  (nvidia_stack_t *, NvU64, NvU64, NvU64, void *, void (*)(void *), void *);
+NV_STATUS  NV_API_CALL  rm_p2p_put_pages          (nvidia_stack_t *, NvU64, NvU32, NvU64, void *);
+NV_STATUS  NV_API_CALL  rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *, void *);
+NV_STATUS  NV_API_CALL  rm_p2p_dma_map_pages      (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU64, NvU32, NvU64 *, void **);
+NV_STATUS  NV_API_CALL  rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle,
+                                                   NvHandle, void *, NvHandle, NvU64, NvU64, NvU8, NvHandle *, void **,
+                                                   NvBool *, NvU32 *, NvBool *, nv_memory_type_t *);
+void       NV_API_CALL  rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle);
+NV_STATUS  NV_API_CALL  rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *,
+                                                   NvHandle, NvHandle, MemoryRange,
+                                                   NvU8, void *, NvBool, MemoryArea *);
+void       NV_API_CALL  rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *,
+                                                    NvHandle, NvHandle, NvU8, void *,
+                                                    NvBool, MemoryArea);
+NV_STATUS  NV_API_CALL  rm_dma_buf_get_client_and_device(nvidia_stack_t *,
+                                                nv_state_t *, NvHandle, NvHandle,
+                                                NvU8, NvHandle *, NvHandle *,
+                                                NvHandle *, void **, NvBool *, NvBool *);
+void       NV_API_CALL  rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *);
+
+void       NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd);
+NvBool     NV_API_CALL rm_get_device_remove_flag(nvidia_stack_t *sp, NvU32 gpu_id);
+NV_STATUS  NV_API_CALL rm_gpu_copy_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *);
+NV_STATUS  NV_API_CALL rm_gpu_handle_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *);
+NvBool     NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *);
+NvBool     NV_API_CALL rm_init_event_locks(nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL rm_destroy_event_locks(nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, nv_ioctl_numa_info_t *);
+NV_STATUS  NV_API_CALL rm_gpu_numa_online(nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL rm_gpu_numa_offline(nvidia_stack_t *, nv_state_t *);
+NvBool     NV_API_CALL rm_is_device_sequestered(nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL rm_check_for_gpu_surprise_removal(nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL rm_set_external_kernel_client_count(nvidia_stack_t *, nv_state_t *, NvBool);
+NV_STATUS  NV_API_CALL rm_schedule_gpu_wakeup(nvidia_stack_t *, nv_state_t *);
+NvBool     NV_API_CALL rm_disable_iomap_wc(void);
+
+void       NV_API_CALL rm_init_tegra_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL rm_init_dynamic_power_management(nvidia_stack_t *, nv_state_t *, NvBool);
+void       NV_API_CALL rm_cleanup_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL rm_enable_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL rm_ref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t);
+void       NV_API_CALL rm_unref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t);
+NV_STATUS  NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool, NvBool *);
+void       NV_API_CALL rm_get_power_info(nvidia_stack_t *, nv_state_t *, nv_power_info_t *);
+
+void       NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32);
+void       NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *);
+
+NvBool     NV_API_CALL rm_is_altstack_in_use(void);
+
+void       NV_API_CALL rm_notify_gpu_addition(nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL rm_notify_gpu_removal(nvidia_stack_t *, nv_state_t *);
+
+/* vGPU VFIO specific functions */
+NV_STATUS  NV_API_CALL  nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *,
+                                               NvU32 *, NvU32 *, NvU32);
+NV_STATUS  NV_API_CALL  nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16);
+NV_STATUS  NV_API_CALL  nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool);
+NV_STATUS  NV_API_CALL  nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8);
+NV_STATUS  NV_API_CALL  nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *,
+                                             NvU64 *, NvU64 *, NvU32 *, NvBool *, NvU8 *);
+NV_STATUS  NV_API_CALL  nv_vgpu_update_sysfs_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU32 *);
+NV_STATUS  NV_API_CALL  nv_vgpu_get_hbm_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU64 *);
+NV_STATUS  NV_API_CALL  nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *);
+NV_STATUS  NV_API_CALL  nv_gpu_bind_event(nvidia_stack_t *, NvU32, NvBool *);
+NV_STATUS  NV_API_CALL  nv_gpu_unbind_event(nvidia_stack_t *, NvU32, NvBool *);
+
+nv_soc_irq_type_t NV_API_CALL nv_get_current_irq_type(nv_state_t*);
+void       NV_API_CALL  nv_flush_coherent_cpu_cache_range(nv_state_t *nv, NvU64 cpu_virtual, NvU64 size);
+
+/* Callbacks should occur roughly every 10ms. */
+#define NV_SNAPSHOT_TIMER_HZ 100
+void NV_API_CALL nv_start_snapshot_timer(void (*snapshot_callback)(void *context));
+void NV_API_CALL nv_flush_snapshot_timer(void);
+void NV_API_CALL nv_stop_snapshot_timer(void);
+
+static inline const NvU8 *nv_get_cached_uuid(nv_state_t *nv)
+{
+    return nv->nv_uuid_cache.valid ? nv->nv_uuid_cache.uuid : NULL;
+}
+
+/* nano second resolution timer callback structure */
+typedef struct nv_nano_timer nv_nano_timer_t;
+
+/* nano timer functions */
+void        NV_API_CALL nv_create_nano_timer(nv_state_t *, void *pTmrEvent, nv_nano_timer_t **);
+void        NV_API_CALL nv_start_nano_timer(nv_state_t *nv, nv_nano_timer_t *, NvU64 timens);
+NV_STATUS   NV_API_CALL rm_run_nano_timer_callback(nvidia_stack_t *, nv_state_t *, void *pTmrEvent);
+void        NV_API_CALL nv_cancel_nano_timer(nv_state_t *, nv_nano_timer_t *);
+void        NV_API_CALL nv_destroy_nano_timer(nv_state_t *nv, nv_nano_timer_t *);
+
+// Host1x specific functions.
+NV_STATUS NV_API_CALL nv_get_syncpoint_aperture(NvU32, NvU64 *, NvU64 *, NvU32 *);
+
+#if defined(NVCPU_X86_64)
+
+static inline NvU64 nv_rdtsc(void)
+{
+    NvU64 val;
+    __asm__ __volatile__ ("rdtsc               \t\n"
+                          "shlq   $0x20,%%rdx  \t\n"
+                          "orq    %%rdx,%%rax  \t\n"
+                          : "=A" (val));
+    return val;
+}
+
+#endif
+
+static inline NvBool nv_dev_needs_vidmem_preservation(const nv_state_t *nv)
+{
+    /*
+     * Tegra iGPUs and SoC display devices don't need vidmem preservation.
+     */
+    return !nv->is_tegra_pci_igpu && !NV_IS_SOC_DISPLAY_DEVICE(nv);
+}
+
+#endif /* NVRM */
+
+static inline int nv_count_bits(NvU64 word)
+{
+    NvU64 bits;
+
+    bits = (word & 0x5555555555555555ULL) + ((word >>  1) & 0x5555555555555555ULL);
+    bits = (bits & 0x3333333333333333ULL) + ((bits >>  2) & 0x3333333333333333ULL);
+    bits = (bits & 0x0f0f0f0f0f0f0f0fULL) + ((bits >>  4) & 0x0f0f0f0f0f0f0f0fULL);
+    bits = (bits & 0x00ff00ff00ff00ffULL) + ((bits >>  8) & 0x00ff00ff00ff00ffULL);
+    bits = (bits & 0x0000ffff0000ffffULL) + ((bits >> 16) & 0x0000ffff0000ffffULL);
+    bits = (bits & 0x00000000ffffffffULL) + ((bits >> 32) & 0x00000000ffffffffULL);
+
+    return (int)(bits);
+}
+
+#endif
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv_escape.h b/userspace/sdks/nv570/nvalloc/unix/include/nv_escape.h
new file mode 100644
index 0000000..601d9de
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/nv_escape.h
@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NV_ESCAPE_H_INCLUDED
+#define NV_ESCAPE_H_INCLUDED
+
+/* 
+ * NOTE: Any new ioctls added here should also be added to RmValidateIoctl() in escape.c
+ * or rm_validate_ioctls() in osapi.c
+ */
+#define NV_ESC_RM_ALLOC_MEMORY                      0x27
+#define NV_ESC_RM_ALLOC_OBJECT                      0x28
+#define NV_ESC_RM_FREE                              0x29
+#define NV_ESC_RM_CONTROL                           0x2A
+#define NV_ESC_RM_ALLOC                             0x2B
+#define NV_ESC_RM_DUP_OBJECT                        0x34
+#define NV_ESC_RM_SHARE                             0x35
+#define NV_ESC_RM_I2C_ACCESS                        0x39
+#define NV_ESC_RM_IDLE_CHANNELS                     0x41
+#define NV_ESC_RM_VID_HEAP_CONTROL                  0x4A
+#define NV_ESC_RM_ACCESS_REGISTRY                   0x4D
+#define NV_ESC_RM_MAP_MEMORY                        0x4E
+#define NV_ESC_RM_UNMAP_MEMORY                      0x4F
+#define NV_ESC_RM_GET_EVENT_DATA                    0x52
+#define NV_ESC_RM_ALLOC_CONTEXT_DMA2                0x54
+#define NV_ESC_RM_ADD_VBLANK_CALLBACK               0x56
+#define NV_ESC_RM_MAP_MEMORY_DMA                    0x57
+#define NV_ESC_RM_UNMAP_MEMORY_DMA                  0x58
+#define NV_ESC_RM_BIND_CONTEXT_DMA                  0x59
+#define NV_ESC_RM_EXPORT_OBJECT_TO_FD               0x5C
+#define NV_ESC_RM_IMPORT_OBJECT_FROM_FD             0x5D
+#define NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO        0x5E
+#define NV_ESC_RM_LOCKLESS_DIAGNOSTIC               0x5F
+
+#endif // NV_ESCAPE_H_INCLUDED
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/os-interface.h b/userspace/sdks/nv570/nvalloc/unix/include/os-interface.h
new file mode 100644
index 0000000..2a80c50
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/os-interface.h
@@ -0,0 +1,298 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+/*
+ * Os interface definitions needed by os-interface.c
+ */
+
+#ifndef OS_INTERFACE_H
+#define OS_INTERFACE_H
+
+/******************* Operating System Interface Routines *******************\
+*                                                                           *
+*       Operating system wrapper functions used to abstract the OS.         *
+*                                                                           *
+\***************************************************************************/
+
+#include <nvtypes.h>
+#include <nvstatus.h>
+#include "nv_stdarg.h"
+#include <nv-kernel-interface-api.h>
+#include <os/nv_memory_type.h>
+#include <os/nv_memory_area.h>
+#include <nv-caps.h>
+
+#include "rs_access.h"
+
+
+
+typedef struct
+{
+    NvU32  os_major_version;
+    NvU32  os_minor_version;
+    NvU32  os_build_number;
+    const char * os_build_version_str;
+    const char * os_build_date_plus_str;
+}os_version_info;
+
+/* Each OS defines its own version of this opaque type */
+struct os_work_queue;
+
+/* Each OS defines its own version of this opaque type */
+typedef struct os_wait_queue os_wait_queue;
+
+/* Flags needed by os_get_current_proccess_flags */
+#define OS_CURRENT_PROCESS_FLAG_NONE            0x0
+#define OS_CURRENT_PROCESS_FLAG_KERNEL_THREAD   0x1
+#define OS_CURRENT_PROCESS_FLAG_EXITING         0x2
+
+/*
+ * ---------------------------------------------------------------------------
+ *
+ * Function prototypes for OS interface.
+ *
+ * ---------------------------------------------------------------------------
+ */
+
+NV_STATUS   NV_API_CALL  os_alloc_mem                     (void **, NvU64);
+void        NV_API_CALL  os_free_mem                      (void *);
+NV_STATUS   NV_API_CALL  os_get_system_time               (NvU32 *, NvU32 *);
+NvU64       NV_API_CALL  os_get_monotonic_time_ns         (void);
+NvU64       NV_API_CALL  os_get_monotonic_time_ns_hr      (void);
+NvU64       NV_API_CALL  os_get_monotonic_tick_resolution_ns (void);
+NV_STATUS   NV_API_CALL  os_delay                         (NvU32);
+NV_STATUS   NV_API_CALL  os_delay_us                      (NvU32);
+NvU64       NV_API_CALL  os_get_cpu_frequency             (void);
+NvU32       NV_API_CALL  os_get_current_process           (void);
+void        NV_API_CALL  os_get_current_process_name      (char *, NvU32);
+NV_STATUS   NV_API_CALL  os_get_current_thread            (NvU64 *);
+char*       NV_API_CALL  os_string_copy                   (char *, const char *);
+NvU32       NV_API_CALL  os_string_length                 (const char *);
+NvU32       NV_API_CALL  os_strtoul                       (const char *, char **, NvU32);
+NvS32       NV_API_CALL  os_string_compare                (const char *, const char *);
+NvS32       NV_API_CALL  os_snprintf                      (char *, NvU32, const char *, ...);
+NvS32       NV_API_CALL  os_vsnprintf                     (char *, NvU32, const char *, va_list);
+void        NV_API_CALL  os_log_error                     (const char *, va_list);
+void*       NV_API_CALL  os_mem_copy                      (void *, const void *, NvU32);
+NV_STATUS   NV_API_CALL  os_memcpy_from_user              (void *, const void *, NvU32);
+NV_STATUS   NV_API_CALL  os_memcpy_to_user                (void *, const void *, NvU32);
+void*       NV_API_CALL  os_mem_set                       (void *, NvU8, NvU32);
+NvS32       NV_API_CALL  os_mem_cmp                       (const NvU8 *, const NvU8 *, NvU32);
+void*       NV_API_CALL  os_pci_init_handle               (NvU32, NvU8, NvU8, NvU8, NvU16 *, NvU16 *);
+NV_STATUS   NV_API_CALL  os_pci_read_byte                 (void *, NvU32, NvU8 *);
+NV_STATUS   NV_API_CALL  os_pci_read_word                 (void *, NvU32, NvU16 *);
+NV_STATUS   NV_API_CALL  os_pci_read_dword                (void *, NvU32, NvU32 *);
+NV_STATUS   NV_API_CALL  os_pci_write_byte                (void *, NvU32, NvU8);
+NV_STATUS   NV_API_CALL  os_pci_write_word                (void *, NvU32, NvU16);
+NV_STATUS   NV_API_CALL  os_pci_write_dword               (void *, NvU32, NvU32);
+NvBool      NV_API_CALL  os_pci_remove_supported          (void);
+void        NV_API_CALL  os_pci_remove                    (void *);
+void*       NV_API_CALL  os_map_kernel_space              (NvU64, NvU64, NvU32);
+void        NV_API_CALL  os_unmap_kernel_space            (void *, NvU64);
+NV_STATUS   NV_API_CALL  os_flush_cpu_cache_all           (void);
+NV_STATUS   NV_API_CALL  os_flush_user_cache              (void);
+void        NV_API_CALL  os_flush_cpu_write_combine_buffer(void);
+NvU8        NV_API_CALL  os_io_read_byte                  (NvU32);
+NvU16       NV_API_CALL  os_io_read_word                  (NvU32);
+NvU32       NV_API_CALL  os_io_read_dword                 (NvU32);
+void        NV_API_CALL  os_io_write_byte                 (NvU32, NvU8);
+void        NV_API_CALL  os_io_write_word                 (NvU32, NvU16);
+void        NV_API_CALL  os_io_write_dword                (NvU32, NvU32);
+NvBool      NV_API_CALL  os_is_administrator              (void);
+NvBool      NV_API_CALL  os_check_access                  (RsAccessRight accessRight);
+void        NV_API_CALL  os_dbg_init                      (void);
+void        NV_API_CALL  os_dbg_breakpoint                (void);
+void        NV_API_CALL  os_dbg_set_level                 (NvU32);
+NvU32       NV_API_CALL  os_get_cpu_count                 (void);
+NvU32       NV_API_CALL  os_get_cpu_number                (void);
+void        NV_API_CALL  os_disable_console_access        (void);
+void        NV_API_CALL  os_enable_console_access         (void);
+NV_STATUS   NV_API_CALL  os_registry_init                 (void);
+NvU64       NV_API_CALL  os_get_max_user_va               (void);
+NV_STATUS   NV_API_CALL  os_schedule                      (void);
+NV_STATUS   NV_API_CALL  os_alloc_spinlock                (void **);
+void        NV_API_CALL  os_free_spinlock                 (void *);
+NvU64       NV_API_CALL  os_acquire_spinlock              (void *);
+void        NV_API_CALL  os_release_spinlock              (void *, NvU64);
+NV_STATUS   NV_API_CALL  os_queue_work_item               (struct os_work_queue *, void *);
+NV_STATUS   NV_API_CALL  os_flush_work_queue              (struct os_work_queue *, NvBool);
+NvBool      NV_API_CALL  os_is_queue_flush_ongoing        (struct os_work_queue *);
+NV_STATUS   NV_API_CALL  os_alloc_mutex                   (void **);
+void        NV_API_CALL  os_free_mutex                    (void *);
+NV_STATUS   NV_API_CALL  os_acquire_mutex                 (void *);
+NV_STATUS   NV_API_CALL  os_cond_acquire_mutex            (void *);
+void        NV_API_CALL  os_release_mutex                 (void *);
+void*       NV_API_CALL  os_alloc_semaphore               (NvU32);
+void        NV_API_CALL  os_free_semaphore                (void *);
+NV_STATUS   NV_API_CALL  os_acquire_semaphore             (void *);
+NV_STATUS   NV_API_CALL  os_cond_acquire_semaphore        (void *);
+NV_STATUS   NV_API_CALL  os_release_semaphore             (void *);
+void*       NV_API_CALL  os_alloc_rwlock                  (void);
+void        NV_API_CALL  os_free_rwlock                   (void *);
+NV_STATUS   NV_API_CALL  os_acquire_rwlock_read           (void *);
+NV_STATUS   NV_API_CALL  os_acquire_rwlock_write          (void *);
+NV_STATUS   NV_API_CALL  os_cond_acquire_rwlock_read      (void *);
+NV_STATUS   NV_API_CALL  os_cond_acquire_rwlock_write     (void *);
+void        NV_API_CALL  os_release_rwlock_read           (void *);
+void        NV_API_CALL  os_release_rwlock_write          (void *);
+NvBool      NV_API_CALL  os_semaphore_may_sleep           (void);
+NV_STATUS   NV_API_CALL  os_get_version_info              (os_version_info*);
+NV_STATUS   NV_API_CALL  os_get_is_openrm                 (NvBool *);
+NvBool      NV_API_CALL  os_is_bif_reset_supported        (void *);
+NvBool      NV_API_CALL  os_is_isr                        (void);
+void        NV_API_CALL  os_dump_stack                    (void);
+NvBool      NV_API_CALL  os_is_efi_enabled                (void);
+NvBool      NV_API_CALL  os_is_xen_dom0                   (void);
+NvBool      NV_API_CALL  os_is_vgx_hyper                  (void);
+NV_STATUS   NV_API_CALL  os_inject_vgx_msi                (NvU16, NvU64, NvU32);
+NvBool      NV_API_CALL  os_is_grid_supported             (void);
+NvU32       NV_API_CALL  os_get_grid_csp_support          (void);
+void        NV_API_CALL  os_bug_check                     (NvU32, const char *);
+NV_STATUS   NV_API_CALL  os_lock_user_pages               (void *, NvU64, void **, NvU32);
+NV_STATUS   NV_API_CALL  os_lookup_user_io_memory         (void *, NvU64, NvU64 **);
+NV_STATUS   NV_API_CALL  os_unlock_user_pages             (NvU64, void *, NvU32);
+NV_STATUS   NV_API_CALL  os_match_mmap_offset             (void *, NvU64, NvU64 *);
+NV_STATUS   NV_API_CALL  os_get_euid                      (NvU32 *);
+NV_STATUS   NV_API_CALL  os_get_smbios_header             (NvU64 *pSmbsAddr);
+NV_STATUS   NV_API_CALL  os_get_acpi_rsdp_from_uefi       (NvU32 *);
+void        NV_API_CALL  os_add_record_for_crashLog       (void *, NvU32);
+void        NV_API_CALL  os_delete_record_for_crashLog    (void *);
+NV_STATUS   NV_API_CALL  os_call_vgpu_vfio                (void *, NvU32);
+NV_STATUS   NV_API_CALL  os_device_vm_present             (void);
+NV_STATUS   NV_API_CALL  os_numa_memblock_size            (NvU64 *);
+NV_STATUS   NV_API_CALL  os_alloc_pages_node              (NvS32, NvU32, NvU32, NvU64 *);
+NV_STATUS   NV_API_CALL  os_get_page                      (NvU64 address);
+NV_STATUS   NV_API_CALL  os_put_page                      (NvU64 address);
+NvU32       NV_API_CALL  os_get_page_refcount             (NvU64 address);
+NvU32       NV_API_CALL  os_count_tail_pages              (NvU64 address);
+void        NV_API_CALL  os_free_pages_phys               (NvU64, NvU32);
+NV_STATUS   NV_API_CALL  os_open_temporary_file           (void **);
+void        NV_API_CALL  os_close_file                    (void *);
+NV_STATUS   NV_API_CALL  os_write_file                    (void *, NvU8 *, NvU64, NvU64);
+NV_STATUS   NV_API_CALL  os_read_file                     (void *, NvU8 *, NvU64, NvU64);
+NV_STATUS   NV_API_CALL  os_open_readonly_file            (const char *, void **);
+NV_STATUS   NV_API_CALL  os_open_and_read_file            (const char *, NvU8 *, NvU64);
+NvBool      NV_API_CALL  os_is_nvswitch_present           (void);
+NV_STATUS   NV_API_CALL  os_get_random_bytes              (NvU8 *, NvU16);
+NvU32       NV_API_CALL  os_get_current_process_flags     (void);
+NV_STATUS   NV_API_CALL  os_alloc_wait_queue              (os_wait_queue **);
+void        NV_API_CALL  os_free_wait_queue               (os_wait_queue *);
+void        NV_API_CALL  os_wait_uninterruptible          (os_wait_queue *);
+void        NV_API_CALL  os_wait_interruptible            (os_wait_queue *);
+void        NV_API_CALL  os_wake_up                       (os_wait_queue *);
+nv_cap_t*   NV_API_CALL  os_nv_cap_init                   (const char *);
+nv_cap_t*   NV_API_CALL  os_nv_cap_create_dir_entry       (nv_cap_t *, const char *, int);
+nv_cap_t*   NV_API_CALL  os_nv_cap_create_file_entry      (nv_cap_t *, const char *, int);
+void        NV_API_CALL  os_nv_cap_destroy_entry          (nv_cap_t *);
+int         NV_API_CALL  os_nv_cap_validate_and_dup_fd    (const nv_cap_t *, int);
+void        NV_API_CALL  os_nv_cap_close_fd               (int);
+NvS32       NV_API_CALL  os_imex_channel_get              (NvU64);
+NvS32       NV_API_CALL  os_imex_channel_count            (void);
+NV_STATUS   NV_API_CALL  os_tegra_igpu_perf_boost         (void *, NvBool, NvU32);
+
+NV_STATUS   NV_API_CALL  os_get_tegra_platform       (NvU32 *);
+enum os_pci_req_atomics_type {
+    OS_INTF_PCIE_REQ_ATOMICS_32BIT,
+    OS_INTF_PCIE_REQ_ATOMICS_64BIT,
+    OS_INTF_PCIE_REQ_ATOMICS_128BIT
+};
+NV_STATUS   NV_API_CALL  os_enable_pci_req_atomics   (void *, enum os_pci_req_atomics_type);
+void        NV_API_CALL  os_pci_trigger_flr(void *handle);
+NV_STATUS   NV_API_CALL  os_get_numa_node_memory_usage (NvS32, NvU64 *, NvU64 *);
+NV_STATUS   NV_API_CALL  os_numa_add_gpu_memory      (void *, NvU64, NvU64, NvU32 *);
+NV_STATUS   NV_API_CALL  os_numa_remove_gpu_memory   (void *, NvU64, NvU64, NvU32); 
+NV_STATUS   NV_API_CALL  os_offline_page_at_address(NvU64 address);
+void*       NV_API_CALL  os_get_pid_info(void);
+void        NV_API_CALL  os_put_pid_info(void *pid_info);
+NV_STATUS   NV_API_CALL  os_find_ns_pid(void *pid_info, NvU32 *ns_pid);
+NvBool      NV_API_CALL  os_is_init_ns(void);
+NV_STATUS   NV_API_CALL  os_iommu_sva_bind(void *arg, void **handle, NvU32 *pasid);
+void        NV_API_CALL  os_iommu_sva_unbind(void *handle);
+NvBool      NV_API_CALL  os_supports_kernel_suspend_notifiers(void);
+
+extern NvU64 os_page_size;
+extern NvU64 os_max_page_size;
+extern NvU64 os_page_mask;
+extern NvU8  os_page_shift;
+extern NvBool os_cc_enabled;
+extern NvBool os_cc_sev_snp_enabled;
+extern NvBool os_cc_sme_enabled;
+extern NvBool os_cc_snp_vtom_enabled;
+extern NvBool os_cc_tdx_enabled;
+extern NvBool os_dma_buf_enabled;
+extern NvBool os_imex_channel_is_supported;
+
+/*
+ * ---------------------------------------------------------------------------
+ *
+ * Debug macros.
+ *
+ * ---------------------------------------------------------------------------
+ */
+
+#define NV_DBG_INFO       0x0
+#define NV_DBG_SETUP      0x1
+#define NV_DBG_USERERRORS 0x2
+#define NV_DBG_WARNINGS   0x3
+#define NV_DBG_ERRORS     0x4
+
+
+void NV_API_CALL  out_string(const char *str);
+int  NV_API_CALL  nv_printf(NvU32 debuglevel, const char *printf_format, ...);
+
+#define NV_DEV_PRINTF(debuglevel, nv, format, ... ) \
+        nv_printf(debuglevel, "NVRM: GPU " NV_PCI_DEV_FMT ": " format, NV_PCI_DEV_FMT_ARGS(nv), ## __VA_ARGS__)
+
+#define NV_DEV_PRINTF_STATUS(debuglevel, nv, status, format, ... ) \
+        nv_printf(debuglevel, "NVRM: GPU " NV_PCI_DEV_FMT ": " format " (0x%x)\n", NV_PCI_DEV_FMT_ARGS(nv), ## __VA_ARGS__, status)
+
+/*
+ * Fields for os_lock_user_pages flags parameter
+ */
+#define NV_LOCK_USER_PAGES_FLAGS_WRITE                     0:0
+#define NV_LOCK_USER_PAGES_FLAGS_WRITE_NO                  0x00000000
+#define NV_LOCK_USER_PAGES_FLAGS_WRITE_YES                 0x00000001
+
+// NV OS Tegra platform type defines
+#define NV_OS_TEGRA_PLATFORM_SIM        0
+#define NV_OS_TEGRA_PLATFORM_FPGA       1
+#define NV_OS_TEGRA_PLATFORM_SILICON    2
+
+/*
+ * Plumbing through cgroup dmem api
+ */
+#define OS_CGROUP_IMPL_NONE 0
+#define OS_CGROUP_IMPL_MISC 1
+#define OS_CGROUP_IMPL_DMEM 2
+NvU32 NV_API_CALL os_cgroup_implementation(void);
+void* NV_API_CALL os_dmem_cgroup_register_region(NvU64 size, const char *name);
+void NV_API_CALL os_dmem_cgroup_unregister_region(void *region);
+NV_STATUS NV_API_CALL os_dmem_cgroup_try_charge(void *region, NvU64 size, void **ret_pool, void **ret_limit_pool);
+void NV_API_CALL os_dmem_cgroup_uncharge(void *pool, NvU64 size);
+
+void* NV_API_CALL os_cgroup_for_pid(int pid, void *pidInfo);
+void* NV_API_CALL os_cgroup_get_from_fd(NvU32 fd);
+void NV_API_CALL os_cgroup_put(void *cgroup);
+
+#endif /* OS_INTERFACE_H */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/os_custom.h b/userspace/sdks/nv570/nvalloc/unix/include/os_custom.h
new file mode 100644
index 0000000..1effaf7
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/os_custom.h
@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _OS_CUSTOM_H_
+#define _OS_CUSTOM_H_
+
+/*!
+ * @file  os_custom.h
+ * @brief OS module specific definitions for this OS 
+ */
+
+#include <os-interface.h>
+
+// File modes, added for NVIDIA capabilities.
+#define OS_RUSR 00400                         // read permission, owner
+#define OS_WUSR 00200                         // write permission, owner
+#define OS_XUSR 00100                         // execute/search permission, owner
+#define OS_RWXU (OS_RUSR | OS_WUSR | OS_XUSR) // read, write, execute/search, owner
+#define OS_RGRP 00040                         // read permission, group
+#define OS_WGRP 00020                         // write permission, group
+#define OS_XGRP 00010                         // execute/search permission, group
+#define OS_RWXG (OS_RGRP | OS_WGRP | OS_XGRP) // read, write, execute/search, group
+#define OS_ROTH 00004                         // read permission, other
+#define OS_WOTH 00002                         // write permission, other
+#define OS_XOTH 00001                         // execute/search permission, other
+#define OS_RWXO (OS_ROTH | OS_WOTH | OS_XOTH) // read, write, execute/search, other
+#define OS_RUGO (OS_RUSR | OS_RGRP | OS_ROTH)
+#define OS_WUGO (OS_WUSR | OS_WGRP | OS_WOTH)
+#define OS_XUGO (OS_XUSR | OS_XGRP | OS_XOTH)
+
+// Trigger for collecting GPU state for later extraction.
+void RmLogGpuCrash(OBJGPU *);
+
+// This is callback function in the miniport.
+// The argument is a device extension, and must be cast as such to be useful.
+typedef void (*MINIPORT_CALLBACK)(void*);
+
+NV_STATUS   osPackageRegistry(OBJGPU *pGpu, PACKED_REGISTRY_TABLE *, NvU32 *);
+
+#endif // _OS_CUSTOM_H_
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/osapi.h b/userspace/sdks/nv570/nvalloc/unix/include/osapi.h
new file mode 100644
index 0000000..6402bdb
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/osapi.h
@@ -0,0 +1,203 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _OSAPI_H_
+#define _OSAPI_H_
+
+#include "core/system.h"
+#include "gpu/gpu.h"
+
+#include <os-interface.h> // NV_DBG_ERRORS
+#include <rmapi/rmapi.h>
+#include <core/thread_state.h>
+
+#if defined(__use_altstack__)
+#if defined(QA_BUILD)
+//---------------------------------------------------------------------------
+//
+// 32 bit debug marker values.
+//
+//---------------------------------------------------------------------------
+
+#define NV_MARKER1 (NvU32)(('M' << 24) | ('R' << 16) | ('V' << 8) | 'N')
+#define NV_MARKER2 (NvU32)(('N' << 24) | ('V' << 16) | ('R' << 8) | 'M')
+
+//
+// The two macros below implement a simple alternate stack usage sanity
+// check for QA_BUILD RM builds. NV_ALTSTACK_WRITE_MARKERS() fills
+// altstacks with NV_MARKER1, which enables NV_ALTSTACK_CHECK_MARKERS()
+// to determine the stack usage fairly reliably by looking for the
+// first clobbered marker. If more than 7/8 of the alternate stack were
+// used, NV_ALTSTACK_CHECK_MARKERS() prints an error and asserts.
+//
+#define NV_ALTSTACK_WRITE_MARKERS(sp)                                           \
+{                                                                               \
+    NvU32 i, *stack = (void *)(sp)->stack;                                      \
+    for (i = 0; i < ((sp)->size / sizeof(NvU32)); i++)                          \
+        stack[i] = NV_MARKER1;                                                  \
+}
+
+#define NV_ALTSTACK_CHECK_MARKERS(sp)                                           \
+{                                                                               \
+    NvU32 i, *stack = (void *)(sp)->stack;                                      \
+    for (i = 0; i < ((sp)->size / sizeof(NvU32)); i++)                          \
+    {                                                                           \
+        if (stack[i] != NV_MARKER1)                                             \
+            break;                                                              \
+    }                                                                           \
+    if ((i * sizeof(NvU32)) < ((sp)->size / 8))                                 \
+    {                                                                           \
+        nv_printf(NV_DBG_ERRORS, "NVRM: altstack: used %d of %d bytes!\n",      \
+                  ((sp)->size - (i * (NvU32)sizeof(NvU32))), (sp)->size);       \
+        NV_ASSERT_PRECOMP((i * sizeof(NvU32)) >= ((sp)->size / 8));             \
+    }                                                                           \
+}
+#else
+#define NV_ALTSTACK_WRITE_MARKERS(sp)
+#define NV_ALTSTACK_CHECK_MARKERS(sp)
+#endif
+#if defined(NVCPU_X86_64)
+#define NV_ENTER_RM_RUNTIME(sp,fp)                                              \
+{                                                                               \
+    NV_ALTSTACK_WRITE_MARKERS(sp);                                              \
+    __asm__ __volatile__ ("movq %%rbp,%0" : "=r" (fp)); /* save %rbp */         \
+    __asm__ __volatile__ ("movq %0,%%rbp" :: "r" ((sp)->top));                  \
+}
+
+#define NV_EXIT_RM_RUNTIME(sp,fp)                                               \
+{                                                                               \
+    register void *__rbp __asm__ ("rbp");                                       \
+    if (__rbp != (sp)->top)                                                     \
+    {                                                                           \
+        nv_printf(NV_DBG_ERRORS, "NVRM: detected corrupted runtime stack!\n");  \
+        NV_ASSERT_PRECOMP(__rbp == (sp)->top);                                  \
+    }                                                                           \
+    NV_ALTSTACK_CHECK_MARKERS(sp);                                              \
+    __asm__ __volatile__ ("movq %0,%%rbp" :: "r" (fp)); /* restore %rbp */      \
+}
+#else
+#error "gcc \"altstacks\" support is not implemented on this platform!"
+#endif
+#else
+#define NV_ENTER_RM_RUNTIME(sp,fp) { (void)sp; (void)fp; }
+#define NV_EXIT_RM_RUNTIME(sp,fp)
+#endif
+
+void       RmShutdownRm           (void);
+
+NvBool     RmInitPrivateState     (nv_state_t *);
+void       RmFreePrivateState     (nv_state_t *);
+
+NvBool     RmInitAdapter          (nv_state_t *);
+NvBool     RmPartiallyInitAdapter (nv_state_t *);
+void       RmShutdownAdapter      (nv_state_t *);
+void       RmDisableAdapter       (nv_state_t *);
+void       RmPartiallyDisableAdapter(nv_state_t *);
+NV_STATUS  RmGetAdapterStatus     (nv_state_t *, NvU32 *);
+NV_STATUS  RmExcludeAdapter       (nv_state_t *);
+
+NvBool     RmGpuHasIOSpaceEnabled (nv_state_t *);
+
+void       RmFreeUnusedClients    (nv_state_t *, nv_file_private_t *);
+NV_STATUS  RmIoctl                (nv_state_t *, nv_file_private_t *, NvU32, void *, NvU32);
+NV_STATUS  RmValidateIoctl        (NvU32, NvU32);
+
+void       RmI2cAddGpuPorts(nv_state_t *);
+
+NV_STATUS  RmInitX86EmuState(OBJGPU *);
+void       RmFreeX86EmuState(OBJGPU *);
+NV_STATUS  RmPowerSourceChangeEvent(nv_state_t *, NvU32);
+
+void       RmRequestDNotifierState(nv_state_t *);
+
+const NvU8 *RmGetGpuUuidRaw(nv_state_t *);
+
+NV_STATUS  nv_vbios_call(OBJGPU *, NvU32 *, NvU32 *);
+
+int        amd_adv_spec_cache_feature(OBJOS *);
+int        amd_msr_c0011022_incompatible(OBJOS *);
+
+NV_STATUS  rm_get_adapter_status    (nv_state_t *, NvU32 *);
+
+void       rm_client_free_os_events (NvHandle);
+
+NV_STATUS  rm_create_mmap_context   (NvHandle, NvHandle, NvHandle, NvP64, NvU64, NvU64, NvU32, NvU32);
+NV_STATUS  rm_update_device_mapping_info  (NvHandle, NvHandle, NvHandle, void *, void *);
+
+NV_STATUS  rm_access_registry       (NvHandle, NvHandle, NvU32, NvP64, NvU32, NvP64, NvU32, NvP64, NvU32 *, NvU32 *, NvU32 *);
+
+// registry management
+NV_STATUS  RmInitRegistry           (void);
+NV_STATUS  RmDestroyRegistry        (nv_state_t *);
+
+NV_STATUS  RmWriteRegistryDword     (nv_state_t *, const char *, NvU32 );
+NV_STATUS  RmReadRegistryDword      (nv_state_t *, const char *, NvU32 *);
+NV_STATUS  RmWriteRegistryString    (nv_state_t *, const char *, const char *, NvU32);
+NV_STATUS  RmReadRegistryBinary     (nv_state_t *, const char *, NvU8 *, NvU32 *);
+NV_STATUS  RmWriteRegistryBinary    (nv_state_t *, const char *, NvU8 *, NvU32);
+NV_STATUS  RmReadRegistryString     (nv_state_t *, const char *, NvU8 *, NvU32 *);
+
+NV_STATUS  RmPackageRegistry        (nv_state_t *, PACKED_REGISTRY_TABLE *, NvU32 *);
+
+NvBool     RmIsNvifFunctionSupported(NvU32, NvU32);
+void       RmInitAcpiMethods        (OBJOS *, OBJSYS *, OBJGPU *);
+void       RmUnInitAcpiMethods      (OBJSYS *);
+
+void       RmInflateOsToRmPageArray (RmPhysAddr *, NvU64);
+void       RmDeflateRmToOsPageArray (RmPhysAddr *, NvU64);
+
+void convertPageArrayBetweenOsAndRm(
+    RmPhysAddr *pteArray, 
+    NvU64 pageCountFrom,
+    NvU64 pageSizeFrom,
+    NvU64 pageCountTo,
+    NvU64 pageSizeTo,
+    NvU64 *newPageCountTo);
+
+#define IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc) \
+    (SYS_GET_INSTANCE()->bEnableDynamicGranularityPageArrays && !memdescGetContiguity(pMemDesc, AT_CPU))
+
+void       RmInitPowerManagement    (nv_state_t *);
+void       RmDestroyPowerManagement (nv_state_t *);
+
+NV_STATUS  RmPowerManagementTegra   (OBJGPU *pGpu, nv_pm_action_t pmAction);
+
+NV_STATUS  os_ref_dynamic_power     (nv_state_t *, nv_dynamic_power_mode_t);
+void       os_unref_dynamic_power   (nv_state_t *, nv_dynamic_power_mode_t);
+void       RmHandleDisplayChange    (nvidia_stack_t *, nv_state_t *);
+void       RmUpdateGc6ConsoleRefCount (nv_state_t *, NvBool);
+
+NvBool     rm_get_uefi_console_status (nv_state_t *);
+NvU64      rm_get_uefi_console_size (nv_state_t *, NvU64 *);
+
+void       rm_check_s0ix_regkey_and_platform_support(void);
+
+RM_API    *RmUnixRmApiPrologue      (nv_state_t *, THREAD_STATE_NODE *, NvU32 module);
+void       RmUnixRmApiEpilogue      (nv_state_t *, THREAD_STATE_NODE *);
+
+static inline NvBool rm_is_system_notebook(void)
+{
+    return (nv_is_chassis_notebook() || nv_acpi_is_battery_present());
+}
+
+#endif // _OSAPI_H_
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/rmobjexportimport.h b/userspace/sdks/nv570/nvalloc/unix/include/rmobjexportimport.h
new file mode 100644
index 0000000..a070c4e
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/rmobjexportimport.h
@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _RMOBJEXPORTIMPORT_H_
+#define _RMOBJEXPORTIMPORT_H_
+
+#include "nvstatus.h"
+
+typedef NvHandle RmObjExportHandle;
+
+NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject,
+                         RmObjExportHandle *pDstObject, NvU32 *pDeviceInstance);
+
+void RmFreeObjExportHandle(RmObjExportHandle hObject);
+
+NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent,
+                         NvHandle *phDstObject, RmObjExportHandle hSrcObject,
+                         NvU8 *pObjectType);
+#endif // _RMOBJEXPORTIMPORT_H_
+
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/debug.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/debug.h
new file mode 100644
index 0000000..6a37dfa
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/debug.h
@@ -0,0 +1,211 @@
+/****************************************************************************
+*
+*                                               Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                                    Copyright (C) David Mosberger-Tang
+*                                          Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for debug definitions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_DEBUG_H
+#define __X86EMU_DEBUG_H
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+/* checks to be enabled for "runtime" */
+
+#define CHECK_IP_FETCH_F                0x1
+#define CHECK_SP_ACCESS_F               0x2
+#define CHECK_MEM_ACCESS_F              0x4 /*using regular linear pointer */
+#define CHECK_DATA_ACCESS_F             0x8 /*using segment:offset*/
+
+#ifdef X86EMU_DEBUG
+# define CHECK_IP_FETCH()               (M.x86.check & CHECK_IP_FETCH_F)
+# define CHECK_SP_ACCESS()              (M.x86.check & CHECK_SP_ACCESS_F)
+# define CHECK_MEM_ACCESS()             (M.x86.check & CHECK_MEM_ACCESS_F)
+# define CHECK_DATA_ACCESS()            (M.x86.check & CHECK_DATA_ACCESS_F)
+#else
+# define CHECK_IP_FETCH()               0
+# define CHECK_SP_ACCESS()              0
+# define CHECK_MEM_ACCESS()             0
+# define CHECK_DATA_ACCESS()            0
+#endif
+
+#ifdef X86EMU_DEBUG
+# define DEBUG_INSTRUMENT()     (M.x86.debug & DEBUG_INSTRUMENT_F)
+# define DEBUG_DECODE()         (M.x86.debug & DEBUG_DECODE_F)
+# define DEBUG_TRACE()          (M.x86.debug & DEBUG_TRACE_F)
+# define DEBUG_STEP()           (M.x86.debug & DEBUG_STEP_F)
+# define DEBUG_DISASSEMBLE()    (M.x86.debug & DEBUG_DISASSEMBLE_F)
+# define DEBUG_BREAK()          (M.x86.debug & DEBUG_BREAK_F)
+# define DEBUG_SVC()            (M.x86.debug & DEBUG_SVC_F)
+# define DEBUG_SAVE_IP_CS()     (M.x86.debug & DEBUG_SAVE_IP_CS_F)
+
+# define DEBUG_FS()             (M.x86.debug & DEBUG_FS_F)
+# define DEBUG_PROC()           (M.x86.debug & DEBUG_PROC_F)
+# define DEBUG_SYSINT()         (M.x86.debug & DEBUG_SYSINT_F)
+# define DEBUG_TRACECALL()      (M.x86.debug & DEBUG_TRACECALL_F)
+# define DEBUG_TRACECALLREGS()  (M.x86.debug & DEBUG_TRACECALL_REGS_F)
+# define DEBUG_SYS()            (M.x86.debug & DEBUG_SYS_F)
+# define DEBUG_MEM_TRACE()      (M.x86.debug & DEBUG_MEM_TRACE_F)
+# define DEBUG_IO_TRACE()       (M.x86.debug & DEBUG_IO_TRACE_F)
+# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F)
+#else
+# define DEBUG_INSTRUMENT()     0
+# define DEBUG_DECODE()         0
+# define DEBUG_TRACE()          0
+# define DEBUG_STEP()           0
+# define DEBUG_DISASSEMBLE()    0
+# define DEBUG_BREAK()          0
+# define DEBUG_SVC()            0
+# define DEBUG_SAVE_IP_CS()     0
+# define DEBUG_FS()             0
+# define DEBUG_PROC()           0
+# define DEBUG_SYSINT()         0
+# define DEBUG_TRACECALL()      0
+# define DEBUG_TRACECALLREGS()  0
+# define DEBUG_SYS()            0
+# define DEBUG_MEM_TRACE()      0
+# define DEBUG_IO_TRACE()       0
+# define DEBUG_DECODE_NOPRINT() 0
+#endif
+
+#ifdef X86EMU_DEBUG
+
+# define DECODE_PRINTF(x)       if (DEBUG_DECODE()) \
+                                                                        x86emu_decode_printf(x)
+# define DECODE_PRINTF2(x,y)    if (DEBUG_DECODE()) \
+                                                                        x86emu_decode_printf2(x,y)
+
+/*
+ * The following allow us to look at the bytes of an instruction.  The
+ * first INCR_INSTRN_LEN, is called everytime bytes are consumed in
+ * the decoding process.  The SAVE_IP_CS is called initially when the
+ * major opcode of the instruction is accessed.
+ */
+#define INC_DECODED_INST_LEN(x)                         \
+        if (DEBUG_DECODE())                             \
+                x86emu_inc_decoded_inst_len(x)
+
+#define SAVE_IP_CS(x,y)                                                 \
+        if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \
+              | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
+                M.x86.saved_cs = x;                                             \
+                M.x86.saved_ip = y;                                             \
+        }
+#else
+# define INC_DECODED_INST_LEN(x)
+# define DECODE_PRINTF(x)
+# define DECODE_PRINTF2(x,y)
+# define SAVE_IP_CS(x,y)
+#endif
+
+#ifdef X86EMU_DEBUG
+#define TRACE_REGS()                                            \
+        if (DEBUG_DISASSEMBLE()) {                                      \
+                x86emu_just_disassemble();                              \
+                goto EndOfTheInstructionProcedure;                      \
+        }                                                       \
+        if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs()
+#else
+# define TRACE_REGS()
+#endif
+
+#ifdef X86EMU_DEBUG
+# define SINGLE_STEP()          if (DEBUG_STEP()) x86emu_single_step()
+#else
+# define SINGLE_STEP()
+#endif
+
+#define TRACE_AND_STEP()        \
+        TRACE_REGS();                   \
+        SINGLE_STEP()
+
+#ifdef X86EMU_DEBUG
+# define START_OF_INSTR()
+# define END_OF_INSTR()         EndOfTheInstructionProcedure: x86emu_end_instr();
+# define END_OF_INSTR_NO_TRACE()        x86emu_end_instr();
+#else
+# define START_OF_INSTR()
+# define END_OF_INSTR()
+# define END_OF_INSTR_NO_TRACE()
+#endif
+
+#ifdef X86EMU_DEBUG
+#include <os/os.h>
+# define  CALL_TRACE(u,v,w,x,s)                                 \
+        if (DEBUG_TRACECALLREGS())                                                                      \
+                x86emu_dump_regs();                                     \
+        if (DEBUG_TRACECALL())                                          \
+                NV_PRINTF(LEVEL_INFO, "%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x);
+# define RETURN_TRACE(n,u,v)                                    \
+        if (DEBUG_TRACECALLREGS())                                                                      \
+                x86emu_dump_regs();                                     \
+        if (DEBUG_TRACECALL())                                          \
+                NV_PRINTF(LEVEL_INFO, "%04x:%04x: %s\n",u,v,n);
+#else
+# define CALL_TRACE(u,v,w,x,s)
+# define RETURN_TRACE(n,u,v)
+#endif
+
+#ifdef X86EMU_DEBUG
+#define DB(x)   x
+#else
+#define DB(x)
+#endif
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {                                    /* Use "C" linkage when in C++ mode */
+#endif
+
+extern void x86emu_inc_decoded_inst_len (int x);
+extern void x86emu_decode_printf (const char *x);
+extern void x86emu_decode_printf2 (const char *x, int y);
+extern void x86emu_just_disassemble (void);
+extern void x86emu_single_step (void);
+extern void x86emu_end_instr (void);
+extern void x86emu_dump_regs (void);
+extern void x86emu_dump_xregs (void);
+extern void x86emu_print_int_vect (u16 iv);
+extern void x86emu_instrument_instruction (void);
+extern void x86emu_check_ip_access (void);
+extern void x86emu_check_sp_access (void);
+extern void x86emu_check_mem_access (u32 p);
+extern void x86emu_check_data_access (uint s, uint o);
+
+#ifdef  __cplusplus
+}                                               /* End of "C" linkage for C++           */
+#endif
+
+#endif /* __X86EMU_DEBUG_H */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/decode.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/decode.h
new file mode 100644
index 0000000..52eff18
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/decode.h
@@ -0,0 +1,88 @@
+/****************************************************************************
+*
+*                                               Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                                    Copyright (C) David Mosberger-Tang
+*                                          Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for instruction decoding logic.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_DECODE_H
+#define __X86EMU_DECODE_H
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+/* Instruction Decoding Stuff */
+
+#define FETCH_DECODE_MODRM(mod,rh,rl)   fetch_decode_modrm(&mod,&rh,&rl)
+#define DECODE_RM_BYTE_REGISTER(r)      decode_rm_byte_register(r)
+#define DECODE_RM_WORD_REGISTER(r)      decode_rm_word_register(r)
+#define DECODE_RM_LONG_REGISTER(r)      decode_rm_long_register(r)
+#define DECODE_CLEAR_SEGOVR()           M.x86.mode &= ~SYSMODE_CLRMASK
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {                                    /* Use "C" linkage when in C++ mode */
+#endif
+
+void    x86emu_intr_raise (u8 type);
+void    fetch_decode_modrm (int *mod,int *regh,int *regl);
+u8      fetch_byte_imm (void);
+u16     fetch_word_imm (void);
+u32     fetch_long_imm (void);
+u8      fetch_data_byte (uint offset);
+u8      fetch_data_byte_abs (uint segment, uint offset);
+u16     fetch_data_word (uint offset);
+u16     fetch_data_word_abs (uint segment, uint offset);
+u32     fetch_data_long (uint offset);
+u32     fetch_data_long_abs (uint segment, uint offset);
+void    store_data_byte (uint offset, u8 val);
+void    store_data_byte_abs (uint segment, uint offset, u8 val);
+void    store_data_word (uint offset, u16 val);
+void    store_data_word_abs (uint segment, uint offset, u16 val);
+void    store_data_long (uint offset, u32 val);
+void    store_data_long_abs (uint segment, uint offset, u32 val);
+u8*     decode_rm_byte_register(int reg);
+u16*    decode_rm_word_register(int reg);
+u32*    decode_rm_long_register(int reg);
+u16*    decode_rm_seg_register(int reg);
+u32     decode_rm00_address(int rm);
+u32     decode_rm01_address(int rm);
+u32     decode_rm10_address(int rm);
+u32     decode_sib_address(int sib, int mod);
+
+#ifdef  __cplusplus
+}                                               /* End of "C" linkage for C++           */
+#endif
+
+#endif /* __X86EMU_DECODE_H */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu.h
new file mode 100644
index 0000000..7c4f24e
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu.h
@@ -0,0 +1,61 @@
+/****************************************************************************
+*
+*                                               Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                                    Copyright (C) David Mosberger-Tang
+*                                          Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for FPU instruction decoding.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_FPU_H
+#define __X86EMU_FPU_H
+
+#ifdef  __cplusplus
+extern "C" {                                    /* Use "C" linkage when in C++ mode */
+#endif
+
+/* these have to be defined, whether 8087 support compiled in or not. */
+
+extern void x86emuOp_esc_coprocess_d8 (u8 op1);
+extern void x86emuOp_esc_coprocess_d9 (u8 op1);
+extern void x86emuOp_esc_coprocess_da (u8 op1);
+extern void x86emuOp_esc_coprocess_db (u8 op1);
+extern void x86emuOp_esc_coprocess_dc (u8 op1);
+extern void x86emuOp_esc_coprocess_dd (u8 op1);
+extern void x86emuOp_esc_coprocess_de (u8 op1);
+extern void x86emuOp_esc_coprocess_df (u8 op1);
+
+#ifdef  __cplusplus
+}                                               /* End of "C" linkage for C++           */
+#endif
+
+#endif /* __X86EMU_FPU_H */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu_regs.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu_regs.h
new file mode 100644
index 0000000..39ee7fe
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu_regs.h
@@ -0,0 +1,119 @@
+/****************************************************************************
+*
+*                                               Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                                    Copyright (C) David Mosberger-Tang
+*                                          Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for FPU register definitions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_FPU_REGS_H
+#define __X86EMU_FPU_REGS_H
+
+#ifdef X86_FPU_SUPPORT
+
+#ifdef PACK
+# pragma PACK
+#endif
+
+/* Basic 8087 register can hold any of the following values: */
+
+union x86_fpu_reg_u {
+    s8                  tenbytes[10];
+    double              dval;
+    float               fval;
+    s16                 sval;
+    s32                 lval;
+        };
+
+struct x86_fpu_reg {
+        union x86_fpu_reg_u reg;
+        char                tag;
+        };
+
+/*
+ * Since we are not going to worry about the problems of aliasing
+ * registers, every time a register is modified, its result type is
+ * set in the tag fields for that register.  If some operation
+ * attempts to access the type in a way inconsistent with its current
+ * storage format, then we flag the operation.  If common, we'll
+ * attempt the conversion.
+ */
+
+#define  X86_FPU_VALID          0x80
+#define  X86_FPU_REGTYP(r)      ((r) & 0x7F)
+
+#define  X86_FPU_WORD           0x0
+#define  X86_FPU_SHORT          0x1
+#define  X86_FPU_LONG           0x2
+#define  X86_FPU_FLOAT          0x3
+#define  X86_FPU_DOUBLE         0x4
+#define  X86_FPU_LDBL           0x5
+#define  X86_FPU_BSD            0x6
+
+#define  X86_FPU_STKTOP  0
+
+struct x86_fpu_registers {
+    struct x86_fpu_reg  x86_fpu_stack[8];
+    int                 x86_fpu_flags;
+    int                 x86_fpu_config;         /* rounding modes, etc. */
+    short               x86_fpu_tos, x86_fpu_bos;
+        };
+
+#ifdef END_PACK
+# pragma END_PACK
+#endif
+
+/*
+ * There are two versions of the following macro.
+ *
+ * One version is for opcode D9, for which there are more than 32
+ * instructions encoded in the second byte of the opcode.
+ *
+ * The other version, deals with all the other 7 i87 opcodes, for
+ * which there are only 32 strings needed to describe the
+ * instructions.
+ */
+
+#endif /* X86_FPU_SUPPORT */
+
+#ifdef X86EMU_DEBUG
+# define DECODE_PRINTINSTR32(t,mod,rh,rl)       \
+        DECODE_PRINTF(t[(mod<<3)+(rh)]);
+# define DECODE_PRINTINSTR256(t,mod,rh,rl)      \
+        DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]);
+#else
+# define DECODE_PRINTINSTR32(t,mod,rh,rl)
+# define DECODE_PRINTINSTR256(t,mod,rh,rl)
+#endif
+
+#endif /* __X86EMU_FPU_REGS_H */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/ops.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/ops.h
new file mode 100644
index 0000000..82d2bbe
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/ops.h
@@ -0,0 +1,45 @@
+/****************************************************************************
+*
+*                                               Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                                    Copyright (C) David Mosberger-Tang
+*                                          Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for operand decoding functions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_OPS_H
+#define __X86EMU_OPS_H
+
+extern void (*x86emu_optab[0x100])(u8 op1);
+extern void (*x86emu_optab2[0x100])(u8 op2);
+
+#endif /* __X86EMU_OPS_H */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/prim_ops.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/prim_ops.h
new file mode 100644
index 0000000..8978004
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/prim_ops.h
@@ -0,0 +1,141 @@
+/****************************************************************************
+*
+*                                               Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                                    Copyright (C) David Mosberger-Tang
+*                                          Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for primitive operation functions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_PRIM_OPS_H
+#define __X86EMU_PRIM_OPS_H
+
+#ifdef  __cplusplus
+extern "C" {                                    /* Use "C" linkage when in C++ mode */
+#endif
+
+u16     aaa_word (u16 d);
+u16     aas_word (u16 d);
+u16     aad_word (u16 d);
+u16     aam_word (u8 d);
+u8      adc_byte (u8 d, u8 s);
+u16     adc_word (u16 d, u16 s);
+u32     adc_long (u32 d, u32 s);
+u8      add_byte (u8 d, u8 s);
+u16     add_word (u16 d, u16 s);
+u32     add_long (u32 d, u32 s);
+u8      and_byte (u8 d, u8 s);
+u16     and_word (u16 d, u16 s);
+u32     and_long (u32 d, u32 s);
+u8      cmp_byte (u8 d, u8 s);
+u16     cmp_word (u16 d, u16 s);
+u32     cmp_long (u32 d, u32 s);
+u8      daa_byte (u8 d);
+u8      das_byte (u8 d);
+u8      dec_byte (u8 d);
+u16     dec_word (u16 d);
+u32     dec_long (u32 d);
+u8      inc_byte (u8 d);
+u16     inc_word (u16 d);
+u32     inc_long (u32 d);
+u8      or_byte (u8 d, u8 s);
+u16     or_word (u16 d, u16 s);
+u32     or_long (u32 d, u32 s);
+u8      neg_byte (u8 s);
+u16     neg_word (u16 s);
+u32     neg_long (u32 s);
+u8      not_byte (u8 s);
+u16     not_word (u16 s);
+u32     not_long (u32 s);
+u8      rcl_byte (u8 d, u8 s);
+u16     rcl_word (u16 d, u8 s);
+u32     rcl_long (u32 d, u8 s);
+u8      rcr_byte (u8 d, u8 s);
+u16     rcr_word (u16 d, u8 s);
+u32     rcr_long (u32 d, u8 s);
+u8      rol_byte (u8 d, u8 s);
+u16     rol_word (u16 d, u8 s);
+u32     rol_long (u32 d, u8 s);
+u8      ror_byte (u8 d, u8 s);
+u16     ror_word (u16 d, u8 s);
+u32     ror_long (u32 d, u8 s);
+u8      shl_byte (u8 d, u8 s);
+u16     shl_word (u16 d, u8 s);
+u32     shl_long (u32 d, u8 s);
+u8      shr_byte (u8 d, u8 s);
+u16     shr_word (u16 d, u8 s);
+u32     shr_long (u32 d, u8 s);
+u8      sar_byte (u8 d, u8 s);
+u16     sar_word (u16 d, u8 s);
+u32     sar_long (u32 d, u8 s);
+u16     shld_word (u16 d, u16 fill, u8 s);
+u32     shld_long (u32 d, u32 fill, u8 s);
+u16     shrd_word (u16 d, u16 fill, u8 s);
+u32     shrd_long (u32 d, u32 fill, u8 s);
+u8      sbb_byte (u8 d, u8 s);
+u16     sbb_word (u16 d, u16 s);
+u32     sbb_long (u32 d, u32 s);
+u8      sub_byte (u8 d, u8 s);
+u16     sub_word (u16 d, u16 s);
+u32     sub_long (u32 d, u32 s);
+void    test_byte (u8 d, u8 s);
+void    test_word (u16 d, u16 s);
+void    test_long (u32 d, u32 s);
+u8      xor_byte (u8 d, u8 s);
+u16     xor_word (u16 d, u16 s);
+u32     xor_long (u32 d, u32 s);
+void    imul_byte (u8 s);
+void    imul_word (u16 s);
+void    imul_long (u32 s);
+void    imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s);
+void    mul_byte (u8 s);
+void    mul_word (u16 s);
+void    mul_long (u32 s);
+void    idiv_byte (u8 s);
+void    idiv_word (u16 s);
+void    idiv_long (u32 s);
+void    div_byte (u8 s);
+void    div_word (u16 s);
+void    div_long (u32 s);
+void    ins (int size);
+void    outs (int size);
+u16     mem_access_word (int addr);
+void    push_word (u16 w);
+void    push_long (u32 w);
+u16     pop_word (void);
+u32             pop_long (void);
+
+#ifdef  __cplusplus
+}                                               /* End of "C" linkage for C++           */
+#endif
+
+#endif /* __X86EMU_PRIM_OPS_H */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/regs.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/regs.h
new file mode 100644
index 0000000..4cd0f8b
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/regs.h
@@ -0,0 +1,340 @@
+/****************************************************************************
+*
+*                                               Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                                    Copyright (C) David Mosberger-Tang
+*                                          Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for x86 register definitions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_REGS_H
+#define __X86EMU_REGS_H
+
+#include "x86emu/debug.h"
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+#ifdef PACK
+# pragma PACK
+#endif
+
+/*
+ * General EAX, EBX, ECX, EDX type registers.  Note that for
+ * portability, and speed, the issue of byte swapping is not addressed
+ * in the registers.  All registers are stored in the default format
+ * available on the host machine.  The only critical issue is that the
+ * registers should line up EXACTLY in the same manner as they do in
+ * the 386.  That is:
+ *
+ * EAX & 0xff  === AL
+ * EAX & 0xffff == AX
+ *
+ * etc.  The result is that alot of the calculations can then be
+ * done using the native instruction set fully.
+ */
+
+#ifdef  __BIG_ENDIAN__
+
+typedef struct {
+    u32 e_reg;
+        } I32_reg_t;
+
+typedef struct {
+        u16 filler0, x_reg;
+        } I16_reg_t;
+
+typedef struct {
+        u8 filler0, filler1, h_reg, l_reg;
+        } I8_reg_t;
+
+#else /* !__BIG_ENDIAN__ */
+
+typedef struct {
+    u32 e_reg;
+        } I32_reg_t;
+
+typedef struct {
+        u16 x_reg;
+        } I16_reg_t;
+
+typedef struct {
+        u8 l_reg, h_reg;
+        } I8_reg_t;
+
+#endif /* __BIG_ENDIAN__ */
+
+typedef union {
+        I32_reg_t   I32_reg;
+        I16_reg_t   I16_reg;
+        I8_reg_t    I8_reg;
+        } i386_general_register;
+
+struct i386_general_regs {
+        i386_general_register A, B, C, D;
+        };
+
+typedef struct i386_general_regs Gen_reg_t;
+
+struct i386_special_regs {
+        i386_general_register SP, BP, SI, DI, IP;
+        u32 FLAGS;
+        };
+
+/*
+ * Segment registers here represent the 16 bit quantities
+ * CS, DS, ES, SS.
+ */
+
+struct i386_segment_regs {
+    u16 CS, DS, SS, ES, FS, GS;
+        };
+
+/* 8 bit registers */
+#define R_AH  gen.A.I8_reg.h_reg
+#define R_AL  gen.A.I8_reg.l_reg
+#define R_BH  gen.B.I8_reg.h_reg
+#define R_BL  gen.B.I8_reg.l_reg
+#define R_CH  gen.C.I8_reg.h_reg
+#define R_CL  gen.C.I8_reg.l_reg
+#define R_DH  gen.D.I8_reg.h_reg
+#define R_DL  gen.D.I8_reg.l_reg
+
+/* 16 bit registers */
+#define R_AX  gen.A.I16_reg.x_reg
+#define R_BX  gen.B.I16_reg.x_reg
+#define R_CX  gen.C.I16_reg.x_reg
+#define R_DX  gen.D.I16_reg.x_reg
+
+/* 32 bit extended registers */
+#define R_EAX  gen.A.I32_reg.e_reg
+#define R_EBX  gen.B.I32_reg.e_reg
+#define R_ECX  gen.C.I32_reg.e_reg
+#define R_EDX  gen.D.I32_reg.e_reg
+
+/* special registers */
+#define R_SP  spc.SP.I16_reg.x_reg
+#define R_BP  spc.BP.I16_reg.x_reg
+#define R_SI  spc.SI.I16_reg.x_reg
+#define R_DI  spc.DI.I16_reg.x_reg
+#define R_IP  spc.IP.I16_reg.x_reg
+#define R_FLG spc.FLAGS
+
+/* special registers */
+#define R_SP  spc.SP.I16_reg.x_reg
+#define R_BP  spc.BP.I16_reg.x_reg
+#define R_SI  spc.SI.I16_reg.x_reg
+#define R_DI  spc.DI.I16_reg.x_reg
+#define R_IP  spc.IP.I16_reg.x_reg
+#define R_FLG spc.FLAGS
+
+/* special registers */
+#define R_ESP  spc.SP.I32_reg.e_reg
+#define R_EBP  spc.BP.I32_reg.e_reg
+#define R_ESI  spc.SI.I32_reg.e_reg
+#define R_EDI  spc.DI.I32_reg.e_reg
+#define R_EIP  spc.IP.I32_reg.e_reg
+#define R_EFLG spc.FLAGS
+
+/* segment registers */
+#define R_CS  seg.CS
+#define R_DS  seg.DS
+#define R_SS  seg.SS
+#define R_ES  seg.ES
+#define R_FS  seg.FS
+#define R_GS  seg.GS
+
+/* flag conditions   */
+#define FB_CF 0x0001            /* CARRY flag  */
+#define FB_PF 0x0004            /* PARITY flag */
+#define FB_AF 0x0010            /* AUX  flag   */
+#define FB_ZF 0x0040            /* ZERO flag   */
+#define FB_SF 0x0080            /* SIGN flag   */
+#define FB_TF 0x0100            /* TRAP flag   */
+#define FB_IF 0x0200            /* INTERRUPT ENABLE flag */
+#define FB_DF 0x0400            /* DIR flag    */
+#define FB_OF 0x0800            /* OVERFLOW flag */
+
+/* 80286 and above always have bit#1 set */
+#define F_ALWAYS_ON  (0x0002)   /* flag bits always on */
+
+/*
+ * Define a mask for only those flag bits we will ever pass back
+ * (via PUSHF)
+ */
+#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF)
+
+/* following bits masked in to a 16bit quantity */
+
+#define F_CF 0x0001             /* CARRY flag  */
+#define F_PF 0x0004             /* PARITY flag */
+#define F_AF 0x0010             /* AUX  flag   */
+#define F_ZF 0x0040             /* ZERO flag   */
+#define F_SF 0x0080             /* SIGN flag   */
+#define F_TF 0x0100             /* TRAP flag   */
+#define F_IF 0x0200             /* INTERRUPT ENABLE flag */
+#define F_DF 0x0400             /* DIR flag    */
+#define F_OF 0x0800             /* OVERFLOW flag */
+
+#define TOGGLE_FLAG(flag)       (M.x86.R_FLG ^= (flag))
+#define SET_FLAG(flag)          (M.x86.R_FLG |= (flag))
+#define CLEAR_FLAG(flag)        (M.x86.R_FLG &= ~(flag))
+#define ACCESS_FLAG(flag)       (M.x86.R_FLG & (flag))
+#define CLEARALL_FLAG(m)        (M.x86.R_FLG = 0)
+
+#define CONDITIONAL_SET_FLAG(COND,FLAG) \
+  if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG)
+
+#define F_PF_CALC 0x010000      /* PARITY flag has been calced    */
+#define F_ZF_CALC 0x020000      /* ZERO flag has been calced      */
+#define F_SF_CALC 0x040000      /* SIGN flag has been calced      */
+
+#define F_ALL_CALC      0xff0000        /* All have been calced   */
+
+/*
+ * Emulator machine state.
+ * Segment usage control.
+ */
+#define SYSMODE_SEG_DS_SS       0x00000001
+#define SYSMODE_SEGOVR_CS       0x00000002
+#define SYSMODE_SEGOVR_DS       0x00000004
+#define SYSMODE_SEGOVR_ES       0x00000008
+#define SYSMODE_SEGOVR_FS       0x00000010
+#define SYSMODE_SEGOVR_GS       0x00000020
+#define SYSMODE_SEGOVR_SS       0x00000040
+#define SYSMODE_PREFIX_REPE     0x00000080
+#define SYSMODE_PREFIX_REPNE    0x00000100
+#define SYSMODE_PREFIX_DATA     0x00000200
+#define SYSMODE_PREFIX_ADDR     0x00000400
+#define SYSMODE_INTR_PENDING    0x10000000
+#define SYSMODE_EXTRN_INTR      0x20000000
+#define SYSMODE_HALTED          0x40000000
+
+#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS      | \
+                                                 SYSMODE_SEGOVR_CS      | \
+                                                 SYSMODE_SEGOVR_DS      | \
+                                                 SYSMODE_SEGOVR_ES      | \
+                                                 SYSMODE_SEGOVR_FS      | \
+                                                 SYSMODE_SEGOVR_GS      | \
+                                                 SYSMODE_SEGOVR_SS)
+#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS      | \
+                                                 SYSMODE_SEGOVR_CS      | \
+                                                 SYSMODE_SEGOVR_DS      | \
+                                                 SYSMODE_SEGOVR_ES      | \
+                                                 SYSMODE_SEGOVR_FS      | \
+                                                 SYSMODE_SEGOVR_GS      | \
+                                                 SYSMODE_SEGOVR_SS      | \
+                                                 SYSMODE_PREFIX_DATA    | \
+                                                 SYSMODE_PREFIX_ADDR)
+
+#define  INTR_SYNCH           0x1
+#define  INTR_ASYNCH          0x2
+#define  INTR_HALTED          0x4
+
+typedef struct {
+    struct i386_general_regs    gen;
+    struct i386_special_regs    spc;
+    struct i386_segment_regs    seg;
+    /*
+     * MODE contains information on:
+     *  REPE prefix             2 bits  repe,repne
+     *  SEGMENT overrides       5 bits  normal,DS,SS,CS,ES
+     *  Delayed flag set        3 bits  (zero, signed, parity)
+     *  reserved                6 bits
+     *  interrupt #             8 bits  instruction raised interrupt
+     *  BIOS video segregs      4 bits
+     *  Interrupt Pending       1 bits
+     *  Extern interrupt        1 bits
+     *  Halted                  1 bits
+     */
+    u32                         mode;
+    volatile int                intr;   /* mask of pending interrupts */
+        int                         debug;
+#ifdef X86EMU_DEBUG
+        int                         check;
+    u16                         saved_ip;
+    u16                         saved_cs;
+    int                         enc_pos;
+    int                         enc_str_pos;
+    char                        decode_buf[32]; /* encoded byte stream  */
+    char                        decoded_buf[256]; /* disassembled strings */
+    char                        debug_cmd[64]; /* input for x86emu_single_step */
+#endif
+    u8                          intno;
+    u8                          __pad[3];
+        } X86EMU_regs;
+
+/****************************************************************************
+REMARKS:
+Structure maintaining the emulator machine state.
+
+MEMBERS:
+mem_base                - Base real mode memory for the emulator
+mem_size                - Size of the real mode memory block for the emulator
+private                 - private data pointer
+x86                     - X86 registers
+****************************************************************************/
+typedef struct {
+        unsigned long   mem_base;
+        unsigned long   mem_size;
+        void*           private;
+        X86EMU_regs             x86;
+        } X86EMU_sysEnv;
+
+#ifdef END_PACK
+# pragma END_PACK
+#endif
+
+/*----------------------------- Global Variables --------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {                                    /* Use "C" linkage when in C++ mode */
+#endif
+
+/* Global emulator machine state.
+ *
+ * We keep it global to avoid pointer dereferences in the code for speed.
+ */
+
+extern    X86EMU_sysEnv _X86EMU_env;
+#define   M             _X86EMU_env
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+/* Function to log information at runtime */
+
+void    printk(const char *fmt, ...);
+
+#ifdef  __cplusplus
+}                                               /* End of "C" linkage for C++           */
+#endif
+
+#endif /* __X86EMU_REGS_H */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/types.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/types.h
new file mode 100644
index 0000000..53c3e87
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/types.h
@@ -0,0 +1,93 @@
+/****************************************************************************
+*
+*                                               Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                                    Copyright (C) David Mosberger-Tang
+*                                          Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for x86 emulator type definitions.
+*
+****************************************************************************/
+
+
+#ifndef __X86EMU_TYPES_H
+#define __X86EMU_TYPES_H
+
+#ifndef NO_SYS_HEADERS
+#include <sys/types.h>
+#endif
+
+/*
+ * The following kludge is an attempt to work around typedef conflicts with
+ * <sys/types.h>.
+ */
+#define u8   x86emuu8
+#define u16  x86emuu16
+#define u32  x86emuu32
+#define u64  x86emuu64
+#define s8   x86emus8
+#define s16  x86emus16
+#define s32  x86emus32
+#define s64  x86emus64
+#define uint x86emuuint
+#define sint x86emusint
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+/* Currently only for Linux/32bit */
+#undef  __HAS_LONG_LONG__
+#if defined(__GNUC__) && !defined(NO_LONG_LONG)
+#define __HAS_LONG_LONG__
+#endif
+
+#define NUM32 int
+
+typedef unsigned char           u8;
+typedef unsigned short          u16;
+typedef unsigned NUM32          u32;
+#ifdef __HAS_LONG_LONG__
+typedef unsigned long long      u64;
+#endif
+
+typedef char                            s8;
+typedef short                           s16;
+typedef NUM32                           s32;
+#ifdef __HAS_LONG_LONG__
+typedef long long                       s64;
+#endif
+
+typedef unsigned int                    uint;
+typedef int                             sint;
+
+typedef u16 X86EMU_pioAddr;
+
+#undef NUM32
+
+#endif  /* __X86EMU_TYPES_H */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emu.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emu.h
new file mode 100644
index 0000000..935cc70
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emu.h
@@ -0,0 +1,205 @@
+/****************************************************************************
+*
+*                                               Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                                    Copyright (C) David Mosberger-Tang
+*                                          Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for public specific functions.
+*               Any application linking against us should only
+*               include this header
+*
+****************************************************************************/
+
+#ifndef __X86EMU_X86EMU_H
+#define __X86EMU_X86EMU_H
+
+// NV
+#ifndef NO_SYS_HEADERS
+#define NO_SYS_HEADERS
+#endif
+
+#ifdef SCITECH
+#include "scitech.h"
+#define X86API  _ASMAPI
+#define X86APIP _ASMAPIP
+typedef int X86EMU_pioAddr;
+#else
+#include "x86emu/types.h"
+#define X86API
+#define X86APIP *
+#endif
+#include "x86emu/regs.h"
+#include "x86emu/debug.h"
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+#ifdef PACK
+# pragma        PACK   /* Don't pack structs with function pointers! */
+#endif
+
+/****************************************************************************
+REMARKS:
+Data structure containing ponters to programmed I/O functions used by the
+emulator. This is used so that the user program can hook all programmed
+I/O for the emulator to handled as necessary by the user program. By
+default the emulator contains simple functions that do not do access the
+hardware in any way. To allow the emualtor access the hardware, you will
+need to override the programmed I/O functions using the X86EMU_setupPioFuncs
+function.
+
+HEADER:
+x86emu.h
+
+MEMBERS:
+inb             - Function to read a byte from an I/O port
+inw             - Function to read a word from an I/O port
+inl     - Function to read a dword from an I/O port
+outb    - Function to write a byte to an I/O port
+outw    - Function to write a word to an I/O port
+outl    - Function to write a dword to an I/O port
+****************************************************************************/
+typedef struct {
+        u8      (X86APIP inb)(X86EMU_pioAddr addr);
+        u16     (X86APIP inw)(X86EMU_pioAddr addr);
+        u32     (X86APIP inl)(X86EMU_pioAddr addr);
+        void    (X86APIP outb)(X86EMU_pioAddr addr, u8 val);
+        void    (X86APIP outw)(X86EMU_pioAddr addr, u16 val);
+        void    (X86APIP outl)(X86EMU_pioAddr addr, u32 val);
+        } X86EMU_pioFuncs;
+
+/****************************************************************************
+REMARKS:
+Data structure containing ponters to memory access functions used by the
+emulator. This is used so that the user program can hook all memory
+access functions as necessary for the emulator. By default the emulator
+contains simple functions that only access the internal memory of the
+emulator. If you need specialised functions to handle access to different
+types of memory (ie: hardware framebuffer accesses and BIOS memory access
+etc), you will need to override this using the X86EMU_setupMemFuncs
+function.
+
+HEADER:
+x86emu.h
+
+MEMBERS:
+rdb             - Function to read a byte from an address
+rdw             - Function to read a word from an address
+rdl     - Function to read a dword from an address
+wrb             - Function to write a byte to an address
+wrw     - Function to write a word to an address
+wrl     - Function to write a dword to an address
+****************************************************************************/
+typedef struct {
+        u8      (X86APIP rdb)(u32 addr);
+        u16     (X86APIP rdw)(u32 addr);
+        u32     (X86APIP rdl)(u32 addr);
+        void    (X86APIP wrb)(u32 addr, u8 val);
+        void    (X86APIP wrw)(u32 addr, u16 val);
+        void    (X86APIP wrl)(u32 addr, u32 val);
+        } X86EMU_memFuncs;
+
+/****************************************************************************
+  Here are the default memory read and write
+  function in case they are needed as fallbacks.
+***************************************************************************/
+extern u8 X86API rdb(u32 addr);
+extern u16 X86API rdw(u32 addr);
+extern u32 X86API rdl(u32 addr);
+extern void X86API wrb(u32 addr, u8 val);
+extern void X86API wrw(u32 addr, u16 val);
+extern void X86API wrl(u32 addr, u32 val);
+
+#ifdef END_PACK
+# pragma        END_PACK
+#endif
+
+/*--------------------- type definitions -----------------------------------*/
+
+typedef void (X86APIP X86EMU_intrFuncs)(int num);
+extern X86EMU_intrFuncs _X86EMU_intrTab[256];
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {                                    /* Use "C" linkage when in C++ mode */
+#endif
+
+void    X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs);
+void    X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs);
+void    X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]);
+void    X86EMU_prepareForInt(int num);
+
+/* decode.c */
+
+void    X86EMU_exec(void);
+void    X86EMU_halt_sys(void);
+
+#ifdef  X86EMU_DEBUG
+#define HALT_SYS()   do {   \
+        NV_PRINTF(LEVEL_INFO, "halt_sys: file %s, line %d\n", __FILE__, __LINE__); \
+        X86EMU_halt_sys(); \
+        } while (0)
+#else
+#define HALT_SYS()      X86EMU_halt_sys()
+#endif
+
+/* Debug options */
+
+#define DEBUG_DECODE_F          0x000001 /* print decoded instruction  */
+#define DEBUG_TRACE_F           0x000002 /* dump regs before/after execution */
+#define DEBUG_STEP_F            0x000004
+#define DEBUG_DISASSEMBLE_F     0x000008
+#define DEBUG_BREAK_F           0x000010
+#define DEBUG_SVC_F             0x000020
+#define DEBUG_SAVE_IP_CS_F      0x000040
+#define DEBUG_FS_F              0x000080
+#define DEBUG_PROC_F            0x000100
+#define DEBUG_SYSINT_F          0x000200 /* bios system interrupts. */
+#define DEBUG_TRACECALL_F       0x000400
+#define DEBUG_INSTRUMENT_F      0x000800
+#define DEBUG_MEM_TRACE_F       0x001000
+#define DEBUG_IO_TRACE_F        0x002000
+#define DEBUG_TRACECALL_REGS_F  0x004000
+#define DEBUG_DECODE_NOPRINT_F  0x008000
+#define DEBUG_EXIT              0x010000
+#define DEBUG_SYS_F             (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F)
+
+void    X86EMU_trace_regs(void);
+void    X86EMU_trace_xregs(void);
+void    X86EMU_dump_memory(u16 seg, u16 off, u32 amt);
+int     X86EMU_trace_on(void);
+int     X86EMU_trace_off(void);
+
+#ifdef  __cplusplus
+}                                               /* End of "C" linkage for C++           */
+#endif
+
+#endif /* __X86EMU_X86EMU_H */
diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emui.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emui.h
new file mode 100644
index 0000000..5788558
--- /dev/null
+++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emui.h
@@ -0,0 +1,113 @@
+/****************************************************************************
+*
+*                                               Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                                    Copyright (C) David Mosberger-Tang
+*                                          Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for system specific functions. These functions
+*                               are always compiled and linked in the OS depedent libraries,
+*                               and never in a binary portable driver.
+*
+****************************************************************************/
+
+
+#ifndef __X86EMU_X86EMUI_H
+#define __X86EMU_X86EMUI_H
+
+/* If we are compiling in C++ mode, we can compile some functions as
+ * inline to increase performance (however the code size increases quite
+ * dramatically in this case).
+ */
+
+// NV
+#ifndef NO_SYS_HEADERS
+#define NO_SYS_HEADERS
+#endif
+#include <stddef.h> /* NULL */
+#if     defined(__cplusplus) && !defined(_NO_INLINE)
+#define _INLINE inline
+#else
+#define _INLINE static
+#endif
+
+/* Get rid of unused parameters in C++ compilation mode */
+
+#ifdef __cplusplus
+#define X86EMU_UNUSED(v)
+#else
+#define X86EMU_UNUSED(v)        v
+#endif
+
+#include "x86emu.h"
+#include "x86emu/regs.h"
+#include "x86emu/debug.h"
+#include "x86emu/decode.h"
+#include "x86emu/ops.h"
+#include "x86emu/prim_ops.h"
+#include "x86emu/fpu.h"
+#include "x86emu/fpu_regs.h"
+
+#ifndef NO_SYS_HEADERS
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#endif
+
+// On x86_64 abs() is not recognized. I don't understand why.
+#ifndef abs
+#define abs(i)  __builtin_abs(i)
+#endif
+
+/*--------------------------- Inline Functions ----------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {                                    /* Use "C" linkage when in C++ mode */
+#endif
+
+extern u8       (X86APIP sys_rdb)(u32 addr);
+extern u16      (X86APIP sys_rdw)(u32 addr);
+extern u32      (X86APIP sys_rdl)(u32 addr);
+extern void (X86APIP sys_wrb)(u32 addr,u8 val);
+extern void (X86APIP sys_wrw)(u32 addr,u16 val);
+extern void (X86APIP sys_wrl)(u32 addr,u32 val);
+
+extern u8       (X86APIP sys_inb)(X86EMU_pioAddr addr);
+extern u16      (X86APIP sys_inw)(X86EMU_pioAddr addr);
+extern u32      (X86APIP sys_inl)(X86EMU_pioAddr addr);
+extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val);
+extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val);
+extern void     (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val);
+
+#ifdef  __cplusplus
+}                                               /* End of "C" linkage for C++           */
+#endif
+
+#endif /* __X86EMU_X86EMUI_H */