Initial commit: Open-IOV vGPU-IO complete stack

- Firmware decompilation: GSP 570.144W (28.5MB ELF, RV64IMAC), 132 decompiled C files
- Kernel modules: nvidia.ko (34MB, OpenRM), open-iov-vfio.ko (2.8MB, VFIO mdev), gsp-vgpu.ko (1.8MB, guest driver)
- Userspace: libiov.so/libvgpu.so (76KB), example_vgpu (28KB), rpc_emulator.c
- PCI config space emulation (256B with PM, MSI, MSI-X, PCIe caps)
- 12 RPC types fully mapped from firmware decompilation
- BAR trap, WPR, scheduling, notification, migration emulation
- Helper scripts: load_vgpu_stack, create_mdev, launch_qemu_vgpu, test_vgpu_stack, setup_guest_driver, unload_vgpu_stack
- Architecture documentation
- Wiki: 10 technical documents
- Git LFS for large binaries (.ko, .bin, .iso, .img, .o, ghidra repos)
- nvidia-open-gpu-kernel-modules as submodule

4 files changed, 1464 insertions, 0 deletions

diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h
new file mode 100644
index 0000000..54c6441
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h
@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrlb0cc/ctrlb0ccbase.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+#include "ctrl/ctrl2080/ctrl2080gpu.h"  // NV2080_CTRL_GPU_REG_OP
+#define NVB0CC_CTRL_CMD(cat,idx)                     NVXXXX_CTRL_CMD(0xB0CC, NVB0CC_CTRL_##cat, idx)
+
+/* MAXWELL_PROFILER command categories (6 bits) */
+#define NVB0CC_CTRL_RESERVED (0x00)
+#define NVB0CC_CTRL_PROFILER (0x01)
+#define NVB0CC_CTRL_INTERNAL (0x02)
+
+/*!
+ * NVB0CC_CTRL_CMD_NULL
+ *
+ *    This command does nothing.
+ *    This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ */
+#define NVB0CC_CTRL_CMD_NULL (0xb0cc0000) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+
+/* _ctrlb0ccbase_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h
new file mode 100644
index 0000000..3723dea
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h
@@ -0,0 +1,283 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrlb0cc/ctrlb0ccinternal.finn
+//
+
+#include "ctrl/ctrlb0cc/ctrlb0ccbase.h"
+
+#include "ctrl/ctrlb0cc/ctrlb0ccprofiler.h"        /* Some controls derivative of b0ccprofiler */
+/*!
+ * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0204) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */
+
+
+// FINN PORT: The below type was generated by the FINN port to
+// ensure that all API's have a unique structure associated
+// with them!
+#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID (0x0U)
+
+typedef struct NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS {
+    NV_DECLARE_ALIGNED(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS params, 8);
+} NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL
+ *
+ * This command is used to quiesce ongoing HWPM streamout and wait for PMA engine to
+ * become idle. After this point, no new PMA records would be generated and
+ * membytes streaming would be triggered if GR context is resident or HWPM ctxsw is disabled.
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL (0xb0cc0201) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS {
+    /*!
+     * [in] The PMA Channel Index associated with a given PMA stream.
+     */
+    NvU32  pmaChannelIdx;
+
+    /*!
+     * [out] Will return if membytes streaming was triggered, to decide if
+     *       we need to poll membytes value on guest to complete streamout.
+     */
+    NvBool bMembytesPollingRequired;
+} NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM
+ *
+ * Currently only used in vGPU full SRIOV mode.
+ * This command is used to promote VAs and required info about the HWPM IB
+ * and PMA buffers from guest to host in full SRIOV mode.
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM (0xb0cc0202) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS {
+    /*!
+     * [in] The PMA Channel Index associated with a given PMA stream.
+     */
+    NvU32 pmaChannelIdx;
+    /*!
+     * [in] PMA records buffer VA.
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8);
+
+    /*!
+     * [in] size of the PMA records buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX.
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8);
+
+    /*!
+     * [in] Membytes buffer VA.
+     */
+    NV_DECLARE_ALIGNED(NvU64 membytesVA, 8);
+
+    /*!
+     * [in] HWPM PMA Instance Block PA
+     */
+    NV_DECLARE_ALIGNED(NvU64 hwpmIBPA, 8);
+
+    /*!
+     * [in] HWPM PMA Instance Block aperture
+     */
+    NvU8  hwpmIBAperture;
+} NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT
+ *
+ * This command is used to convey the client permissions for appropriate
+ * profiling capability initialization
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT (0xb0cc0203) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS {
+    /*!
+     * [in] Is Admin profiling permitted
+     */
+    NvBool bAdminProfilingPermitted;
+
+    /*!
+     * [in] Is Device profiling permitted
+     */
+    NvBool bDevProfilingPermitted;
+
+    /*!
+     * [in] Is Device tracing permitted
+     */
+    NvBool bDevTracePermitted;
+
+    /*!
+     * [in] Is Context profiling permitted
+     */
+    NvBool bCtxProfilingPermitted;
+
+    /*!
+     * [in] Is Video memory profiling permitted
+     */
+    NvBool bVideoMemoryProfilingPermitted;
+
+    /*!
+     * [in] Is SYS memory profiling permitted
+     */
+    NvBool bSysMemoryProfilingPermitted;
+
+    /*!
+     * [in] Is Async CE profiling permitted
+     */
+    NvBool bAsyncCeProfilingPermitted;
+} NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS;
+
+#define NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS {
+    /*!
+     * [in] Memory handle (RW memory) for streaming records.
+     * Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize.
+     */
+    NvHandle hMemPmaBuffer;
+
+    /*!
+     * [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer).
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8);
+
+    /*!
+     * [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX.
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8);
+
+    /*!
+     * [in] Memory handle (RO memory) for streaming number of bytes available.
+     * Size of this must be of at least @ref pmaBytesAvailableOffset +
+     * @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE.
+     */
+    NvHandle hMemPmaBytesAvailable;
+
+    /*!
+     * [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable).
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8);
+
+    /*!
+     * [in] Enable ctxsw for PMA stream.
+     */
+    NvBool   ctxsw;
+
+    /*!
+     * [in/out] The PMA Channel Index associated with a given PMA stream.
+     * This parameter is input when bInputPmaChIdx is true, else it's output parameter.
+     */
+    NvU32    pmaChannelIdx;
+
+    /*!
+     * [out] PMA buffer VA. Note that this is a HWPM Virtual address.
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8);
+
+    /*!
+    * [In] This field must be specified by the client to indicate whether the
+    * pmaChannelIdx is input parameter or output parameter.
+    */
+    NvBool   bInputPmaChIdx;
+} NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS;
+
+
+
+/*!
+ * NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM
+ *
+ * Internal logic for PMA Stream Free
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM (0xb0cc0206) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS {
+    /*!
+     * [in] The PMA channel index associated with a given PMA stream.
+     */
+    NvU32 pmaChannelIdx;
+} NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS
+ *
+ * Get the maximum number of PMA channels
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS (0xb0cc0207) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS {
+    /*!
+     * [out] Max number of PMA channels
+     */
+    NvU32 maxPmaChannels;
+} NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES
+ *
+ * Internally bind PM resources.
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES   (0xb0cc0208) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x8" */
+
+
+/*!
+ * NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES
+ *
+ * Internally unbind PM resources.
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES (0xb0cc0209) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x9" */
+
+/*!
+ * NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY
+ *
+ * Reserve legacy HWPM resources
+ */
+#define NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY (0xb0cc020a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0xaU)
+
+typedef struct NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS {
+    /*!
+     * [in] Enable ctxsw for HWPM.
+     */
+    NvBool ctxsw;
+} NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS;
+
+/* _ctrlb0ccinternal_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h
new file mode 100644
index 0000000..672aa24
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h
@@ -0,0 +1,402 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrlb0cc/ctrlb0ccpower.finn
+//
+
+#include "ctrl/ctrlb0cc/ctrlb0ccbase.h"
+
+/*
+ * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES
+ *
+ * This command attempts to enable or disable various clock-gating features of
+ * the GPU on behalf of the profiler. If this command is unable to set the
+ * clock-gating feature state of any of the requested features, this command
+ * will fail and none of the requested features will be modified. If this
+ * command fails because one or more clock-gating feature requests were
+ * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus
+ * parameter and the fields in the statusMask parameter for the features for
+ * which the requests were rejected will have the value
+ * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED.
+ * If a given feature is not supported on the GPU, the field for that clock-
+ * gating feature will have the value
+ * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED in the
+ * statusMask parameter, but this condition by itself will not cause the
+ * command to fail. Even if this command fails, the field for clock-gating
+ * features which would have successfully changed will have the value
+ * NVB0CC_CTRL_POWER_FEATURE_MASK_*_FULFILLED in the statusMask
+ * parameter.
+ *
+ * Each of the clock-gating features is reference-counted individually, so
+ * that multiple MAXWELL_PROFILER objects may request and rely on the same
+ * settings for the features simultaneously. Each clock-gating feature is
+ * locked to the requested state until the MAXWELL_PROFILER object is freed or
+ * the NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES command is called for that
+ * feature.
+ *
+ * Currently, only MAXWELL_PROFILER requests for power features using this
+ * command are reference counted. Changes to the power feature settings made
+ * either by other control commands or the RM itself may interfere with the
+ * settings requested by MAXWELL_PROFILER instances.
+ *
+ * This command will always return NV_OK when given valid
+ * parameters. If there is any other failure that prevents the clock-gating
+ * features from being set appropriately, the globalStatus parameter will
+ * indicate this and the statusMask parameter will indicate which clock-gating
+ * feature requests failed and why.
+ *
+ *   controlMask
+ *     This parameter indicates which clock-gating features the request should
+ *     apply to. This parameter has the following fields:
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG
+ *         The value of this field indicates whether this request should apply
+ *         to engine-level clock-gating of the GR engine. Valid values for
+ *         this field are:
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE
+ *             This value indicates that the GR engine-level clock-gating
+ *             should be ignored. This will not affect the reference count for
+ *             this feature.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE
+ *             This value indicates that the GR engine-level clock-gating
+ *             should be disabled.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE
+ *             This value indicates that the GR engine-level clock-gating
+ *             should be enabled.
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG
+ *         The value of this field indicates whether this request should apply
+ *         to block-level clock-gating. Valid values for this field are:
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE
+ *             This value indicates that block-level clock-gating should be
+ *             ignored. This will not affect the reference count for this
+ *             feature.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE
+ *             This value indicates that block-level clock-gating should be
+ *             disabled.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE
+ *             This value indicates that block-level clock-gating should be
+ *             enabled.
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG
+ *         The value of this field indicates whether this request should apply
+ *         to second-level clock-gating. Valid values for this field are:
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE
+ *             This value indicates that second-level clock-gating should be
+ *             ignored. This will not affect the reference count for this
+ *             feature.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE
+ *             This value indicates that second-level clock-gating should be
+ *             disabled.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE
+ *             This value indicates that second-level clock-gating should be
+ *             enabled.
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG
+ *         The value of this field indicates whether this request should apply
+ *         to GR engine-level power-gating. Valid values for this field are:
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE
+ *             This value indicates that engine-level power-gating should be
+ *             ignored. This will not affect the reference count for this
+ *             feature.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE
+ *             This value indicates that engine-level power-gating should be
+ *             disabled.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE
+ *             This value indicates that engine-level power-gating should be
+ *             enabled.
+ *         Note that this field is only temporary to allow reference counting
+ *         restricted to MAXWELL_PROFILER instances, until the time when the
+ *         existing controls for this power feature can be updated to support
+ *         reference counting across all clients and the RM.
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN
+ *         The value of this field indicates whether this request should apply
+ *         to SM idle slowdown. Valid values for this field are:
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE
+ *             This value indicates that SM idle slowdown should be ignored.
+ *             This will not affect the reference count for this feature.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE
+ *             This value indicates that SM idle slowdown should be disabled.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE
+ *             This value indicates that SM idle slowdown should be enabled.
+ *         Note that this field is only temporary to allow reference counting
+ *         restricted to MAXWELL_PROFILER instances, until the time when the
+ *         existing controls for this power feature can be updated to support
+ *         reference counting across all clients and the RM.
+  *       NVB0CC_CTRL_POWER_FEATURE_MASK_VAT
+ *         The value of this field indicates whether this request should apply
+ *         to VAT. Valid values for this field are:
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE
+ *             This value indicates that VAT should be ignored.
+ *             This will not affect the reference count for this feature.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE
+ *             This value indicates that VAT should be disabled.
+ *           NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE
+ *             This value indicates that VAT should be enabled.
+ *         Note that this field is only temporary to allow reference counting
+ *         restricted to MAXWELL_PROFILER instances, until the time when the
+ *         existing controls for this power feature can be updated to support
+ *         reference counting across all clients and the RM.
+ *   globalStatus
+ *     This parameter returns the overall status of the requests for all
+ *     clock-gating controls. If the value of this parameter is not
+ *     NV_OK, none of the clock-gating controls will be set as
+ *     requested. Possible values for this parameter are:
+ *       NV_OK
+ *         This value indicates that all of the clock-gating control requests
+ *         were either fulfilled or not supported on the hardware.
+ *       NV_ERR_INVALID_REQUEST
+ *         This value indicates that at least one of the clock-gating control
+ *         requests were invalid given the MAXWELL_PROFILER instance's
+ *         outstanding requests.
+ *       NV_ERR_STATE_IN_USE
+ *         This value indicates that at least one of the clock-gating controls
+ *         has already been locked to a conflicting state by another
+ *         MAXWELL_PROFILER instance or the RM itself.
+ *   statusMask
+ *     This parameter returns the status of the request to set each clock-
+ *     gating control specified by the controlMask parameter. The fields are
+ *     identical to those of the controlMask parameter. For each field for
+ *     which the corresponding field in the controlMask parameter has the
+ *     value NVB0CC_CTRL_POWER_FEATURE_MASK_*_IGNORE, the value is
+ *     undefined. For each field for which the corresponding field in the
+ *     controlMask parameter has the value
+ *     NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST, the value will be
+ *     one of the following:
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FULFILLED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question was enabled or disabled according to the
+ *         controlMask parameter, and the reference count for the feature was
+ *         incremented accordingly.
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question was not set to the expected state according
+ *         to the controlMask parameter because another conflicting request is
+ *         currently outstanding for the clock-gating feature.
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FAILED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question was not set to the expected state according
+ *         to the controlMask parameter because the attempt to do so failed
+ *         with an error other than a conflicting request.
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED
+ *         This value indicates that the clock-gating feature corresponding to
+ *         the field in question is not supported on this GPU.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES (0xb0cc0301) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID << 8) | NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS {
+    NvU32 globalStatus;
+    NvU32 controlMask;
+    NvU32 statusMask;
+} NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS;
+
+/* valid fields for the controlMask and statusMask parameters */
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG                                1:0
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG                                3:2
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG                                5:4
+
+/* 
+ * The following are temporary fields for the controlMask and statusMask
+ * parameters. They are required to reference count their respective features
+ * until the existing RM controls can be safely updated, and the definitions
+ * for these features will be removed soon after that.
+ */
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG                                7:6
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN                       9:8
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT                               11:10
+
+/* valid values for fields in the controlMask parameter */
+#define NVB0CC_CTRL_POWER_FEATURE_IGNORE                                   (0x00000000)
+#define NVB0CC_CTRL_POWER_FEATURE_DISABLE                                  (0x00000001)
+#define NVB0CC_CTRL_POWER_FEATURE_ENABLE                                   (0x00000002)
+
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE                         NVB0CC_CTRL_POWER_FEATURE_IGNORE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE                        NVB0CC_CTRL_POWER_FEATURE_DISABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE                         NVB0CC_CTRL_POWER_FEATURE_ENABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE                         NVB0CC_CTRL_POWER_FEATURE_IGNORE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE                        NVB0CC_CTRL_POWER_FEATURE_DISABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE                         NVB0CC_CTRL_POWER_FEATURE_ENABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE                         NVB0CC_CTRL_POWER_FEATURE_IGNORE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE                        NVB0CC_CTRL_POWER_FEATURE_DISABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE                         NVB0CC_CTRL_POWER_FEATURE_ENABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE                         NVB0CC_CTRL_POWER_FEATURE_IGNORE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE                        NVB0CC_CTRL_POWER_FEATURE_DISABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE                         NVB0CC_CTRL_POWER_FEATURE_ENABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE                NVB0CC_CTRL_POWER_FEATURE_IGNORE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE               NVB0CC_CTRL_POWER_FEATURE_DISABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE                NVB0CC_CTRL_POWER_FEATURE_ENABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE                          NVB0CC_CTRL_POWER_FEATURE_IGNORE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE                         NVB0CC_CTRL_POWER_FEATURE_DISABLE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE                          NVB0CC_CTRL_POWER_FEATURE_ENABLE
+/* possible values for fields in the statusMask parameter */
+#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED                        (0x00000000)
+#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED                         (0x00000001)
+#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED                    (0x00000002)
+#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED                           (0x00000003)
+
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED              NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED               NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED          NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED                 NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED              NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED               NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED          NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED                 NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED              NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED               NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED          NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED                 NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED              NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED               NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED          NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED                 NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED     NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED      NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED        NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED               NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED                NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED           NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED                  NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
+
+/* utility masks for the controlMask parameter for all controls */
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL                                   \
+    DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG) |                     \
+    DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG) |                     \
+    DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG) |                     \
+    DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG) |                     \
+    DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN) |            \
+    DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_VAT)
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_IGNORE                            \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _IGNORE) |                \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _IGNORE) |                \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _IGNORE) |                \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _IGNORE) |                \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _IGNORE) |       \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _IGNORE)
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_DISABLE                           \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _DISABLE) |               \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _DISABLE) |               \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _DISABLE) |               \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _DISABLE) |               \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _DISABLE)|       \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _DISABLE)
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_ENABLE                            \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _ENABLE) |                \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _ENABLE) |                \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _ENABLE) |                \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _ENABLE) |                \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _ENABLE) |       \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _ENABLE)
+
+/*
+ * NVB0CC_CTRL_CMD_POWER_RELEASE_FEATUERS
+ *
+ * This command releases the MAXWELL_PROFILER's request for the given clock-
+ * gating features that was previously created by the
+ * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES command. If the MAXWELL_PROFILER
+ * object does not have an outstanding request to one or more of the given
+ * clock-gating features, those features will be ignored while the other
+ * feature requests will be released.
+ *
+ * After calling this command, the calling client may not rely on the current
+ * value of any of the released clock-gating features to remain, even if
+ * several identical requests for the given clock-gating features were made
+ * using NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES. The RM only reference-
+ * counts the settings requested by MAXWELL_PROFILER instances - it does not
+ * reference-count multiple identical requests made using the same
+ * MAXWELL_PROFILER instance.
+ *
+ * All outstanding requests made using this MAXWELL_PROFILER object are
+ * implicitly released when the MAXWELL_PROFILER is freed.
+ *
+ *   controlMask
+ *     This parameter indicates which clock-gating features the RM should
+ *     release the MAXWELL_PROFILER's reference to. See
+ *     NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES for valid fields. Valid
+ *     values for each field are:
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE
+ *         This value indicates that the clock-gating feature associated with
+ *         the field should not be released, even if the MAXWELL_PROFILER has an
+ *         outstanding request for it. This will not affect the reference
+ *         count for the feature.
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE
+ *       NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE
+ *         This value indicates that the MAXWELL_PROFILER's outstanding request
+ *         for the clock-gating feature associated with the field should be
+ *         released. This will decrement the reference count for the feature
+ *         if the MAXWELL_PROFILER has an outstanding request for it.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES                             (0xb0cc0302) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID << 8) | NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS {
+    NvU32 controlMask;
+} NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS;
+
+/* 
+ * valid values for the controlMask parameter in addition to
+ * NVB0CC_CTRL_POWER_FEATURE_MASK_*_IGNORE
+ */
+#define NVB0CC_CTRL_POWER_FEATURE_RELEASE                    (0x00000003)
+
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE          NVB0CC_CTRL_POWER_FEATURE_RELEASE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE          NVB0CC_CTRL_POWER_FEATURE_RELEASE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE          NVB0CC_CTRL_POWER_FEATURE_RELEASE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE          NVB0CC_CTRL_POWER_FEATURE_RELEASE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE           NVB0CC_CTRL_POWER_FEATURE_RELEASE
+
+
+/* _ctrlb0ccpower_h_ */
+
+/* utility mask for the controlMask parameter for all fields */
+#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_RELEASE                           \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _RELEASE) |               \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _RELEASE) |               \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _RELEASE) |               \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _RELEASE) |               \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _RELEASE)|       \
+    DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _RELEASE)
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
new file mode 100644
index 0000000..e55436a
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
@@ -0,0 +1,727 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrlb0cc/ctrlb0ccprofiler.finn
+//
+
+#include "ctrl/ctrlb0cc/ctrlb0ccbase.h"
+
+
+/*!
+ * NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY
+ *
+ * Reserves the HWPM legacy PM system for use by the calling client.
+ * This PM system will only be accessible if this reservation is
+ * taken.
+ *
+ * If a device level reservation is held by another client, then this command
+ * will fail regardless of reservation scope.
+ *
+ * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY.
+ *
+ */
+
+
+#define NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY (0xb0cc0101) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS {
+    /*!
+     * [in] Enable ctxsw for HWPM.
+     */
+    NvBool ctxsw;
+} NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY
+ *
+ * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY.
+ *
+ * This command does not take any parameters.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY  (0xb0cc0102) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x2" */
+
+/*!
+ * NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC
+ *
+ * Reserves the SMPC PM system for use by the calling client.
+ * This PM system will only be accessible if this reservation is
+ * taken.
+ *
+ * Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY.
+ *
+ * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC (0xb0cc0103) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS {
+    /*!
+     * [in] Enable ctxsw for SMPC.
+     */
+    NvBool ctxsw;
+} NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC
+ *
+ * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC.
+ *
+ * This command does not take any parameters.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC (0xb0cc0104) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x4" */
+
+/*!
+ * NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM
+ *
+ * Allocates PMA VA and map it to the buffers for streaming records and for
+ * for streaming the updated bytes available in the buffer.
+ *
+ */
+#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM     (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Defines the maximum size of PMA buffer for streamout. It can be up to 4GB minus one page
+ * reserved for streaming mem_bytes (see @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE).
+ */
+#define NVB0CC_PMA_BUFFER_SIZE_MAX           (0xffe00000ULL) /* finn: Evaluated from "(4 * 1024 * 1024 * 1024 - 2 * 1024 * 1024)" */
+#define NVB0CC_PMA_BYTES_AVAILABLE_SIZE      (0x1000) /* finn: Evaluated from "(4 * 1024)" */
+
+#define NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS {
+    /*!
+     * [in] Memory handle (RW memory) for streaming records.
+     * Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize.
+     */
+    NvHandle hMemPmaBuffer;
+
+    /*!
+     * [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer).
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8);
+
+    /*!
+     * [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX.
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8);
+
+    /*!
+     * [in] Memory handle (RO memory) for streaming number of bytes available.
+     * Size of this must be of at least @ref pmaBytesAvailableOffset +
+     * @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE.
+     */
+    NvHandle hMemPmaBytesAvailable;
+
+    /*!
+     * [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable).
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8);
+
+    /*!
+     * [in] Enable ctxsw for PMA stream.
+     */
+    NvBool   ctxsw;
+
+    /*!
+     * [out] The PMA Channel Index associated with a given PMA stream.
+     */
+    NvU32    pmaChannelIdx;
+
+    /*!
+     * [out] PMA buffer VA. Note that this is a HWPM Virtual address.
+     */
+    NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8);
+} NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_FREE_PMA_STREAM
+ *
+ * Releases (unmap and free) PMA stream allocated through
+ * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM.
+ *
+ */
+#define NVB0CC_CTRL_CMD_FREE_PMA_STREAM (0xb0cc0106) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS {
+    /*!
+     * [in] The PMA channel index associated with a given PMA stream.
+     */
+    NvU32 pmaChannelIdx;
+} NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS;
+
+
+
+/*!
+ * NVB0CC_CTRL_CMD_BIND_PM_RESOURCES
+ *
+ * Binds all PM resources reserved through @ref NVB0CC_CTRL_CMD_RESERVE_*
+ * and with @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM with PMA engine.
+ * After this call, interface is ready for programming a collection
+ * of counters.
+ * @Note: Any new PM resource reservation via NVB0CC_CTRL_CMD_RESERVE_* or
+ * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM request after this call will fail,
+ * clients need to unbind (see @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES) to
+ * reserve more resources.
+ *
+ * This can be unbound with @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES.
+ *
+ */
+#define NVB0CC_CTRL_CMD_BIND_PM_RESOURCES         (0xb0cc0107) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x7" */
+
+/*!
+ * NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES
+ *
+ * Unbinds PM resources that were bound with @ref NVB0CC_CTRL_CMD_BIND_PM_RESOURCES
+ *
+ */
+#define NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES       (0xb0cc0108) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x8" */
+
+/*!
+ * NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT
+ *
+ * This command updates bytes consumed by the SW and optionally gets the
+ * current available bytes in the buffer.
+ *
+ */
+#define NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT (0xb0cc0109) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE      0xFFFFFFFF
+#define NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS {
+    /*!
+     * [in] Total bytes consumed by SW since last update.
+     */
+    NV_DECLARE_ALIGNED(NvU64 bytesConsumed, 8);
+
+    /*!
+     * [in] Initiate streaming of the bytes available (see @ref hMemPmaBytesAvailable).
+     * RM will set the memory for streaming (see @ref hMemPmaBytesAvailable) to NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE and
+     * client can optionally wait (see @ref bWait) for it to change from this value.
+     */
+    NvBool bUpdateAvailableBytes;
+
+    /*!
+     * [in] Waits for available bytes to get updated
+     */
+    NvBool bWait;
+
+    /*!
+     * [out] Bytes available in the PMA buffer (see @ref hMemPmaBuffer) for SW to consume.
+     * This will only be populated if both bUpdateAvailableBytes and bWait are set
+     * to TRUE.
+     */
+    NV_DECLARE_ALIGNED(NvU64 bytesAvailable, 8);
+
+    /*!
+     * [in] If set to TRUE, current put pointer will be returned in @ref putPtr.
+     */
+    NvBool bReturnPut;
+
+    /*!
+     * [out] Current PUT pointer (MEM_HEAD).
+     * This will only be populated if bReturnPut is set to TRUE.
+     */
+    NV_DECLARE_ALIGNED(NvU64 putPtr, 8);
+
+    /*!
+     * [in] The PMA Channel Index associated with a given PMA stream.
+     */
+    NvU32  pmaChannelIdx;
+
+    /*!
+     * [out] Set to TRUE if PMA buffer has overflowed.
+     */
+    NvBool bOverflowStatus;
+} NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS;
+
+/*!
+ * Maximum number of register operations allowed in a single request.
+ * @NOTE: @ref NVB0CC_REGOPS_MAX_COUNT is chosen to keep struct size
+ * of @ref NVB0CC_CTRL_EXEC_REG_OPS_PARAMS under 4KB.
+ */
+#define NVB0CC_REGOPS_MAX_COUNT      (124)
+
+/*!
+ * NVB0CC_CTRL_CMD_EXEC_REG_OPS
+ *
+ * This command is used to submit an array containing one or more
+ * register operations for processing.  Each entry in the
+ * array specifies a single read or write operation. Each entry is
+ * checked for validity in the initial pass: Only registers from PM area
+ * are allowed using this interface and only register from PM systems for
+ * which user has a valid reservation are allowed (see @ref NVB0CC_CTRL_CMD_RESERVE_*).
+ * Operation type (@ref  NV2080_CTRL_GPU_REG_OP_TYPE_*) is not required to be passed in.
+ */
+#define NVB0CC_CTRL_CMD_EXEC_REG_OPS (0xb0cc010a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Structure definition for register operation. See @ref NV2080_CTRL_GPU_REG_OP.
+ */
+typedef NV2080_CTRL_GPU_REG_OP NVB0CC_GPU_REG_OP;
+
+/*!
+ * Enumeration of different REG_OPS modes. This mode determines how a failure
+ * of a regop is handled in a batch of regops.
+ */
+typedef enum NVB0CC_REGOPS_MODE {
+
+    /*!
+     * Either all regops will be executed or none of them will be executed.
+     * Failing regop will have the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus).
+     */
+    NVB0CC_REGOPS_MODE_ALL_OR_NONE = 0,
+    /*!
+     * All regops will be attempted and the ones that failed will have the
+     * the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus).
+     */
+    NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR = 1,
+} NVB0CC_REGOPS_MODE;
+
+#define NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS {
+    /*!
+     * [in] Number of valid entries in the regOps array. This value cannot
+     * exceed NVB0CC_REGOPS_MAX_COUNT.
+     */
+    NvU32              regOpCount;
+
+    /*!
+     * [in] Specifies the mode for the entire operation see @ref NVB0CC_REGOPS_MODE.
+     */
+    NVB0CC_REGOPS_MODE mode;
+
+    /*!
+     * [out] Provides status for the entire operation. This is only valid for
+     * mode @ref NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR.
+     */
+    NvBool             bPassed;
+
+    /*!
+     * [out] This is currently not populated.
+     */
+    NvBool             bDirect;
+
+    /*!
+     * [in/out] An array (of fixed size NVB0CC_REGOPS_MAX_COUNT) of register read or write
+     * operations (see @ref NVB0CC_GPU_REG_OP)
+     *
+     */
+    NVB0CC_GPU_REG_OP  regOps[NVB0CC_REGOPS_MAX_COUNT];
+} NVB0CC_CTRL_EXEC_REG_OPS_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER
+ *
+ * Reserves the PC sampler system for use by the calling client.
+ *
+ * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER.
+ *
+ * This command does not take any parameters.
+ *
+ * PC sampler is always context switched with a GR context, so reservation scope is
+ * always context. This requires that profiler object is instantiated with a valid GR
+ * context. See @ref NVB2CC_ALLOC_PARAMETERS.
+ */
+
+#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER (0xb0cc010b) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xB" */
+
+/*!
+ * NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER
+ *
+ * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER.
+ *
+ * This command does not take any parameters.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER (0xb0cc010c) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xC" */
+
+/*!
+ * NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS
+ *
+ * Gets the total high speed streaming credits available for the client.
+ *
+ * This command can only be performed after a bind using NVB0CC_CTRL_CMD_BIND_PM_RESOURCES.
+ *
+ */
+#define NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS       (0xb0cc010d) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS {
+    NvU32 numCredits;
+} NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_SET_HS_CREDITS_CHIPLET
+ *
+ * Sets per chiplet (pmm router) credits for high speed streaming for a pma channel.
+ *
+ * @note: This command resets the current credits to 0 before setting the new values also
+ *        if programming fails, it will reset credits to 0 for all the chiplets.
+ *
+ */
+#define NVB0CC_CTRL_CMD_SET_HS_CREDITS (0xb0cc010e) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID" */
+
+typedef enum NVB0CC_CHIPLET_TYPE {
+    NVB0CC_CHIPLET_TYPE_INVALID = 0,
+    NVB0CC_CHIPLET_TYPE_FBP = 1,
+    NVB0CC_CHIPLET_TYPE_GPC = 2,
+    NVB0CC_CHIPLET_TYPE_SYS = 3,
+
+    NVB0CC_CHIPLET_TYPE_IODN = 4,
+    NVB0CC_CHIPLET_TYPE_IODS = 5,
+
+} NVB0CC_CHIPLET_TYPE;
+
+typedef enum NVB0CC_HS_CREDITS_CMD_STATUS {
+    NVB0CC_HS_CREDITS_CMD_STATUS_OK = 0,
+    /*!
+     * More credits are requested than the total credits. Total credits can be queried using @ref NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS
+     */
+    NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CREDITS = 1,
+    /*!
+     * Chiplet index is invalid.
+     */
+    NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET = 2,
+} NVB0CC_HS_CREDITS_CMD_STATUS;
+
+typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO {
+    /*!
+     * Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE.
+     */
+    NvU8  chipletType;
+
+    /*!
+     * Specifies the logical index of the chiplet.
+     */
+    NvU8  chipletIndex;
+
+    /*!
+     * Specifies the number of credits for the chiplet.
+     */
+    NvU16 numCredits;
+} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO;
+
+typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS {
+    /*!
+     * Status for the command @ref NVB0CC_HS_CREDITS_CMD_STATUS.
+     */
+    NvU8 status;
+
+    /*!
+     * Index of the failing @ref NVB0CC_CTRL_SET_HS_CREDITS_PARAMS::creditInfo entry. This
+     * is only relevant if status is NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET.
+     */
+    NvU8 entryIndex;
+} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS;
+
+#define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63)
+
+typedef struct NVB0CC_CTRL_HS_CREDITS_PARAMS {
+    /*!
+     * [in] The PMA Channel Index associated with a given PMA stream.
+     */
+    NvU8                                     pmaChannelIdx;
+
+    /*!
+     * [in] Number of valid entries in creditInfo.
+     */
+    NvU8                                     numEntries;
+
+    /*!
+     * [out] Provides status for the entire operation.
+     */
+    NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS statusInfo;
+
+    /*!
+     * [in] Credit programming per chiplet
+     */
+    NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO   creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES];
+} NVB0CC_CTRL_HS_CREDITS_PARAMS;
+
+#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU)
+
+typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_SET_HS_CREDITS_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_GET_HS_CREDITS
+ *
+ * Gets per chiplet (pmm router) high speed streaming credits for a pma channel.
+ *
+ */
+#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID (0xFU)
+
+typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS;
+
+
+
+#define NVB0CC_CTRL_HES_INVALID (0x00000000)
+#define NVB0CC_CTRL_HES_CWD     (0x00000001)
+
+#define NVB0CC_CTRL_HES_TPC     (0x00000002)
+
+
+
+typedef struct NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS {
+    /*!
+     * [in] Enable ctxsw for HES_CWD.
+     */
+    NvBool ctxsw;
+} NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS;
+
+typedef struct NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS {
+        /*!
+        * [in] Enable ctxsw for HES_TPC.
+        */
+    NvBool ctxsw;
+} NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS;
+
+
+
+/*
+ * NVB0CC_CTRL_HES_RESERVATION_UNION
+ *
+ * Union of all HES reservation params
+ *
+ */
+typedef union NVB0CC_CTRL_HES_RESERVATION_UNION {
+    NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS cwd;
+
+    NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS tpc;
+
+} NVB0CC_CTRL_HES_RESERVATION_UNION;
+
+/*!
+ * NVB0CC_CTRL_CMD_RESERVE_HES
+ *
+ * Reserves HES for use by the calling client.
+ * This PM system will only be accessible if this reservation is
+ * taken.
+ *
+ * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HES.
+ *
+ * Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RESERVE_HES (0xb0cc0113) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NVB0CC_CTRL_RESERVE_HES_PARAMS {
+    /*!
+     * [in] Denotes the HES reservation type. Choose from @NVB0CC_CTRL_HES_TYPE.
+     */
+    NvU32                             type;
+
+    /*!
+     * [in] Union of all possible reserve param structs. Initialize the reserveParams corresponding to the chosen type.
+     */
+    NVB0CC_CTRL_HES_RESERVATION_UNION reserveParams;
+} NVB0CC_CTRL_RESERVE_HES_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_RELEASE_HES
+ *
+ * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HES.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RELEASE_HES (0xb0cc0114) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS {
+    /*!
+     * [in] type of HES needs to be released.
+     */
+    NvU32 type;
+} NVB0CC_CTRL_RELEASE_HES_PARAMS;
+
+/*!
+ * Defines the maximum count of output credit pools.
+ * 30 is estimate based on the # of PMAs (2) and chiplet types(3),
+ * which should be big enough to accommodate the required number of credit pools
+ */
+#define NVB0CC_CREDIT_POOL_MAX_COUNT 30
+
+/*!
+ * NVB0CC_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL
+ *
+ * Gets the total high speed streaming credits available for the client
+ * in each chiplet pool.
+ *
+ * This command is similar to @ref NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS but
+ * supports multiple chiplet credit pools.
+ *
+ */
+typedef struct NVB0CC_CTRL_CREDIT_POOL_INFO {
+    /*!
+     * [out] number of credits.
+     */
+    NvU16 numCredits;
+
+    /*!
+     * [out] index of credit pool.
+     */
+    NvU8  poolIndex;
+
+    /*!
+     * [out] chiplet type of credit pool.
+     */
+    NvU8  chipletType;
+} NVB0CC_CTRL_CREDIT_POOL_INFO;
+#define NVB0CC_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL (0xb0cc0115) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_MESSAGE_ID" */
+
+#define NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_MESSAGE_ID (0x15U)
+
+typedef struct NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL {
+    /*!
+     * [out] chiplet-level credit pool.
+     */
+    NVB0CC_CTRL_CREDIT_POOL_INFO poolInfos[NVB0CC_CREDIT_POOL_MAX_COUNT];
+
+    /*!
+     * [out] number of credit pools.
+     */
+    NvU32                        poolInfosCount;
+} NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL;
+
+typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO {
+    /*!
+     * [in] Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE.
+     */
+    NvU8 chipletType;
+
+    /*!
+     * [in] Specifies the logical index of the chiplet.
+     */
+    NvU8 chipletIndex;
+
+    /*!
+     * [out] Specifies the index of credits pool for the chiplet.
+     */
+    NvU8 poolIndex;
+} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO;
+
+/*!
+ * NVB0CC_CTRL_CMD_GET_HS_CREDITS_MAPPING
+ *
+ * Query the associated PMA credit pool index for given chiplet.
+ *
+ */
+#define NVB0CC_CTRL_CMD_GET_HS_CREDITS_MAPPING (0xb0cc0116) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_MESSAGE_ID" */
+#define NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS {
+    /*!
+     * [in]: number of input queries.
+     */
+    NvU16                                          numQueries;
+
+    /*!
+     * [out] Provides status for the entire operation.
+     */
+    NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS       statusInfo;
+
+    /*!
+     * [in/out]: Used to query the PMA credit pool index of specified chiplet.
+     */
+    NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO queries[NVB0CC_MAX_CREDIT_INFO_ENTRIES];
+} NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS;
+
+
+/*!
+ * NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST
+ *
+ * Disable the Dynamic MMA clock boost during profiler lifetime.
+ *
+ */
+#define NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST (0xb0cc0117) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID" */
+#define NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID (0x17U)
+
+typedef struct NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS {
+    /*!
+     * [in]: En/Disable Dynamic MMA Boost.  True = disable Boost; False = re-enable Boost.
+     */
+    NvBool disable;
+} NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS;
+
+/*!
+ * NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS
+ *
+ * Request the Dynamic MMA clock boost feature enablement status.
+ *
+ */
+#define NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS (0xb0cc0118) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID" */
+#define NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS {
+    /*!
+     * [out]: Dynamic MMA Boost status: true = boost enabled/available; False = Boost disabled/unavailable.
+     */
+    NvBool enabled;
+} NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS;
+
+
+/*!
+ * NVB0CC_CTRL_CMD_RESERVE_CCU_PROF
+ *
+ * Reserves CCU Prof resource for use by the calling client.
+ * This CCU prof resource will be accessible only if this reservation is
+ * taken.
+ *
+ * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_CCU_PROF.
+ *
+ */
+#define NVB0CC_CTRL_CMD_RESERVE_CCU_PROF (0xb0cc0119) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_MESSAGE_ID" */
+#define NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS {
+    /*!
+     * [in] Enable ctxsw for CCU prof.
+     */
+    NvBool ctxsw;
+} NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS;
+
+#define NVB0CC_CTRL_CMD_RELEASE_CCU_PROF (0xb0cc011a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x1a" */
+
+
+
+/* _ctrlb0ccprofiler_h_ */