Initial commit: Open-IOV vGPU-IO complete stack

- Firmware decompilation: GSP 570.144W (28.5MB ELF, RV64IMAC), 132 decompiled C files
- Kernel modules: nvidia.ko (34MB, OpenRM), open-iov-vfio.ko (2.8MB, VFIO mdev), gsp-vgpu.ko (1.8MB, guest driver)
- Userspace: libiov.so/libvgpu.so (76KB), example_vgpu (28KB), rpc_emulator.c
- PCI config space emulation (256B with PM, MSI, MSI-X, PCIe caps)
- 12 RPC types fully mapped from firmware decompilation
- BAR trap, WPR, scheduling, notification, migration emulation
- Helper scripts: load_vgpu_stack, create_mdev, launch_qemu_vgpu, test_vgpu_stack, setup_guest_driver, unload_vgpu_stack
- Architecture documentation
- Wiki: 10 technical documents
- Git LFS for large binaries (.ko, .bin, .iso, .img, .o, ghidra repos)
- nvidia-open-gpu-kernel-modules as submodule

53 files changed, 32222 insertions, 0 deletions

diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080acr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080acr.h
new file mode 100644
index 0000000..d67b0f2
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080acr.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080acr.finn
+//
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080base.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080base.h
new file mode 100644
index 0000000..be142a2
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080base.h
@@ -0,0 +1,119 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080base.finn
+//
+
+#include "ctrl/ctrlxxxx.h"
+/* NV20_SUBDEVICE_XX control commands and parameters */
+
+#define NV2080_CTRL_CMD(cat,idx)                NVXXXX_CTRL_CMD(0x2080, NV2080_CTRL_##cat, idx)
+
+/* Subdevice command categories (6bits) */
+#define NV2080_CTRL_RESERVED                      (0x00)
+#define NV2080_CTRL_GPU                           (0x01)
+#define NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED     (0x81) /* finn: Evaluated from "(NV2080_CTRL_GPU | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_FUSE                          (0x02)
+#define NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED    (0x82) /* finn: Evaluated from "(NV2080_CTRL_FUSE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_EVENT                         (0x03)
+#define NV2080_CTRL_TIMER                         (0x04)
+#define NV2080_CTRL_THERMAL                       (0x05)
+#define NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED     (0xc5) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED (0x85) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_I2C                           (0x06)
+#define NV2080_CTRL_EXTI2C                        (0x07)
+#define NV2080_CTRL_BIOS                          (0x08)
+#define NV2080_CTRL_CIPHER                        (0x09)
+#define NV2080_CTRL_INTERNAL                      (0x0A)
+#define NV2080_CTRL_CLK_LEGACY_PRIVILEGED         (0xd0) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED     (0x90) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_CLK                           (0x10)
+#define NV2080_CTRL_FIFO                          (0x11)
+#define NV2080_CTRL_GR                            (0x12)
+#define NV2080_CTRL_FB                            (0x13)
+#define NV2080_CTRL_NOISE                         (0x15)
+#define NV2080_CTRL_MC                            (0x17)
+#define NV2080_CTRL_BUS                           (0x18)
+#define NV2080_CTRL_PERF_LEGACY_PRIVILEGED        (0xe0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED    (0xa0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_PERF                          (0x20)
+#define NV2080_CTRL_NVIF                          (0x21)
+#define NV2080_CTRL_RC                            (0x22)
+#define NV2080_CTRL_GPIO                          (0x23)
+#define NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED    (0xa3) /* finn: Evaluated from "(NV2080_CTRL_GPIO | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_NVD                           (0x24)
+#define NV2080_CTRL_DMA                           (0x25)
+#define NV2080_CTRL_PMGR                          (0x26)
+#define NV2080_CTRL_PMGR_LEGACY_PRIVILEGED        (0xe6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED    (0xa6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_POWER                         (0x27)
+#define NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED   (0xa7) /* finn: Evaluated from "(NV2080_CTRL_POWER | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_LPWR                          (0x28)
+#define NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED    (0xa8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_LPWR_LEGACY_PRIVILEGED        (0xe8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_ACR                           (0x29)
+#define NV2080_CTRL_CE                            (0x2A)
+#define NV2080_CTRL_SPI                           (0x2B)
+#define NV2080_CTRL_NVLINK                        (0x30)
+#define NV2080_CTRL_FLCN                          (0x31)
+#define NV2080_CTRL_VOLT                          (0x32)
+#define NV2080_CTRL_VOLT_LEGACY_PRIVILEGED        (0xf2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED    (0xb2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_RIST                          (0x33)
+#define NV2080_CTRL_RIST_LEGACY_PRIVILEGED        (0xf3) /* finn: Evaluated from "(NV2080_CTRL_RIST | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
+#define NV2080_CTRL_RIST_LEGACY_NON_PRIVILEGED    (0xb3) /* finn: Evaluated from "(NV2080_CTRL_RIST | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_ECC                           (0x34)
+#define NV2080_CTRL_ECC_NON_PRIVILEGED            (0xb4) /* finn: Evaluated from "(NV2080_CTRL_ECC | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_FLA                           (0x35)
+#define NV2080_CTRL_GSP                           (0x36)
+#define NV2080_CTRL_NNE                           (0x37)
+#define NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED     (0xb7) /* finn: Evaluated from "(NV2080_CTRL_NNE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
+#define NV2080_CTRL_GRMGR                         (0x38)
+#define NV2080_CTRL_UCODE_FUZZER                  (0x39)
+#define NV2080_CTRL_DMABUF                        (0x3A)
+#define NV2080_CTRL_BIF                           (0x3B)
+
+
+
+// per-OS categories start at highest category and work backwards
+#define NV2080_CTRL_OS_WINDOWS                    (0x3F)
+#define NV2080_CTRL_OS_MACOS                      (0x3E)
+#define NV2080_CTRL_OS_UNIX                       (0x3D)
+
+
+/*
+ * NV2080_CTRL_CMD_NULL
+ *
+ * This command does nothing.
+ * This command does not take any parameters.
+ *
+ * Possible status values returned are:
+ *     NV_OK
+ */
+#define NV2080_CTRL_CMD_NULL                      (0x20800000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */
+
+/* _ctrl2080base_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bif.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bif.h
new file mode 100644
index 0000000..e1344e2
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bif.h
@@ -0,0 +1,85 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023-25 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080bif.finn
+//
+
+#include "nvcfg_sdk.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX bif control commands and parameters
+ * This control command is intended for handling APIs that GET/SET information
+ * related to PCIe.
+ */
+
+typedef enum NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG {
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_INVALID = 0,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_DEVICE_CTRL_STATUS = 1,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_LINK_CTRL_STATUS = 2,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_DEVICE_CTRL_STATUS_2 = 3,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_LINK_CAP = 4,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_L1_PM_SUBSTATES_CTRL1 = 5,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_STATUS = 6,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_STATUS = 7,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_STATUS = 8,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_MASK = 9,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_MASK = 10,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_MASK = 11,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_SEVERITY = 12,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_SEVERITY = 13,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_SEVERITY = 14,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TLP_ENCRYPTION_STATUS = 15,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_LINK_STREAM_ENABLED = 16,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_SELECTIVE_STREAM_ENABLED = 17,
+    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_FLOW_THROUGH_STREAM_ENABLED = 18,
+} NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG;
+
+#define NV2080_CTRL_CMD_BIF_DATA_PARAMS_MAX 32
+
+#define NV2080_CTRL_CMD_BIF_GET_DATA        (0x20803b01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIF_INTERFACE_ID << 8) | NV2080_CTRL_BIF_GET_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BIF_GET_DATA_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_BIF_GET_DATA_PARAMS {
+    NvU32 featureId;
+    NvU32 paramId[NV2080_CTRL_CMD_BIF_DATA_PARAMS_MAX];
+    NvU32 paramVal[NV2080_CTRL_CMD_BIF_DATA_PARAMS_MAX];
+    NvU32 flags;
+    NvU32 paramSize;
+} NV2080_CTRL_BIF_GET_DATA_PARAMS;
+
+typedef enum NV2080_CTRL_BIF_FEATURE_ID {
+    NV2080_CTRL_BIF_FEATURE_ID_INVALID = 0,
+    NV2080_CTRL_BIF_FEATURE_ID_CONFIG_REG = 1,
+
+} NV2080_CTRL_BIF_FEATURE_ID;
+
+
+
+/* _ctrl2080bif_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bios.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bios.h
new file mode 100644
index 0000000..203c94a
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bios.h
@@ -0,0 +1,484 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080bios.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX bios-related control commands and parameters */
+
+
+
+typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BIOS_INFO;
+
+/* Maximum number of bios infos that can be queried at once */
+#define NV2080_CTRL_BIOS_INFO_MAX_SIZE                              (0x0000000F)
+
+#define NV2080_CTRL_BIOS_INFO_INDEX_REVISION                        (0x00000000)
+#define NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION                    (0x00000001)
+
+
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_INFO
+ *
+ * This command returns bios information for the associated GPU.
+ * Requests to retrieve bios information use a list of one or more
+ * NV2080_CTRL_BIOS_INFO structures.
+ *
+ *   biosInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     biosInfoList.
+ *   biosInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the bios information is to be returned.
+ *     This buffer must be at least as big as biosInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_BIOS_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_BIOS_GET_INFO                               (0x20800802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | 0x2" */
+
+typedef struct NV2080_CTRL_BIOS_GET_INFO_PARAMS {
+    NvU32 biosInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 biosInfoList, 8);
+} NV2080_CTRL_BIOS_GET_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_INFO_V2
+ *
+ * This command returns bios information for the associated GPU.
+ * Requests to retrieve bios information use a list of one or more
+ * NV2080_CTRL_BIOS_INFO structures.
+ *
+ *   biosInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     biosInfoList.
+ *   biosInfoList
+ *     Bios information to be returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_BIOS_GET_INFO_V2 (0x20800810) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS {
+    NvU32                 biosInfoListSize;
+    NV2080_CTRL_BIOS_INFO biosInfoList[NV2080_CTRL_BIOS_INFO_MAX_SIZE];
+} NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_BIOS_NBSI
+ *
+ * NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH
+ *   This is the maximum length of a given registry string input (in characters).
+ *
+ * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII
+ *   This is a value indicating the format of a registry string is ascii.
+ * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE
+ *   This is a value indicating the format of a registry string is unicode.
+ * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH
+ *   This is a value indicating a registry string is actually a pre-hashed value.
+ *
+ * NV2080_CTRL_BIOS_NBSI_REG_STRING
+ *   This is a structure used to store a registry string object.
+ *   The members are as follows:
+ *
+ *   size
+ *     This is the size (in bytes) of the data contained in the string. If this
+ *     is greater than the maximum registry string length, an error will be
+ *     returned.
+ *   type
+ *     This is the type of data contained in the registry string. It can be either
+ *     ascii, unicode or a pre-hashed value.
+ *   value
+ *     This is the value of the string. Depending on the type, a different object
+ *     will be used to access the data.
+ */
+#define NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH (0x00000100)
+
+#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII     (0x00000000)
+#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE   (0x00000001)
+#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH      (0x00000002)
+
+#define NV2080_CTRL_BIOS_NBSI_MODULE_ROOT           (0x00000000)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_RM             (0x00000001)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER  (0x00000002)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO          (0x00000003)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_CPL            (0x00000004)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_D3D            (0x00000005)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_OGL            (0x00000006)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_PMU            (0x00000007)
+#define NV2080_CTRL_BIOS_NBSI_MODULE_MODE           (0x00000008)
+// this should equal the last NBSI_MODULE plus 1.
+#define NV2080_CTRL_BIOS_NBSI_NUM_MODULES           (0x00000009)
+
+//
+// Never use this value! It's needed for DD/Video modules, but does not correspond
+// to a valid NBSI hive!
+//
+#define NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN        (0x80000000)
+
+typedef struct NV2080_CTRL_BIOS_NBSI_REG_STRING {
+    NvU32 size;
+    NvU32 type;
+
+    union {
+        NvU8  ascii[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH];
+        NvU16 unicode[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH];
+        NvU16 hash;
+    } value;
+} NV2080_CTRL_BIOS_NBSI_REG_STRING;
+
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_NBSI
+ *
+ * module
+ *   This field specifies the given module per the MODULE_TYPES enum.
+ * path
+ *   This field specifies the full path and registry node name for a
+ *   given NBSI object. This is a maximum of 255 unicode characters,
+ *   but may be provided as ascii or a pre-formed hash per the type
+ *   member. The size (in bytes) of the given string/hash should be
+ *   provided in the size member.
+ *
+ *   NOTE: In the case of an incomplete path such as HKR, one may pass
+ *   in simply the root node. E.g.:
+ *   1.) Normal case: HKLM\Path\Subpath
+ *   2.) Unknown case: HKR
+ *   It is expected that all unknown/incomplete paths will be determined
+ *   prior to NBSI programming! There is otherwise NO WAY to match
+ *   the hash given by an incomplete path to that stored in NBSI!
+ *
+ * valueName
+ *   This field specifies the registry name for a given NBSI object.
+ *   This is a maximum of 255 unicode characters, but may be provided
+ *   in ascii or a pre-formed hash per the type member. The size (in bytes)
+ *   of the given string/hash should be provided in the size member.
+ * retBuf
+ *   This field provides a pointer to a buffer into which the value
+ *   retrieved from NBSI may be returned
+ * retSize
+ *   This field is an input/output. It specifies the maximum size of the
+ *   return buffer as an input, and the size of the returned data as an
+ *   output.
+ * errorCode
+ *   This field is a return value. It gives an error code representing
+ *   failure to return a value (as opposed to failure of the call).
+ *   This obeys the following:
+ *
+ *   NV2080_CTRL_BIOS_GET_NBSI_SUCCESS
+ *     The call has returned complete and valid data.
+ *   NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE
+ *     The call returned complete and valid data which is expected to override
+ *     any stored registry settings.
+ *   NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE
+ *     The call returned data, but the size of the return buffer was
+ *     insufficient to contain it. The value returned in retSize represents
+ *     the total size necessary (in bytes) to contain the data.
+ *     if the size was non-0, the buffer is filled with the object contents up
+ *     to that size. Can be used with retBufOffset to use multiple calls to get
+ *     tables of very large size.
+ *   NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND
+ *     The call did not find a valid NBSI object for this key. This indicates
+ *     NBSI has no opinion and, more importantly, any data returned is identical
+ *     to data passed in.
+ *
+ * Possible return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_BIOS_GET_NBSI_SUCCESS         (0x00000000)
+#define NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE        (0x00000001)
+#define NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH        (0xFFFFFFFA)
+#define NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS (0xFFFFFFFB)
+#define NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE       (0xFFFFFFFC)
+#define NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE        (0xFFFFFFFD)
+#define NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE      (0xFFFFFFFE)
+#define NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND       (0xFFFFFFFF)
+
+#define NV2080_CTRL_CMD_BIOS_GET_NBSI             (0x20800803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_BIOS_GET_NBSI_PARAMS {
+    NvU32                            module;
+    NV2080_CTRL_BIOS_NBSI_REG_STRING path;
+    NV2080_CTRL_BIOS_NBSI_REG_STRING valueName;
+    NV_DECLARE_ALIGNED(NvP64 retBuf, 8);
+    NvU32                            retSize;
+    NvU32                            errorCode;
+} NV2080_CTRL_BIOS_GET_NBSI_PARAMS;
+
+#define NV2080_CTRL_CMD_BIOS_GET_NBSI_V2  (0x2080080e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_BIOS_GET_NBSI_MAX_RET_SIZE (0x100)
+
+#define NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS {
+    NvU32                            module;
+    NV2080_CTRL_BIOS_NBSI_REG_STRING path;
+    NV2080_CTRL_BIOS_NBSI_REG_STRING valueName;
+    NvU8                             retBuf[NV2080_BIOS_GET_NBSI_MAX_RET_SIZE];
+    NvU32                            retSize;
+    NvU32                            errorCode;
+} NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ
+ *
+ * globType
+ *   This field specifies the glob type wanted
+ *   0xffff: APItest... returns NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS
+ * globIndex
+ *   Index for globType desired
+ *      0 = best fit
+ *      1..255 = actual index
+ * globSource
+ *   Index to nbsi directory sources used when getting entire directory
+ *      0 = registry
+ *      1 = VBIOS
+ *      2 = SBIOS
+ *      3 = ACPI
+ * retBufOffset
+ *   When making multiple calls to get the object (if retSize is too small)
+ *   offset into real object (0=start of object)
+ * retBuf
+ *   This field provides a pointer to a buffer into which the object
+ *   retrieved from NBSI may be returned
+ * retSize
+ *   This field is an input/output. It specifies the maximum size of the
+ *   return buffer as an input, and the size of the returned data as an
+ *   output.
+ * totalObjSize
+ *   This field is an output, where the total size of the object being
+ *   retrieved is returned.
+ * errorCode
+ *   This field is a return value. It gives an error code representing
+ *   failure to return a value (as opposed to failure of the call).
+ *   This obeys the following:
+ *
+ *   NV2080_CTRL_BIOS_GET_NBSI_SUCCESS
+ *     The call has returned complete and valid data.
+ *   NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE
+ *     The call returned complete and valid data which is expected to override
+ *     any stored registry settings.
+ *   NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE
+ *     The call returned data, but the size of the return buffer was
+ *     insufficient to contain it. The value returned in retSize represents
+ *     the total size necessary (in bytes) to contain the data.
+ *   NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND
+ *     The call did not find a valid NBSI object for this key. This indicates
+ *     NBSI has no opinion and, more importantly, any data returned is identical
+ *     to data passed in.
+ *
+ * Possible return values are:
+ *   NV2080_CTRL_BIOS_GET_NBSI_SUCCESS
+ *   NV2080_CTRL_BIOS_GET_NBSI_APITEST_NODIRACCESS
+ *   NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS
+ *   NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE
+ *   NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE
+ *   NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE
+ *   NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ (0x20800806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS {
+    NvU16 globType;
+    NvU8  globIndex;
+    NvU16 globSource;
+    NvU32 retBufOffset;
+    NV_DECLARE_ALIGNED(NvP64 retBuf, 8);
+    NvU32 retSize;
+    NvU32 totalObjSize;
+    NvU32 errorCode;
+} NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS;
+
+#define GLOB_TYPE_GET_NBSI_DIR                       0xfffe
+#define GLOB_TYPE_APITEST                            0xffff
+#define GLOB_TYPE_GET_NBSI_ACPI_RAW                  0xfffd
+
+
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_SKU_INFO
+ *
+ * This command returns information about the current board SKU.
+ * NV_ERR_INVALID_OWNER will be returned if the call
+ * isn't made with the OS as the administrator.
+ *
+ *  chipSKU
+ *    This field returns the sku for the current chip.
+ *  chipSKUMod
+ *    This field returns the SKU modifier.
+ *  skuConfigVersion
+ *    Version number for the SKU configuration detailing pstate, thermal, VF curve and so on.
+ *  project
+ *    This field returns the Project (Board) number.
+ *  projectSKU
+ *    This field returns the Project (Board) SKU number.
+ *  CDP
+ *    This field returns the Collaborative Design Project Number.
+ *  projectSKUMod
+ *    This field returns the Project (Board) SKU Modifier.
+ *  businessCycle
+ *    This field returns the business cycle the board is associated with.
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_OWNER
+ */
+#define NV2080_CTRL_CMD_BIOS_GET_SKU_INFO (0x20800808) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS {
+    NvU32 BoardID;
+    char  chipSKU[9];
+    char  chipSKUMod[5];
+    NvU32 skuConfigVersion;
+    char  project[5];
+    char  projectSKU[5];
+    char  CDP[6];
+    char  projectSKUMod[2];
+    NvU32 businessCycle;
+} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_POST_TIME
+
+ * This command is used to get the GPU POST time (in milliseconds).
+ * If the associated GPU is the master GPU this value will be recorded
+ * by the VBIOS and retrieved from the KDA buffer.  If the associated
+ * GPU is a secondaryGPU then this value will reflect the devinit
+ * processing time.
+ *
+ * vbiosPostTime
+ *   This parameter returns the vbios post time in msec.
+ *
+ * Possible return status values are
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME (0x20800809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 vbiosPostTime, 8);
+} NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT
+ *
+ * This function is used to give out the UEFI version, UEFI image presence and
+ * Graphics Firmware Mode i.e. whether system is running in UEFI or not.
+ *
+ *   version
+ *     This parameter returns the UEFI version.
+ *
+ *   flags
+ *     This parameter indicates UEFI image presence and Graphics Firmware mode.
+ *       NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE
+ *         This field returns UEFI presence value. Legal values for this
+ *         field include:
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO
+ *             This value indicates that UEFI image is not present.
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES
+ *             This value indicates that UEFI image is present.
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER
+ *             This value indicates that there is a dummy UEFI placeholder,
+ *             which can later be updated with a valid UEFI image.
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN
+ *             This value indicates that UEFI image is hidden.
+ *       NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING
+ *         This field indicates the UEFI running value. Legal values for
+ *         this parameter include:
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE
+ *             This value indicates that UEFI is not running.
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE
+ *             This value indicates that UEFI is running.
+ *       NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT
+ *         This field indicates the EFI running value. Legal values for
+ *         this parameter include:
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE
+ *             This value indicates that display is in vbios mode.
+ *           NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE
+ *             This value indicates that display is in EFI mode.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_READY
+ *   NV_ERR_INVALID_STATE
+ */
+
+#define NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT (0x2080080b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS {
+    NvU32 version;
+    NvU32 flags;
+} NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS;
+
+/* Legal values for flags parameter */
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE               1:0
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO          (0x00000000)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES         (0x00000001)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER (0x00000002)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN      (0x00000003)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING                2:2
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE        (0x00000000)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE         (0x00000001)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT            3:3
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE    (0x00000000)
+#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE     (0x00000001)
+
+
+
+/* _ctrl2080bios_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobj.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobj.h
new file mode 100644
index 0000000..43912a6
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobj.h
@@ -0,0 +1,1280 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080boardobj.finn
+//
+
+
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h"
+
+/*!
+ * @brief   NV20_SUBDEVICE_XX BOARDOBJ-related control commands and parameters.
+ *
+ * Base structures in RMCTRL equivalent to BOARDOBJ/BOARDOBJGRP in RM. NV2080
+ * structs in this file carry info w.r.t BOARDOBJ/BOARDOBJGRP.
+ */
+
+/*!
+ * @brief Type for representing an index of a BOARDOBJ within a
+ * BOARDOBJGRP.  This type can also represent the number of elements
+ * within a BOARDOBJGRP or the number of bits in a BOARDOBJGRPMASK.
+ */
+typedef NvU16 NvBoardObjIdx;
+
+/*!
+ * @brief Type for representing an index into a mask element within a
+ * BOARDOBJGRPMASK to a @ref NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE.
+ */
+typedef NvU16 NvBoardObjMaskIdx;
+
+/*!
+ * @brief   Primitive type which a BOARDOBJGRPMASK is composed of.
+ *
+ * For example, a 32 bit mask will have one of these elements and a 256 bit
+ * mask will have eight.
+ */
+typedef NvU32 NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE;
+
+/*!
+ * @brief   Min value a single BOARDOBJGRPMASK element can hold.
+ *
+ * @note    Must be kept in sync with @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE.
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_ELEMENT_MIN           NV_U32_MIN
+
+/*!
+ * @brief   Max value a single BOARDOBJGRPMASK element can hold.
+ *
+ * @note    Must be kept in sync with @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE.
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_ELEMENT_MAX           NV_U32_MAX
+
+/*!
+ * @brief   Number of bits in a the NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE type.
+ *
+ * This exists to eliminate the assumption that 32-bits is the width of
+ * NV2080_CTRL_BOARDOBJGRP_MASK primitive element.
+ *
+ * @note    Left shift by 3 (multiply by 8) converts the sizeof in bytes to the
+ * number of bits in our primitive/essential mask type.
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32
+
+/*!
+ * @brief   Value for an invalid Board Object index.
+ *
+ * This value should only be used directly for input to and output
+ * from BOARDOBJ and BOARDOBJGRP code.
+ *
+ * @note This define should not be referenced directly in any
+ * implementing object code.  Instead, each object should define it's
+ * own IDX_INVALID macro and alias it to whatever size fits their
+ * specific index storage type.
+ * For example, many objects still store indexes as NvU8 (because the
+ * GRPs are either _E32 or _E255) while others store as NvBoardObjIdx
+ * (currently aliased to NvU16), so they should alias to a correct
+ * type.
+ */
+#define NV2080_CTRL_BOARDOBJ_IDX_INVALID                   NV_U16_MAX
+
+/*!
+ * @brief   Value for an invalid Board Object index.
+ *
+ * This value encodes an invalid/unsupported BOARDOBJ index for an
+ * 8-bit value.  This should be used within by any legacy appcode
+ * implementing BOARDOBJGRP which stores/encodes indexes as 8-bit
+ * values.
+ *
+ * All new groups should use @ref NV2080_CTRL_BOARDOBJ_IDX_INVALID.
+ *
+ * @note This define should not be referenced directly in any
+ * implementing object code.  Instead, each object should define it's
+ * own IDX_INVALID macro and alias it to whatever size fits their
+ * specific index storage type.
+ * For example, many objects still store indexes as NvU8 (because the
+ * GRPs are either _E32 or _E255) while others store as NvU16 (for
+ * GRPs larger than _E255), so they should alias to a correct type.
+ */
+#define NV2080_CTRL_BOARDOBJ_IDX_INVALID_8BIT              NV_U8_MAX
+
+/*!
+ * @brief   Computes the array index of a NV2080_CTRL_BOARDOBJGRP_MASK element
+ *          storing requested bit.
+ *
+ * @note    Designed to be used in conjunction with @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET.
+ *
+ * @param[in]   _bit    Index of a bit within a bit mask.
+ *
+ * @return  Array index of mask element containing @ref _bit.
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit)                  \
+    ((_bit) / NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE)
+
+/*!
+ * @brief   Computes bit-position within NV2080_CTRL_BOARDOBJGRP_MASK element
+ *          corresponding to requested bit.
+ *
+ * @note    Designed to be used in conjunction with @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX.
+ *
+ * @param[in]   _bit    Index of a bit within a bit mask.
+ *
+ * @return  Offset (in bits) within a mask element for @ref _bit.
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(_bit)                 \
+    ((_bit) % NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE)
+
+/*!
+ * @brief   Computes the size of an array of NV2080_CTRL_BOARDOBJGRP_MASK
+ *          elements that can store all mask's bits.
+ *
+ * @param[in]   _bits   Size of the mask in bits.
+ *
+ * @return  Number of array elements needed to store @ref _bits number of bits.
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits)                          \
+    (NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1U) + 1U)
+
+
+/*!
+ * @brief   Number of elements that are in the NV2080_CTRL_BOARDOBJGRP_MASK base
+ *          class.
+ *
+ * @note    "START_SIZE" is used here to represent the size of the mask that
+ *          derived classes must build up from. See @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_E32, @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_E255, @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_E512, @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_E1024, @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_E2048, @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_E8192.
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE      1U
+
+/*!
+ * @brief   Macro used to determine the number of NV2080_CTRL_BOARDOBJGRP_MASK
+ *          elements required to extend the base number of elements in a mask,
+ *          @ref NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE.
+ *
+ * @note    Used in order to avoid dynamic memory allocation and related
+ *          code/data waste as well as two levels of indirection while accessing
+ *          the data bits stored in an array of @ref
+ *          NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE sized words. The
+ *          NV2080_CTRL_BOARDOBJGRP_MASK super-class array's size should be
+ *          zero and actual data should be completely stored in child's array.
+ *          Since most compilers reject structures with zero-sized arrays first
+ *          element word was moved to the super-class and remaining array
+ *          elements to child class.
+ *
+ * @param[in]   _bits   Total number of bits to be represented in the
+ *                      NV2080_CTRL_BOARDOBJGRP_MASK extending mask class.
+ *
+ * @return  Number of additional mask elements that must be allocated in order
+ *          to extend the NV2080_CTRL_BOARDOBJGRP_MASK base class.
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits)               \
+    (NV2080_CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) -                           \
+     (NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE))
+
+/*!
+ * @deprecated  DO NOT USE! Use a sub-class specific
+ *              NV2080_CTRL_BOARDOBJGRP_MASK_E*_BIT_GET variant 
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_BIT_GET__DEPRECATED_DO_NOT_USE(_pMask, _bitIdx) \
+    (((_pMask)->pData[NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bitIdx)]\
+      & NVBIT_TYPE(NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(_bitIdx),  \
+                   NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE)) != 0U)
+
+/*!
+ * @deprecated  DO NOT USE!: Use a sub-class specific
+ *              @ref NV2080_CTRL_BOARDOBJGRP_MASK_E*_FOR_EACH_INDEX_TYPED
+ *              variant 
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_FOR_EACH_INDEX__DEPRECATED_DO_NOT_USE(_maxObjects,_index,_pMask) \
+{                                                                              \
+    for ((_index) = 0; (_index) < (_maxObjects); (_index)++)                   \
+    {                                                                          \
+        if(!NV2080_CTRL_BOARDOBJGRP_MASK_BIT_GET__DEPRECATED_DO_NOT_USE((_pMask), (_index))) \
+        {                                                                      \
+            continue;                                                          \
+        }
+#define NV2080_CTRL_BOARDOBJGRP_MASK_FOR_EACH_INDEX_END                        \
+    }                                                                          \
+}
+
+/*!
+ * @deprecated  DO NOT USE! Use type-safe
+ *              @ref NV2080_CTRL_BOARDOBJGRP_MASK_E32_FOR_EACH_INDEX
+ *              instead
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_E32_FOR_EACH_INDEX__DEPRECATED(_index,_pMask) \
+    NV2080_CTRL_BOARDOBJGRP_MASK_FOR_EACH_INDEX__DEPRECATED_DO_NOT_USE( \
+        NV2080_CTRL_BOARDOBJGRP_E32_MAX_OBJECTS,_index,_pMask)
+
+/*!
+ * @deprecated  DO NOT USE! Use type-safe
+ *              @ref NV2080_CTRL_BOARDOBJGRP_MASK_E255_FOR_EACH_INDEX
+ *              instead
+ */
+#define NV2080_CTRL_BOARDOBJGRP_MASK_E255_FOR_EACH_INDEX__DEPRECATED(_index,_pMask) \
+    NV2080_CTRL_BOARDOBJGRP_MASK_FOR_EACH_INDEX__DEPRECATED_DO_NOT_USE(                               \
+        NV2080_CTRL_BOARDOBJGRP_E255_MAX_OBJECTS,_index,_pMask)
+
+/*!
+ * @brief   Board Object Group Mask base class.
+ *
+ * Used to unify access to all NV2080_CTRL_BOARDOBJGRP_MASK_E** child classes.
+ */
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK {
+    /*!
+     * @brief   Start with a single element array which is enough to represent
+     *          NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE bits.
+     *
+     * @note    Must be the last member of this structure.
+     */
+    // FINN PORT: The below field is a bit vector!
+    // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array
+    // FINN generates an array of NvU32's on the back end for these bit vectors
+    NvU32 pData[1] /* 32 bits */;
+} NV2080_CTRL_BOARDOBJGRP_MASK;
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK *PNV2080_CTRL_BOARDOBJGRP_MASK;
+
+/*!
+ * @brief   NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 32 bits
+ *          indexed between 0..31.
+ */
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E32 {
+    /*!
+     * @brief   NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first
+     *          member of the structure.
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK super;
+} NV2080_CTRL_BOARDOBJGRP_MASK_E32;
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E32 *PNV2080_CTRL_BOARDOBJGRP_MASK_E32;
+
+/*!
+ * @brief   NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 255 bits
+ *          indexed between 0..254.
+ */
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E255 {
+    /*!
+     * @brief   NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first
+     *          member of the structure.
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK super;
+
+    /*!
+     * @brief   Continuation of the array of
+     *          NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE elements representing the
+     *          bit-mask.
+     *
+     * @note    Must be the second member of the structure.
+     */
+
+    // FINN PORT: The below field is a bit vector!
+    // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array
+    // FINN generates an array of NvU32's on the back end for these bit vectors
+    NvU32 pDataE255[7] /* 223 bits */;
+} NV2080_CTRL_BOARDOBJGRP_MASK_E255;
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E255 *PNV2080_CTRL_BOARDOBJGRP_MASK_E255;
+
+/*!
+ * @brief   NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 512 bits
+ *          indexed between 0..511.
+ */
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E512 {
+    /*!
+     * @brief   NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first
+     *          member of the structure.
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK super;
+
+    /*!
+     * @brief   Continuation of the array of
+     *          NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE elements representing the
+     *          bit-mask.
+     *
+     * @note    Must be the second member of the structure.
+     */
+
+    // FINN PORT: The below field is a bit vector!
+    // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array
+    // FINN generates an array of NvU32's on the back end for these bit vectors
+    NvU32 pDataE512[15] /* 480 bits */;
+} NV2080_CTRL_BOARDOBJGRP_MASK_E512;
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E512 *PNV2080_CTRL_BOARDOBJGRP_MASK_E512;
+
+/*!
+ * @brief   NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 1024 bits
+ *          indexed between 0..1023.
+ */
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E1024 {
+    /*!
+     * @brief   NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first
+     *          member of the structure.
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK super;
+
+    /*!
+     * @brief   Continuation of the array of
+     *          NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE elements representing the
+     *          bit-mask.
+     *
+     * @note    Must be the second member of the structure.
+     */
+
+    // FINN PORT: The below field is a bit vector!
+    // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array
+    // FINN generates an array of NvU32's on the back end for these bit vectors
+    NvU32 pDataE1024[31] /* 992 bits */;
+} NV2080_CTRL_BOARDOBJGRP_MASK_E1024;
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E1024 *PNV2080_CTRL_BOARDOBJGRP_MASK_E1024;
+
+/*!
+ * @brief   NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 2048 bits
+ *          indexed between 0..2047.
+ */
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E2048 {
+    /*!
+     * @brief   NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first
+     *          member of the structure.
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK super;
+
+    /*!
+     * @brief   Continuation of the array of
+     *          NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE elements representing the
+     *          bit-mask.
+     *
+     * @note    Must be the second member of the structure.
+     */
+
+    // FINN PORT: The below field is a bit vector!
+    // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array
+    // FINN generates an array of NvU32's on the back end for these bit vectors
+    NvU32 pDataE2048[63] /* 2016 bits */;
+} NV2080_CTRL_BOARDOBJGRP_MASK_E2048;
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E2048 *PNV2080_CTRL_BOARDOBJGRP_MASK_E2048;
+
+/*!
+ * @brief   NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 8192 bits
+ *          indexed between 0..8191.
+ */
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E8192 {
+    /*!
+     * @brief   NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first
+     *          member of the structure.
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK super;
+
+    /*!
+     * @brief   Continuation of the array of
+     *          NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE elements representing the
+     *          bit-mask.   
+     *
+     * @note    Must be the second member of the structure.
+     */
+
+    // FINN PORT: The below field is a bit vector!
+    // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array
+    // FINN generates an array of NvU32's on the back end for these bit vectors 
+    NvU32 pDataE8192[255] /* 8160 bits */;
+} NV2080_CTRL_BOARDOBJGRP_MASK_E8192;
+typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E8192 *PNV2080_CTRL_BOARDOBJGRP_MASK_E8192;
+
+/*!
+ * @brief   Macro to provide the BOARDOBJ type for a given (UNIT, CLASS, TYPE)
+ *          combination.
+ *
+ * @details For arguments (FOO, BAR, BAZ), this macro will return
+ *          NV2080_CTRL_FOO_BAR_TYPE_BAZ
+ *
+ * @param[in]   _unit   The unit.
+ * @param[in]   _class  The class.
+ * @param[in]   _type   The type.
+ *
+ * @return  BOARDOBJ object type identifier.
+ */
+#define NV2080_CTRL_BOARDOBJ_TYPE(_unit, _class, _type)                        \
+    NV2080_CTRL_##_unit##_##_class##_TYPE_##_type
+
+
+
+/*!
+ * @brief   Base structure which describes a BOARDOBJ CLIENT_INFO in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO {
+    /*!
+     * @brief   BOARDOBJ type.
+     *
+     * This should be a unique value within the class that the BOARDOBJ belongs.
+     */
+    NvU8 type;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO;
+
+/*!
+ * @brief   Base structure which describes a BOARDOBJ CLIENT_STATUS in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS {
+    /*!
+     * @brief   BOARDOBJ type.
+     *
+     * This should be a unique value within the class that the BOARDOBJ belongs.
+     */
+    NvU8 type;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS;
+
+/*!
+ * @brief   Base structure which describes a BOARDOBJ CLIENT_CONTROL in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL {
+    /*!
+     * @brief   BOARDOBJ type.
+     *
+     * This should be a unique value within the class that the BOARDOBJ belongs.
+     */
+    NvU8 type;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL;
+
+/*!
+ * @brief   Base structure which describes a BOARDOBJ CLIENT_READINGS in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS {
+    /*!
+     * @brief   BOARDOBJ type.
+     *
+     * This should be a unique value within the class that the BOARDOBJ belongs.
+     */
+    NvU8 type;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS;
+
+/*!
+ * @brief   Base structure which describes a CLIENT_INFO BOARDOBJ_INTERFACE in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE {
+    /*!
+     * @brief   Reserved for future use cases.
+     */
+    NvU8 rsvd;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE;
+
+/*!
+ * @brief   Base structure which describes a CLIENT_STATUS BOARDOBJ_INTERFACE in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE {
+    /*!
+     * @brief   Reserved for future use cases.
+     */
+    NvU8 rsvd;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE;
+
+/*!
+ * @brief   Base structure which describes a CLIENT_CONTROL BOARDOBJ_INTERFACE in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE {
+    /*!
+     * @brief   Reserved for future use cases.
+     */
+    NvU8 rsvd;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE;
+
+/*!
+ * @brief   Base structure which describes a CLIENT_READINGS BOARDOBJ_INTERFACE in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE {
+    /*!
+     * @brief   Reserved for future use cases.
+     */
+    NvU8 rsvd;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE;
+
+/*!
+ * @brief   Structure representing CLIENT_INFO for a BOARDOBJ_IFACE_MODEL interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL {
+    /*!
+     * Super class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL;
+
+/*!
+ * @brief   Structure representing CLIENT_INFO for a BOARDOBJ_IFACE_MODEL_20
+ *          interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20 {
+    /*!
+     * Super class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20;
+
+/*!
+ * @brief   Structure representing CLIENT_INFO for a
+ *          BOARDOBJ_IFACE_MODEL_PMU_INIT_1X interface
+ *
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X {
+    /*!
+     * Super class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20 super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X;
+
+/*!
+ * @brief   Structure representing CLIENT_STATUS for a BOARDOBJ_IFACE_MODEL interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL {
+    /*!
+     * Super class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL;
+
+/*!
+ * @brief   Structure representing CLIENT_STATUS for a BOARDOBJ_IFACE_MODEL_20
+ *          interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20 {
+    /*!
+     * Super class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20;
+
+/*!
+ * @brief   Structure representing CLIENT_STATUS for a
+ *          BOARDOBJ_IFACE_MODEL_PMU_INIT_1X interface
+ *
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X {
+    /*!
+     * Super class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20 super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X;
+
+/*!
+ * @brief   Structure representing CLIENT_CONTROL for a BOARDOBJ_IFACE_MODEL interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL {
+    /*!
+     * Super class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL;
+
+/*!
+ * @brief   Structure representing CLIENT_CONTROL for a BOARDOBJ_IFACE_MODEL_20
+ *          interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20 {
+    /*!
+     * Super class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20;
+
+/*!
+ * @brief   Structure representing CLIENT_CONTROL for a
+ *          BOARDOBJ_IFACE_MODEL_PMU_INIT_1X interface
+ *
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X {
+    /*!
+     * Super class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20 super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X;
+
+/*!
+ * @brief   Structure representing CLIENT_READINGS for a BOARDOBJ_IFACE_MODEL interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL {
+    /*!
+     * Super class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL;
+
+/*!
+ * @brief   Structure representing CLIENT_READINGS for a BOARDOBJ_IFACE_MODEL_20
+ *          interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20 {
+    /*!
+     * Super class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20;
+
+/*!
+ * @brief   Structure representing CLIENT_READINGS for a
+ *          BOARDOBJ_IFACE_MODEL_PMU_INIT_1X interface
+ *
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X {
+    /*!
+     * Super class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20 super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X;
+
+/*!
+ * CLIENT_INFO data for @ref BOARDOBJGRP base class
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO {
+    /*!
+     * @brief   Concrete class type of this BOARDOBJGRP
+     */
+    NvU8 classType;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO;
+
+/*!
+ * CLIENT_INFO SUPER_ALIAS version for @ref BOARDOBJGRP base class
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_SUPER_ALIAS {
+    /*!
+     * Base class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super;
+
+    NV2080_CTRL_BOARDOBJGRP_MASK                 objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_SUPER_ALIAS;
+
+/*!
+ * CLIENT_STATUS data for @ref BOARDOBJGRP base class
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS {
+    /*!
+     * @brief   Concrete class type of this BOARDOBJGRP
+     */
+    NvU8 classType;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS;
+
+/*!
+ * CLIENT_STATUS SUPER_ALIAS version for @ref BOARDOBJGRP base class
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_SUPER_ALIAS {
+    /*!
+     * Base class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super;
+
+    NV2080_CTRL_BOARDOBJGRP_MASK                   objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_SUPER_ALIAS;
+
+/*!
+ * CLIENT_CONTROL data for @ref BOARDOBJGRP base class
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL {
+    /*!
+     * @brief   Concrete class type of this BOARDOBJGRP
+     */
+    NvU8 classType;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL;
+
+/*!
+ * CLIENT_CONTROL SUPER_ALIAS version for @ref BOARDOBJGRP base class
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_SUPER_ALIAS {
+    /*!
+     * Base class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super;
+
+    NV2080_CTRL_BOARDOBJGRP_MASK                    objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_SUPER_ALIAS;
+
+/*!
+ * CLIENT_READINGS data for @ref BOARDOBJGRP base class
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS {
+    /*!
+     * @brief   Concrete class type of this BOARDOBJGRP
+     */
+    NvU8   classType;
+
+    /*!
+     * Whether the CLIENT_READINGS have been initialized.
+     * This should be set to false on any initial call into the API
+     */
+    NvBool bInitialized;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS;
+
+/*!
+ * CLIENT_READINGS SUPER_ALIAS version for @ref BOARDOBJGRP base class
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_SUPER_ALIAS {
+    /*!
+     * Base class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super;
+
+    NV2080_CTRL_BOARDOBJGRP_MASK                     objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_SUPER_ALIAS;
+
+/*!
+ * CLIENT_INFO for @ref BOARDOBJGRP_E32
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E32 {
+    /*!
+     * Base class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E32             objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E32;
+
+/*!
+ * CLIENT_STATUS for @ref BOARDOBJGRP_E32
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E32 {
+    /*!
+     * Base class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E32               objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E32;
+
+/*!
+ * CLIENT_CONTROL for @ref BOARDOBJGRP_E32
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E32 {
+    /*!
+     * Base class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E32                objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E32;
+
+/*!
+ * CLIENT_READINGS for @ref BOARDOBJGRP_E32
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E32 {
+    /*!
+     * Base class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E32                 objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E32;
+
+/*!
+ * CLIENT_INFO for @ref BOARDOBJGRP_E255
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E255 {
+    /*!
+     * Base class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E255            objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E255;
+
+/*!
+ * CLIENT_STATUS for @ref BOARDOBJGRP_E255
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E255 {
+    /*!
+     * Base class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E255              objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E255;
+
+/*!
+ * CLIENT_CONTROL for @ref BOARDOBJGRP_E255
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E255 {
+    /*!
+     * Base class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E255               objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E255;
+
+/*!
+ * CLIENT_READINGS for @ref BOARDOBJGRP_E255
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E255 {
+    /*!
+     * Base class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E255                objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E255;
+
+/*!
+ * CLIENT_INFO for @ref BOARDOBJGRP_E512
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E512 {
+    /*!
+     * Base class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E512            objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E512;
+
+/*!
+ * CLIENT_STATUS for @ref BOARDOBJGRP_E512
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E512 {
+    /*!
+     * Base class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E512              objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E512;
+
+/*!
+ * CLIENT_CONTROL for @ref BOARDOBJGRP_E512
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E512 {
+    /*!
+     * Base class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E512               objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E512;
+
+/*!
+ * CLIENT_READINGS for @ref BOARDOBJGRP_E512
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E512 {
+    /*!
+     * Base class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E512                objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E512;
+
+/*!
+ * CLIENT_INFO for @ref BOARDOBJGRP_E1024
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E1024 {
+    /*!
+     * Base class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E1024           objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E1024;
+
+/*!
+ * CLIENT_STATUS for @ref BOARDOBJGRP_E1024
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E1024 {
+    /*!
+     * Base class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E1024             objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E1024;
+
+/*!
+ * CLIENT_CONTROL for @ref BOARDOBJGRP_E1024
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E1024 {
+    /*!
+     * Base class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E1024              objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E1024;
+
+/*!
+ * CLIENT_READINGS for @ref BOARDOBJGRP_E1024
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E1024 {
+    /*!
+     * Base class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E1024               objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E1024;
+
+/*!
+ * CLIENT_INFO for @ref BOARDOBJGRP_E2048
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E2048 {
+    /*!
+     * Base class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E2048           objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E2048;
+
+/*!
+ * CLIENT_STATUS for @ref BOARDOBJGRP_E2048
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E2048 {
+    /*!
+     * Base class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E2048             objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E2048;
+
+/*!
+ * CLIENT_CONTROL for @ref BOARDOBJGRP_E2048
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E2048 {
+    /*!
+     * Base class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E2048              objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E2048;
+
+/*!
+ * CLIENT_READINGS for @ref BOARDOBJGRP_E2048
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E2048 {
+    /*!
+     * Base class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E2048               objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E2048;
+
+
+/*!
+ * CLIENT_INFO for @ref BOARDOBJGRP_E8192
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E8192 {
+    /*!
+     * Base class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E8192           objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E8192;
+
+/*!
+ * CLIENT_STATUS for @ref BOARDOBJGRP_E8192
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E8192 {
+    /*!
+     * Base class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E8192             objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E8192;
+
+/*!
+ * CLIENT_CONTROL for @ref BOARDOBJGRP_E8192
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E8192 {
+    /*!
+     * Base class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E8192              objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E8192;
+
+/*!
+ * CLIENT_READINGS for @ref BOARDOBJGRP_E8192
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E8192 {
+    /*!
+     * Base class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super;
+
+    /*!
+     * Mask of valid @ref BOARDOBJ objects within the payload
+     */
+    NV2080_CTRL_BOARDOBJGRP_MASK_E8192               objMask;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E8192;
+
+
+/*!
+ * @brief   Structure representing CLIENT_INFO for a BOARDOBJGRP_INTERFACE in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE {
+    /*!
+     * @brief   Reserved for future use cases.
+     */
+    NvU8 rsvd;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE;
+
+/*!
+ * @brief   Structure representing CLIENT_INFO for a BOARDOBJGRP_IFACE_MODEL interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL {
+    /*!
+     * Super class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL;
+
+/*!
+ * @brief   Structure representing CLIENT_INFO for a BOARDOBJGRP_IFACE_MODEL_20
+ *          interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20 {
+    /*!
+     * Super class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20;
+
+/*!
+ * @brief   Structure representing CLIENT_INFO for a
+ *          BOARDOBJGRP_IFACE_MODEL_PMU_INIT_1X interface
+ *
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X {
+    /*!
+     * Super class CLIENT_INFO
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20 super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X;
+
+/*!
+ * @brief   Structure representing CLIENT_STATUS for a BOARDOBJGRP_INTERFACE in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE {
+    /*!
+     * @brief   Reserved for future use cases.
+     */
+    NvU8 rsvd;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE;
+
+/*!
+ * @brief   Structure representing CLIENT_STATUS for a BOARDOBJGRP_IFACE_MODEL interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL {
+    /*!
+     * Super class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL;
+
+/*!
+ * @brief   Structure representing CLIENT_STATUS for a BOARDOBJGRP_IFACE_MODEL_20
+ *          interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20 {
+    /*!
+     * Super class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20;
+
+/*!
+ * @brief   Structure representing CLIENT_STATUS for a
+ *          BOARDOBJGRP_IFACE_MODEL_PMU_INIT_1X interface
+ *
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X {
+    /*!
+     * Super class CLIENT_STATUS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20 super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X;
+
+/*!
+ * @brief   Structure representing CLIENT_CONTROL for a BOARDOBJGRP_INTERFACE in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE {
+    /*!
+     * @brief   Reserved for future use cases.
+     */
+    NvU8 rsvd;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE;
+
+/*!
+ * @brief   Structure representing CLIENT_CONTROL for a BOARDOBJGRP_IFACE_MODEL interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL {
+    /*!
+     * Super class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL;
+
+/*!
+ * @brief   Structure representing CLIENT_CONTROL for a BOARDOBJGRP_IFACE_MODEL_20
+ *          interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20 {
+    /*!
+     * Super class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20;
+
+/*!
+ * @brief   Structure representing CLIENT_CONTROL for a
+ *          BOARDOBJGRP_IFACE_MODEL_PMU_INIT_1X interface
+ *
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X {
+    /*!
+     * Super class CLIENT_CONTROL
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20 super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X;
+
+/*!
+ * @brief   Structure representing CLIENT_READINGS for a BOARDOBJGRP_INTERFACE in RMCTRL.
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE {
+    /*!
+     * @brief   Reserved for future use cases.
+     */
+    NvU8 rsvd;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE;
+
+/*!
+ * @brief   Structure representing CLIENT_READINGS for a BOARDOBJGRP_IFACE_MODEL interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL {
+    /*!
+     * Super class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL;
+
+/*!
+ * @brief   Structure representing CLIENT_READINGS for a BOARDOBJGRP_IFACE_MODEL_20
+ *          interface
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20 {
+    /*!
+     * Super class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20;
+
+/*!
+ * @brief   Structure representing CLIENT_READINGS for a
+ *          BOARDOBJGRP_IFACE_MODEL_PMU_INIT_1X interface
+ *
+ */
+typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X {
+    /*!
+     * Super class CLIENT_READINGS
+     */
+    NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20 super;
+} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X;
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h
new file mode 100644
index 0000000..5a11107
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn
+//
+
+
+
+#include "nvtypes.h"
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bus.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bus.h
new file mode 100644
index 0000000..5d0b593
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bus.h
@@ -0,0 +1,1696 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080bus.finn
+//
+
+#include "nvcfg_sdk.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX bus control commands and parameters */
+
+/**
+ * NV2080_CTRL_CMD_BUS_GET_PCI_INFO
+ *
+ * This command returns PCI bus identifier information for the specified GPU.
+ *
+ *   pciDeviceId
+ *       This parameter specifies the internal PCI device and vendor
+ *       identifiers for the GPU.
+ *   pciSubSystemId
+ *       This parameter specifies the internal PCI subsystem identifier for
+ *       the GPU.
+ *   pciRevisionId
+ *       This parameter specifies the internal PCI device-specific revision
+ *       identifier for the GPU.
+ *   pciExtDeviceId
+ *       This parameter specifies the external PCI device identifier for
+ *       the GPU.  It contains only the 16-bit device identifier.  This
+ *       value is identical to the device identifier portion of
+ *       pciDeviceId since non-transparent bridges are no longer supported.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_BUS_GET_PCI_INFO (0x20801801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS {
+    NvU32 pciDeviceId;
+    NvU32 pciSubSystemId;
+    NvU32 pciRevisionId;
+    NvU32 pciExtDeviceId;
+} NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_BUS_INFO
+ *
+ * This structure represents a single 32bit bus engine value.  Clients
+ * request a particular bus engine value by specifying a unique bus
+ * information index.
+ *
+ * Legal bus information index values are:
+ *   NV2080_CTRL_BUS_INFO_INDEX_TYPE
+ *     This index is used to request the bus type of the GPU.
+ *     Legal return values for this index are:
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS
+ *       NV2080_CTRL_BUS_INFO_TYPE_FPCI
+ *   NV2080_CTRL_BUS_INFO_INDEX_INTLINE
+ *     This index is used to request the interrupt line (or irq) assignment
+ *     for the GPU.  The return value is system-dependent.
+ *   NV2080_CTRL_BUS_INFO_INDEX_CAPS
+ *     This index is used to request the bus engine capabilities for the GPU.
+ *     The return value is specified as a mask of capabilities.
+ *     Legal return values for this index are:
+ *       NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH
+ *       NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS
+ *     These indices are used to request PCI Express link-specific
+ *     capabilities values.  A value of zero is returned for non-PCIE GPUs.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS
+ *     These indices are used to request PCI Express link-specific
+ *     control status values.  A value of zero is returned for non-PCIE GPUs.
+ *   NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS
+ *     This index is used to request coherent dma transfer flags.
+ *     Valid coherent dma transfer flags include:
+ *       NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA
+ *       NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART
+ *   NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS
+ *     This index is used to request noncoherent dma transfer flags.
+ *     Valid noncoherent dma transfer flags include:
+ *       NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA
+ *       NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART
+ *       NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE
+ *   NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE
+ *     This index is used to request the size of the GPU GART in MBytes.
+ *   NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS
+ *     This index is used to request GPU GART flags.
+ *     Valid gart flags include:
+ *       NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH
+ *         This flag indicates that GPU GART clients need to do an explicit
+ *         flush via an appropriate SetContextDma method.
+ *       NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED
+ *         This flag indicates that the GART address range includes both
+ *         system and video memory.
+ *   NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER
+ *     This index is used to request the PCI-based bus number of the GPU.
+ *     Support for this index is platform-dependent.
+ *   NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER
+ *     This index is used to request the PCI-based device number of the GPU.
+ *     Support for this index is platform-dependent.
+ *   NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER
+ *     This index is used to request the PCI-based domain number of the GPU.
+ *     Support for this index is platform-dependent.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS
+ *     These indices are used to request PCI Express error status.
+ *     The current status is cleared as part of these requests.
+ *     Valid PCI Express error status values include:
+ *       NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR
+ *       NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR
+ *       NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR
+ *       NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST
+ *   NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE
+ *     This index is used to request the bus interface type of the GPU.
+ *     Legal return values for this index are:
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS
+ *       NV2080_CTRL_BUS_INFO_TYPE_FPCI
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO // DEPRECATED
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO  // REPLACES "GEN2" variant
+ *     This index is used to retrieve PCI Express Gen configuration support
+ *     This index is used to retrieve PCI Express Gen2 configuration support 
+ *     for the GPU.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1
+ *          The GPU is PCI Express Gen1 capable.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2
+ *          The GPU is PCI Express Gen2 capable.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3
+ *          The GPU is PCI Express Gen3 capable.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4
+ *          The GPU is PCI Express Gen4 capable.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5
+ *          The GPU is PCI Express Gen5 capable.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1
+ *          The GPU is configured in PCI Express Gen1 mode.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2
+ *          The GPU is configured in PCI Express Gen2 mode.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3
+ *          The GPU is configured in PCI Express Gen3 mode.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4
+ *          The GPU is configured in PCI Express Gen4 mode.
+ *      NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5
+ *          The GPU is configured in PCI Express Gen5 mode.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER
+ *     This index retrieves PCI Express Advanced Error Reporting (AER) errors 
+ *     for the GPU.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS
+ *     This index retrieves the PCI Express link capabilities for the
+ *     board.  For example, a Quadro FX4700X2 has two GPUs and PCIe
+ *     switch.  With this board, this index returns the link
+ *     capabilities of the PCIe switch.  In a single GPU board, this
+ *     index returns the link capabilities of the GPU.  A value of
+ *     zero is returned for non-PCIE GPUs.
+ *     UPSTREAM_LINK_CAPS is kept for backwards compatibility.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS
+ *     This index retrieves the PCI Express link status for the board.
+ *     For example, a Quadro FX4700X2 has two GPUs and PCIe switch.
+ *     With this board, this index returns the link capabilities of
+ *     the PCIe switch.  In a single GPU board, this index returns the
+ *     link status of the GPU.  A value of zero is returned for
+ *     non-PCIE GPUs.
+ *     UPSTREAM_LINK_CTRL_STATUS is kept for backwards compatibility.
+ *   NV2080_CTRL_BUS_INFO_INDEX_ASLM_STATUS
+ *     This index is used to request the PCI Express ASLM settings.
+ *     This index is only valid when NV2080_CTRL_BUS_INFO_TYPE indicates PCIE.
+ *     A value of zero is returned for non-PCI Express bus type.
+ *     _ASLM_STATUS_PCIE is always _PRESENT if PCI Express bus type.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT
+ *     This index is used to get the ASLM switching error count.
+ *     A value of zero will be returned if no errors occurs while
+ *     ASLM switching
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_SWITCH_ERROR_COUNT
+ *     This index is used to get the Gen1<-->Gen2 switching error count
+ *     A value of zero will be returned in case speed change from Gen1 to
+ *     Gen2 is clean or if chipset is not gen2 capable or if gen1<-->gen2 
+ *     switching is disabled.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM
+ *     This index is used to get the ASPM CYA L0s\L1 enable\disable status.
+ *     Legal return value is specified as a mask of valid and data field
+ *     possible return values are:
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1
+ *      NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS
+ *     These indices are used to request detailed PCI Express error counters.
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR
+ *   NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR
+ *     These indices are used to clear detailed PCI Express error counters.
+ *   NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE
+ *     This index is used to request the internal interface type of the GPU.
+ *     Legal return values for this index are:
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI
+ *       NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS
+ *       NV2080_CTRL_BUS_INFO_TYPE_FPCI
+ *   NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE
+ *     This index queries the type of sysmem connection to CPU
+ *     NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE
+ *     NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK
+ *     NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C
+ *
+ */
+
+typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BUS_INFO;
+
+/* valid bus info index values */
+
+/**
+ *  This index is used to request the bus type of the GPU.
+ *  Legal return values for this index are:
+ *    NV2080_CTRL_BUS_INFO_TYPE_PCI
+ *    NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS
+ *    NV2080_CTRL_BUS_INFO_TYPE_FPCI
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_TYPE                                     (0x00000000)
+#define NV2080_CTRL_BUS_INFO_INDEX_INTLINE                                  (0x00000001)
+#define NV2080_CTRL_BUS_INFO_INDEX_CAPS                                     (0x00000002)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS                       (0x00000003)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS                      (0x00000004)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS                  (0x00000005)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS                (0x00000006)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS                (0x00000007)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS               (0x00000008)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS           (0x00000009)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS         (0x0000000A)
+/**
+ * This index is used to request coherent dma transfer flags.
+ * Valid coherent dma transfer flags include:
+ *   NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA
+ *   NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS                       (0x0000000B)
+/**
+ * This index is used to request noncoherent dma transfer flags.
+ * Valid noncoherent dma transfer flags include:
+ *   NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA
+ *   NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART
+ *   NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS                    (0x0000000C)
+/**
+ * This index is used to request the size of the GPU GART in MBytes.
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE                            (0x0000000D)
+/**
+ * This index is used to request GPU GART flags.
+ * Valid gart flags include:
+ *   NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH
+ *     This flag indicates that GPU GART clients need to do an explicit
+ *     flush via an appropriate SetContextDma method.
+ *   NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED
+ *     This flag indicates that the GART address range includes both
+ *     system and video memory.
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS                           (0x0000000E)
+#define NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER                               (0x0000000F)
+#define NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER                            (0x00000010)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS                     (0x00000011)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS                    (0x00000012)
+#define NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE                           (0x00000013)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO                           (0x00000014)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER                        (0x00000015)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS                     (0x00000016)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS              (0x00000017)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS                         (0x00000018)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT       (0x00000019)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT       (0x0000001A)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM                        (0x0000001B)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS            (0x0000001C)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS                 (0x0000001D)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED              (0x0000001E)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS           (0x0000001F)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR      (0x00000020)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR           (0x00000021)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR        (0x00000022)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR     (0x00000023)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS         (0x00000024)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS            (0x00000025)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS               (0x00000026)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS       (0x00000027)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR   (0x00000028)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR      (0x00000029)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR         (0x0000002A)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR (0x0000002B)
+#define NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER                            (0x0000002C)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO                            (0x0000002D)
+#define NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE                       (0x0000002E)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO                   (0x0000002F)
+#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO                      (0x00000030)
+#define NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO                                 (0x00000031)
+/**
+ * This index is used to request the top 32 bits of the size of the GPU
+ * GART in MBytes.
+ */
+#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI                         (0x00000032)
+#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE                   (0x00000033)
+#define NV2080_CTRL_BUS_INFO_INDEX_MAX                                      NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE
+#define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE                                  (0x00000034)
+
+/* valid bus info type return values */
+#define NV2080_CTRL_BUS_INFO_TYPE_PCI                                       (0x00000001)
+#define NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS                               (0x00000003)
+#define NV2080_CTRL_BUS_INFO_TYPE_FPCI                                      (0x00000004)
+#define NV2080_CTRL_BUS_INFO_TYPE_AXI                                       (0x00000008)
+
+/* valid bus capability flags */
+#define NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH                             (0x00000001)
+#define NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED                           (0x00000002)
+
+/* 
+ * Format of PCIE link caps return values
+ * Note that Link Capabilities register format is followed only for bits 11:0
+ */
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED               3:0
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS               (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS               (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS               (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS              (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS              (0x00000005)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS              (0x00000006)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH               9:4
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM                    11:10
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE                        (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S                         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1                      (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN                     15:12
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1                         (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2                         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3                         (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4                         (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5                         (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6                         (0x00000005)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL              19:16
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1                  (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2                  (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3                  (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4                  (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5                  (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6                  (0x00000005)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN                 23:20
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1                     (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2                     (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3                     (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4                     (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5                     (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6                     (0x00000005)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES           24:24
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED            (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED           (0x00000001)
+
+/* format of PCIE control status return values */
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM                 1:0
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED            (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S                 (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1                  (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1              (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED           19:16
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS      (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS      (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS      (0x00000003)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS     (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS     (0x00000005)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS     (0x00000006)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH           25:20
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED     (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1            (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2            (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4            (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8            (0x00000008)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12           (0x0000000C)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16           (0x00000010)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32           (0x00000020)
+
+/* coherent dma transfer flags */
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA             0:0
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE                (0x00000000)
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE                 (0x00000001)
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART            2:2
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE               (0x00000000)
+#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE                (0x00000001)
+
+/* noncoherent dma transfer flags */
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA          0:0
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE             (0x00000000)
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE              (0x00000001)
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART         2:2
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE            (0x00000000)
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE             (0x00000001)
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE        3:3
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE           (0x00000000)
+#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE            (0x00000001)
+
+/* GPU GART flags */
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH               0:0
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE                  (0x00000000)
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE                   (0x00000001)
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED                1:1
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE                   (0x00000000)
+#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE                    (0x00000001)
+
+/* format of PCIE errors return values */
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR                    (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR               (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR                   (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST                (0x00000008)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY              (0x00000010)
+
+/* PCIE Gen2 capability and current level */
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP                    0:0
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE                       (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE                        (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL             1:1
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1                 (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2                 (0x00000001)
+
+/* format of PCIE AER return values */
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR              (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR           (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP              (0x00000004)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR              (0x00000008)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT               (0x00000010)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT                 (0x00000020)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL                 (0x00000040)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW             (0x00000080)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP             (0x00000100)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR                (0x00000200)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ           (0x00000400)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR                     (0x00010000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP                     (0x00020000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP                    (0x00040000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER               (0x00080000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT                (0x00100000)
+#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL           (0x00200000)
+
+/* format of PCIE ASLM status return value */
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE                  0:0
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR                    (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT                  (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED             1:1
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO                  (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES                 (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE            2:2
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO                 (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES                (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED          3:3
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO               (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES              (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04                  4:4
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING                  (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT                  (0x00000001)
+
+/* format of GPU CYA CAPS return value */
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID               0:0
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO                     (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES                    (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM                     2:1
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED                     (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S                          (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1                           (0x00000002)
+#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1                       (0x00000003)
+
+/* format of MSI INFO return value */
+#define NV2080_CTRL_BUS_INFO_MSI_STATUS                            0:0
+#define NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED                            (0x00000000)
+#define NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED                             (0x00000001)
+
+/*format of L1PM Substates capabilities information */
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED         0:0
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES        (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO         (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED         1:1
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES        (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO         (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED          2:2
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO          (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED          3:3
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO          (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED               4:4
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES              (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO               (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_RESERVED                     7:5
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PORT_RESTORE_TIME            15:8
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_SCALE             17:16
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_VALUE             23:19
+
+/*format of L1 PM Substates Control 1 Register */
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED         0:0
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES        (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO         (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED         1:1
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES        (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO         (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED          2:2
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO          (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED          3:3
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES         (0x00000001)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO          (0x00000000)
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_COMMON_MODE_RESTORE_TIME   15:8
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_VALUE   25:16
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_SCALE   31:29
+
+/*format of L1 PM Substates Control 2 Register */
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_SCALE           1:0
+#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_VALUE           7:3
+
+/* valid sysmem connection type values */
+#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE              (0x00000000)
+#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK            (0x00000001)
+#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C               (0x00000002)
+
+/**
+ * NV2080_CTRL_CMD_BUS_GET_INFO
+ *
+ * This command returns bus engine information for the associated GPU.
+ * Requests to retrieve bus information use a list of one or more
+ * NV2080_CTRL_BUS_INFO structures.
+ *
+ *   busInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     busInfoList.
+ *   busInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the bus information is to be returned.
+ *     This buffer must be at least as big as busInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_BUS_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_BUS_GET_INFO                                        (0x20801802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_BUS_GET_INFO_PARAMS {
+    NvU32 busInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 busInfoList, 8);
+} NV2080_CTRL_BUS_GET_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_BUS_GET_INFO_V2 (0x20801823) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV2080_CTRL_BUS_GET_INFO_V2_PARAMS {
+    NvU32                busInfoListSize;
+    NV2080_CTRL_BUS_INFO busInfoList[NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE];
+} NV2080_CTRL_BUS_GET_INFO_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_BUS_PCI_BAR_INFO
+ *
+ * This structure describes PCI bus BAR information.
+ *
+ *   flags
+ *     This field contains any flags for the associated BAR.
+ *   barSize
+ *     This field contains the size in megabytes of the associated BAR.
+ *     DEPRECATED, please use barSizeBytes.
+ *   barSizeBytes
+ *     This field contains the size in bytes of the associated BAR.
+ *   barOffset
+ *     This field contains the PCI bus offset in bytes of the associated BAR.
+ */
+typedef struct NV2080_CTRL_BUS_PCI_BAR_INFO {
+    NvU32 flags;
+    NvU32 barSize;
+    NV_DECLARE_ALIGNED(NvU64 barSizeBytes, 8);
+    NV_DECLARE_ALIGNED(NvU64 barOffset, 8);
+} NV2080_CTRL_BUS_PCI_BAR_INFO;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO
+ *
+ * This command returns PCI bus BAR information.
+ *
+ *   barCount
+ *     This field returns the number of BARs for the associated subdevice.
+ *     Legal values for this parameter will be between one to
+ *      NV2080_CTRL_BUS_MAX_BARS.
+ *   barInfo
+ *     This field returns per-BAR information in the form of an array of
+ *     NV2080_CTRL_BUS_PCI_BAR_INFO structures.  Information for as many as
+ *     NV2080_CTRL_BUS_MAX_PCI_BARS will be returned.  Any unused entries will
+ *     be initialized to zero.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO (0x20801803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum number of BARs per subdevice */
+#define NV2080_CTRL_BUS_MAX_PCI_BARS         (8)
+
+#define NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS {
+    NvU32 pciBarCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_BUS_PCI_BAR_INFO pciBarInfo[NV2080_CTRL_BUS_MAX_PCI_BARS], 8);
+} NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH
+ *
+ * This command sets PCI-E link width to the specified new value.
+ *
+ *   pcieLinkWidth
+ *      This field specifies the new PCI-E link width.
+ *
+ *   failingReason
+ *      This field specifies the reason why the change of link width fails.
+ *      It is valid only when this routine returns NV_ERR_GENERIC.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_GENERIC
+ */
+#define NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH (0x20801804) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS {
+    NvU32 pcieLinkWidth;
+    NvU32 failingReason;
+} NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS;
+
+#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE          (0x00000001)
+#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS (0x00000002)
+#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING        (0x00000004)
+
+/*
+ * NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED
+ *
+ * This command Initiates a change in PCIE Bus Speed
+ *
+ *   busSpeed
+ *     This field is the target speed to train to.
+ *     Legal values for this parameter are:
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS
+ *       NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED                        (0x20801805) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS {
+    NvU32 busSpeed;
+} NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS;
+
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS  (0x00000001)
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS  (0x00000002)
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS  (0x00000003)
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS (0x00000004)
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS (0x00000005)
+#define NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS (0x00000006)
+
+
+/*
+ * NV2080_CTRL_CMD_BUS_MAP_BAR2
+ *
+ * This command sets up BAR2 page tables for passed-in memory handle.
+ * This command MUST be executed before NV2080_CTRL_CMD_BUS_UNMAP_BAR2
+ * or NV2080_CTRL_CMD_BUS_VERIFY_BAR2. Not supported on SLI.
+ *
+ * hMemory
+ *    This field is a handle to physical memory.
+ *
+ * Possible status values returned are
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_BUS_MAP_BAR2             (0x20801809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_BUS_MAP_BAR2_PARAMS {
+    NvHandle hMemory;
+} NV2080_CTRL_BUS_MAP_BAR2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_UNMAP_BAR2
+ *
+ * This command unmaps any pending BAR2 page tables created with
+ * NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed in must
+ * match the handle used to map the page tables. Not supported on SLI.
+ *
+ * hMemory
+ *    This field is a handle to physical memory.
+ *
+ * Possible status values returned are
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_BUS_UNMAP_BAR2 (0x2080180a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS {
+    NvHandle hMemory;
+} NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_VERIFY_BAR2
+ *
+ * This command tests BAR2 against BAR0 if there are BAR2 page tables
+ * set up with NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed
+ * in must match the handle used to map the page tables. Not supported on SLI.
+ *
+ * hMemory
+ *    This field is a handle to physical memory.
+ * offset
+ *    Base offset of the surface where the test will make its first dword write.
+ * size
+ *    Test will write '(size/4)*4' bytes starting at surface offset `offset'.
+ *
+ * Possible status values returned are
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_BUS_VERIFY_BAR2 (0x2080180b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS {
+    NvHandle hMemory;
+    NvU32    offset;
+    NvU32    size;
+} NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE
+ *  This command would reports the current Audio device power state or Sets new power state.
+ *
+ * command
+ *  This parametrer specifies the target GPU multifunction state.
+ *      NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE      Enables the multi function state
+ *      NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE     Disables the multi function state.
+ *      NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE         Get the Current device power state.
+ *
+ * Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_GENERIC
+ */
+
+#define NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE (0x20801812) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS {
+    NvU8  command;
+    NvU32 deviceState;
+} NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS;
+
+#define NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE  (0x00000000)
+#define NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE (0x00000001)
+#define NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE     (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * pexCounterMask
+ *  This parameter specifies the input mask for desired counter types.
+ *
+ * pexTotalCorrectableErrors
+ *  This parameter gives the total correctable errors which includes
+ *  NV_XVE_ERROR_COUNTER1 plus LCRC Errors, 8B10B Errors, NAKS and Failed L0s
+ *
+ * pexCorrectableErrors
+ *  This parameter only includes NV_XVE_ERROR_COUNTER1 value.
+ *
+ * pexTotalNonFatalErrors
+ *  This parameter returns total Non-Fatal Errors which may or may not
+ *  include Correctable Errors.
+ *
+ * pexTotalFatalErrors
+ *  This parameter returns Total Fatal Errors
+ *
+ * pexTotalUnsupportedReqs
+ *  This parameter returns Total Unsupported Requests
+ *
+ * pexErrors
+ *  This array contains the error counts for each error type as requested from
+ *  the pexCounterMask. The array indexes correspond to the mask bits one-to-one.
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS        (0x20801813) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PEX_MAX_COUNTER_TYPES           31
+#define NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS {
+    NvU32 pexCounterMask;
+    NvU32 pexTotalCorrectableErrors;
+    NvU16 pexCorrectableErrors;
+    NvU8  pexTotalNonFatalErrors;
+    NvU8  pexTotalFatalErrors;
+    NvU8  pexTotalUnsupportedReqs;
+    NvU16 pexCounters[NV2080_CTRL_PEX_MAX_COUNTER_TYPES];
+} NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS;
+
+/*
+ * Note that MAX_COUNTER_TYPES will need to be updated each time
+ * a new counter type gets added to the list below. The value
+ * depends on the bits set for the last valid define. Look
+ * at pexCounters[] comments above for details.
+ *
+ */
+#define NV2080_CTRL_BUS_PEX_COUNTER_TYPE                          0x00000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS               0x00000001
+#define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT                  0x00000002
+#define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT         0x00000004
+#define NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT                0x00000008
+#define NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT                 0x00000010
+#define NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT            0x00000020
+#define NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT      0x00000040
+#define NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT             0x00000080
+#define NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT        0x00000100
+#define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT               0x00000200
+#define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT               0x00000400
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS                   0x00000800
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT          0x00001000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT          0x00002000
+#define NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT                0x00004000
+#define NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT  0x00008000
+#define NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT      0x00010000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT                0x00020000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT               0x00040000
+#define NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT           0x00080000
+#define NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT                    0x00100000
+#define NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT        0x00200000
+#define NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT              0x00400000
+#define NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT         0x00800000
+#define NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT             0x01000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT              0x02000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT              0x04000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT              0x08000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT              0x10000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT 0x20000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT       0x40000000
+
+/*
+ * NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTER_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * pexCounterMask
+ *  This parameter specifies the input mask for desired counters to be
+ *  cleared. Note that all counters cannot be cleared.
+ */
+
+#define NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS                    (0x20801814) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS {
+    NvU32 pexCounterMask;
+} NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * pexCounterMask
+ *  This parameter specifies the input mask for desired counters to be
+ *  freezed. Note that all counters cannot be frozen.
+ * 
+ * bFreezeRmCounter
+ *  This parameter decides whether API will freeze it or unfreeze it.
+ *  NV_TRUE for freeze and NV_FALSE for unfreeze.
+ */
+
+#define NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS (0x20801815) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS {
+    NvU32  pexCounterMask;
+    NvBool bFreezeRmCounter;
+} NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS
+ *  This command gets the per Lane Counters and the type of errors.
+ *
+ * pexLaneErrorStatus
+ *  This mask specifies the type of error detected on any of the Lanes.
+ *
+ * pexLaneCounter
+ *  This array gives the counters per Lane. Each index corresponds to Lane
+ *  index + 1
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS (0x20801816) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PEX_MAX_LANES                 16
+#define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS {
+    NvU16 pexLaneErrorStatus;
+    NvU8  pexLaneCounter[NV2080_CTRL_PEX_MAX_LANES];
+} NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE                  0x00000000
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR   0x00000001
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR    0x00000002
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR       0x00000004
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR      0x00000008
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR        0x00000010
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW  0x00000020
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW 0x00000040
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR     0x00000080
+#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR     0x00000100
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY               (0x20801817) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x17U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS {
+    NvBool bPexLtrRegkeyOverride;
+    NvBool bPexRootPortLtrSupported;
+    NvBool bPexGpuLtrSupported;
+    NvU16  pexLtrSnoopLatencyValue;
+    NvU8   pexLtrSnoopLatencyScale;
+    NvU16  pexLtrNoSnoopLatencyValue;
+    NvU8   pexLtrNoSnoopLatencyScale;
+} NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS;
+
+#define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY (0x20801818) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS {
+    NvU16 pexLtrSnoopLatencyValue;
+    NvU8  pexLtrSnoopLatencyScale;
+    NvU16 pexLtrNoSnoopLatencyValue;
+    NvU8  pexLtrNoSnoopLatencyScale;
+} NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * pexCounterMask
+ *  This parameter specifies the input mask for desired counter types.
+ *
+ */
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES   0x00000001
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES   0x00000002
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0      0x00000004
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0      0x00000008
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S     0x00000010
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S     0x00000020
+#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S 0x00000040
+#define NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES      7
+
+#define NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS   (0x20801819) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS {
+    NvU32 pexCounterMask;
+    NvU32 pexCounters[NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES];
+} NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTER_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * pexCounterMask
+ *  This parameter specifies the input mask for desired counters to be
+ *  cleared. Note that all counters cannot be cleared.
+ * 
+ * NOTE: EX_UTIL_COUNTER_UPSTREAM & NV2080_CTRL_BUS_PEX_UTIL_COUNTER_DOWNSTREAM
+ *       belongs to PMU. The ctrl function will not reset nor disable/enable them.
+ */
+#define NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS (0x20801820) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS {
+    NvU32 pexCounterMask;
+} NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS (0x20801824) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS {
+    NvBool bEnable;
+} NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK
+ *
+ * This command returns cached(SW only) NVLINK peer id mask. Currently, this control
+ * call is only needed inside a SR-IOV enabled guest where page table management is
+ * being done by the guest. Guest needs this mask to derive the peer id corresponding
+ * to the peer GPU. This peer id will then be programmed inside the PTEs by guest RM.
+ *
+ *   nvlinkPeerIdMask[OUT]
+ *      - The peer id mask is returned in this array.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK (0x20801825) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_MAX_NUM_GPUS                32
+
+#define NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS {
+    NvU32 nvlinkPeerIdMask[NV2080_CTRL_BUS_MAX_NUM_GPUS];
+} NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS;
+
+/* 
+ * NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS
+ * This command takes parameters eomMode, eomNblks and eomNerrs from the client
+ * and then sends it out to PMU.
+ */
+#define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS (0x20801826) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID (0x26U)
+
+typedef struct NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS {
+    NvU8 eomMode;
+    NvU8 eomNblks;
+    NvU8 eomNerrs;
+} NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS;
+
+/* 
+ * NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE
+ * This command takes parameters UPHY register's address and lane from the client
+ * and then sends it out to PMU.
+ */
+#define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE (0x20801827) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID (0x27U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS {
+    NvU32 regAddress;
+    NvU32 laneSelectMask;
+    NvU16 regValue;
+} NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_EOM_STATUS
+ *
+ */
+#define NV2080_CTRL_CMD_BUS_GET_EOM_STATUS (0x20801828) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_MAX_NUM_LANES      32
+
+#define NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID (0x28U)
+
+typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS {
+    NvU8  eomMode;
+    NvU8  eomNblks;
+    NvU8  eomNerrs;
+    NvU8  eomBerEyeSel;
+    NvU8  eomPamEyeSel;
+    NvU32 laneMask;
+    NvU16 eomStatus[NV2080_CTRL_BUS_MAX_NUM_LANES];
+} NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS
+ *
+ * This command returns the PCIe requester atomics operation capabilities
+ * of the GPU with regards to the aspect of support the client is asking for.
+ *
+ *
+ * capType [IN]
+ *  The aspect of the atomics support the client is querying atomics capability for.
+ *  Supported types are defined under NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_*.
+ *
+ * dbdf [IN] -
+ * Argument used to identify the PCIe peer endpoint. Used only for the _CAPTYPE_P2P.
+ * Encoded as: domain (31:16), bus (15:8), device (7:3), function (2:0)
+ *
+ * atomicsCaps[OUT]
+ *  Mask of supported PCIe requester atomic operations in the form of
+ *  NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_*
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS (0x20801829) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x29U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS {
+    NvU32 capType;
+    NvU32 dbdf;
+    NvU32 atomicsCaps;
+} NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS;
+
+/*
+ * Defined methods to expose atomics capability.
+ *
+ * NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM
+ *  Exposes the state of atomics support between GPU and Sysmem.
+ * NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU
+ *  Exposes the state of the GPU atomics support without taking into account PCIe topology.
+ * NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P
+ *  Exposes the state of atomics support between the source (this GPU)
+ *  and peer GPU identified by the dbdf argument.
+ */
+#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM 0x0
+#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU    0x1
+#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P    0x2
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32      0:0
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO  (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64      1:1
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO  (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32          2:2
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES     (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO      (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64          3:3
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES     (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO      (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32           4:4
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES      (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO       (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64           5:5
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES      (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO       (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128          6:6
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES     (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO      (0x00000000)
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS
+ *
+ * This command returns the supported GPU atomic operations
+ * that map to the capable PCIe atomic operations from GPU to
+ * coherent SYSMEM.
+ *
+ * capType [IN]
+ *  The aspect of the atomics support the client is querying atomics capability for.
+ *  Supported types are defined under NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_*.
+ *
+ * dbdf [IN] -
+ * Argument used to identify the PCIe peer endpoint. Used only for the _CAPTYPE_P2P.
+ * Encoded as: domain (31:16), bus (15:8), device (7:3), function (2:0)
+ *
+ * atomicOp[OUT]
+ *  Array of NV2080_CTRL_BUS_PCIE_GPU_ATOMICS that contains the atomic operation
+ *  supported status and its attributes. The array can be
+ *  indexed using one of NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_*
+ *  
+ */
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS            (0x2080182a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD           0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN           1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX           2
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC            3
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC            4
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND           5
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR            6
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR           7
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH           8
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS            9
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD           10
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN           11
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX           12
+
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT          13
+
+/*
+ * NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO
+ *
+ *  Describes the support state and related attributes of a single GPU atomic op.
+ *
+ *  bSupported
+ *   Is the GPU atomic operation natively supported by the PCIe
+ *
+ *  attributes
+ *   Provides the attributes mask of the GPU atomic operation when supported
+ *   in the form of
+ *   NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_*
+ */
+typedef struct NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO {
+    NvBool bSupported;
+    NvU32  attributes;
+} NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO;
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID (0x2AU)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
+    NvU32                                   capType;
+    NvU32                                   dbdf;
+    NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT];
+} NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS;
+
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR         0:0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES    1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO     0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR         1:1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES    1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO     0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION      2:2
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES 1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO  0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32        3:3
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES   1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO    0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64        4:4
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES   1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO    0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128       5:5
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES  1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO   0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED         6:6
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES    1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO     0
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED       7:7
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES  1
+#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO   0
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_C2C_INFO
+ *
+ * This command returns the C2C links information.
+ *
+ *   bIsLinkUp[OUT]
+ *       NV_TRUE if the C2C links are present and the links are up.
+ *       The below remaining fields are valid only if return value is
+ *       NV_OK and bIsLinkUp is NV_TRUE.
+ *   bLinkInHS[OUT]
+ *       NV_TRUE if the C2C links are in high speed mode.
+ *   nrLinks[OUT]
+ *       Total number of C2C links that are up.
+ *   maxNrLinks[OUT]
+ *       Maximum number of C2C links that are supported.
+ *   linkMask[OUT]
+ *       Bitmask of the C2C links present and up.
+ *   perLinkBwMBps[OUT]
+ *       Theoretical per link bandwidth in MBps.
+ *   perLinkLaneWidth[OUT]
+ *       Lane width per link.
+ *   remoteType[OUT]
+ *       Type of the device connected to the remote end of the C2C link.
+ *       Valid values are :
+ *       NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU
+ *       NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU - connected to another GPU
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *
+ * Please also review the information below for additional information on
+ * select fields:
+ *
+ *   remoteType[OUT]
+ *       NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU
+ *       in either self-hosted mode or externally-hostedmode.
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO                            (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_INSTANCES          2
+#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS_PER_INSTANCE 7
+#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS              (0xe) /* finn: Evaluated from "NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_INSTANCES * NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS_PER_INSTANCE" */
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID (0x2BU)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
+    NvBool bIsLinkUp;
+    NvBool bLinkInHS;
+
+    NvBool bEncryptionEnabled;
+
+
+    NvU32  nrLinks;
+    NvU32  maxNrLinks;
+    NvU32  linkMask;
+    NvU32  perLinkBwMBps;
+    NvU32  perLinkLaneWidth;
+    NvU32  remoteType;
+} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS;
+
+#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1
+#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2
+
+
+
+/*
+ * NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS
+ *
+ * This command disables the GPU system memory access after quiescing the GPU,
+ * or re-enables sysmem access.
+ *
+ *   bDisable
+ *     If NV_TRUE the GPU is quiesced and system memory access is disabled .
+ *     If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS            (0x2080182c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID (0x2CU)
+
+typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS {
+    NvBool bDisable;
+} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO
+ *
+ * This command returns the C2C error info for a C2C links.
+ *
+ * errCnts[OUT]
+ *  Array of structure that contains the error counts for
+ *  number of times one of C2C fatal error interrupt has happened.
+ *  The array size should be NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS.
+ *
+ *  nrCrcErrIntr[OUT]
+ *   Number of times CRC error interrupt triggered.
+ *  nrReplayErrIntr[OUT]
+ *   Number of times REPLAY error interrupt triggered.
+ *  nrReplayB2bErrIntr[OUT]
+ *   Number of times REPLAY_B2B error interrupt triggered.
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_INVALID_STATE
+ *  NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU)
+
+typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
+    struct {
+        NvU32 nrCrcErrIntr;
+        NvU32 nrReplayErrIntr;
+        NvU32 nrReplayB2bErrIntr;
+    } errCnts[NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS];
+} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING
+ *
+ * This command sets P2P mapping.
+ *
+ * connectionType[IN]
+ *   Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION
+ * peerId[IN]
+ *   peerId of remote GPU from local GPU on which call is made.
+ * bSpaAccessOnly[IN]
+ *   SPA access only. SPA addressing mode is supported when we support ATS.
+ * bUseUuid [in]
+ *   Option only available for Guest RPCs and is not avaliable for external clients.
+ *   Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU.
+ * remoteGpuId[IN]
+ *   GPU ID of remote GPU.
+ * remoteGpuUuid [in]
+ *   Alternative to gpuId; used to identify target GPU for which caps are being queried.
+ *   Option only available for Guest RPCs.
+ *   If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU.
+ *   If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default.
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_INVALID_ARGUMENT
+ *  NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING                           (0x2080182e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID   0
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK    1
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE      2
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 3
+#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C       4
+
+#define NV2080_SET_P2P_MAPPING_UUID_LEN                               16U
+
+#define NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2EU)
+
+typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS {
+    NvU32  connectionType;
+    NvU32  peerId;
+    NvBool bEgmPeer;
+    NvBool bSpaAccessOnly;
+    NvBool bUseUuid;
+    NvU32  remoteGpuId;
+    NvU8   remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN];
+} NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING
+ *
+ * This command unsets P2P mapping.
+ *
+ * connectionType[IN]
+ *   Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION
+ * peerId[IN]
+ *   peerId of remote GPU from local GPU on which call is mad.
+ * bUseUuid [in]
+ *   Option only available for Guest RPCs and is not avaliable for external clients.
+ *   Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU.
+ * remoteGpuId[IN]
+ *   GPU ID of remote GPU.
+ * remoteGpuUuid [in]
+ *   Alternative to gpuId; used to identify target GPU for which caps are being queried.
+ *   Option only available for Guest RPCs.
+ *   If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU.
+ *   If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default.
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_INVALID_ARGUMENT
+ *  NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING (0x2080182f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2FU)
+
+typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS {
+    NvU32  connectionType;
+    NvU32  peerId;
+    NvBool bUseUuid;
+    NvU32  remoteGpuId;
+    NvU8   remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN];
+} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS
+ *
+ * This command returns the PCIe completer atomics operation capabilities
+ * of the GPU.
+ *
+ * atomicsCaps[OUT]
+ *  Mask of supported PCIe completer atomic operations in the form of
+ *  NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_*
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS (0x20801830) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x30U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS {
+    NvU32 atomicsCaps;
+} NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS;
+
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32      0:0
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO  (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64      1:1
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO  (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32          2:2
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES     (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO      (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64          3:3
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES     (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO      (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32           4:4
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES      (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO       (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64           5:5
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES      (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO       (0x00000000)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128          6:6
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES     (0x00000001)
+#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO      (0x00000000)
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS
+ *
+ * This command returns C2C low power statistics.
+ * Units for residency and latency are in microsceconds.
+ *   c2cStateSupportMask[OUT]
+        Support Mask of supplrted C2C State. CL0 will always be supported (FULL_POWER)
+ *   cl3EntryCount[OUT]
+ *       Count of the number of times CL3 state has been entered.
+ *   cl3ResidentTimeUs[OUT]
+ *       Total/Average resident time in CL3 state.
+ *   cl3AvgEntryLatencyUs[OUT]
+ *       Average entry latency for CL3 state.
+ *   cl3AvgExitLatencyUs[OUT]
+ *       Average exit latency for CL3 state.
+ *   cl3PstateSupportMask[OUT]
+        Pstate Support Mask for CL3 state
+ *   cl3IdleThresholdUs[OUT]
+ *       Get idle threshold for CL3 state.
+ *   cl4EntryCount[OUT]
+ *       Count of the number of times CL4 state has been entered.
+ *   cl4ResidentTimeUs[OUT]
+ *       Total/Average resident time in CL4 state.
+ *   cl4AvgEntryLatencyUs[OUT]
+ *       Average entry latency for CL4 state.
+ *   cl4AvgExitLatencyUs[OUT]
+ *       Average exit latency for CL4 state.
+ *   cl4PstateSupportMask[OUT]
+        Pstate Support Mask for CL4 state
+ *   cl4IdleThresholdUs[OUT]
+ *       Get idle threshold for CL4 state.
+ *   localPowerState[OUT]
+ *       Power state of the local end of the C2C link.
+ *       Valid values are :
+ *       NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER - Full power state
+ *       NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 - Low power state
+ *       NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 - Low power state
+ *   remotePowerState[OUT]
+ *       Power state of the remote end of the C2C link.
+ *       Valid values are :
+ *       NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER - Full power state
+ *       NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 - Low power state
+ *       NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 - Low power state
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *
+ * Please also review the information below for additional information on
+ * select fields:
+ *
+ *   cl3EntryCount/cl4EntryCount[OUT]
+ *       These may not represent current exact count, as low power transitions could have
+ *       occured after reading the counter register.
+ */
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS                        (0x20801831) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID (0x31U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS {
+    NvU32  c2cStateSupportMask;
+    NvBool bCl3Support;
+    NvU32  cl3EntryCount;
+    NvU32  cl3ExitCount;
+    NvU32  cl3ResidentTimeUs;
+    NvU32  cl3AvgEntryLatencyUs;
+    NvU32  cl3AvgExitLatencyUs;
+    NvU32  cl3PstateSupportMask;
+    NvU32  cl3DisallowReasonMask;
+    NvBool bCl4Support;
+    NvU32  cl4EntryCount;
+    NvU32  cl4ExitCount;
+    NvU32  cl4ResidentTimeUs;
+    NvU32  cl4AvgEntryLatencyUs;
+    NvU32  cl4AvgExitLatencyUs;
+    NvU32  cl4PstateSupportMask;
+    NvU32  cl4DisallowReasonMask;
+    NvU32  c2cLpwrStateAllowedMask;
+    NvU32  localPowerState;
+    NvU32  remotePowerState;
+    NvU32  cl3IdleThresholdUs;
+    NvU32  cl4IdleThresholdUs;
+} NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS;
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER 0x0
+#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3        0x1
+#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4        0x2
+
+/*
+ * NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE
+ *
+ * This command sets the allow vote for C2C Lpwr States.
+ *   c2cLpwrStateId[IN]
+ *      C2C LowPower State Id : NV2080_CTRL_LPWR_C2C_STATE_ID_CLx
+ *   bAllowed[in]
+ *      State Allowed/disallowed flag
+ */
+#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE  (0x20801832) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID (0x32U)
+
+typedef struct NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS {
+    NvU32  c2cLpwrStateId;
+    NvBool bAllowed;
+} NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD
+ *
+ * This command sets the idle threshold for C2C Lpwr States.
+ *   c2cLpwrStateId[IN]
+ *      C2C LowPower State Id : NV2080_CTRL_LPWR_C2C_STATE_ID_CLx
+ *   idleThresholdUs[in]
+ *      The Idle Threshold for the C2C Ctrl in Micro Seconds
+ */
+#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD (0x20801836) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS_MESSAGE_ID (0x36U)
+
+typedef struct NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS {
+    NvU32 c2cLpwrStateId;
+    NvU32 idleThresholdUs;
+} NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS
+ *
+ * This command gets packet counter values for all C2C links. This
+ * is intended for testing and debug only. These values cannot be used to
+ * measure bandwidth.
+ *   packetCounters[OUT]
+ *      An array of C2C packet counters
+ *
+ */
+#define NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS (0x20801837) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS_MESSAGE_ID (0x37U)
+
+typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS {
+    NvU32 packetCounters[NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS];
+} NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS;
+
+
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ce.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ce.h
new file mode 100644
index 0000000..d6b353e
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ce.h
@@ -0,0 +1,577 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080ce.finn
+//
+
+
+
+#include "nvcfg_sdk.h"
+
+
+/* NV20_SUBDEVICE_XX ce control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_CAPS
+ *
+ * This command returns the set of CE capabilities for the device
+ * in the form of an array of unsigned bytes.
+ *
+ *   ceEngineType
+ *     This parameter specifies the copy engine type
+ *   capsTblSize
+ *     This parameter specifies the size in bytes of the caps table per CE.
+ *     This value should be set to NV2080_CTRL_CE_CAPS_TBL_SIZE.
+ *   capsTbl
+ *     This parameter specifies a pointer to the client's caps table buffer
+ *     into which the CE caps bits will be transferred by the RM.
+ *     The caps table is an array of unsigned bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_CAPS  (0x20802a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+/*
+ * Size in bytes of CE caps table.  This value should be one greater
+ * than the largest byte_index value below.
+ */
+#define NV2080_CTRL_CE_CAPS_TBL_SIZE 2
+
+#define NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_CE_GET_CAPS_PARAMS {
+    NvU32 ceEngineType;
+    NvU32 capsTblSize;
+    NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
+} NV2080_CTRL_CE_GET_CAPS_PARAMS;
+
+#define NV2080_CTRL_CMD_CE_GET_CAPS_V2 (0x20802a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
+    NvU32 ceEngineType;
+    NvU8  capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE];
+} NV2080_CTRL_CE_GET_CAPS_V2_PARAMS;
+
+/* extract cap bit setting from tbl */
+#define NV2080_CTRL_CE_GET_CAP(tbl,c)               (((NvU8)tbl[(1?c)]) & (0?c))
+
+/* caps format is byte_index:bit_mask */
+#define NV2080_CTRL_CE_CAPS_CE_GRCE                          0:0x01
+#define NV2080_CTRL_CE_CAPS_CE_SHARED                        0:0x02
+#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ                   0:0x04
+#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE                  0:0x08
+#define NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P                    0:0x10
+#define NV2080_CTRL_CE_CAPS_CE_SYSMEM                        0:0x20
+#define NV2080_CTRL_CE_CAPS_CE_P2P                           0:0x40
+#define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED      0:0x80
+#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL      1:0x01
+#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL         1:0x02
+#define NV2080_CTRL_CE_CAPS_CE_CC_SECURE                     1:0x04
+#define NV2080_CTRL_CE_CAPS_CE_DECOMP_SUPPORTED              1:0x08
+#define NV2080_CTRL_CE_CAPS_CE_CC_WORK_SUBMIT                1:0x10
+#define NV2080_CTRL_CE_CAPS_CE_SCRUB                         1:0x40
+
+/*
+ *   NV2080_CTRL_CE_CAPS_CE_GRCE
+ *     Set if the CE is synchronous with GR
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SHARED
+ *     Set if the CE shares physical CEs with any other CE
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ
+ *     Set if the CE can give enhanced performance for SYSMEM reads over other CEs
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE
+ *     Set if the CE can give enhanced performance for SYSMEM writes over other CEs
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P
+ *     Set if the CE can be used for P2P transactions using NVLINK
+ *     Once a CE is exposed for P2P over NVLINK, it will remain available for the life of RM
+ *     PCE2LCE mapping may change based on the number of GPUs registered in RM however
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SYSMEM
+ *     Set if the CE can be used for SYSMEM transactions
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_P2P
+ *     Set if the CE can be used for P2P transactions
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED
+ *     Set if the CE supports BL copy size greater than 64K
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL
+ *     Set if the CE supports non-pipelined Block linear
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL
+ *     Set if the CE supports pipelined Block Linear
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_CC_SECURE
+ *     Set if the CE is capable of encryption/decryption
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_DECOMP_SUPPORTED
+ *     Set if the CE is capable of handling decompression workloads;
+ *     async copies will not be supported on the same CE
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_CC_WORK_SUBMIT
+ *     Set if the CE can be used for work launch/completion in CC mode
+ *
+ *   NV2080_CTRL_CE_CAPS_CE_SCRUB
+ *     Set if the CE can be used for fast scrubbing
+ */
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK
+ *
+ * This command returns the mapping of PCE's for the given LCE.
+ * The pceMask is local to the CE shim that ceEngineType belongs to.
+ *
+ *   ceEngineType
+ *     This parameter specifies the copy engine type
+ *   pceMask
+ *     This parameter specifies a mask of PCEs that correspond
+ *     to the LCE specified in ceEngineType
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS {
+    NvU32 ceEngineType;
+    NvU32 pceMask;
+} NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG
+ *
+ * This command sets the PCE2LCE configuration
+ *
+ *   pceLceConfig[NV2080_CTRL_MAX_PCES]
+ *     This parameter specifies the PCE-LCE mapping requested
+ *   grceLceConfig[NV2080_CTRL_MAX_GRCES]
+ *     This parameter specifies which LCE is the GRCE sharing with
+ *     0xF -> Does not share with any LCE
+ *     0-MAX_LCE -> Shares with the given LCE
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MAX_PCES                  64
+#define NV2080_CTRL_MAX_GRCES                 4
+
+#define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
+    NvU32 ceEngineType;
+    NvU32 pceLceMap[NV2080_CTRL_MAX_PCES];
+    NvU32 grceSharedLceMap[NV2080_CTRL_MAX_GRCES];
+} NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS
+ *
+ * This command updates the PCE-LCE mappings
+ *
+ *   pceLceMap [IN]
+ *     This parameter contains the array of PCE to LCE mappings.
+ *     The array is indexed by the PCE index, and contains the
+ *     LCE index that the PCE is assigned to.  A unused PCE is
+ *     tagged with NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE.
+ *
+ *   grceConfig [IN]
+ *     This parameter contains the array of GRCE configs.
+ *     0xF -> GRCE does not share with any LCE
+ *     0-MAX_LCE -> GRCE shares with the given LCE
+ *
+ *   exposeCeMask [IN]
+ *     This parameter specifies the mask of LCEs to export to the
+ *     clients after the update.
+ *
+ *   bUpdateNvlinkPceLce [IN]
+ *     Whether PCE-LCE mappings need to be updated for nvlink topology.
+ *     If this is NV_FALSE, RM would ignore the above values.  However,
+ *     PCE-LCE mappings will still be updated if there were any regkey
+ *     overrides.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_GENERIC
+ */
+#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS {
+    NvU32  pceLceMap[NV2080_CTRL_MAX_PCES];
+    NvU32  grceConfig[NV2080_CTRL_MAX_GRCES];
+    NvU32  exposeCeMask;
+    NvBool bUpdateNvlinkPceLce;
+} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS;
+
+#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE      0xf
+
+/*
+ * NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB
+ *
+ * This function triggers an update of the exported CE classes.  CEs with
+ * no physical resources will not be exported.  A record of these
+ * will be return in in the stubbedCeMask.
+ *
+ * An example if NV2080_ENGINE_TYPE_COPY4 is stubbed (1<<4) will be
+ * set in stubbedCeMask.
+ *
+ * This function operates on all CE shims.
+ */
+#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS {
+    NvU32 stubbedCeMask;
+} NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS
+ *
+ * Query _CE_GRCE, _CE_SHARED, _CE_SUPPORTS_PIPELINED_BL, _CE_SUPPORTS_NONPIPELINED_BL bits of CE
+ * capabilities.
+ *
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0x7U)
+
+typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS;
+
+#define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS {
+    NvU32 size;
+} NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS;
+
+#define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASKS
+ *
+ * Get HSHUB and FBHUB PCE masks.
+ *
+ *   [out] hshubPceMasks
+ *     PCE mask for each HSHUB
+ *   [out] fbhubPceMask
+ *     FBHUB PCE mask
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK             (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_MAX_HSHUBS                       32
+
+#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS {
+    NvU32 hshubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS];
+    NvU32 fbhubPceMask;
+} NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_ALL_CAPS
+ *
+ * Query caps of all CEs.
+ *
+ *   [out] capsTbl
+ *     Array of CE caps in the order of CEs. The caps bits interpretation is the same as in
+ *     NV2080_CTRL_CMD_CE_GET_CAPS.
+ *   [out] present
+ *     Bit mask indicating which CEs are usable by the client and have their caps indicated in capsTbl.
+ *     If a CE is not marked present, its caps bits should be ignored.
+ *     If client is subscribed to a MIG instance, only the CEs present in the instance are tagged as such.
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MAX_CES             64
+
+#define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU)
+
+typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
+    NvU8 capsTbl[NV2080_CTRL_MAX_CES][NV2080_CTRL_CE_CAPS_TBL_SIZE];
+    NV_DECLARE_ALIGNED(NvU64 present, 8);
+} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS;
+
+#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0xbU)
+
+typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO
+ *
+ * This command queries LCE shim information of a specified CE.
+ * The information includes the shim instance the CE belongs to.
+ * And the local LCE within the shim.
+ *
+ *   [in] ceEngineType
+ *     This parameter specifies the copy engine type, NV2080 define
+ *   [out] shimInstance
+ *     The shim instance the ceEngineType belongs to.
+ *   [out] shimLocalLceIdx
+ *     The local LCE index within the shim
+ *
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO (0x20802a0c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID (0xcU)
+
+typedef struct NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS {
+    NvU32 ceEngineType;
+    NvU32 shimInstance;
+    NvU32 shimLocalLceIdx;
+} NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS;
+
+/*
+ * This command is identical to NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS
+ * but supports more than one CE shim.
+ *
+ * This command updates the PCE-LCE mappings for one CE shim.  On
+ * GPUs with multiple CE shims, this interface must be called for
+ * each shim.
+ *
+ *   shimInstance [IN]
+ *     Specify which CE shim instance to operate on.
+ */
+
+#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2 (0x20802a0d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID (0xdU)
+
+typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS {
+    NvU32  pceLceMap[NV2080_CTRL_MAX_PCES];
+    NvU32  grceConfig[NV2080_CTRL_MAX_GRCES];
+    NvU32  exposeCeMask;
+    NvBool bUpdateNvlinkPceLce;
+    NvU32  shimInstance;
+} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS;
+
+/*
+ * This command is identical to NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_PARAMS
+ * but supports more than one CE shim.
+ *
+ * This command gets HSHUB/CEHUB and FBHUB PCE Mask.  On
+ * GPUs with multiple CE shims, this interface must be called for
+ * each shim.
+ *
+ *   [in] shimInstance
+ *     Specify which CE shim instance to operate on.
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2 (0x20802a0e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID (0xeU)
+
+typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS {
+    NvU32 connectingHubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS];
+    NvU32 fbhubPceMask;
+    NvU32 shimInstance;
+} NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS;
+
+typedef enum NV2080_CTRL_CE_LCE_TYPE {
+    NV2080_CTRL_CE_LCE_TYPE_PCIE = 1,
+    NV2080_CTRL_CE_LCE_TYPE_DECOMP = 2,
+    NV2080_CTRL_CE_LCE_TYPE_SCRUB = 3,
+    NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = 4,
+    NV2080_CTRL_CE_LCE_TYPE_C2C = 5,
+    NV2080_CTRL_CE_LCE_TYPE_PCIE_RD = 6,
+    NV2080_CTRL_CE_LCE_TYPE_PCIE_WR = 7,
+    NV2080_CTRL_CE_LCE_TYPE_C2C_H2D = 8,
+    NV2080_CTRL_CE_LCE_TYPE_C2C_D2H = 9,
+    NV2080_CTRL_CE_LCE_TYPE_CC_WORK_SUBMIT = 10,
+} NV2080_CTRL_CE_LCE_TYPE;
+
+typedef enum NV2080_CTRL_CE_SHIM_PREFERENCE {
+    NV2080_CTRL_CE_SHIM_PREFERENCE_SAME_SHIM = 1,
+    NV2080_CTRL_CE_SHIM_PREFERENCE_DIFFERENT_SHIM = 2,
+} NV2080_CTRL_CE_SHIM_PREFERENCE;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE
+ *
+ * This command queries the PCE config required for the specified LCE type.
+ *
+ *  [in] lceType
+ *      LCE type. Should be one of NV2080_CTRL_CE_LCE_TYPE_* values.
+ *  [in] metadataForLceType
+ *      Metadata for LCE type.
+ *  [out] numPces
+ *      Number of PCEs supported per LCE
+ *  [out] numLces
+ *      Maximum number of LCEs supported by the chip for the specified LCE type.
+ *  [out] supportedPceMask
+ *      The mask of the PCEs that support the specified LCE type.
+ *  [out] supportedLceMask
+ *      The mask of the LCEs that support the specified LCE type.
+ *  [out] pcePerHshub
+ *      Numbers of PCEs from any given HSHUB that can be assigned to this LCE type.
+ *  [out] multipleLceShimPreference
+ *      Shim selection preference in case there are multiple LCEs
+ *
+ *  @return NV_OK
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE (0x20802a0f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID (0xfU)
+
+typedef struct NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS {
+    NV2080_CTRL_CE_LCE_TYPE        lceType;
+    NvU32                          metadataForLceType;
+    NvU32                          numPces;
+    NvU32                          numLces;
+    NvU32                          supportedPceMask;
+    NvU32                          supportedLceMask;
+    NvU32                          pcePerHshub;
+    NV2080_CTRL_CE_SHIM_PREFERENCE multipleLceShimPreference;
+} NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK
+ *
+ * This command gets the mask of LCEs that are enabled for decomp workloads.
+ * On GPUs with multiple CE shims, this interface must be called for
+ * each shim.
+ *
+ *   [in] shimInstance
+ *     Specify which CE shim instance to operate on.
+ *   [out] decompLceMask
+ *     Returns a 64-bit mask of which LCEs in given shim are marked as decomp CEs
+ */
+
+#define NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK (0x20802a11) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 decompLceMask, 8);
+    NvU32 shimInstance;
+} NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED
+ *
+ * This command returns whether a given global LCE index is enabled for decomp workloads.
+ * It has to be given a global LCE index (cannot support shim local LCE ID)
+ *
+ *   [in]  lceIndex
+ *   [out] bDecompEnabled
+ *     Returns NV_TRUE if LCE is enabled for decompression, else returns NV_FALSE
+ */
+
+#define NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED (0x20802a12) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS {
+    NvU32  lceIndex;
+    NvBool bDecompEnabled;
+} NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE
+ *
+ * This command queries the PCE config required for the specified MIG GPU Instance.
+ * Mappings will prioritize utilizing 1 LCE each for sysmem read and write if available
+ * and ensure maximum number of PCEs are allocated for those LCEs to allow maximum bandwidth.
+ *
+ * [in] lceMask
+ *    Mask of LCEs which are being requested
+ * [in] numLCEs
+ *    Number of LCEs available for this GPU Instance
+ * [out] pceAvailableMask
+ *    Mask of PCEs which are available for this specific LCE mask given
+ * [out] numLcesToMap
+ *    Number of LCEs to map based on total num LCEs given
+ * [out] lceAvailableMask
+ *    Mask of LCEs which should be mapped for this GPU Instance based on num LCEs given
+ * [out] numMinPcesPerLce
+ *    Number of PCEs to be mapped for each LCE
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE (0x20802a13) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS {
+    NvU32 lceMask;
+    NvU32 numLces;
+    NvU32 pceAvailableMask;
+    NvU32 numLcesToMap;
+    NvU32 lceAvailableMask;
+    NvU32 numMinPcesPerLce;
+} NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS;
+
+/*
+ * NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS
+ *
+ * Apply CE Mappings for MIG GPU Instance
+ *
+ * [in] pceLceMap
+ *    Array of mappings indexed by PCE
+ * [in] lceAvailableMask
+ *    Mask of LCEs available to this MIG GPU Instance
+ */
+
+#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS (0x20802a14) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS {
+    NvU32 pceLceMap[NV2080_CTRL_MAX_PCES];
+    NvU32 lceAvailableMask;
+    NvU32 shimInstance;
+} NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS;
+
+/* _ctrl2080ce_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080cipher.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080cipher.h
new file mode 100644
index 0000000..b46acf7
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080cipher.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080cipher.finn
+//
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clk.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clk.h
new file mode 100644
index 0000000..deecc8e
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clk.h
@@ -0,0 +1,128 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080clk.finn
+//
+
+#include "nvfixedtypes.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080boardobj.h"
+#include "ctrl/ctrl2080/ctrl2080gpumon.h"
+#include "ctrl/ctrl2080/ctrl2080clkavfs.h"
+#include "ctrl/ctrl2080/ctrl2080volt.h"
+#include "ctrl/ctrl2080/ctrl2080pmumon.h"
+
+#define NV2080_CTRL_CLK_DOMAIN_TEGRA_UNDEFINED             (0x00000000U)
+#define NV2080_CTRL_CLK_DOMAIN_TEGRA_GPCCLK                (0x00000001U)
+#define NV2080_CTRL_CLK_DOMAIN_TEGRA_NVDCLK                (0x00000002U)
+
+
+
+/*!
+ * NV2080_CTRL_CMD_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES
+ *
+ * Control call to query the samples within the PWR_CHANNELS PMUMON queue.
+ */
+#define NV2080_CTRL_CMD_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES (0x20801037) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CLK_INTERFACE_ID << 8) | NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS_MESSAGE_ID" */
+
+/*!
+ * @brief   With sample period being potentially as fast every 20ms, this gives
+ *          us 5 seconds worth of data.
+ */
+#define NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_COUNT    (250U)
+
+/*!
+ * Temporary until an INFO control call is stubbed out that exposes the supported
+ * feature set of the sampling.
+ */
+#define NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_INVALID  (NV_U32_MAX)
+
+/*!
+ * A single sample of the power channels at a particular point in time.
+ */
+typedef struct NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE {
+    /*!
+     * Ptimer timestamp of when this data was collected.
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_PMUMON_SAMPLE super, 8);
+
+    /*!
+     * Point sampled programmed GPCCLK frequency in KHz.
+     *
+     * NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_INVALID if not supported.
+     */
+    NvU32 gpcClkFreqKHz;
+
+    /*!
+     * Point sampled programmed DRAMCLK frequency in KHz.
+     *
+     * NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_INVALID if not supported.
+     */
+    NvU32 dramClkFreqKHz;
+
+    /*!
+     * Point sampled programmed NVDCLK frequency in KHz.
+     *
+     * NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_INVALID if not supported.
+     */
+    NvU32 nvdClkFreqKHz;
+
+    /*!
+     * Point sampled programmed active GPCCLK frequency in KHz.
+     *
+     * NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_INVALID if not supported.
+     */
+    NvU32 activeGpcClkFreqKHz;
+} NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE;
+typedef struct NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE *PNV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE;
+
+/*!
+ * Input/Output parameters for @ref NV2080_CTRL_CMD_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES
+ */
+#define NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS_MESSAGE_ID (0x37U)
+
+typedef struct NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS {
+    /*!
+     * [in/out] Meta-data for the samples[] below. Will be modified by the
+     *          control call on caller's behalf and should be passed back in
+     *          un-modified for subsequent calls.
+     */
+    NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER super;
+
+    /*!
+     * [out] Between the last call and current call, samples[0...super.numSamples-1]
+     *       have been published to the pmumon queue. Samples are copied into
+     *       this buffer in chronological order. Indexes within this buffer do
+     *       not represent indexes of samples in the actual PMUMON queue.
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE samples[NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_COUNT], 8);
+} NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS;
+typedef struct NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS *PNV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS;
+
+/* _ctrl2080clk_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clkavfs.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clkavfs.h
new file mode 100644
index 0000000..2d339fa
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clkavfs.h
@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080clkavfs.finn
+//
+
+
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080boardobj.h"
+#include "ctrl/ctrl2080/ctrl2080volt.h"
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dma.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dma.h
new file mode 100644
index 0000000..4a380d1
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dma.h
@@ -0,0 +1,180 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080dma.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX dma control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_DMA_INVALIDATE_TLB
+ *
+ * This command invalidates the GPU TLB. This is intended to be used
+ * by RM clients that manage their own TLB consistency when updating
+ * page tables on their own, or with DEFER_TLB_INVALIDATION options
+ * to other RM APIs.
+ *
+ *    hVASpace
+ *       This parameter specifies the VASpace object whose MMU TLB entries needs to be invalidated.
+ *       Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace.
+ *       Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC.
+ *
+ * This call can be used with the NV50_DEFERRED_API_CLASS (class 0x5080).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_TIMEOUT_RETRY
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_DMA_INVALIDATE_TLB (0x20802502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS {
+    NvHandle hClient; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
+    NvHandle hDevice; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
+    NvU32    engine;  // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
+    NvHandle hVASpace;
+} NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS;
+
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS             0:0
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE    (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE     (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO                1:1
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE       (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE        (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY              2:2
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE     (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE      (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE              3:3
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE     (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE      (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB                  4:4
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE         (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE          (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV                   5:5
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE          (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE           (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG                 6:6
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE        (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE         (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD                  7:7
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE         (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE          (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION           8:8
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE  (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE   (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON              9:9
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE     (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE      (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS          10:10
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE  (0x00000001)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR                  11:11
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE         (0x00000000)
+#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE          (0x00000001)
+
+/*
+ * NV2080_CTRL_DMA_INFO
+ *
+ * This structure represents a single 32bit dma engine value.  Clients
+ * request a particular DMA engine value by specifying a unique dma
+ * information index.
+ *
+ * Legal dma information index values are:
+ *   NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
+ *     This index can be used to request the system address size in bits.
+ */
+typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_DMA_INFO;
+
+/* valid dma info index values */
+#define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000)
+
+/* set INDEX_MAX to greatest possible index value */
+#define NV2080_CTRL_DMA_INFO_INDEX_MAX                 NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
+
+/*
+ * NV2080_CTRL_CMD_DMA_GET_INFO
+ *
+ * This command returns dma engine information for the associated GPU.
+ * Requests to retrieve dma information use an array of one or more
+ * NV2080_CTRL_DMA_INFO structures.
+ *
+ *   dmaInfoTblSize
+ *     This field specifies the number of valid entries in the dmaInfoList
+ *     array.  This value cannot exceed NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES.
+ *   dmaInfoTbl
+ *     This parameter contains the client's dma info table into
+ *     which the dma info values will be transferred by the RM.
+ *     The dma info table is an array of NV2080_CTRL_DMA_INFO structures.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_DMA_GET_INFO                   (0x20802503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum number of NV2080_CTRL_DMA_INFO entries per request */
+#define NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES           (256)
+
+#define NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_DMA_GET_INFO_PARAMS {
+    NvU32                dmaInfoTblSize;
+    /*
+     * C form:
+     * NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES];
+     */
+    NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES];
+} NV2080_CTRL_DMA_GET_INFO_PARAMS;
+
+typedef struct NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO {
+    /*! 
+     * 64KB aligned address of source 64KB tile for comptag reswizzle.
+     */
+    NvU32 srcAddr;
+
+    /*! 
+     * 64KB aligned address of destination 64KB tile for comptag reswizzle.
+     */
+    NvU32 dstAddr;
+
+    /*!
+     * Comptag index assigned to the 64K sized tile relative to
+     * the compcacheline. Absolute comptag index would be:
+     * startComptagIndex + relComptagIndex.
+     */
+    NvU16 relComptagIndex;
+} NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO;
+
+// _ctrl2080dma_h_
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dmabuf.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dmabuf.h
new file mode 100644
index 0000000..34fa680
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dmabuf.h
@@ -0,0 +1,127 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080dmabuf.finn
+//
+
+
+
+/*
+ * NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD
+ *
+ * Exports RM vidmem and sysmem handles to a dma-buf fd.
+ *
+ * The objects in the 'handles' array are exported to the fd as range:
+ * [index, index + numObjects).
+ *
+ * A dma-buf fd is created the first time this control call is called.
+ * The fd is an input parameter for subsequent calls to attach additional handles
+ * over NV2080_CTRL_DMABUF_MAX_HANDLES.
+ *
+ * fd
+ *   A dma-buf file descriptor. If -1, a new FD will be created.
+ *
+ * totalObjects
+ *   The total number of objects that the client wishes to export to the FD.
+ *   This parameter will be honored only when the FD is getting created.
+ *
+ * numObjects
+ *   The number of handles the user wishes to export in this call.
+ *
+ * index
+ *   The index into the export fd at which to start exporting the handles in
+ *   'handles'. This index cannot overlap a previously used index.
+ *
+ * totalSize
+ *   The total size of memory being exported in bytes, needed to create the dma-buf.
+ *   This size includes the memory that will be exported in future export calls
+ *   for this dma-buf.
+ *
+ * mappingType
+ *   The type of mapping that must be used for this dma-buf.
+ *   See NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_* for all possible values.
+ *
+ *   With type DEFAULT, the driver shall decide the type based on platform coherency:
+ *       C2C for coherent
+ *       PCIe BAR1 for non-coherent
+ *   Type FORCE_PCIE field is a workaround for platforms with Grace (PCIe Gen4/Gen5 RPs) paired with
+ *   Gen6 parts like Blackwell GPUs and CX8 NICs, requiring a separate Gen6 PCIe link to maximize RDMA
+ *   bandwidth. This type allows dma-buf to be mapped over this Gen6 PCIe link.
+ *
+ *   This call shall return NV_ERR_NOT_SUPPORTED if FORCE_PCIE type is used on non-Grace platforms.
+ *
+ * bAllowMmap
+ *   mmap support is allowed or not for the specific dmabuf based fd. User can control it.
+ *   That way user can enable mmap for testing/specific use cases and not for any all handles.
+ *
+ * handles
+ *   An array of {handle, offset, size} that describes the dma-buf.
+ *   The offsets and sizes must be OS page-size aligned.
+ *
+ * Limitations:
+ *   1. This call supports vidmem and sysmem objects.
+ *   2. All memory handles should belong to the same GPU or the same GPU MIG instance.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_NOT_SUPPORTED
+ *    NV_ERR_NO_MEMORY
+ *    NV_ERR_OPERATING_SYSTEM
+ *    NV_ERR_IN_USE
+ *    NV_ERR_INVALID_OBJECT
+ *    NV_ERR_INVALID_OBJECT_PARENT
+ */
+#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD       (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_DMABUF_MAX_HANDLES                    128
+
+#define NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT    (0x00000000U)
+#define NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE (0x00000001U)
+
+typedef struct NV2080_CTRL_DMABUF_MEM_HANDLE_INFO {
+    NvHandle hMemory;
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+} NV2080_CTRL_DMABUF_MEM_HANDLE_INFO;
+
+#define NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS {
+    NvS32  fd;
+    NvU32  totalObjects;
+    NvU32  numObjects;
+    NvU32  index;
+    NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
+    NvU8   mappingType;
+    NvBool bAllowMmap;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_DMABUF_MEM_HANDLE_INFO handles[NV2080_CTRL_DMABUF_MAX_HANDLES], 8);
+} NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS;
+
+// _ctrl2080dmabuf_h_
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ecc.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ecc.h
new file mode 100644
index 0000000..85b3599
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ecc.h
@@ -0,0 +1,256 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080ecc.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+
+
+#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS
+ *
+ * sramParityUncorrectedUnique  [out]
+ * sramSecDedUncorrectedUnique  [out]
+ * sramCorrectedUnique          [out]
+ * dramUncorrectedTotal         [out]
+ * dramCorrectedTotal           [out]
+ *      Aggregate error counts for SRAM and DRAM.
+ *
+ * lastClearedTimestamp         [out]
+ *      unix-epoch based timestamp. These fields indicate when the error counters
+ *      were last cleared by the user.
+ *
+ * sramBucketL2                 [out]
+ * sramBucketSM                 [out]
+ * sramBucketPcie               [out]
+ * sramBucketFirmware           [out]
+ * sramBucketOther              [out]
+ *      Aggregate unique uncorrctable error counts for SRAM buckets.
+ *
+ * sramErrorThresholdExceeded   [out]
+ *      Boolean flag which is set if SRAM error threshold was exceeded
+ */
+
+#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U)
+
+typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 sramParityUncorrectedUnique, 8);
+    NV_DECLARE_ALIGNED(NvU64 sramSecDedUncorrectedUnique, 8);
+    NV_DECLARE_ALIGNED(NvU64 sramCorrectedUnique, 8);
+    NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotal, 8);
+    NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotal, 8);
+
+    NvU32  lastClearedTimestamp;
+
+    NV_DECLARE_ALIGNED(NvU64 sramBucketL2, 8);
+    NV_DECLARE_ALIGNED(NvU64 sramBucketSM, 8);
+    NV_DECLARE_ALIGNED(NvU64 sramBucketPcie, 8);
+    NV_DECLARE_ALIGNED(NvU64 sramBucketFirmware, 8);
+    NV_DECLARE_ALIGNED(NvU64 sramBucketOther, 8);
+
+    NvBool sramErrorThresholdExceeded;
+} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS;
+
+/*
+ * NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS
+ *
+ * Reports count of volatile errors
+ *
+ * sramCorUni                   [out]:
+ *      Unique correctable SRAM error count
+ * sramUncParityUni             [out]:
+ *      Unique uncorrectable SRAM parity error count
+ * sramUncSecDedUni             [out]:
+ *      Unique uncorrectable SRAM SEC-DED error count
+ * dramCorTot                   [out]:
+ *      Total correctable DRAM error count
+ * dramUncTot                   [out]:
+ *      total uncorrectable DRAM error count
+ */
+#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 sramCorUni, 8);
+    NV_DECLARE_ALIGNED(NvU64 sramUncParityUni, 8);
+    NV_DECLARE_ALIGNED(NvU64 sramUncSecDedUni, 8);
+    NV_DECLARE_ALIGNED(NvU64 dramCorTot, 8);
+    NV_DECLARE_ALIGNED(NvU64 dramUncTot, 8);
+} NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS;
+
+typedef struct eccLocation {
+    NvU32 location;
+    NvU32 sublocation;
+    NvU32 extlocation;
+} eccLocation;
+
+/*
+ * NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY
+ *
+ * unit
+ *   The unit the error occurred in
+ * location
+ *   The location info for the error
+ * address
+ *   The address of the error
+ * bIsParity
+ *   True if error is parity error, false if error is SEC-DED error
+ * count
+ *   The number of uncorrectable unique error counts that occurred
+ */
+
+typedef struct NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY {
+    NvU32       unit;
+    eccLocation location;
+    NvU32       address;
+    NvBool      bIsParity;
+    NvU32       count;
+} NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY;
+
+/*
+ * NV2080_CTRL_CMD_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS
+ *
+ * This command is used to query the ECC inforom object and determine the number
+ * of unique uncorrectable error counts that occurred at an address.
+ *
+ *   entryCount
+ *     The number of entries
+ *
+ *   entries
+ *     The array of NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY
+ */
+
+#define NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_MAX_COUNT 600
+
+#define NV2080_CTRL_CMD_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS   (0x20803402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS {
+    NvU32                                           entryCount;
+    NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY entries[NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_MAX_COUNT];
+} NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS;
+
+#define NV2080_CTRL_ECC_ERROR_TYPE_CORRECTED    0
+#define NV2080_CTRL_ECC_ERROR_TYPE_UNCORRECTED  1
+
+
+
+/*
+ * NV2080_CTRL_CMD_ECC_INJECT_ERROR
+ *
+ * This command is used to inject ECC errors.
+ *
+ *   unit
+ *     The ECC unit
+ *
+ *   errorType
+ *     The type of error to be injected
+ *
+ *   location
+ *     The location within the ECC unit to be injected
+ *
+ *   flags
+ *     Specific injection flags
+ *
+ *   address
+ *     Specific injection address for DRAM
+ */
+#define NV2080_CTRL_CMD_ECC_INJECT_ERROR                         (0x20803403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_ECC_INJECT_ERROR_PARAMS {
+    NvU32       unit;
+    NvU8        errorType;
+    eccLocation location;
+    NvU32       flags;
+    NV_DECLARE_ALIGNED(NvU64 address, 8);
+} NV2080_CTRL_ECC_INJECT_ERROR_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_ECC_GET_REPAIR_STATUS
+ *
+ * This command is used to query the status of TPC/Channel repair
+ *
+ * bTpcRepairPending
+ *   Boolean indicating if TPC repair is pending
+ * bChannelRepairPending
+ *   Boolean indicating if Channel repair is pending
+ */
+
+#define NV2080_CTRL_CMD_ECC_GET_REPAIR_STATUS (0x20803404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS {
+    NvBool bTpcRepairPending;
+    NvBool bChannelRepairPending;
+} NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_ECC_INJECTION_SUPPORTED
+ *
+ * Determines if error injection is supported for a given HW unit
+ *
+ * unit [in]:
+ *      The ECC protected unit for which ECC injection support is being checked
+ *
+ * bCorrectableSupported [out]:
+ *      Boolean value that shows if correcatable errors can be injected
+ *
+ * bUncorrectableSupported [out]:
+ *      Boolean value that shows if uncorrecatable errors can be injected
+*/
+
+#define NV2080_CTRL_CMD_ECC_INJECTION_SUPPORTED (0x20803405) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS {
+    NvU32       unit;
+    eccLocation location;
+    NvBool      bCorrectableSupported;
+    NvBool      bUncorrectableSupported;
+} NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS;
+
+#define NV2080_CTRL_CMD_ECC_GET_UNREPAIRABLE_MEMORY_FLAG (0x20803406) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS {
+    NvBool bUnrepairableMemory;
+} NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS;
+
+/* _ctrl2080ecc_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080event.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080event.h
new file mode 100644
index 0000000..a496ce2
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080event.h
@@ -0,0 +1,396 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080event.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+#include "nv_vgpu_types.h"
+/* NV20_SUBDEVICE_XX event-related control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION
+ *
+ * This command sets event notification state for the associated subdevice.
+ * This command requires that an instance of NV01_EVENT has been previously
+ * bound to the associated subdevice object.
+ *
+ *   event
+ *     This parameter specifies the type of event to which the specified
+ *     action is to be applied.  This parameter must specify a valid
+ *     NV2080_NOTIFIERS value (see cl2080.h for more details) and should
+ *     not exceed one less NV2080_NOTIFIERS_MAXCOUNT.
+ *   action
+ *     This parameter specifies the desired event notification action.
+ *     Valid notification actions include:
+ *       NV2080_CTRL_SET_EVENT_NOTIFICATION_DISABLE
+ *         This action disables event notification for the specified
+ *         event for the associated subdevice object.
+ *       NV2080_CTRL_SET_EVENT_NOTIFICATION_SINGLE
+ *         This action enables single-shot event notification for the
+ *         specified event for the associated subdevice object.
+ *       NV2080_CTRL_SET_EVENT_NOTIFICATION_REPEAT
+ *         This action enables repeated event notification for the specified
+ *         event for the associated system controller object.
+ *    bNotifyState
+ *      This boolean is used to indicate the current state of the notifier
+ *      at the time of event registration. This is optional and its semantics
+ *      needs to be agreed upon by the notifier and client using the notifier
+ *    info32
+ *      This is used to send 32-bit initial state info with the notifier at
+ *      time of event registration
+ *    info16
+ *      This is used to send 16-bit initial state info with the notifier at
+ *      time of event registration
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION (0x20800301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
+    NvU32  event;
+    NvU32  action;
+    NvBool bNotifyState;
+    NvU32  info32;
+    NvU16  info16;
+} NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
+
+/* valid action values */
+#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
+#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE  (0x00000001)
+#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT  (0x00000002)
+
+/* XUSB/PPC D-state defines */
+#define NV2080_EVENT_DSTATE_XUSB_D0                       (0x00000000)
+#define NV2080_EVENT_DSTATE_XUSB_D3                       (0x00000003)
+#define NV2080_EVENT_DSTATE_XUSB_INVALID                  (0xFFFFFFFF)
+#define NV2080_EVENT_DSTATE_PPC_D0                        (0x00000000)
+#define NV2080_EVENT_DSTATE_PPC_D3                        (0x00000003)
+#define NV2080_EVENT_DSTATE_PPC_INVALID                   (0xFFFFFFFF)
+
+// HDACODEC Decice DState, D3_COLD is only for verbose mapping, it cannot be logged
+typedef enum NV2080_EVENT_HDACODEC_DSTATE {
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = 0,
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = 1,
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = 2,
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = 3,
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = 4,
+    NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = 5,
+} NV2080_EVENT_HDACODEC_DSTATE;
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_TRIGGER
+ *
+ * This command triggers a software event for the associated subdevice.
+ * This command accepts no parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER         (0x20800302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | 0x2" */
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
+ *
+ *     hMemory
+ *       This parameter specifies the handle of the memory object
+ *       that identifies the memory address translation for this
+ *       subdevice instance's notification(s).  The beginning of the
+ *       translation points to an array of notification data structures.
+ *       The size of the translation must be at least large enough to hold the
+ *       maximum number of notification data structures identified by
+ *       the NV2080_MAX_NOTIFIERS value.
+ *       Legal argument values must be instances of the following classes:
+ *         NV01_NULL
+ *         NV04_MEMORY
+ *       When hMemory specifies the NV01_NULL_OBJECT value then any existing
+ *       memory translation connection is cleared.  There must not be any
+ *       pending notifications when this command is issued.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x20800303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
+    NvHandle hMemory;
+} NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
+
+#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0
+#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING  1
+#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR    2
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY
+ *
+ *     hSemMemory
+ *       This parameter specifies the handle of the memory object that
+ *       identifies the semaphore memory associated with this subdevice
+ *       event notification.  Once this is set RM will generate an event
+ *       only when there is a change in the semaphore value.  It is
+ *       expected that the semaphore memory value will be updated by
+ *       the GPU indicating that there is an event pending. This
+ *       command is used by VGX plugin to determine which virtual
+ *       machine has generated a particular event.
+ *
+ *     semOffset
+ *       This parameter indicates the memory offset of the semaphore.
+ *
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_PARAM_STRUCT
+ *      NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY   (0x20800304) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS {
+    NvHandle hSemMemory;
+    NvU32    semOffset;
+} NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI
+ *
+ *     hSemMemory
+ *       This parameter specifies the handle of the memory object that
+ *       identifies the semaphore memory associated with this subdevice
+ *       event notification.  Once this is set RM will generate an event
+ *       only when there is a change in the semaphore value.  It is
+ *       expected that the semaphore memory value will be updated by
+ *       the GPU indicating that there is an event pending. This
+ *       command is used by VGX plugin to determine which virtual
+ *       machine has generated a particular event.
+ *
+ *     guestMSIAddr
+ *       This parameter indicates the guest allocated MSI address.
+ *
+ *     guestMSIData
+ *       This parameter indicates the MSI data set by the guest OS.
+ *
+ *     vgpuUuid
+ *       This parameter specifies the uuid of vGPU assigned to VM.
+ *
+ *     domainId
+ *       This parameter specifies the unique guest virtual machine identifier
+ *
+ * Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_PARAM_STRUCT
+ *      NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI (0x20800305) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 guestMSIAddr, 8);
+    NvU32    guestMSIData;
+    NvHandle hSemMemory;
+    NvBool   isReset;
+    NvU8     vgpuUuid[VM_UUID_SIZE];
+    NV_DECLARE_ALIGNED(NvU64 domainId, 8);
+} NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION
+ *
+ *     hSemMemory
+ *       This parameter specifies the handle of the memory object that
+ *       identifies the semaphore memory associated with this subdevice
+ *       event notification.  Once this is set RM will generate an event
+ *       only when there is a change in the semaphore value.  It is
+ *       expected that the semaphore memory value will be updated by
+ *       the GPU indicating that there is an event pending. This
+ *       command is used by VGX plugin to determine which virtual
+ *       machine has generated a particular event.
+ *
+ *     isSemaMemValidationEnabled
+ *       This parameter used to enable/disable change in sema value check
+ *       while generating an event.
+ *
+ * Possible status values returned are:
+ *      NVOS_STATUS_SUCCESS
+ *      NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE
+ *      NVOS_STATUS_ERROR_INVALID_ARGUMENT
+ */
+
+
+#define NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION (0x20800306) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS {
+    NvHandle hSemMemory;
+    NvBool   isSemaMemValidationEnabled;
+} NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO
+ *
+ * This command triggers a FIFO event for the associated subdevice.
+ *
+ *  hEvent
+ *    Handle of the event that should be notified. If zero, all
+ *    non-stall interrupt events for this subdevice will be notified.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO (0x20800308) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS {
+    NvHandle hEvent;
+} NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF_FOR_UID
+ *
+ * This command is used to create a video bind-point to an event buffer that
+ * is filtered by UID.
+ *
+ *  hEventBuffer[IN]
+ *      The event buffer to bind to
+ *
+ *  recordSize[IN]
+ *      The size of the FECS record in bytes
+ *
+ *  levelOfDetail[IN]
+ *      One of NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_:
+ *          FULL: Report all CtxSw events
+ *          SIMPLE: Report engine start and engine end events only
+ *          CUSTOM: Report events in the eventFilter field
+ *      NOTE: RM may override the level-of-detail depending on the caller
+ *
+ *  eventFilter[IN]
+ *      Bitmask of events to report if levelOfDetail is CUSTOM
+ *
+ *  bAllUsers[IN]
+ *     Only report video data for the current user if false, for all users if true
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF (0x20800309) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD {
+    NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = 0,
+    NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = 1,
+    NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = 2,
+} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD;
+
+#define NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS {
+    NvHandle                                hEventBuffer;
+    NvU32                                   recordSize;
+    NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD levelOfDetail;
+    NvU32                                   eventFilter;
+    NvBool                                  bAllUsers;
+} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_FOR_UID
+ *
+ * This command is used to create a RATS tracing bindpoint to eventbuffer.
+ *
+ *  hEventBuffer[IN]
+ *      The event buffer to bind to
+ *
+ *  tracepointMask[IN]
+ *      Bitmask for selecting tracepoints
+ *
+ *  gspLoggingBufferSize[IN]
+ *      User defined size of GSP owned event logging buffer
+ *
+ *  gspLoggingBufferWatermark[IN]
+ *      User defined watermark that triggers RPC to kernel of traces
+ *      HINT: set higher for more frequent trace updates
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF (0x2080030a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS {
+    NvHandle hEventBuffer;
+    NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8);
+    NvU32    gspLoggingBufferSize;
+    NvU32    gspLoggingBufferWatermark;
+} NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS;
+
+ /*
+  * NV2080_CTRL_CMD_EVENT_NOCAT_BIND_EVTBUF
+  *
+  * This command is used to create a NOCAT bind-point to an event buffer.
+  *
+  *  hEventBuffer[IN]
+  *      The event buffer to bind to
+  *
+  * Possible status values returned are:
+  *   NV_OK
+  *   NV_ERR_INVALID_ARGUMENT
+  *   NV_ERR_NOT_SUPPORTED
+  */
+#define NV2080_CTRL_CMD_EVENT_NOCAT_BIND_EVTBUF (0x2080030b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS {
+    NvHandle hEventBuffer;
+} NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS;
+
+
+
+/* _ctrl2080event_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fan.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fan.h
new file mode 100644
index 0000000..1221171
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fan.h
@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080fan.finn
+//
+
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fb.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fb.h
new file mode 100644
index 0000000..06653bd
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fb.h
@@ -0,0 +1,3093 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080fb.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX fb control commands and parameters */
+
+#include "nvlimits.h"
+#include "nvcfg_sdk.h"
+
+/*
+ * NV2080_CTRL_FB_INFO
+ *
+ * This structure represents a single 32bit fb engine value.  Clients
+ * request a particular fb engine value by specifying a unique fb
+ * information index.
+ *
+ * Legal fb information index values are:
+ *   NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT
+ *     This index is used to request the number of tiled regions supported
+ *     by the associated subdevice.  The return value is GPU
+ *     implementation-dependent.  A return value of 0 indicates the GPU
+ *     does not support tiling.
+ *   NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE
+ *     This index is used to request the amount of compression (in bytes)
+ *     supported by the associated subdevice.  The return value is GPU
+ *     implementation-dependent.  A return value of 0 indicates the GPU
+ *     does not support compression.
+ *   Nv2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE
+ *     This index is used to request the DRAM page stride (in bytes)
+ *     supported by the associated subdevice.  The return value is GPU
+ *     implementation-dependent.
+ *   NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT
+ *     This index is used to request the number of free tiled regions on
+ *     the associated subdevice.  The return value represents the current
+ *     number of free tiled regions at the time the command is processed and
+ *     is not guaranteed to remain unchanged.  A return value of 0 indicates
+ *     that there are no available tiled regions on the associated subdevice.
+ *   NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT
+ *     This index is used to request the number of frame buffer partitions
+ *     on the associated subdevice. Starting with Fermi there are now two units
+ *     with the name framebuffer partitions. On those chips this index returns
+ *     the number of FBPAs. For number of FBPs use
+ *     NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE
+ *     This index is used to request the amount of framebuffer memory in
+ *     kilobytes physically present on the associated subdevice.  This
+ *     value will never exceed the value reported by
+ *     NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE.
+ *     This an SMC aware attribute, so the per-partition framebuffer memory
+ *     size will be returned when the client has a partition subscription.
+ *   NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE
+ *     This index is used to request the total amount of video memory in
+ *     kilobytes for use with the associated subdevice.  This value will
+ *     reflect both framebuffer memory as well as any system memory dedicated
+ *     for use with the subdevice.
+ *     This an SMC aware attribute, so the per-partition video memory size
+ *     will be returned when the client has a partition subscription.
+ *   NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE
+ *     This index is used to request the amount of total RAM in kilobytes
+ *     available for user allocations.  This value reflects the total ram
+ *     size less the amount of memory reserved for internal use.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_HEAP_START
+ *     This index is used to request the offset for start of heap in
+ *     kilobytes.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE
+ *     This index is used to request the available amount of video memory in
+ *     kilobytes for use with the associated subdevice or the SMC partition.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required to query per partition information, if the device is partitioned.
+ *     Alternatively, the SMC/MIG monitor capability can be acquired to query
+ *     aggregate available memory across all the valid partitions.
+ *   NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE
+ *     This index reflects the amount of heap memory in kilobytes that
+ *     is accessible by the CPU.  On subdevices with video memory sizes that
+ *     exceed the amount that can be bus mappable this value will be less
+ *     than that reported by NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH
+ *     This index is used to request the FB bus bandwidth on the associated
+ *     subdevice.
+ *   NV2080_CTRL_FB_INFO_INDEX_RAM_CFG
+ *     This index is used to request the implementation-dependent RAM
+ *     configuration value of the associated subdevice.
+ *   NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE
+ *     This index is used to request the type of RAM used for the framebuffer
+ *     on the associated subdevice.  Legal RAM types include:
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4
+ *       NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5
+ *   NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT
+ *     This index is used to request the number of FB banks on the associated
+ *     subdevice.
+ *   NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT
+ *     This index is used to request the offset relative to the start of the
+ *     overlay surface(s), in bytes, at which scanout should happen if the
+ *     primary and the overlay surfaces are all aligned on large page
+ *     boundaries.
+ *   NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB
+ *     This index is used to request the size of the GPU's virtual address
+ *     space in kilobytes.
+ *   NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB
+ *     This index is used to request the size of the GPU's virtual address
+ *     space heap (minus RM-reserved space) in kilobytes.
+ *   NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB
+ *     This index is used to request the size of the GPU's BAR1 mappable
+ *     virtual address space in kilobytes.
+ *   NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW
+ *     This index is deprecated, and returns zero value.
+ *   NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK
+ *   NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0
+ *   NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1
+ *   NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_2
+ *   NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_3
+ *     This index is used to request the mask of currently active partitions.
+ *     Each active partition has an ID that's equivalent to the corresponding
+ *     bit position in the mask.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *     This value is moving from 32bits to 64bits, so PARTITION_MASK
+ *     (though kept for backwards compatibility on older chips), on newer chips
+ *     will be replaced by:
+ *     PARTITION_MASK_0 for the lower 32bits
+ *     PARTITION_MASK_1 for the next 32bits
+ *     PARTITION_MASK_2 for the next 32bits
+ *     PARTITION_MASK_3 for the upper 32bits
+ *     Note that PARTITION_MASK and PARTITION_MASK_0 are handled the same, and
+ *     use the same enum value.
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_MASK
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_2
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_3
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_4
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_5
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_6
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_7
+ *     This index is used to request the mask of currently active LTCs.
+ *     Each active LTC has an ID that's equivalent to the corresponding
+ *     bit position in the mask.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *     This value is moving from 32bits to 64bits, so LTC_MASK
+ *     (though kept for backwards compatibility on older chips), on newer chips
+ *     will be replaced by:
+ *     LTC_MASK_0 for the lower 32bits
+ *     LTC_MASK_1 for the next 32bits
+ *     LTC_MASK_2 for the next 32bits
+ *     LTC_MASK_3 for the next 32bits
+ *     LTC_MASK_4 for the next 32bits
+ *     LTC_MASK_5 for the next 32bits
+ *     LTC_MASK_6 for the next 32bits
+ *     LTC_MASK_7 for the upper 32bits
+ *     Note that LTC_MASK and LTC_MASK_0 are handled the same, and
+ *     use the same enum value.
+ *   NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE
+ *     This index is used to request the amount of total RAM in kilobytes
+ *     reserved for internal RM allocations on Vista.  This will need to
+ *     be subtracted from the total heap size to get the amount available to
+ *     KMD.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION
+ *     This index is used to distinguish between different memory
+ *     configurations.
+ *   NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN
+ *     This index is used to check if the FB is functional
+ *   NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT
+ *     This index is used to get the number of FBPs on the subdevice. This
+ *     field is not to be confused with
+ *     NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (returns number of FBPAs).
+ *     Starting with Fermi the term partition is an ambiguous term, both FBP
+ *     and FBPA mean FB partitions. The FBPA is the low level DRAM controller,
+ *     while a FBP is the aggregation of one or more FBPAs, L2, ROP, and some
+ *     other units.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE
+ *     This index is used to get the size of the L2 cache in Bytes.
+ *     A value of zero indicates that the L2 cache isn't supported on the
+ *     associated subdevice.
+ *   NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID
+ *     This index is used to get the memory vendor ID information from
+ *     the Memory Information Table in the VBIOS.  Legal memory Vendor ID
+ *     values include:
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_RESERVED
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT
+ *       NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON
+ *   NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE
+ *     This index is used to request the amount of unused bar1 space. The
+ *     data returned is a value in KB. It is not guaranteed to be entirely
+ *     accurate since it is a snapshot at a particular time and can
+ *     change quickly.
+ *   NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE
+ *     This index is used to request the amount of largest unused contiguous
+ *     block in bar1 space.  The data returned is a value in KB. It is not
+ *     guaranteed to be entirely accurate since it is a snapshot at a particular
+ *     time and can change quickly.
+ *   NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE
+ *     This index is used to request the amount of usable framebuffer memory in
+ *     kilobytes physically present on the associated subdevice.  This
+ *     value will never exceed the value reported by
+ *     NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT
+ *     Returns the active LTC count across all active FBPs.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT
+ *     Returns the active LTS count across all active LTCs.
+ *     This an SMC aware attribute, thus necessary partition subscription is
+ *     required if the device is partitioned.
+ *   NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE
+ *     This is used to identify if pseudo-channel mode is enabled for HBM
+ *   NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE
+ *     This is used by WDDM-KMD to determine whether and how much RM reserved BAR1 for smooth transition
+ *   NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE
+ *     Returns the total size of the all dynamically offlined pages in KiB
+ *   NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED
+ *     Returns true if 1to1 comptag is enabled
+ *   NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE
+ *     Returns the total size of the memory(FB) that will saved/restored during save/restore cycle
+ *   NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT
+ *     Returns true if page retirement is allowed
+ *   NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED
+ *     Returns true if poison fuse is enabled
+ *   NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED
+ *     Returns true if ECC is enabled for FBPA
+ *   NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED
+ *     Returns true if dynamic page blacklisting is enabled
+ *   NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED
+ *     Returns true if 64KB mapping on BAR1 is force-enabled
+ *   NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE
+ *     Returns the P2P mailbox size to be allocated by the client. 
+ *     Returns 0 if the P2P mailbox is allocated by RM.
+ *   NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT_SIZE
+ *     Returns the P2P mailbox alignment requirement.
+ *     Returns 0 if the P2P mailbox is allocated by RM.
+ *   NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB
+ *     Returns the P2P mailbox max offset requirement.
+ *     Returns 0 if the P2P mailbox is allocated by RM.
+ *   NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB
+ *     Returns total protected memory when memory protection is enabled
+ *     Returns 0 when memory protection is not enabled.
+ *   NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB
+ *     Returns protected memory available for allocation when memory
+ *     protection is enabled.
+ *     Returns 0 when memory protection is not enabled.
+ *   NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE
+ *     Returns the ECC status size (corresponds to subpartitions or channels
+ *     depending on architecture/memory type).
+ *   NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB
+ *      Returns true if FB is not present on this chip
+ *   NV2080_CTRL_FB_INFO_INDEX_ACCESS_COUNTER_BUFFER_COUNT
+ *      Returns the count of access counter buffers supported by GPU
+ */
+typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
+
+/* valid fb info index values */
+#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT                 (0x00000000U) // Deprecated
+#define NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE                  (0x00000001U)
+#define NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE                  (0x00000002U)
+#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT            (0x00000003U)
+#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT                   (0x00000004U)
+#define NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE                         (0x00000005U)
+#define NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT            (0x00000006U)
+#define NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE                          (0x00000007U)
+#define NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE                    (0x00000008U)
+#define NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE                         (0x00000009U)
+#define NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE                (0x0000000AU)
+#define NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH                         (0x0000000BU)
+#define NV2080_CTRL_FB_INFO_INDEX_RAM_CFG                           (0x0000000CU)
+#define NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE                          (0x0000000DU)
+#define NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT                        (0x0000000EU)
+#define NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT         (0x0000000FU) // Deprecated (index reused to return 0)
+#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB           (0x0000000FU) // Deprecated (index reused to return 0)
+#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB            (0x0000000FU) // Deprecated (index reused to return 0)
+#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB         (0x0000000FU) // Deprecated (index reused to return 0)
+#define NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW                      (0x0000000FU) // Deprecated (index reused to return 0)
+#define NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB                    (0x00000010U)
+#define NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB                      (0x00000011U)
+#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB       (0x00000012U)
+#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB       (0x00000013U)
+#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK                    (0x00000014U)
+#define NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE          (0x00000015U)
+#define NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE                         (0x00000016U)
+#define NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION                      (0x00000017U)
+#define NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN                      (0x00000018U)
+#define NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT                         (0x00000019U)
+#define NV2080_CTRL_FB_INFO_INDEX_FBP_MASK                          (0x0000001AU)
+#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE                      (0x0000001BU)
+#define NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID              (0x0000001CU)
+#define NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE                   (0x0000001DU)
+#define NV2080_CTRL_FB_INFO_INDEX_HEAP_START                        (0x0000001EU)
+#define NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE    (0x0000001FU)
+#define NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE                   (0x00000020U)
+#define NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T                        (0x00000021U)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT                         (0x00000022U)
+#define NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT                         (0x00000023U)
+#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE                 (0x00000024U)
+#define NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE               (0x00000025U)
+#define NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE         (0x00000026U)
+#define NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE                 (0x00000027U)
+#define NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED              (0x00000028U)
+#define NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE          (0x00000029U)
+#define NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT             (0x0000002AU)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK                          (0x0000002BU)
+#define NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED                     (0x0000002CU)
+#define NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED                        (0x0000002DU)
+#define NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED          (0x0000002EU)
+#define NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED  (0x0000002FU)
+#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE                  (0x00000030U)
+#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT             (0x00000031U)
+#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB  (0x00000032U)
+#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB       (0x00000033U)
+#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB        (0x00000034U)
+#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE                   (0x00000035U)
+#define NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB                        (0x00000036U)
+#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0                  (NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK)
+#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1                  (0x00000037U)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0                        (NV2080_CTRL_FB_INFO_INDEX_LTC_MASK)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1                        (0x00000038U)
+#define NV2080_CTRL_FB_INFO_INDEX_ACCESS_COUNTER_BUFFER_COUNT       (0x00000039U)
+#define NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO                    (0x0000003AU)
+#define NV2080_CTRL_FB_INFO_INDEX_NUMA_NODE_ID                      (0x0000003BU)
+#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_2                  (0x0000003CU)
+#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_3                  (0x0000003DU)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_2                        (0x0000003EU)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_3                        (0x0000003FU)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_4                        (0x00000040U)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_5                        (0x00000041U)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_6                        (0x00000042U)
+#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_7                        (0x00000043U)
+
+#define NV2080_CTRL_FB_INFO_INDEX_MAX                               NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_7
+
+/* Intentionally picking a value much bigger than NV2080_CTRL_FB_INFO_INDEX_MAX to prevent VGPU plumbing updates */
+#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE                           (0x00000080U)
+
+/* valid fb RAM type values */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN                        (0x00000000U)
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM                          (0x00000001U)
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1                           (0x00000002U) /* SDDR and GDDR (aka DDR1 and GDDR1) */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2                          (0x00000003U) /* SDDR2 Used on NV43 and later */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2                           NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 /* Deprecated alias */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2                          (0x00000004U) /* GDDR2 Used on NV30 and some NV36 */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3                          (0x00000005U) /* GDDR3 Used on NV40 and later */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4                          (0x00000006U) /* GDDR4 Used on G80 and later (deprecated) */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3                          (0x00000007U) /* SDDR3 Used on G9x and later */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3                           NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 /* Deprecated alias */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5                          (0x00000008U) /* GDDR5 Used on GT21x and later */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2                         (0x00000009U) /* LPDDR (Low Power SDDR) used on T2x and later. */
+
+
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4                          (0x0000000CU) /* SDDR4 Used on Maxwell and later */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4                         (0x0000000DU) /* LPDDR (Low Power SDDR) used on T21x and later.*/
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1                           (0x0000000EU) /* HBM1 (High Bandwidth Memory) used on GP100 */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2                           (0x0000000FU) /* HBM2 (High Bandwidth Memory-pseudo channel) */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X                         (0x00000010U) /* GDDR5X Used on GP10x */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6                          (0x00000011U) /* GDDR6 Used on TU10x */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X                         (0x00000012U) /* GDDR6X Used on GA10x */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5                         (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3                           (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */
+
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7                          (0x00000015U) /* GDDR7 */
+
+
+/*
+ * Guarding the macro which reveal the use of HBM4.
+ */
+#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM4                           (0x00000016U) /* HBM4 (High Bandwidth Memory) v4 */
+
+
+
+/* valid RAM LOCATION types */
+#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED              (0x00000000U)
+#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED                 (0x00000001U)
+#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED              (0x00000002U)
+
+/* valid Memory Vendor ID values */
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG            (0x00000001U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA            (0x00000002U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA             (0x00000003U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON              (0x00000004U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA              (0x00000005U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX              (0x00000006U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL              (0x00000007U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND            (0x00000008U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT               (0x00000009U)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON             (0x0000000FU)
+#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN            (0xFFFFFFFFU)
+
+#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED         (0x00000000U)
+#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED            (0x00000001U)
+#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED             (0x00000002U)
+
+#define NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO_NON_FULLY_COHERENT (0x00000000U)
+#define NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO_FULLY_COHERENT     (0x00000001U)
+
+/**
+ * NV2080_CTRL_CMD_FB_GET_INFO
+ *
+ * This command returns fb engine information for the associated GPU.
+ * Requests to retrieve fb information use a list of one or more
+ * NV2080_CTRL_FB_INFO structures.
+ *
+ *   fbInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     fbInfoList.
+ *   fbInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the fb information is to be returned.
+ *     This buffer must be at least as big as fbInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_FB_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_FB_GET_INFO                                 (0x20801301U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_FB_GET_INFO_PARAMS {
+    NvU32 fbInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 fbInfoList, 8);
+} NV2080_CTRL_FB_GET_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_FB_GET_INFO_V2 (0x20801303U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS {
+    NvU32               fbInfoListSize;
+    NV2080_CTRL_FB_INFO fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE];
+} NV2080_CTRL_FB_GET_INFO_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET
+ *
+ * This command returns the GPU virtual address of a bar1
+ * allocation, given the CPU virtual address.
+ *
+ *   cpuVirtAddress
+ *     This field specifies the associated CPU virtual address of the
+ *     memory allocation.
+ *   gpuVirtAddress
+ *     The GPU virtual address associated with the allocation
+ *     is returned in this field.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET (0x20801310U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 cpuVirtAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 gpuVirtAddress, 8);
+} NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS;
+
+/*
+ * NV2080_CTRL_FB_CMD_GET_CALIBRATION_LOCK_FAILED
+ *
+ * This command returns the failure counts for calibration.
+ *
+ *   uFlags
+ *     Just one for now -- ehether to reset the counts.
+ *   driveStrengthRiseCount
+ *     This parameter specifies the failure count for drive strength rising.
+ *   driveStrengthFallCount
+ *     This parameter specifies the failure count for drive strength falling.
+ *   driveStrengthTermCount
+ *     This parameter specifies the failure count for drive strength
+ *     termination.
+ *   slewStrengthRiseCount
+ *     This parameter specifies the failure count for slew strength rising.
+ *   slewStrengthFallCount
+ *     This parameter specifies the failure count for slew strength falling.
+ *   slewStrengthTermCount
+ *     This parameter specifies the failure count for slew strength
+ *     termination.
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NVOS_STATUS_INVALID_PARAM_STRUCT
+ *     NVOS_STATUS_NOT_SUPPORTED
+ *     NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED (0x2080130cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS {
+    NvU32 flags;
+    NvU32 driveStrengthRiseCount;
+    NvU32 driveStrengthFallCount;
+    NvU32 driveStrengthTermCount;
+    NvU32 slewStrengthRiseCount;
+    NvU32 slewStrengthFallCount;
+} NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS;
+
+/* valid flags parameter values */
+#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE    (0x00000000U)
+#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET   (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL
+ *
+ * If supported by hardware and the OS, this command implements a streamlined version of
+ * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE which can be called at high IRQL and Bypass the
+ * RM Lock.
+ *
+ * Requires the following NVOS54_PARAMETERS to be set for raised IRQ / Lock Bypass operation:
+ *   NVOS54_FLAGS_IRQL_RAISED
+ *   NVOS54_FLAGS_LOCK_BYPASS
+ *
+ *   flags
+ *     Contains flags to control various aspects of the flush.  Valid values
+ *     are defined in NV2080_CTRL_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS*.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ * See Also:
+ *   NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
+ *     This is the more generalized version which is not intended to be called at raised IRQ level
+ *   NV0080_CTRL_CMD_DMA_FLUSH
+ *     Performs flush operations in broadcast for the GPU cache and other hardware
+ *     engines.  Use this call if you want to flush all GPU caches in a
+ *     broadcast device.
+ *    NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
+ *     Flushes memory associated with a single allocation if the hardware
+ *     supports it.  Use this call if you want to flush a single allocation and
+ *     you have a memory object describing the physical memory.
+ */
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS {
+    NvU32 flags;
+} NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS;
+
+/* valid fields and values for flags */
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK         0:0
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO  (0x00000000U)
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES (0x00000001U)
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE         1:1
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO  (0x00000000U)
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES (0x00000001U)
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH           2:2
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO    (0x00000000U)
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES   (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
+ *
+ * This command flushes a cache on the GPU which all memory accesses go
+ * through.  The types of flushes supported by this API may not be supported by
+ * all hardware.  Attempting an unsupported flush type will result in an error.
+ *
+ *   addressArray
+ *     An array of physical addresses in the aperture defined by
+ *     NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE.  Each entry points to a
+ *     contiguous block of memory of size memBlockSizeBytes.  The addresses are
+ *     aligned down to addressAlign before coalescing adjacent addresses and
+ *     sending flushes to hardware.
+ *   addressAlign
+ *     Used to align-down addresses held in addressArray.  A value of 0 will be
+ *     forced to 1 to avoid a divide by zero.  Value is treated as minimum
+ *     alignment and any hardware alignment requirements above this value will
+ *     be honored.
+ *   addressArraySize
+ *     The number of entries in addressArray.
+ *   memBlockSizeBytes
+ *     The size in bytes of each memory block pointed to by addressArray.
+ *   flags
+ *     Contains flags to control various aspects of the flush.  Valid values
+ *     are defined in NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS*.  Not all flags are
+ *     valid for all defined FLUSH_MODEs or all GPUs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ * See Also:
+ *   NV0080_CTRL_CMD_DMA_FLUSH
+ *     Performs flush operations in broadcast for the GPU cache and other hardware
+ *     engines.  Use this call if you want to flush all GPU caches in a
+ *     broadcast device.
+ *    NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
+ *     Flushes memory associated with a single allocation if the hardware
+ *     supports it.  Use this call if you want to flush a single allocation and
+ *     you have a memory object describing the physical memory.
+ */
+#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE                           (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES                 500U
+
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 addressArray[NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES], 8);
+    NvU32 addressArraySize;
+    NvU32 addressAlign;
+    NV_DECLARE_ALIGNED(NvU64 memBlockSizeBytes, 8);
+    NvU32 flags;
+} NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS;
+
+/* valid fields and values for flags */
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE              1:0
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY    (0x00000000U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY   (0x00000001U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY     (0x00000002U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK            2:2
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO            (0x00000000U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES           (0x00000001U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE            3:3
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO            (0x00000000U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES           (0x00000001U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE            4:4
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY (0x00000000U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE    (0x00000001U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH              5:5
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO              (0x00000000U)
+#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES             (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_FB_IS_KIND
+ *
+ * This command is used to perform various operations like 'IS_KIND_VALID',
+ * 'IS_KIND_COMPRESSIBLE'on the kind passed by the caller. The operation to be
+ * performed should be passed in the 'operation' parameter of
+ * NV2080_CTRL_FB_IS_KIND_PARAMS, the kind on which the operation is to be
+ * performed should be passed in the 'kind' parameter. The result of the
+ * operation (true/false) will be returned in the 'result' parameter.
+ *
+ *   operation
+ *     Specifies what operation is to be performed on the kind passed by the
+ *     caller. The supported operations are
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure is
+ *         supported for this GPU. Returns nonzero value in 'result' parameter
+ *         if the input kind is supported, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure is
+ *         compressible. Returns nonzero value in 'result' parameter if the
+ *         input kind is compressible, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports
+ *         1 bit compression. Returns nonzero value in 'result' parameter if
+ *         kind supports 1 bit compression, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports
+ *         2 bit compression. Returns nonzero value in 'result' parameter if
+ *         kind supports 1 bit compression, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports
+ *         4 bit compression. Returns nonzero value in 'result' parameter if
+ *         kind supports 4 bit compression, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure
+ *         supports ZBC. Returns nonzero value in 'result' parameter if the
+ *         input kind supports ZBC, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure
+ *         supports 1 bit ZBC. Returns nonzero value in 'result' parameter if
+ *         the input kind supports 1 bit ZBC, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure
+ *         supports 2 bit ZBC. Returns nonzero value in 'result' parameter if
+ *         the input kind supports 2 bit ZBC, else returns zero in the result.
+ *       NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4
+ *         This operation checks whether the kind passed in the 'kind'
+ *         parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure
+ *         supports 4 bit ZBC. Returns nonzero value in 'result' parameter if
+ *         the input kind supports 4 bit ZBC, else returns zero in the result.
+ *   kind
+ *     Specifies the kind on which the operation is to be carried out. The
+ *     legal range of values for the kind parameter is different on different
+ *     GPUs. For e.g. on Fermi, valid range is 0x00 to 0xfe. Still, some values
+ *     inside this legal range can be invalid i.e. not defined.
+ *     So its always better to first check if a particular kind is supported on
+ *     the current GPU with 'NV2080_CTRL_FB_IS_KIND_SUPPORTED' operation.
+ *   result
+ *     Upon return, this parameter will hold the result (true/false) of the
+ *     operation performed on the kind.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_IS_KIND                                    (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_FB_IS_KIND_PARAMS {
+    NvU32  operation;
+    NvU32  kind;
+    NvBool result;
+} NV2080_CTRL_FB_IS_KIND_PARAMS;
+
+/* valid values for operation */
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED      (0x00000000U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE   (0x00000001U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 (0x00000002U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 (0x00000003U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 (0x00000004U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC            (0x00000005U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1   (0x00000006U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2   (0x00000007U)
+#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4   (0x00000008U)
+
+/**
+ * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO
+ *
+ * This command returns the state of a cache which all GPU memory accesess go
+ * through.
+ *
+ *   powerState
+ *     Returns the power state of the cache.  Possible values are defined in
+ *     NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE.
+ *
+ *   writeMode
+ *     Returns the write mode of the cache.  Possible values are defined in
+ *     NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE.
+ *
+ *   bypassMode
+ *     Returns the bypass mode of the L2 cache.  Possible values are defined in
+ *     NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE.
+ *
+ *   rcmState
+ *     Returns the RCM state of the cache.  Possible values are defined in
+ *     NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE.
+ *
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO           (0x20801315U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS {
+    NvU32 powerState;
+    NvU32 writeMode;
+    NvU32 bypassMode;
+    NvU32 rcmState;
+} NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS;
+
+/* valid values for powerState */
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED     (0x00000000U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED    (0x00000001U)
+/* valid values for writeMode */
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH (0x00000000U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK    (0x00000001U)
+/* valid values for bypassMode */
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED    (0x00000000U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED     (0x00000001U)
+/* valid values for rcmState */
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL          (0x00000000U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING (0x00000001U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED       (0x00000002U)
+#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE    (0x00000003U)
+
+/*
+ * NV2080_CTRL_FB_CMD_GET_FB_REGION_INFO
+ *
+ * This command returns the FB memory region characteristics.
+ *
+ *   numFBRegions
+ *     Number of valid regions returned in fbRegion[]
+ *   fbRegion[].base
+ *     Base address of region.  The first valid address in the range
+ *     [base..limit].
+ *   fbRegion[].limit
+ *     Last/end address of region.  The last valid address in the range
+ *     [base..limit].
+ *     (limit - base + 1) = size of the region
+ *   fbRegion[].reserved
+ *     Amount of memory that RM speculatively needs within the region.  A
+ *     client doing its own memory management should leave at least this much
+ *     memory available for RM use.  This particularly applies to a driver
+ *     model like LDDM.
+ *   fbRegion[].performance
+ *     Relative performance of this region compared to other regions.
+ *     The definition is vague, and only connotes relative bandwidth or
+ *     performance.  The higher the value, the higher the performance.
+ *   fbRegion[].supportCompressed
+ *     TRUE if compressed surfaces/kinds are supported
+ *     FALSE if compressed surfaces/kinds are not allowed to be allocated in
+ *     this region
+ *   fbRegion[].supportISO
+ *     TRUE if ISO surfaces/kinds are supported (Display, cursor, video)
+ *     FALSE if ISO surfaces/kinds are not allowed to be allocated in this
+ *     region
+ *   fbRegion[].bProtected
+ *     TRUE if this region is a protected memory region.  If true only
+ *     allocations marked as protected (NVOS32_ALLOC_FLAGS_PROTECTED) can be
+ *     allocated in this region.
+ *   fbRegion[].blackList[] - DEPRECATED: Use supportISO
+ *     TRUE for each NVOS32_TYPE_IMAGE* that is NOT allowed in this region.
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO                     (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES           18U
+
+// add tags as needed for regions through either memmgrInitFbRegions or memmgrInsertFbRegion
+typedef enum NV2080_FB_REGION_TAG {
+    NV2080_FB_REGION_TAG_NONE = 0,                 // default tag
+    NV2080_FB_REGION_TAG_GSP_CARVEOUT = 1,         // GSP carveout region, usually at highest address    
+    NV2080_FB_REGION_TAG_CPU_RM_RESERVED = 2,      // first reserved region for structures in CPU RM
+    NV2080_FB_REGION_TAG_CPU_RM_RESERVED_HEAP = 3, // second reserved region for structures in CPU RM
+    NV2080_FB_REGION_TAG_GSP_RM_RESERVED = 4,      // first reserved region for structures in GSP RM
+    NV2080_FB_REGION_TAG_GSP_RM_RESERVED_HEAP = 5,  // second reserved region for structures in GSP RM
+} NV2080_FB_REGION_TAG;
+
+typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 limit, 8);
+    NV_DECLARE_ALIGNED(NvU64 reserved, 8);
+    NvU32                performance;
+    NvBool               supportCompressed;
+    NvBool               supportISO;
+    NvBool               bProtected;
+    NvBool               blackList[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES];
+    NV2080_FB_REGION_TAG regionTag;
+} NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO;
+
+#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES 16U
+
+#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS {
+    NvU32 numFBRegions;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO fbRegion[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES], 8);
+} NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_OFFLINE_PAGES
+ *
+ * This command adds video memory page addresses to the list of offlined
+ * addresses so that they're not allocated to any client. The newly offlined
+ * addresses take effect after a reboot.
+ *
+ *   offlined
+ *     This input parameter is an array of NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO
+ *     structures, containing the video memory physical page numbers that
+ *     are to be blacklisted. This array can hold a maximum of NV2080_CTRL_FB_
+ *     BLACKLIST_PAGES_MAX_PAGES address pairs. Valid entries are adjacent.
+ *   pageSize
+ *     This input parameter contains the size of the page that is to be
+ *     blacklisted.
+ *   validEntries
+ *     This input parameter specifies the number of valid entries in the
+ *     offlined array.
+ *   numPagesAdded
+ *     This output parameter specifies how many of the validEntries were
+ *     actually offlined. If numPagesAdded < validEntries, it
+ *     means that only addresses from offlined[0] to offlined[numPagesAdded - 1]
+ *     were added to the list of offlined addresses.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_OFFLINE_PAGES              (0x20801321U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES       (0x00000040U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS (0xffffffffffffffffULL)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K    (0x00000000U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K   (0x00000001U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K  (0x00000002U)
+
+/*
+ * NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO
+ *
+ *   pageAddressWithEccOn
+ *     Address of the memory page retired when ECC is enabled on the board.
+ *   pageAddressWithEccOff
+ *     Address of the memory page retired when ECC is disabled on the board.
+ *   rbcAddress
+ *     Row/Bank/Column Address of the faulty memory which caused the page to
+ *     be retired
+ *   source
+ *     The reason for the page to be retired
+ *   status
+ *      Non-exceptional reasons for a page retirement failure
+ *         NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK
+ *            No error
+ *         NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT
+ *            The given address is already pending retirement or has
+ *            been retired during the current driver run. The page
+ *            will be offlined during the next driver run.
+ *         NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED
+ *            The given page was retired on a previous driver run,
+ *            so it should not be accessible unless offlining failed.
+ *            Failing to offline a page is strongly indicative of a
+ *            driver offlining bug.
+ *         NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL
+ *            The PBL is full and no more pages can be retired
+ *         NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR
+ *            Internal driver error
+ *
+ */
+
+
+
+typedef struct NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO {
+    NV_DECLARE_ALIGNED(NvU64 pageAddressWithEccOn, 8);
+    NV_DECLARE_ALIGNED(NvU64 pageAddressWithEccOff, 8);
+    NvU32 rbcAddress;
+    NvU32 source;
+    NvU32 status;
+    NvU32 timestamp;
+} NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO;
+
+/* valid values for source */
+#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE    (0x00000002U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE             (0x00000004U)
+
+
+
+/* valid values for status */
+#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK                  (0x00000000U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT  (0x00000001U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED (0x00000002U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL          (0x00000003U)
+#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR      (0x00000004U)
+
+/* deprecated */
+#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE        NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE
+#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE                 NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE
+
+
+#define NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8);
+    NvU32 pageSize;
+    NvU32 validEntries;
+    NvU32 numPagesAdded;
+} NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES
+ *
+ * This command returns the list of video memory page addresses in the
+ * Inforom's blacklist.
+ *
+ *   offlined
+ *     This output parameter is an array of NV2080_CTRL_FB_BLACKLIST_ADDRESS_
+ *     INFO structures, containing the video memory physical page numbers that
+ *     are blacklisted. This array can hold a maximum of NV2080_CTRL_FB_
+ *     BLACKLIST_PAGES_MAX_PAGES address pairs. Valid entries are adjacent.
+ *     The array also contains the Row/Bank/Column Address and source.
+ *   validEntries
+ *     This output parameter specifies the number of valid entries in the
+ *     offlined array.
+ *   bRetirementPending (DEPRECATED, use retirementPending instead)
+ *     This output parameter returns if any pages on the list are pending
+ *     retirement.
+ *   retirementPending
+ *     Communicates to the caller whether retirement updates are pending and the
+ *     reason for the updates. Possible fields are:
+ *     NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_*:
+ *       NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE:
+ *         Indicates whether pages are pending retirement due to SBE.
+ *       NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE:
+ *         Indicates whether pages are pending retirement due to DBE. Driver
+ *         reload needed to retire bad memory pages and allow compute app runs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+
+
+#define NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES                            (0x20801322U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE          0:0
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE   0U
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE    1U
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE          1:1
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE   0U
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE    1U
+
+
+
+#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8);
+    NvU32  validEntries;
+    NvBool bRetirementPending;
+    NvU8   retirementPending;
+} NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_QUERY_ACR_REGION
+ *
+ * This control command is used to query the secured region allocated
+ *
+ * queryType
+ *          NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_STATUS: Provides the alloc
+ *          status and ACR region ID.
+ *          NV2080_CTRL_CMD_FB_QUERY_MAP_REGION : Maps the region on BAR1
+ *           it returns the "pCpuAddr" and pPriv to user.
+ *          NV2080_CTRL_CMD_FB_QUERY_UNMAP_REGION: Unmaps the mapped region.
+ *          it takes the pPriv as input
+ *
+ * clientReq : struct ACR_REQUEST_PARAMS
+ *          It is used to find the allocated ACR region for that client
+ *          clientId     : ACR Client ID
+ *          reqReadMask  : read mask of ACR region
+ *          reqWriteMask : Write mask of ACR region
+ *          regionSize   : ACR region Size
+ *
+ * clientReqStatus : struct ACR_STATUS_PARAMS
+ *          This struct is stores the output of requested ACR region.
+ *          allocStatus     : Allocated Status of ACR region
+ *          regionId        : ACR region ID
+ *          physicalAddress : Physical address on FB
+ *
+ *
+ * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE
+ *          NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE : Control command executed successfully
+ *          NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST : Please check the parameter
+ *                      for ACR client request
+ *          NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_FAILED_TO_MAP_ON_BAR1 : RM Fails to map ACR region
+ *                      on BAR1
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+*/
+#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION (0x20801325U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID" */
+
+//
+// We can create an ACR region by using RMCreateAcrRegion[1|2] regkey or mods -acr[1|2]_size
+// Client ID for such region is 2 in RM.
+//
+#define NV2080_CTRL_CMD_FB_ACR_CLIENT_ID    2U
+
+typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE {
+    NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = 0,
+    NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY = 1,
+    NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS = 2,
+} NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE;
+
+typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE {
+    NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE = 0,
+    NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST = 1,
+} NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE;
+
+typedef struct ACR_REQUEST_PARAMS {
+    NvU32 clientId;
+    NvU32 reqReadMask;
+    NvU32 reqWriteMask;
+    NvU32 regionSize;
+} ACR_REQUEST_PARAMS;
+
+typedef struct ACR_REGION_ID_PROP {
+    NvU32 regionId;
+    NvU32 readMask;
+    NvU32 writeMask;
+    NvU32 regionSize;
+    NvU32 clientMask;
+    NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8);
+} ACR_REGION_ID_PROP;
+
+typedef struct ACR_STATUS_PARAMS {
+    NvU32 allocStatus;
+    NvU32 regionId;
+    NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8);
+} ACR_STATUS_PARAMS;
+
+typedef struct ACR_REGION_HANDLE {
+    NvHandle hClient;
+    NvHandle hParent;
+    NvHandle hMemory;
+    NvU32    hClass;
+    NvHandle hDevice;
+} ACR_REGION_HANDLE;
+
+typedef struct ACR_FALCON_LS_STATUS {
+    NvU16  falconId;
+    NvBool bIsInLs;
+} ACR_FALCON_LS_STATUS;
+
+#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS {
+    NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE       queryType;
+    NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE errorCode;
+    NV_DECLARE_ALIGNED(ACR_REGION_ID_PROP acrRegionIdProp, 8);
+    ACR_REQUEST_PARAMS                      clientReq;
+    NV_DECLARE_ALIGNED(ACR_STATUS_PARAMS clientReqStatus, 8);
+    ACR_REGION_HANDLE                       handle;
+    ACR_FALCON_LS_STATUS                    falconStatus;
+} NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES
+ *
+ * This command clears offlined video memory page addresses from the Inforom.
+ *
+ *   sourceMask
+ *     This is a bit mask of NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE. Pages
+ *     offlined from the specified sources will be cleared/removed from the
+ *     Inforom PBL object denylist.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES (0x20801326U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x26U)
+
+typedef struct NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS {
+    NvU32 sourceMask;
+} NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO
+ *
+ * Gets pointer to then object of class CompBitCopy, which is used for swizzling
+ * compression bits in the compression backing store. The caller is expected to
+ * have the appropriate headers for class CompBitCopy. Also retrieves values of some
+ * parameters needed to call the compbit swizzling method.
+ *
+ * @params[out] void *pCompBitCopyObj
+ *     Opaque pointer to object of class CompBitCopy
+ * @params[out] void *pSwizzleParams
+ *     Opaque pointer to values needed to call the compbit
+ *     swizzle method.
+ *
+ * Possible status values returned are:
+ *   NV_OK NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO (0x20801327U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID (0x27U)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pCompBitCopyObj, 8);
+    NV_DECLARE_ALIGNED(NvP64 pSwizzleParams, 8);
+} NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP
+ *
+ * Gets the count and mask of LTCs for a given FBP.
+ *
+ *   fbpIndex
+ *     The physical index of the FBP to get LTC info for.
+ *   ltcMask
+ *     The mask of active LTCs for the given FBP.
+ *   ltcCount
+ *     The count of active LTCs for the given FBP.
+ *   ltsMask
+ *      The mask of active LTSs for the given FBP
+ *   ltsCount
+ *      The count of active LTSs for the given FBP
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP (0x20801328U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID (0x28U)
+
+typedef struct NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS {
+    NvU8  fbpIndex;
+    NvU32 ltcMask;
+    NvU32 ltcCount;
+    NvU32 ltsMask;
+    NvU32 ltsCount;
+} NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS;
+
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT               < Deprecated >
+ *
+ * "set the context" for following CompBitCopy member functions.
+ * These are the CompBitCopy member variables that remain connstant
+ * over multiple CompBitCopy member function calls, yet stay the same
+ * throughout a single surface eviction.
+ *
+ * @params[in] UINT64  backingStorePA;
+ *     Physical Address of the Backing Store
+ * @params[in] UINT08 *backingStoreVA;
+ *     Virtual Address of the Backing Store
+ * @params[in] UINT64  backingStoreChunkPA;
+ *     Physical Address of the "Chunk Buffer"
+ * @params[in] UINT08 *backingStoreChunkVA;
+ *     Virtual Address of the "Chunk Buffer"
+ * @params[in] UINT32  backingStoreChunkSize;
+ *     Size of the "Chunk Buffer"
+ * @params[in] UINT08 *cacheWriteBitMap;
+ *     Pointer to the bitmap which parts of the
+ *     "Chunk" was updated.
+ * @params[in] bool    backingStoreChunkOverfetch;
+ *     Overfetch factor.
+ * @params[in] UINT32  PageSizeSrc;
+ *     Page size of Source Surface.
+ * @params[in] UINT32  PageSizeDest;
+ *     page size of Destination Surface.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT (0x20801329U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x29" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS {
+    NvU32  CBCBaseAddress;
+    NV_DECLARE_ALIGNED(NvU64 backingStorePA, 8);
+    NV_DECLARE_ALIGNED(NvU8 *backingStoreVA, 8);
+    NV_DECLARE_ALIGNED(NvU64 backingStoreChunkPA, 8);
+    NV_DECLARE_ALIGNED(NvU8 *backingStoreChunkVA, 8);
+    NvU32  backingStoreChunkSize;
+    NV_DECLARE_ALIGNED(NvU8 *cacheWriteBitMap, 8);
+    NvBool backingStoreChunkOverfetch;
+    NvU32  PageSizeSrc;
+    NvU32  PageSizeDest;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS              < Deprecated >
+ *
+ * Retrieves the Compression and Fast Clear bits for the surface+offset given.
+ *
+ * @params[out] NvU32  *fcbits;
+ *     Fast Clear Bits returned
+ * @params[out] NvU32  *compbits;
+ *     Compression Bits returned
+ * @params[in] NvU64  dataPhysicalStart;
+ *     Start Address of Data
+ * @params[in] NvU64  surfaceOffset;
+ *     Offset in the surface
+ * @params[in] NvU32  comptagLine;
+ *     Compression Tag Number
+ * @params[in] NvBool upper64KBCompbitSel;
+ *     Selects Upper or Lower 64K
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTEDD
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS (0x2080132aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2A" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU32 *fcbits, 8);
+    NV_DECLARE_ALIGNED(NvU32 *compbits, 8);
+    NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
+    NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
+    NvU32  comptagLine;
+    NvBool upper64KBCompbitSel;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS              < Deprecated >
+ *
+ * Sets the Compression and Fast Clear bits for the surface+offset given.
+ *
+ * @params[in] NvU32  fcbits;
+ *     Fast Clear Bits to write.
+ * @params[in] NvU32  compbits;
+ *     Compression Bits to write
+ * @params[in] NvBool writeFc;
+ *     Indicates if Fast Clear Bits should be written
+ * @params[in] NvU64  dataPhysicalStart;
+ *     Start Address of Data
+ * @params[in] NvU64  surfaceOffset;
+ *     Offset in the surface
+ * @params[in] NvU32  comptagLine;
+ *     Compression Tag Number
+ * @params[in] NvBool upper64KBCompbitSel;
+ *     Selects Upper or Lower 64K
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS (0x2080132bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2B" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS {
+    NvU32  fcbits;
+    NvU32  compbits;
+    NvBool writeFc;
+    NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
+    NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
+    NvU32  comptagLine;
+    NvBool upper64KBCompbitSel;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB         < Deprecated >
+ *
+ * Read 64KB chunk of CompBits
+ *
+ * @params[in] NvU64  SrcDataPhysicalStart;
+ *     Start Address of Data
+ * @params[in] NvU32  SrcComptagLine;
+ *     Compression Tag Number
+ * @params[in] NvU32  page64KB;
+ *     Which 64K block to read from.
+ * @params[out] NvU32  *compbitBuffer;
+ *     Buffer for CompBits read,
+ * @params[in] NvBool upper64KBCompbitSel;
+ *     Selects Upper or Lower 64K
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB (0x2080132cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2C" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 SrcDataPhysicalStart, 8);
+    NvU32  SrcComptagLine;
+    NvU32  page64KB;
+    NV_DECLARE_ALIGNED(NvU32 *compbitBuffer, 8);
+    NvBool upper64KBCompbitSel;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB        < Deprecated >
+ *
+ * Write 64K chunk of COmpBits.
+ *
+ * @params[in] NvU64  SrcDataPhysicalStart;
+ *     Start Address of Data
+ * @params[in] NvU32  SrcComptagLine;
+ *     Compression Tag Number
+ * @params[in] NvU32  page64KB;
+ *     Which 64K block to read from.
+ * @params[in] NvU32  *compbitBuffer;
+ *     Buffer for CompBits to write.
+ * @params[in] NvBool upper64KBCompbitSel
+ *     Selects Upper or Lower 64K
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB (0x2080132dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2D" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 DstDataPhysicalStart, 8);
+    NvU32  DstComptagLine;
+    NvU32  page64KB;
+    NV_DECLARE_ALIGNED(NvU32 *compbitBuffer, 8);
+    NvBool upper64KBCompbitSel;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1                    < Deprecated >
+ *
+ * Used by MODS (and possibly other clients) to have compbit code write
+ * write directly to BAR1, rather than a intermediate buffer.
+ *
+ * @params[in] NvBool bForceBar1;
+ *     Enables or disables direct writes to BAR1.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 (0x20801335U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x35" */
+
+typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS {
+    NvBool bForceBar1;
+} NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_AMAP_CONF
+ *
+ * Fills in fields of a structure of class ConfParamsV1, which is used for
+ * swizzling compression bits in the compression backing store.
+ * The caller is expected to have the appropriate headers for class ConfParamsV1.
+ *
+ * @params[in|out] void *pAmapConfParms
+ *     Opaque pointer to structure of values for ConfParamsV1
+ * @params[in|out] void *pCbcSwizzleParms
+ *     Opaque pointer to structure of values for CbcSwizzleParamsV1
+ *
+ * Possible status values returned are:
+ *   NV_OK NV_ERR_NOT_SUPPORTED
+ *
+ * pCbcSwizzleParams will be filled in with certain parameters from
+ * @CbcSwizzleParamsV1.  However, the caller is responsible for making sure
+ * all parameters are filled in before using it.
+ */
+#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF (0x20801336U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID (0x36U)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pAmapConfParams, 8);
+    NV_DECLARE_ALIGNED(NvP64 pCbcSwizzleParams, 8);
+} NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_CBC_OP
+ *
+ * Provides a way for clients to request a CBC Operation
+ *
+ * @params[in] CTRL_CMD_FB_CBC_OP fbCBCOp
+ *      CBC Operation requested.
+ *      Valid Values:
+ *          CTRL_CMD_FB_CBC_OP_CLEAN
+ *          CTRL_CMD_FB_CBC_OP_INVALIDATE
+ *
+ * Possible status values returned are:
+ *   NV_OK NV_ERR_NOT_SUPPORTED NV_ERR_INVALID_ARGUMENT NV_ERR_TIMEOUT
+ */
+#define NV2080_CTRL_CMD_FB_CBC_OP (0x20801337U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Permitted CBC Operations
+ */
+typedef enum CTRL_CMD_FB_CBC_OP {
+    CTRL_CMD_FB_CBC_OP_CLEAN = 0,
+    CTRL_CMD_FB_CBC_OP_INVALIDATE = 1,
+} CTRL_CMD_FB_CBC_OP;
+
+#define NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID (0x37U)
+
+typedef struct NV2080_CTRL_CMD_FB_CBC_OP_PARAMS {
+    CTRL_CMD_FB_CBC_OP fbCBCOp;
+} NV2080_CTRL_CMD_FB_CBC_OP_PARAMS;
+
+/*!
+ *  NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION
+ *
+ *  The call will fetch the compression tags reserved for CBC eviction.
+ *
+ *  Each comptag will correspond to a unique compression cacheline. The usage of
+ *  these comptags is to evict the CBC by making accesses to a dummy compressed page,
+ *  thereby evicting each CBC line.
+ *
+ *  @param [in][out] NvU32 pCompTags
+ *     Array of reserved compression tags of size @ref NV2080_MAX_CTAGS_FOR_CBC_EVICTION
+ *  @param [out] numCompTags
+ *     Number of entries returned in @ref pCompTags
+ *
+ *  @returns
+ *      NV_OK
+ *      NV_ERR_INVALID_STATE
+ *      NV_ERR_OUT_OF_RANGE
+ *      NV_ERR_INVALID_PARAMETER
+ */
+#define NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION (0x20801338U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Max size of @ref NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS::pCompTags
+ * Arbitrary, but sufficiently large number. Should be checked against CBC size.
+ */
+#define NV2080_MAX_CTAGS_FOR_CBC_EVICTION             0x7FU
+
+
+#define NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID (0x38U)
+
+typedef struct NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS {
+    NvU32 pCompTags[NV2080_MAX_CTAGS_FOR_CBC_EVICTION];
+    NvU32 numCompTags;
+} NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE
+ *
+ * This Call will allocate compression tag
+ *
+ * @params[in] NvU32 attr
+ *      Stores the information:
+ *          1. NVOS32_ATTR_COMPR_REQUIRED or not
+ *          2. NVOS32_ATTR_PAGE_SIZE
+ * @params[in] NvU32 attr2
+ *      Determine whether to allocate
+ *      an entire cache line or allocate by size
+ * @params[in] NvU32 size
+ *      Specify the size of allocation, in pages not bytes
+ * @params[in] NvU32 ctagOffset
+ *      Determine the offset usage of the allocation
+ * @params[out] NvU32 hwResId
+ *      Stores the result of the allocation
+ * @params[out] NvU32 RetcompTagLineMin
+ *      The resulting min Ctag Number from the allocation
+ * @params[out] NvU32 RetcompTagLineMax
+ *      The resulting max Ctag Number from the allocation
+ * @returns
+ *      NV_OK
+ *      NV_ERR_INSUFFICIENT_RESOURCES
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_INVALID_STATE
+ */
+
+#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE (0x20801339U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID (0x39U)
+
+typedef struct NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS {
+    NvU32 attr;
+    NvU32 attr2;
+    NvU32 size;
+    NvU32 ctagOffset;
+    NvU32 hwResId;
+    NvU32 retCompTagLineMin;
+    NvU32 retCompTagLineMax;
+} NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_FREE_TILE
+ *
+ * This control call is used to release tile back to the free pool
+ *
+ * @params[in] NvU32 hwResId
+ *      Stores the information of a previous allocation
+ * @returns
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_INVALID_STATE
+ */
+
+#define NV2080_CTRL_CMD_FB_FREE_TILE (0x2080133aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID (0x3AU)
+
+typedef struct NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS {
+    NvU32 hwResId;
+} NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_FB_SETUP_VPR_REGION
+ *
+ * This control command is used to request vpr region setup
+ *
+ * requestType
+ *          NV2080_CTRL_CMD_FB_SET_VPR: Request to setup VPR
+ *
+ * requestParams : struct VPR_REQUEST_PARAMS
+ *          It contains the VPR region request details like,
+ *          startAddr : FB offset from which we need to setup VPR
+ *          size      : required size of the region
+ *
+ * statusParams  : struct VPR_STATUS_PARAMS
+ *          This struct stores the output of requested VPR region
+ *          status    : Whether the request was successful
+ *
+ * NV2080_CTRL_CMD_FB_VPR_ERROR_CODE :
+ *          NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC : Some unknown error occurred
+ *          NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST : Request was invalid
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION (0x2080133bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE {
+    NV2080_CTRL_CMD_FB_SET_VPR = 0,
+} NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE;
+
+typedef enum NV2080_CTRL_CMD_FB_VPR_ERROR_CODE {
+    NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC = 0,
+    NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST = 1,
+} NV2080_CTRL_CMD_FB_VPR_ERROR_CODE;
+
+typedef struct VPR_REQUEST_PARAMS {
+    NvU32 startAddr;
+    NvU32 size;
+} VPR_REQUEST_PARAMS;
+
+typedef struct VPR_STATUS_PARAMS {
+    NvU32 status;
+} VPR_STATUS_PARAMS;
+
+#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID (0x3BU)
+
+typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS {
+    NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE requestType;
+    VPR_REQUEST_PARAMS                  requestParams;
+    VPR_STATUS_PARAMS                   statusParams;
+} NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS;
+typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS *PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES
+ *
+ * This command returns the list of offlined video memory page addresses in the
+ * region managed by Client
+ *
+ *   offlinedPages
+ *     This output parameter is an array of video memory physical page numbers that
+ *     are offlined. This array can hold a maximum of NV2080_CTRL_FB_
+ *     OFFLINED_PAGES_MAX_PAGES addresses.
+ *   pageSize
+ *     This output parameter contains the size of the page that is offlined.
+ *   validEntries
+ *     This output parameter specifies the number of valid entries in the
+ *     offlined array.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES (0x2080133cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x3CU)
+
+typedef struct NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS {
+    NvU32 offlinedPages[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES];    // A 32B can hold enough.
+    NvU32 pageSize;
+    NvU32 validEntries;
+} NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO
+ *
+ * This command returns parameters required to initialize compbit copy object
+ * used by address mapping library
+ *
+ *   defaultPageSize
+ *     Page size used by @ref CompBitCopy methods
+ *   comptagsPerCacheLine
+ *     Number of compression tags in a single compression cache line.
+ *   unpackedComptagLinesPerCacheLine;
+ *     From hw (not adjusted for CompBits code)  Number of compression tags
+ *     in a single compression cache line.
+ *   compCacheLineSizePerLTC;
+ *     Size of compression cache line per L2 slice. Size in Bytes.
+ *   unpackedCompCacheLineSizePerLTC;
+ *     From hw (not adjusted for CompBits code) size of compression
+ *     cache line per L2 slice. Size in Bytes
+ *   slicesPerLTC;
+ *     Number of L2 slices per L2 cache.
+ *   numActiveLTCs;
+ *     Number of active L2 caches. (Not floorswept)
+ *   familyName;
+ *     Family name for the GPU.
+ *   chipName;
+ *     Chip name for the GPU.
+ *   bitsPerRAMEntry;
+ *     Bits per RAM entry. (Need better doc)
+ *   ramBankWidth;
+ *     Width of RAM bank. (Need better doc)
+ *   bitsPerComptagLine;
+ *     Number of bits per compression tag line.
+ *   ramEntriesPerCompCacheLine;
+ *     Number of RAM entries spanned by 1 compression cache line.
+ *   comptagLineSize;
+ *     Size of compression tag line, in Bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO (0x2080133dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID (0x3DU)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS {
+    NvU32 defaultPageSize;
+    NvU32 comptagsPerCacheLine;
+    NvU32 unpackedComptagLinesPerCacheLine;
+    NvU32 compCacheLineSizePerLTC;
+    NvU32 unpackedCompCacheLineSizePerLTC;
+    NvU32 slicesPerLTC;
+    NvU32 numActiveLTCs;
+    NvU32 familyName;
+    NvU32 chipName;
+    NvU32 bitsPerRAMEntry;
+    NvU32 ramBankWidth;
+    NvU32 bitsPerComptagLine;
+    NvU32 ramEntriesPerCompCacheLine;
+    NvU32 comptagLineSize;
+} NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_RRD
+ *
+ * Sets the row-to-row delay on the GPU's FB
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  Any error code
+ */
+#define NV2080_CTRL_CMD_FB_SET_RRD (0x2080133eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_SET_RRD_RESET_VALUE (~((NvU32)0))
+#define NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID (0x3EU)
+
+typedef struct NV2080_CTRL_FB_SET_RRD_PARAMS {
+    NvU32 rrd;
+} NV2080_CTRL_FB_SET_RRD_PARAMS;
+
+/*
+ * NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
+ *
+ * This is not a control call of it's own, but there are common definitions for
+ * the two NV2080_CTRL_CMD_FB_SET_READ/WRITE_LIMIT control calls.
+ */
+typedef struct NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS {
+    NvU8 limit;
+} NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS;
+#define NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE (0xffU)
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_READ_LIMIT
+ *
+ * Sets the READ_LIMIT to be used in the NV_PFB_FBPA_DIR_ARB_CFG0 register
+ *
+ *  limit
+ *      The limit value to use
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  Any error code
+ */
+#define NV2080_CTRL_CMD_FB_SET_READ_LIMIT               (0x2080133fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE       NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE
+#define NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID (0x3FU)
+
+typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT
+ *
+ * Sets the WRITE_LIMIT to be used in the NV_PFB_FBPA_DIR_ARB_CFG0 register
+ *
+ *  limit
+ *      The limit value to us
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  Any error code
+ */
+#define NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT         (0x20801340U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE
+#define NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID (0x40U)
+
+typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING
+ *
+ * Patches some VBIOS values related to PBR to better suit mining applications
+ *
+ *  bEnable
+ *      Set the mining-specific values or reset to the original values
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  Any error code
+ */
+#define NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING (0x20801341U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID (0x41U)
+
+typedef struct NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS {
+    NvBool bEnable;
+} NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT
+ *
+ * Get memory alignment. Replacement for NVOS32_FUNCTION_GET_MEM_ALIGNMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID (0x42U)
+
+typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS {
+    NvU32 alignType;                                 // Input
+    NvU32 alignAttr;
+    NvU32 alignInputFlags;
+    NvU32 alignHead;
+    NV_DECLARE_ALIGNED(NvU64 alignSize, 8);
+    NvU32 alignHeight;
+    NvU32 alignWidth;
+    NvU32 alignPitch;
+    NvU32 alignPad;
+    NvU32 alignMask;
+    NvU32 alignKind;
+    NvU32 alignAdjust;                                // Output -- If non-zero the amount we need to adjust the offset
+    NvU32 alignAttr2;
+} NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_CBC_BASEADDR
+ *
+ * Get the CBC Base physical address
+ * This control call is required by error containment tests
+ * NV2080_CTRL_CMD_FB_GET_AMAP_CONF can also return CBC base address
+ * but it requires kernel privilege, and it not callalble from SRT test
+ *
+ * @params[out] NvU64 cbcBaseAddr
+ *     Base physical address for CBC data.
+ *
+ * Possible status values returned are:
+ *   NV_OK NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR (0x20801343U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID (0x43U)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS {
+    NvU32 cbcBaseAddress;
+    NvU32 compCacheLineSize;
+    NV_DECLARE_ALIGNED(NvU64 backingStoreStartPA, 8);
+    NV_DECLARE_ALIGNED(NvU64 backingStoreAllocPA, 8);
+    NvU32 backingStoreChunkOverfetch;
+} NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS;
+
+#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING                             0:0
+#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE 0U
+#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE  1U
+#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE                              1:1
+#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE_FALSE  0U
+#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE_TRUE   1U
+
+
+
+typedef struct NV2080_CTRL_FB_ROW_REMAP_ENTRY {
+    NvU32 remapRegVal;
+    NvU32 timestamp;
+    NvU8  fbpa;
+    NvU8  sublocation;
+    NvU8  source;
+    NvU8  flags;
+} NV2080_CTRL_FB_ROW_REMAP_ENTRY;
+
+/* valid values for source */
+
+
+#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD         (0x00000002U)
+#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD         (0x00000003U)
+
+#define NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS                (0x00000200U)
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS
+ *
+ * This command returns the list of remapped rows stored in the Inforom.
+ *
+ *   entryCount
+ *     This output parameter specifies the number of remapped rows
+ *   flags
+ *     This output parameter contains info on whether or not there are pending
+ *     remappings and whether or not a remapping failed
+ *   entries
+ *     This output parameter is an array of NV2080_CTRL_FB_REMAP_ENTRY
+ *     containing inforomation on the remapping that occurred. This array can
+ *     hold a maximum of NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_INVALID_POINTER
+ *    NV_ERR_OBJECT_NOT_FOUND
+ *    NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS                 (0x20801344U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING                       \
+    NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE  NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE                       1:1
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE 0U
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE  1U
+
+#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x44U)
+
+typedef struct NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS {
+    NvU32                          entryCount;
+    NvU8                           flags;
+    NV2080_CTRL_FB_ROW_REMAP_ENTRY entries[NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS];
+} NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS;
+
+// Max size of the queryParams in Bytes, so that the NV2080_CTRL_FB_FS_INFO_QUERY struct is still 32B
+#define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE 24U
+
+/*!
+ * Structure holding the out params for NV2080_CTRL_FB_FS_INFO_INVALID_QUERY.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS {
+    // Unused param, will ensure the size of NV2080_CTRL_FB_FS_INFO_QUERY struct to be 32B
+    NvU8 data[NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE];
+} NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBP_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS {
+    /*!
+     * [in]: swizzId
+     * PartitionID associated with a created smc partition. Currently used only for a
+     * device monitoring client to get the physical values of the FB. The client needs to pass
+     * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId.
+     * RM will consider this request similar to a legacy case.
+     * The client's subscription is used only as a capability check and not as an input swizzId.
+     */
+    NvU32 swizzId;
+    /*!
+     * [out]: physical/local fbp mask.
+     */
+    NV_DECLARE_ALIGNED(NvU64 fbpEnMask, 8);
+} NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LTC_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS {
+    /*!
+     * [in]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [out]: physical/local ltc mask.
+     */
+    NvU32 ltcEnMask;
+} NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LTS_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS {
+    /*!
+     * [in]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [out]: physical/local lts mask.
+     * Note that lts bits are flattened out for all ltc with in a fbp.
+     */
+    NvU32 ltsEnMask;
+} NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBPA_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS {
+    /*!
+     * [in]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [out]: physical/local FBPA mask.
+     */
+    NvU32 fbpaEnMask;
+} NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS {
+    /*!
+     * [in]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [out]: physical/local FBPA-SubPartition mask.
+     */
+    NvU32 fbpaSubpEnMask;
+} NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS {
+    /*!
+     * [in]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [out]: Logical/local FBP index
+     */
+    NvU32 fbpLogicalIndex;
+} NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_ROP_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS {
+    /*!
+     * [in]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [out]: physical/local ROP mask.
+     */
+    NvU32 ropEnMask;
+} NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_SYS_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS {
+    /*!
+     * [in]: swizzId
+     * PartitionID associated with a created smc partition. Currently used only for a
+     * device monitoring client to get the physical values of the sys. The client needs to pass
+     * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId.
+     * RM will consider this request similar to a legacy case.
+     */
+    NvU32 swizzId;
+    /*!
+     * [out]: physical/local sys mask.
+     */
+    NV_DECLARE_ALIGNED(NvU64 sysEnMask, 8);
+} NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS {
+    /*!
+     * [in]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [in]: swizzId
+     * PartitionID associated with a created smc partition.
+     */
+    NvU32 swizzId;
+    /*!
+     * [out]: physical ltc mask.
+     */
+    NvU32 ltcEnMask;
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS {
+    /*!
+     * [in]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [in]: swizzId
+     * PartitionID associated with a created smc partition.
+     */
+    NvU32 swizzId;
+    /*!
+     * [out]: physical lts mask.
+     */
+    NvU32 ltsEnMask;
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS {
+    /*!
+     * [in]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [in]: swizzId
+     * PartitionID associated with a created smc partition.
+     */
+    NvU32 swizzId;
+    /*!
+     * [out]: physical fbpa mask.
+     */
+    NvU32 fbpaEnMask;
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS {
+    /*!
+     * [in]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [in]: swizzId
+     * PartitionID associated with a created smc partition.
+     */
+    NvU32 swizzId;
+    /*!
+     * [out]: physical rop mask.
+     */
+    NvU32 ropEnMask;
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS {
+    /*!
+     * [in]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [in]: swizzId
+     * PartitionID associated with a created smc partition. Currently used only for a
+     * device monitoring client to get the physical values of the FB. The client needs to pass
+     * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId.
+     * RM will consider this request similar to a legacy case.
+     * The client's subscription is used only as a capability check and not as an input swizzId.
+     */
+    NvU32 swizzId;
+    /*!
+     * [out]: physical FBPA_SubPartition mask associated with requested partition.
+     */
+    NV_DECLARE_ALIGNED(NvU64 fbpaSubpEnMask, 8);
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK.
+ */
+typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS {
+    /*!
+     * [in]: physical/local sys Id.
+     */
+    NvU32 sysIdx;
+    /*!
+     * [out]: physical/local sysltc mask.
+     */
+    NvU32 sysl2LtcEnMask;
+} NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK.
+ */
+typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS {
+   /*!
+    * [IN]: physical/local SYS index.
+    */
+    NvU32 sysIdx;
+   /*!
+    * [OUT]: physical/local lts mask.
+    * Note: this lts mask should be flattened out within a sys chiplet
+    */
+    NV_DECLARE_ALIGNED(NvU64 sysl2LtsEnMask, 8);
+} NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PAC_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS {
+    /*!
+     * [in]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [out]: physical/local PAC mask.
+     */
+    NvU32 pacEnMask;
+} NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS {
+    /*!
+     * [in]: physical/local FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [out]: logical/local ltc mask.
+     */
+    NV_DECLARE_ALIGNED(NvU64 logicalLtcEnMask, 8);
+} NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS;
+
+/*!
+ * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK.
+ */
+typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS {
+    /*!
+     * [in]: Physical FB partition index.
+     */
+    NvU32 fbpIndex;
+    /*!
+     * [in]: swizzId
+     * PartitionID associated with a created smc partition.
+     */
+    NvU32 swizzId;
+    /*!
+     * [out]: logical ltc mask.
+     */
+    NV_DECLARE_ALIGNED(NvU64 logicalLtcEnMask, 8);
+} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS;
+
+// Possible values for queryType
+#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY                 0x0U
+#define NV2080_CTRL_FB_FS_INFO_FBP_MASK                      0x1U
+#define NV2080_CTRL_FB_FS_INFO_LTC_MASK                      0x2U
+#define NV2080_CTRL_FB_FS_INFO_LTS_MASK                      0x3U
+#define NV2080_CTRL_FB_FS_INFO_FBPA_MASK                     0x4U
+#define NV2080_CTRL_FB_FS_INFO_ROP_MASK                      0x5U
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK         0x6U
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK         0x7U
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK        0x8U
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK         0x9U
+#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK                0xAU
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK   0xBU
+#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP               0xCU
+#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK                0xDU
+#define NV2080_CTRL_FB_FS_INFO_PAC_MASK                      0xEU
+#define NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK              0xFU
+#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK 0x10U
+#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK                0x11U
+#define NV2080_CTRL_FB_FS_INFO_SYS_MASK                      0x12U
+
+typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
+    NvU16 queryType;
+    NvU8  reserved[2];
+    NvU32 status;
+    union {
+        NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS          inv;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS fbp, 8);
+        NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS               ltc;
+        NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS               lts;
+        NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS              fbpa;
+        NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS               rop;
+        NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS  dmLtc;
+        NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS  dmLts;
+        NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS dmFbpa;
+        NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS  dmRop;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS dmFbpaSubp, 8);
+        NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS         fbpaSubp;
+        NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS        fbpLogicalMap;
+        NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS         sysl2Ltc;
+        NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS               pac;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS logicalLtc, 8);
+        NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS dmLogicalLtc, 8);
+        NV_DECLARE_ALIGNED(NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS sysl2Lts, 8);
+        NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS sys, 8);
+    } queryParams;
+} NV2080_CTRL_FB_FS_INFO_QUERY;
+
+// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_FB_GET_FS_INFO
+#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 120U
+
+#define NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID (0x46U)
+
+typedef struct NV2080_CTRL_FB_GET_FS_INFO_PARAMS {
+    NvU16 numQueries;
+    NvU8  reserved[6];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_QUERY queries[NV2080_CTRL_FB_FS_INFO_MAX_QUERIES], 8);
+} NV2080_CTRL_FB_GET_FS_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_FS_INFO
+ *
+ * This control call returns the fb engine information for a partition/GPU.
+ * Supports an interface so that the caller can issue multiple queries by batching them
+ * in a single call. Returns the first error it encounters.
+ *
+ * numQueries[IN]
+ *     - Specifies the number of valid queries.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_FS_INFO                             (0x20801346U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS              (0x0U)
+#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW           (0x1U)
+#define NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS (0x2U)
+#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW          (0x3U)
+#define NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS             (0x4U)
+
+#define NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID (0x47U)
+
+typedef struct NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS {
+    NvU32 histogram[5];
+} NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM
+ *
+ * This control call returns stats on the number of banks that have a certain
+ * number of rows remapped in the bank. Specifically the number of banks that
+ * have 0, 1, 2 through (max-2), max-1 and max number of rows remapped in the
+ * bank. Values will be returned in an array.
+ *
+ * Index values are:
+ *
+ *   NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS
+ *     Number of banks with zero rows remapped
+     NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW
+ *     Number of banks with one row remapped
+     NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS
+ *     Number of banks with 2 through (max-2) rows remapped
+     NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW
+ *     Number of banks with (max-1) rows remapped
+     NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS
+ *     Number of banks with max rows remapped
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM (0x20801347U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_DYNAMICALLY_BLACKLISTED_PAGES
+ *
+ * This command returns the list of dynamically blacklisted video memory page addresses
+ * after last driver load.
+ *
+ *   blackList
+ *     This output parameter is an array of NV2080_CTRL_FB_DYNAMIC_BLACKLIST_ADDRESS_INFO
+ *     This array can hold a maximum of NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES.
+ *   validEntries
+ *     This output parameter specifies the number of valid entries in the
+ *     blackList array.
+ *   baseIndex
+ *     With the limit of up to 512 blacklisted pages, the size of this array
+ *     exceeds the rpc buffer limit. This control call will collect the data
+ *     in multiple passes. This parameter indicates the start index of the
+ *     data to be passed back to the caller
+ *     This cannot be greater than NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES
+ *   bMore
+ *     This parameter indicates whether there are more valid elements to be
+ *     fetched.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES (0x20801348U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */
+
+/* Maximum pages that can be dynamically blacklisted */
+#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES    512U
+
+/*
+ * Maximum entries that can be sent in a single pass of 
+ * NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES
+ */
+#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES  64U
+
+/**
+ * NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO
+ *   pageNumber
+ *     This output parameter specifies the dynamically blacklisted page number.
+ *   source
+ *     The reason for the page to be retired. Valid values for
+ *     this parameter include:
+ *        NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_INVALID
+ *           Invalid source.
+ *        NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE
+ *           Page retired by dynamic page retirement due to a double bit
+ *           error seen.
+ */
+typedef struct NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO {
+    NV_DECLARE_ALIGNED(NvU64 pageNumber, 8);
+    NvU8 source;
+} NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO;
+
+#define NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x48U)
+
+typedef struct NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES], 8);
+    NvU32  validEntries;
+    NvU32  baseIndex;
+    NvBool bMore;
+} NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS;
+
+/* valid values for source */
+
+#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID (0x00000000U)
+#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO
+ *
+ * This control command is used by clients to query information pertaining to client allocations.
+ *
+ *
+ * @params [IN/OUT] NvU64 allocCount:
+ *        Client specifies the allocation count that it received using the
+ *        previous NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO control call.
+ *        RM will get the total number of allocations known by RM and fill
+ *        allocCount with it.
+ *
+ * @params [IN] NvP64 pAllocInfo:
+ *        Pointer to the buffer allocated by client of size NV2080_CTRL_CMD_FB_ALLOCATION_INFO *
+ *        allocCount. RM returns the info pertaining to each  of the contiguous client
+ *        allocation chunks in pAllocInfo. The format of the allocation information is given by
+ *        NV2080_CTRL_CMD_FB_ALLOCATION_INFO. The client has to sort the returned information if
+ *        it wants to retain the legacy behavior of SORTED BY OFFSET. Information is only returned
+ *        if and only if allocCount[IN]>=allocCount[OUT] and clientCount[IN]>=clientCount[OUT].
+ *
+ * @params [IN/OUT] NvP64 clientCount:
+ *        Client specifies the client count that it received using the
+ *        previous NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO control call.
+ *        RM will get the total number of clients that have allocations with RM
+ *        and fill clientCount with it.
+ *
+ * @params [IN] NvP64 pClientInfo:
+ *        Pointer to the buffer allocated by client of size NV2080_CTRL_CMD_FB_CLIENT_INFO *
+ *        clientCount. RM returns the info pertaining to each of the clients that have allocations
+ *        known about by RM in pClientInfo. The format of the allocation information is given by
+ *        NV2080_CTRL_CMD_FB_CLIENT_INFO. Information is only returned if and only if
+ *        allocCount[IN]>=allocCount[OUT] and clientCount[IN]>=clientCount[OUT].
+ *
+ * @returns Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_POINTER
+ *   NV_ERR_NO_MEMORY
+ *
+ * @Usage: All privileged RM clients for debugging only. Initially, call this with allocCount =
+ *         clientCount = 0 to get client count, and then call again with allocated memory and sizes.
+ *         Client can repeat with the new count-sized allocations until a maximum try count is
+ *         reached or client is out of memory.
+ */
+
+#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO           (0x20801349U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * These work with the FLD_SET_REF_NUM and FLD_TEST_REF macros and describe the 'flags' member
+ * of the NV2080_CTRL_CMD_FB_ALLOCATION_INFO struct.
+ */
+
+// Address space of the allocation
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE 4:0
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM         0U
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM         1U
+
+// Whether the allocation is shared
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED 5:5
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE        0U
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE         1U
+
+// Whether this client owns this allocation
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER 6:6
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE         0U
+#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE          1U
+
+typedef struct NV2080_CTRL_CMD_FB_ALLOCATION_INFO {
+    NvU32 client;                        /* [OUT] Identifies the client that made or shares the allocation (index into pClientInfo)*/
+    NvU32 flags;                         /* [OUT] Flags associated with the allocation (see previous defines) */
+    NV_DECLARE_ALIGNED(NvU64 beginAddr, 8);   /* [OUT] Starting physical address of the chunk */
+    NV_DECLARE_ALIGNED(NvU64 size, 8);   /* [OUT] Size of the allocated contiguous chunk in bytes */
+} NV2080_CTRL_CMD_FB_ALLOCATION_INFO;
+
+typedef struct NV2080_CTRL_CMD_FB_CLIENT_INFO {
+    NvHandle handle;                                    /* [OUT] Handle of the client that made or shares the allocation */
+    NvU32    pid;                                       /* [OUT] PID of the client that made or shares the allocation */
+
+    /* For the definition of the subprocessID and subprocessName params, see NV0000_CTRL_CMD_SET_SUB_PROCESS_ID */
+    NvU32    subProcessID;                              /* [OUT] Subprocess ID of the client that made or shares the allocation */
+    char     subProcessName[NV_PROC_NAME_MAX_LENGTH];   /* [OUT] Subprocess Name of the client that made or shares the allocation */
+} NV2080_CTRL_CMD_FB_CLIENT_INFO;
+
+#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID (0x49U)
+
+typedef struct NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 allocCount, 8);
+    NV_DECLARE_ALIGNED(NvP64 pAllocInfo, 8);
+    NV_DECLARE_ALIGNED(NvU64 clientCount, 8);
+    NV_DECLARE_ALIGNED(NvP64 pClientInfo, 8);
+} NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS
+ *
+ * This control command is used by clients to update the NUMA status.
+ *
+ * @params [IN] NvBool bOnline:
+ *
+ * @returns Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *
+ */
+#define NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS (0x20801350U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID (0x50U)
+
+typedef struct NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS {
+    NvBool bOnline;
+} NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_NUMA_INFO
+ *
+ * This control command is used by clients to get per-subdevice or
+ * subscribed MIG partition(when MIG is enabled) NUMA memory information as
+ * assigned by the system.
+ *
+ * numaNodeId[OUT]
+ *     - Specifies the NUMA node ID.
+ *
+ * numaMemAddr[OUT]
+ *     - Specifies the NUMA memory address.
+ *
+ * numaMemSize[OUT]
+ *     - Specifies the NUMA memory size.
+ *
+ * numaOfflineAddressesCount[IN/OUT]
+ *     - If non-zero, then it specifies the maximum number of entries in
+ *       numaOfflineAddresses[] for which the information is required.
+ *       It will be updated with the actual number of entries present in
+ *       the numaOfflineAddresses[].
+ *
+ * numaOfflineAddresses[OUT]
+ *      - If numaOfflineAddressesCount is non-zero, it contains the addresses
+ *        of offline pages in the NUMA region.
+ *
+ * @returns Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_NUMA_INFO               (0x20801351U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64U
+
+#define NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID (0x51U)
+
+typedef struct NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS {
+    NvS32 numaNodeId;
+    NV_DECLARE_ALIGNED(NvU64 numaMemAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 numaMemSize, 8);
+    NvU32 numaOfflineAddressesCount;
+    NV_DECLARE_ALIGNED(NvU64 numaOfflineAddresses[NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES], 8);
+} NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT
+ *
+ * This control command is used by clients to get NV_SEMAPHORE_SURFACE layout/caps before allocation.
+ * A semaphore surface can be viewed as an array of independent semaphore entries.
+ *
+ * maxSubmittedSemaphoreValueOffset[OUT]
+ *     - An offset of the max submitted value, relative to the semaphore surface entry start, if used.
+ *       Used to emulate 64-bit semaphore values on chips where 64-bit semaphores are not supported.
+ *
+ * monitoredFenceThresholdOffset[OUT]
+ *     - An offset of the monitored fence memory, relative to the semaphore surface entry start, if supported.
+ *
+ * size[OUT]
+ *     - A size of a single semaphore surface entry.
+ *
+ * caps[OUT]
+ *     - A mask of NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_* values.
+ */
+#define NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT                             (0x20801352U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED  (0x00000001U)
+#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED (0x00000002U)
+
+#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID (0x52U)
+
+typedef struct NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 maxSubmittedSemaphoreValueOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 monitoredFenceThresholdOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32 caps;
+} NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE
+ *
+ * This control command is used by clients to commit TLB invalidates
+ *
+ * gfid[OUT]
+ *     - Specifices GPU function ID.
+ *
+ * invalidateAll[OUT]
+ *     - Specifies whether to invalidate all using boolean
+ *
+ * @returns Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE (0x20801353U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID (0x53U)
+
+typedef struct NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS {
+    NvU32  gfid;
+    NvBool invalidateAll;
+} NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS;
+
+// NV_FB_ALLOC_RM_INTERNAL_OWNER__MAX - NV_FB_ALLOC_RM_INTERNAL_OWNER__MIN //
+#define NV2080_CTRL_CMD_FB_STATS_MAX_OWNER 201U
+
+typedef struct NV2080_CTRL_CMD_FB_STATS_OWNER_INFO {
+    //! Total allocated size for this owner
+    NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
+
+    //! Total memory blocks belonging this owner
+    NvU32 numBlocks;
+
+    //! Total reserved size for this owner
+    NV_DECLARE_ALIGNED(NvU64 rsvdSize, 8);
+} NV2080_CTRL_CMD_FB_STATS_OWNER_INFO;
+
+#define NV2080_CTRL_CMD_RM_FB_STATS_ENTRY_MESSAGE_ID (0x2AU)
+
+typedef struct NV2080_CTRL_CMD_RM_FB_STATS_ENTRY {
+    //! RM reserved heap memory
+    NV_DECLARE_ALIGNED(NvU64 reservedHeap, 8);
+
+    //! Free RM heap memory (reserved but not allocated)
+    NV_DECLARE_ALIGNED(NvU64 reservedHeapFree, 8);
+
+    //! RM reserved memory
+    NV_DECLARE_ALIGNED(NvU64 reserved, 8);
+
+    //! owner info table
+    NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_STATS_OWNER_INFO fbBlockInfo[NV2080_CTRL_CMD_FB_STATS_MAX_OWNER], 8);
+} NV2080_CTRL_CMD_RM_FB_STATS_ENTRY;
+
+
+/*
+ * NV2080_CTRL_CMD_FB_STATS_GET
+ *
+ * Get the FB allocations info from CPU-RM and GSP-RM.
+ */
+#define NV2080_CTRL_CMD_FB_STATS_GET (0x2080132f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID (0x2FU)
+
+typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS {
+    //! Total physical memory available (accounts row-remapping)
+    NV_DECLARE_ALIGNED(NvU64 total, 8);
+
+    //! Total usable memory for OS/KMD
+    NV_DECLARE_ALIGNED(NvU64 os, 8);
+
+    //! GSP carveout size
+    NV_DECLARE_ALIGNED(NvU64 gspCarveout, 8);
+
+    //! misc reserved region size (console, vGPU-specific, CBC, etc.)
+    NV_DECLARE_ALIGNED(NvU64 miscReserved, 8);
+
+    //! CPU-RM sizes info
+    NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_RM_FB_STATS_ENTRY cpuFbInfo, 8);
+
+    //! GSP-RM sizes info
+    NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_RM_FB_STATS_ENTRY gspFbInfo, 8);
+} NV2080_CTRL_CMD_FB_STATS_GET_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GSP_FB_STATS_GET
+ *
+ * Get the FB allocations info from GSP-RM.
+ */
+#define NV2080_CTRL_CMD_GSP_FB_STATS_GET        (0x2080132a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_RM_FB_STATS_ENTRY_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO
+ *
+ * This command returns the GPU static BAR1 Info
+ * This is for general P2P DMA. NV50_P2P is for GPU P2P.
+ *
+ * @params [OUT] NvBool bStaticBar1Enabled:
+ *      This field indicates the static BAR1 mode is enabled. All the following fields are valid
+ *      only if static BAR1 mode is enabled.
+  * @params [OUT] NvU64 staticBar1StartOffset:
+ *      Static BAR1 may start at nonzero BAR1 address.
+ *      This field indicates the start offset of the static BAR1.
+ * @params [OUT] NvU64 staticBar1Size:
+ *      This field indicates the size of the static BAR1.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO (0x20801354U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID (0x54U)
+
+typedef struct NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS {
+    NvBool bStaticBar1Enabled;
+    NvBool bStaticBar1WriteCombined;
+    NV_DECLARE_ALIGNED(NvU64 staticBar1StartOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 staticBar1Size, 8);
+} NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION
+ *
+ * This command returns the current DRAM encryption configuration
+ * setting for a GPU given its subdevice handle.  The value returned
+ * is the current DRAM encryption setting for the GPU stored in non-volatile
+ * memory on the board.
+ *
+ *   currentConfiguration
+ *      The current DRAM encryption configuration setting.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION      (0x20801355U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED (0x00000000U)
+#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED  (0x00000001U)
+
+#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID (0x55U)
+
+typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS {
+    NvU32 currentConfiguration;
+} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION
+ *
+ * This command changes the DRAM encryption configuration setting for
+ * a GPU given its subdevice handle.  The value specified is stored
+ * in non-volatile memory on the board and will take effect with the
+ * next GPU reset.
+ *
+ *   newConfiguration
+ *     The new configuration setting to take effect with
+ *     the next GPU reset.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION     (0x20801356U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE (0x00000000U)
+#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE  (0x00000001U)
+
+#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID (0x56U)
+
+typedef struct NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS {
+    NvU32 newConfiguration;
+} NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT
+ *
+ * This command returns whether or not DRAM encryption config object is supported via the InfoROM.
+ *
+ *  isSupported [OUT]
+ *     This parameter returns whether the DRAM Encryption inforom object is present in the inforom.
+ *     The various values of isSupported is:
+ *         1. NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED
+ *         2. NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT          (0x20801357U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED (0x00000000U)
+#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED  (0x00000001U)
+
+#define NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID (0x57U)
+
+typedef struct NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS {
+    NvU32 isSupported;
+} NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS
+ *
+ * This command returns the current DRAM encryption status.
+ *
+ *   currentStatus
+ *      The current DRAM encryption status.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS          (0x20801358U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED (0x00000000U)
+#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED  (0x00000001U)
+
+#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID (0x58U)
+
+typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS {
+    NvU32 currentStatus;
+} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS
+ *
+ * This command returns the memory boot training flags from VBIOS table.
+ *
+ *  flagCollectSchmooData
+ *  flagWrTrHybridVrefEn
+ *  flagWrTrHybridNonVrefEn
+ *  flagRdTrHybridVrefEn
+ *  flagRdTrHybridNonVrefEn
+ *  skipBootTraining
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS (0x20801359U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID (0x59U)
+
+typedef struct NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS {
+    NvBool flagCollectSchmooData;
+    NvBool flagWrTrHybridVrefEn;
+    NvBool flagWrTrHybridNonVrefEn;
+    NvBool flagRdTrHybridVrefEn;
+    NvBool flagRdTrHybridNonVrefEn;
+    NvBool skipBootTraining;
+} NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS;
+
+/*
+ * NV2080_CTRL_FB_CMD_GET_CARVEOUT_REGION_INFO
+ *
+ * This command returns the carveout memory region characteristics.
+ *
+ *   numCarveoutRegions
+ *     Number of valid regions returned in carveoutRegion[].
+ *   carveoutRegion[].base
+ *     Base address of carveout memory region.
+ *   carveoutRegion[].size
+ *     size of carveout memory region.
+ *   carveoutType
+ *     carveout type for carveout memory region.
+ *
+ *   Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_CARVEOUT_REGION_INFO (0x20801360U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE {
+    NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM = 0,
+    NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM_RESERVED = 1,
+    NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_UEFI = 2,
+} NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE;
+
+typedef struct NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE carveoutType;
+} NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO;
+
+#define NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_MAX_ENTRIES 8U
+
+#define NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS_MESSAGE_ID (0x60U)
+
+typedef struct NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS {
+    NvU32 numCarveoutRegions;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO carveoutRegion[NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_MAX_ENTRIES], 8);
+} NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS;
+
+/* valid values for source */
+
+
+#define NV2080_CTRL_FB_REMAPPED_BANK_SOURCE_FIELD          (0x00000002U)
+
+#define NV2080_CTRL_FB_REMAPPED_BANKS_MAX_BANKS            (0x00000200U)
+
+typedef struct NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM {
+    NvU32 maxGroupCount;
+    NvU32 noSpareGroupCount;
+} NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_REMAPPED_BANKS
+ *
+ * This command returns the list of remapped banks stored in the Inforom.
+ *
+ *   entryCount
+ *     This output parameter specifies the number of remapped banks
+ *   flags
+ *     This output parameter contains info on whether or not there are pending
+ *     remappings and whether or not a remapping failed
+ *   histogram
+ *     This output parameter contains the group histogram of bank remapper.
+ *   entries
+ *     This output parameter is an array of NV2080_CTRL_FB_BANK_REMAP_ENTRY
+ *     containing inforomation on the remapping that occurred. This array can
+ *     hold a maximum of NV2080_CTRL_FB_REMAPPED_BANKS_MAX_BANKS
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_INVALID_POINTER
+ *    NV_ERR_OBJECT_NOT_FOUND
+ *    NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FB_GET_REMAPPED_BANKS                 (0x20801361U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_REMAPPED_BANKS_FLAGS_PENDING                         0:0
+#define NV2080_CTRL_FB_GET_REMAPPED_BANKS_FLAGS_PENDING_FALSE 0U
+#define NV2080_CTRL_FB_GET_REMAPPED_BANKS_FLAGS_PENDING_TRUE  1U
+
+typedef struct NV2080_CTRL_FB_BANK_REMAP_ENTRY {
+    NvU32 remapRegVal;
+    NvU32 timestamp;
+    NvU8  fbpa;
+    NvU8  channel;
+    NvU8  pseudoChannel;
+    NvU8  group;
+    NvU8  source;
+    NvU8  flags;
+} NV2080_CTRL_FB_BANK_REMAP_ENTRY;
+
+#define NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS_MESSAGE_ID (0x61U)
+
+typedef struct NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS {
+    NvU32                               entryCount;
+    NvU8                                flags;
+    NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM histogram;
+    NV2080_CTRL_FB_BANK_REMAP_ENTRY     entries[NV2080_CTRL_FB_REMAPPED_BANKS_MAX_BANKS];
+} NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GET_UGPU_MEMORY_INFO
+ *
+ * @brief Returns free nonlocalized memory available as well as localizable memory available per uGPU.
+ *
+ * @param[out]  totalMemory Total memory available for nonlocalized allocations.
+ *                          Identical to NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE when PMA is enabled.
+ * @param[out]  freeMemory Free memory available for nonlocalized allocations.
+ *                         Identical to NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE when PMA is enabled.
+ * @param[out]  ugpuTotalMemory Array of total memory sizes available for localized allocations per uGPU.
+ *                              Analogous to NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE, but relects memory available to each uGPU.
+ * @param[out]  ugpuFreeMemory  Array of free memory sizes available for localized allocations per uGPU.
+ *                              Analogous to NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE, but relects memory available to each uGPU.
+ *
+ * @return NV_OK, NV_ERR_NOT_SUPPORTED if localization is not supported.
+ */
+#define NV2080_CTRL_CMD_FB_GET_UGPU_MEMORY_INFO       (0x20801362U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_MAX_UGPUS 2U
+
+#define NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS_MESSAGE_ID (0x62U)
+
+typedef struct NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 totalMemory, 8);
+    NV_DECLARE_ALIGNED(NvU64 freeMemory, 8);
+    NV_DECLARE_ALIGNED(NvU64 ugpuTotalMemory[NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_MAX_UGPUS], 8);
+    NV_DECLARE_ALIGNED(NvU64 ugpuFreeMemory[NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_MAX_UGPUS], 8);
+} NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_CPU_COHERENT_RANGE
+ *
+ * This command returns the CPU-coherent FB range.
+ * Only applicable on self-hosted platforms.
+ *
+ *   coherentCpuFbBase
+ *     FB offset of the start of the CPU-coherent range
+ *   coherentCpuFbEnd
+ *     FB offset of the end (exclusive) of the CPU-coherent range
+ */
+#define NV2080_CTRL_CMD_FB_GET_CPU_COHERENT_RANGE (0x20801363U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS_MESSAGE_ID (0x63U)
+
+typedef struct NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 coherentCpuFbBase, 8);
+    NV_DECLARE_ALIGNED(NvU64 coherentCpuFbEnd, 8);
+} NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FB_GET_WPR_REGION_INFO
+ *
+ * This command returns information about WPR regions.
+ *
+ *   wpr1Start
+ *     FB offset of the start of WPR1
+ *   wpr1End
+ *     FB offset of the end (exclusive) of WPR1
+ *   wpr2Start
+ *     FB offset of the start of WPR1
+ *   wpr2End
+ *     FB offset of the end (exclusive) of WPR1
+ *   fbRegionOfWpr2Start
+ *     FB offset of the start of the FB region (as tracked by RM) that contains WPR2
+ */
+#define NV2080_CTRL_CMD_FB_GET_WPR_REGION_INFO (0x20801364U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS_MESSAGE_ID (0x64U)
+
+typedef struct NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 wpr1Start, 8);
+    NV_DECLARE_ALIGNED(NvU64 wpr1End, 8);
+    NV_DECLARE_ALIGNED(NvU64 wpr2Start, 8);
+    NV_DECLARE_ALIGNED(NvU64 wpr2End, 8);
+    NV_DECLARE_ALIGNED(NvU64 fbRegionOfWpr2Start, 8);
+} NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS;
+
+/* _ctrl2080fb_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fifo.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fifo.h
new file mode 100644
index 0000000..e0d6c0a
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fifo.h
@@ -0,0 +1,1140 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080fifo.finn
+//
+
+#include "nvcfg_sdk.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/*
+ * NV2080_CTRL_CMD_SET_GPFIFO
+ *
+ * This command set the GPFIFO offset and number of entries for a channel
+ * after it has been allocated. The channel must be idle and not pending,
+ * otherwise ERROR_IN_USE will be returned.
+ *
+ *   hChannel
+ *     The handle to the channel.
+ *   base
+ *     The base of the GPFIFO in the channel ctxdma.
+ *   numEntries
+ *     The number of entries in the GPFIFO.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_CHANNEL
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV2080_CTRL_CMD_SET_GPFIFO (0x20801102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_CMD_SET_GPFIFO_PARAMS {
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NvU32    numEntries;
+} NV2080_CTRL_CMD_SET_GPFIFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT
+ *
+ * This command returns the maximum number of physical channels available for
+ * allocation on the current GPU.  This may be less than or equal to the total
+ * number of channels supported by the current hardware.
+ *
+ * physChannelCount
+ *   This output parameter contains the maximum physical channel count.
+ *
+ *   physChannelCountInUse
+ *     This output parameter contains the number of physical channels in use
+ *
+ * Possible return status values returned are
+ *   NV_OK
+ *
+ */
+#define NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT (0x20801108) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS {
+    NvU32 physChannelCount;
+    NvU32 physChannelCountInUse;
+} NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS;
+
+/*
+ * NV2080_CTRL_FIFO_INFO
+ *
+ * This structure represents a single 32bit fifo engine value.  Clients
+ * request a particular FIFO engine value by specifying a unique fifo
+ * information index.
+ *
+ * Legal fifo information index values are:
+ *   NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL
+ *     This index can be used to request the amount of instance space
+ *     in kilobytes reserved by the fifo engine.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS
+ *     This index can be used to query the maximum number of channel groups
+ *     that can be allocated on the GPU.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP
+ *     This index can be used to query the maximum number of channels that can
+ *    be allocated in a single channel group.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP
+ *     This index can be used to query the maximum number of subcontext that can
+ *     be allocated in a single channel group.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET
+ *     This index can be used to query the starting offset of the RM
+ *     pre-allocated USERD range in BAR1. This index query is honored only
+ *     on Legacy-vGPU host RM.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE
+ *     This index can be used to query the default timeslice value
+ *     (microseconds) used for a channel or channel group.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE
+ *     This index can be used to query the number of channel groups that are
+ *     already allocated on the GPU.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED
+ *     This index can be used to check if per runlist channel ram is supported, and
+ *     to query the supported number of channels per runlist.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE
+ *     This index can be used to get max channel groups supported per engine/runlist.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE
+ *     This index can be used too get channel groups currently in use per engine/runlist.
+ *   NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT
+ *     This index can be used to query the maximum "lower" subcontext index
+ *     allocated under NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER.
+ *     Note: Includes subcontext ID 0, which will be allocated last in ASYNC allocation mode.
+ *
+ */
+typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO;
+
+/* valid fifo info index values */
+#define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL                       (0x000000000)
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS                   (0x000000001)
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP               (0x000000002)
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP             (0x000000003)
+#define NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET              (0x000000004)
+#define NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE            (0x000000005)
+#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE                (0x000000006)
+#define NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED (0x000000007)
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE        (0x000000008)
+#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE     (0x000000009)
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT                 (0x00000000a)
+
+
+/* set INDEX_MAX to greatest possible index value */
+#define NV2080_CTRL_FIFO_INFO_INDEX_MAX                                  NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT
+
+#define NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT                     (12)
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_INFO
+ *
+ * This command returns fifo engine information for the associated GPU.
+ * Requests to retrieve fifo information use an array of one or more
+ * NV2080_CTRL_FIFO_INFO structures.
+ *
+ *   fifoInfoTblSize
+ *     This field specifies the number of valid entries in the fifoInfoList
+ *     array.  This value cannot exceed NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES.
+ *   fifoInfoTbl
+ *     This parameter contains the client's fifo info table into
+ *     which the fifo info values will be transferred by the RM.
+ *     The fifo info table is an array of NV2080_CTRL_FIFO_INFO structures.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FIFO_GET_INFO                                    (0x20801109) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum number of NV2080_CTRL_FIFO_INFO entries per request */
+#define NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES                            (256)
+
+#define NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_FIFO_GET_INFO_PARAMS {
+    NvU32                 fifoInfoTblSize;
+    /*
+     * C form:
+     * NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES];
+     */
+    NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES];
+    NvU32                 engineType;
+} NV2080_CTRL_FIFO_GET_INFO_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL
+ *
+ * This command removes the specified channel from the associated GPU's runlist
+ * and then initiates RC recovery.  If the channel is active it will first be preempted.
+ *   hChannel
+ *     The handle to the channel to be preempted.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_CHANNEL
+ */
+#define NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL (0x2080110a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS {
+    NvHandle hChannel;
+} NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS
+ *
+ * This command will disable or enable scheduling of channels described in the
+ * list provided. Whether or not the channels are also preempted off the GPU
+ * can be controlled by bOnlyDisableScheduling. By default channels are preempted
+ * off the GPU.
+ *
+ *  bDisable
+ *      This value determines whether to disable or
+ *      enable the set of channels.
+ *  numChannels
+ *      The number of channels to be stopped.
+ *  bOnlyDisableScheduling
+ *      When false and bDisable=NV_TRUE,the call will ensure none of the listed
+ *      channels are running in hardware and will not run until a call with
+ *      bDisable=NV_FALSE is made. When true and bDisable=NV_TRUE, the control
+ *      call will ensure that none of the listed channels can be scheduled on the
+ *      GPU until a call with bDisable=NV_FALSE is made, but will not remove any
+ *      of the listed channels from hardware if they are currently running. When
+ *      bDisable=NV_FALSE this field is ignored.
+ *  bRewindGpPut
+ *      If a channel is being disabled and bRewindGpPut=NV_TRUE, the channel's RAMFC
+ *      will be updated so that GP_PUT is reset to the value of GP_GET.
+ *  hClientList
+ *      An array of NvU32 listing the client handles
+ *  hChannelList
+ *      An array of NvU32 listing the channel handles
+ *      to be stopped.
+ *  pRunlistPreemptEvent
+ *      KEVENT handle for Async HW runlist preemption (unused on preMaxwell)
+ *      When NULL, will revert to synchronous preemption with spinloop
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NVOS_INVALID_STATE
+ */
+
+#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS         (0x2080110b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES (64)
+
+#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS {
+    NvBool   bDisable;
+    NvU32    numChannels;
+    NvBool   bOnlyDisableScheduling;
+    NvBool   bRewindGpPut;
+    NV_DECLARE_ALIGNED(NvP64 pRunlistPreemptEvent, 8);
+    // C form:  NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]
+    NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES];
+    // C form:  NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]
+    NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES];
+} NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS;
+
+#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE         (0x00000000)
+#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE          (0x00000001)
+#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE (0x00000000)
+#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE  (0x00000001)
+
+/*
+ * NV2080_CTRL_FIFO_MEM_INFO
+ *
+ * This structure describes the details of a block of memory. It consists
+ * of the following fields
+ *
+ * aperture
+ *   One of the NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_* values
+ * base
+ *   Physical base address of the memory
+ * size
+ *   Size in bytes of the memory
+*/
+typedef struct NV2080_CTRL_FIFO_MEM_INFO {
+    NvU32 aperture;
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+} NV2080_CTRL_FIFO_MEM_INFO;
+
+/*
+ * NV2080_CTRL_FIFO_CHANNEL_MEM_INFO
+ *
+ * This structure describes the details of the instance memory, ramfc
+ * and method buffers a channel. It consists of the following fields
+ *
+ *   inst
+ *     Structure describing the details of instance memory
+ *   ramfc
+ *     Structure describing the details of ramfc
+ *   methodBuf
+ *     Array of structures describing the details of method buffers
+ *   methodBufCount
+ *     Number of method buffers(one per runqueue)
+ */
+
+// max runqueues
+#define NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT 0x2
+
+typedef struct NV2080_CTRL_FIFO_CHANNEL_MEM_INFO {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO inst, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO ramfc, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO methodBuf[NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT], 8);
+    NvU32 methodBufCount;
+} NV2080_CTRL_FIFO_CHANNEL_MEM_INFO;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM
+ *
+ * This command returns the memory aperture, physical base address and the
+ * size of each of the instance memory, cache1 and ramfc of a channel.
+ *
+ *   hChannel
+ *     The handle to the channel for which the memory information is desired.
+ *   chMemInfo
+ *     A NV2080_CTRL_FIFO_CHANNEL_MEM_INFO structure
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_CHANNEL
+*/
+
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO (0x2080110c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS {
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_CHANNEL_MEM_INFO chMemInfo, 8);
+} NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID     0x00000000
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM      0x00000001
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH  0x00000002
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH 0x00000003
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION
+ *
+ *    This command determines the location (vidmem/sysmem)
+ *    and attribute (cached/uncached/write combined) of memory where USERD is located.
+ *
+ *   aperture
+ *     One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_* values.
+ *
+ *   attribute
+ *     One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_* values.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_POINTER
+*/
+
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION                   (0x2080110d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS {
+    NvU32 aperture;
+    NvU32 attribute;
+} NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS;
+
+// support for CPU coherent vidmem (VIDMEM_NVILINK_COH) is not yet available in RM
+
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM         0x00000000
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM         0x00000001
+
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED        0x00000000
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED      0X00000001
+#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002
+
+
+#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN                   0
+#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER                     1
+#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT               2
+#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE               3
+#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE               4
+
+// Count of the supported vGPU scheduler policies
+#define NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT           3
+
+#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT                      0
+#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE                      1
+#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE                       2
+
+/*
+ * NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG
+ *
+ * This command returns the OBJSCHED_SW log enties.
+ *
+ *   engineId
+ *     This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log
+ *     entries are to be fetched.
+ *
+ *   count
+ *     This field returns the count of log entries fetched.
+ *
+ *   entry
+ *     The array of SW runlist log entries.
+ *
+ *       timestampNs
+ *         Timestamp in ns when this SW runlist was preeempted.
+ *
+ *       timeRunTotalNs
+ *         Total time in ns this SW runlist has run as compared to others.
+ *
+ *       timeRunNs
+ *         Time in ns this SW runlist ran before preemption.
+ *
+ *       swrlId
+ *         SW runlist Id.
+ *
+ *   schedPolicy
+ *     This field returns the runlist scheduling policy. It specifies the
+ *     NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
+ *
+ *   arrEnabled
+ *     This field returns if Adaptive round robin scheduler
+ *     is enabled/disabled.
+ *
+ *   arrAvgFactor
+ *     This field returns the average factor to be used in compensating the timeslice
+ *     for Adaptive scheduler mode.
+ *
+ *  targetTimesliceNs
+ *      This field returns the target timeslice duration in ns for each SW runlist
+ *      as configured by the user or the default value otherwise.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+*/
+
+#define NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG                        (0x2080110e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT                              32
+#define NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS                          8
+#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES                    200
+
+typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY {
+    NV_DECLARE_ALIGNED(NvU64 timestampNs, 8);
+    NV_DECLARE_ALIGNED(NvS64 timeRunTotalNs, 8);
+    NvU32 timeRunNs;
+    NvU32 swrlId;
+    NvU32 targetTimeSlice;
+    NV_DECLARE_ALIGNED(NvU64 cumulativePreemptionTime, 8);
+    NV_DECLARE_ALIGNED(NvU64 cumulativeIdleTime, 8);
+    NvU32 weight;
+    NV_DECLARE_ALIGNED(NvU64 counters[NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS], 8);
+} NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY;
+
+#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS {
+    NvU32 engineId;
+    NvU32 count;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY entry[NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES], 8);
+    NvU32 schedPolicy;
+    NvU32 arrEnabled;
+    NvU32 arrAvgFactor;
+    NvU32 targetTimesliceNs;
+} NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS;
+
+
+
+
+/*
+ * NV2080_CTRL_CMD_FIFO_CONFIG_CTXSW_TIMEOUT
+ *
+ * This command can be used to enable and set the engine
+ * context switch timeout
+ *
+ * timeout: Timeout in number of microsec PTIMER ticks
+ * 1 microsec PTIMER tick = 1024 PTIMER nanoseconds
+ * bEnable: TRUE/FALSE
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+*/
+
+#define NV2080_CTRL_CMD_FIFO_CONFIG_CTXSW_TIMEOUT (0x20801110) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS {
+    NvU32  timeout;
+    NvBool bEnable;
+} NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE
+ *
+ *  This command retrieves entries from the SW encoded GPU device info table
+ *  from Host RM.
+ *
+ *  Parameters:
+ *
+ *    baseIndex [in]
+ *      The starting index to read from the devinfo table. Must be a multiple of
+ *      MAX_ENTRIES.
+ *
+ *    entries [out]
+ *      A buffer to store up to MAX_ENTRIES entries of the devinfo table.
+ *
+ *    numEntries [out]
+ *      Number of populated entries in the provided buffer.
+ *
+ *    bMore [out]
+ *      A boolean flag indicating whether more valid entries are available to be
+ *      read. A value of NV_TRUE indicates that a further call to this control
+ *      with baseIndex incremented by MAX_ENTRIES will yield further valid data.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ */
+#define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE                 (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES         256
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES         32
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES   16
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA    2
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16
+
+/*
+ * NV2080_CTRL_FIFO_DEVICE_ENTRY
+ *
+ * This structure contains the engine, engine name and
+ * push buffers information of FIFO device entry. It consists of the following fields
+ *
+ *   engineData
+ *     Type of the engine
+ *   pbdmaIds
+ *     List of pbdma ids associated with engine
+ *   pbdmaFaultIds
+ *     List of pbdma fault ids associated with engine
+ *   numPbdmas
+ *     Number of pbdmas
+ *   engineName
+ *     Name of the engine
+ */
+typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY {
+    NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES];
+    NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
+    NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
+    NvU32 numPbdmas;
+    char  engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN];
+} NV2080_CTRL_FIFO_DEVICE_ENTRY;
+
+#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS {
+    NvU32                         baseIndex;
+    NvU32                         numEntries;
+    NvBool                        bMore;
+    // C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
+    NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
+} NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT
+ *
+ *  This command clears the ENGINE or PBDMA FAULTED bit and reschedules the faulted channel
+ *  by ringing channel's doorbell
+ *
+ *  Parameters:
+ *
+ *    engineType [in]
+ *      The NV2080_ENGINE_TYPE of the engine to which the faulted
+ *      channel is bound. This may be a logical id for guest RM in
+ *      case of SMC.
+ *
+ *    vChid [in]
+ *      Virtual channel ID on which the fault occurred
+ *
+ *    faultType [in]
+ *      Whether fault was triggered by engine (_ENGINE_FAULTED) or PBDMA (_PBDMA_FAULTED)
+ *      The value specified must be one of the NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_* values
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_STATE
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT               (0x20801113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE 0x00000001
+#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA  0x00000002
+
+#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS {
+    NvU32 engineType;
+    NvU32 vChid;
+    NvU32 faultType;
+} NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY
+ *
+ * Allows clients to set the global scheduling policy for all runlists
+ * associated to the given subdevice.
+ *
+ * Currently, this is only supported for HW runlists.
+ *
+ * Since this is a global setting, only privileged clients will be allowed to
+ * set it. Regular clients will get NV_ERR_INSUFFICIENT_PERMISSIONS error.
+ *
+ * Once a certain scheduling policy is set, that policy cannot be changed to a
+ * different one unless all clients which set it have either restored the policy
+ * (using the corresponding restore flag) or died. Clients trying to set a
+ * policy while a different one is locked by another client will get a
+ * NV_ERR_INVALID_STATE error.
+ *
+ * The same client can set a scheduling policy and later change to another one
+ * only when no other clients have set the same policy. Such sequence will be
+ * equivalent to restoring the policy in between.
+ *
+ * For instance, the following sequence:
+ *
+ *      1. Set policy A
+ *      2. Set policy B
+ *
+ * is equivalent to:
+ *
+ *      1. Set policy A
+ *      2. Restore policy
+ *      3. Set policy B
+ *
+ * Parameters:
+ *
+ *   flags
+ *     This field specifies the operational properties to be applied:
+ *
+ *      - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE
+ *          Try to set the provided 'schedPolicy' scheduling policy. If the
+ *          operation succeeds, other clients will be prevented from setting a
+ *          different scheduling policy until all clients using it have either
+ *          restored it or died.
+ *
+ *      - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE
+ *          Let the scheduler know the client no longer requires the current
+ *          scheduling policy. This may or may not actually change the
+ *          scheduling policy, depending on how many other clients are also
+ *          using the current policy.
+ *
+ *          The 'schedPolicy' parameter is ignored when this flag is set.
+ *
+ *   schedPolicy
+ *     One of:
+ *
+ *      - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT
+ *          Set the default scheduling policy and prevent other clients from
+ *          changing it.
+ *
+ *      - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED
+ *          This scheduling policy will make channels to be scheduled according
+ *          to their interleave level. See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL
+ *          description for more details.
+ *      - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM
+ *          This scheduling policy will make channels to be scheduled according
+ *          to their interleave level per WDDM policy.
+ *          See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY                     (0x20801115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID" */
+
+/* schedPolicy values */
+#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT                     0x0
+#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED         0x1
+#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM    0x2
+
+/* SET_SCHED_POLICY flags */
+#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE        0:0
+#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE (0x00000000)
+#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE  (0x00000001)
+
+#define NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS {
+    NvU32 flags;
+    NvU32 schedPolicy;
+} NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO
+ *
+ *  This command updates the channel info params for an existing channel
+ *
+ *  Can be a deferred Api. The control call can be used for migrating a
+ *
+ *  channel to a new userd and gpfifo
+ *
+ *  Parameters:
+ *     [in] hClient  - Client handle
+ *     [in] hChannel - Channel handle
+ *     [in] hUserdMemory  - UserD handle
+ *     [in] gpFifoEntries - Number of Gpfifo Entries
+ *     [in] gpFifoOffset  - Gpfifo Virtual Offset
+ *     [in] userdOffset   - UserD offset
+ *
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_STATE
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO (0x20801116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS {
+    NvHandle hClient;
+    NvHandle hChannel;
+    NvHandle hUserdMemory;
+    NvU32    gpFifoEntries;
+    NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 userdOffset, 8);
+} NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS
+ *
+ * This command will disable or enable scheduling of all usermode channels.
+ *
+ *  bDisable
+ *      This value determines whether to disable or enable the usermode channels.
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS (0x20801117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID (0x17U)
+
+typedef struct NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS {
+    NvBool bDisable;
+} NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB
+ *
+ * When a VF subcontext is marked as a zombie, host RM points its PDB to a dummy
+ * page allocated by guest RM in GPA space. This command provides the parameters
+ * of the guest RMs memory descriptor to be able to create a corresponding
+ * memory descriptor on the host RM. Host RM uses this to program the PDB of a
+ * zombie subcontext.
+ *
+ *  Parameters:
+ *  Input parameters to describe the memory descriptor
+ *     [in] base
+ *     [in] size
+ *     [in] addressSpace
+ *     [in] cacheAttrib
+ */
+#define NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB (0x20801118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32 addressSpace;
+    NvU32 cacheAttrib;
+} NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS
+ *
+ * Get's a bitmask of allocated channels. No guarantees are made about
+ * synchronization. A channel returned as allocated by this ctrl cmd might have
+ * already been destructed.
+ *
+ * Parameters:
+ * [in]     runlistId
+ * [in,out] bitMask   A 1 bit indicates that a channel with this index/id is
+ *                    allocated. This field is a multiple of 32 bits and each 32
+ *                    bit group must be accessed as a platform 32 bit int to
+ *                    correctly map channel IDs.
+ *
+ */
+#define NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS          (0x20801119) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID" */
+
+/*
+ * The maximum number than can be returned by
+ * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS
+ */
+#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS 4096
+
+#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS {
+    NvU32 runlistId;
+    NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32];
+} NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION
+ *
+ * This command will disable and preempt channels described in the
+ * list provided and mark them ready for key rotation.
+ * hClient <-> hChannel pairs should use the same index in the arrays.
+ *
+ *  numChannels
+ *      The number of valid entries in hChannelList array.
+ *  hClientList
+ *      An array of NvHandle listing the client handles
+ *  hChannelList
+ *      An array of NvHandle listing the channel handles
+ *      to be stopped.
+ *  bEnableAfterKeyRotation
+ *      This determines if channel is enabled by RM after it completes key rotation.
+ * Possible status values returned are:
+ *    NV_OK
+ *    NVOS_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION         (0x2080111a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES (64)
+
+#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0x1AU)
+
+typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS {
+    NvU32    numChannels;
+    NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
+    NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
+    NvBool   bEnableAfterKeyRotation;
+} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2
+ *
+ * This command does the same thing as @ref NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION.
+ * The difference is that it doesn't take a list of clients and instead all channels belong
+ * to the client on which this control call is made.
+ *
+ *  numChannels
+ *      The number of valid entries in hChannelList array.
+ *  hChannelList
+ *      An array of NvHandle listing the channel handles
+ *      to be stopped.
+ *  bEnableAfterKeyRotation
+ *      This determines if channel is enabled by RM after it completes key rotation.
+ * Possible status values returned are:
+ *    NV_OK
+ *    NVOS_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 (0x2080111b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID (0x1BU)
+
+typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS {
+    NvU32    numChannels;
+    NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
+    NvBool   bEnableAfterKeyRotation;
+} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_ROTATE_KEYS
+ *
+ * This command will disable and preempt channels described in the
+ * list provided and force key rotation on these channels.
+ * hClient <-> hChannel pairs should use the same index in the arrays.
+ * This control call is only for Blackwell and newer GPUs.
+ *
+ *  numChannels
+ *      The number of valid entries in hChannelList array.
+ *  hClientList
+ *      An array of NvHandle listing the client handles
+ *  hChannelList
+ *      An array of NvHandle listing the channel handles
+ *      to be stopped.
+ *  bEnableAfterKeyRotation
+ *      This determines if channel is enabled by RM after it completes key rotation.
+ * Possible status values returned are:
+ *    NV_OK
+ *    NVOS_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_FIFO_ROTATE_KEYS (0x2080111c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS_MESSAGE_ID (0x1CU)
+
+typedef struct NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS {
+    NvU32    numChannels;
+    NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
+    NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
+    NvBool   bEnableAfterKeyRotation;
+} NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE
+ *
+ * This command returns the vGPU schedular state.
+ *
+ *   engineId
+ *     This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log
+ *     entries are to be fetched.
+ *
+ *   schedPolicy
+ *     This field returns the runlist scheduling policy. It specifies the
+ *     NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
+ *
+ *   arrEnabled
+ *     This field returns if Adaptive round robin scheduler
+ *     is enabled/disabled.
+ *
+ *  targetTimesliceNs
+ *      This field returns the target timeslice duration in ns for each SW runlist
+ *      as configured by the user or the default value otherwise.
+ *
+ *   arrAvgFactor
+ *     This field returns the average factor to be used in compensating the timeslice
+ *     for Adaptive scheduler mode.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE (0x20801120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS {
+    NvU32 engineId;
+    NvU32 schedPolicy;
+    NvU32 arrEnabled;
+    NvU32 targetTimesliceNs;
+    NvU32 arrAvgFactor;
+} NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE
+ *
+ * This command set the vGPU schedular state.
+ *
+ *  engineId
+ *     This field specifies the NV2080_ENGINE_TYPE_* engine.
+ *
+ *  schedPolicy
+ *    This field sets the runlist scheduling policy. It specifies the
+ *    NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
+ *
+ *  enableArr
+ *    This field sets the Adaptive round robin scheduler
+ *    is enabled/disabled.
+ *
+ *  timesliceTargetNs
+ *    This field sets the time slice target time in ns.
+ *
+ *  frequencyForARR
+ *    This field sets the scheduling frequency for Adaptive round robin scheduler mode.
+ *
+ *  avgFactorForARR
+ *    This field sets the average factor to be used in compensating the timeslice
+ *    for Adaptive scheduler mode.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_DEVICE
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE (0x20801121) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS {
+    NvU32 engineId;
+    NvU32 schedPolicy;
+    NvU32 enableArr;
+    NvU32 timesliceTargetNs;
+    NvU32 frequencyForARR;
+    NvU32 avgFactorForARR;
+} NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS
+ *
+ * This command returns the vGPU schedular capabilities.
+ *
+ *   engineId [in]
+ *     This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log
+ *     entries are to be fetched.
+ *
+ *   supportedSchedulers [out]
+ *     This field returns the supported runlist scheduling policies on the device.
+ *     It specifies the NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
+ *
+ *   bIsArrModeSupported [out]
+ *     This field returns if Adaptive scheduler mode is enabled/disabled.
+ *
+ *   maxTimesliceNs [out]
+ *      This field returns the maximum time slice value in ns.
+ *
+ *   minTimesliceNs [out]
+ *     This field returns the minimum time slice value in ns.
+ *
+ *   maxFrequencyForARR [out]
+ *     This field returns the maximum scheduling frequency for
+ *     Adaptive round robin scheduler mode.
+ *
+ *   minFrequencyForARR [out]
+ *     This field returns the minimum scheduling frequency for
+ *     Adaptive round robin scheduler mode.
+ *
+ *   maxAvgFactorForARR [out]
+ *     This field returns the maximum average factor in compensating
+ *     the timeslice for Adaptive scheduler mode.
+ *
+ *   minAvgFactorForARR [out]
+ *     This field returns the minimum average factor in compensating
+ *     the timeslice for Adaptive scheduler mode.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS (0x20801122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS {
+    NvU32  engineId;
+    NvU32  supportedSchedulers[NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT];
+    NvBool bIsArrModeSupported;
+    NvU32  maxTimesliceNs;
+    NvU32  minTimesliceNs;
+    NvU32  maxFrequencyForARR;
+    NvU32  minFrequencyForARR;
+    NvU32  maxAvgFactorForARR;
+    NvU32  minAvgFactorForARR;
+} NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS;
+
+// Max channels per group is limited by NV_RAMRL_ENTRY_TSG_LENGTH_MAX for the arch.
+#define NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG             128
+
+/*
+ * NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO
+ *   hClient
+ *      Input parameter
+ *      This parameter specifies the client handle associated input channel/TSG
+ *   hChannelOrTsg
+ *     Input parameter.
+ *     This parameter specifies the handle of input channel handle (or channel
+ *     group)
+ *   tsgId
+ *     Output parameter.
+ *     This field return the Unique of TSG object if user specified a channel group handle
+ *     with hChannelOrTsg.
+ *   numChannels
+ *     Output parameter.
+ *     This field return the number of channels under TSG if user specify a
+ *     channel group handle or return 1 if user specify a channel handle.
+ *   channelUniqueID
+ *     Output parameter.
+ *     This array field returns unique Channel ID for each channel.
+ *   vasUniqueID
+ *     Output parameter.
+ *     This array field returns unique IDs of VA Space objects of channels under TSG or channel.
+ *   veid
+ *     Output parameter.
+ *     This array field returns VEID for channels under TSG or channel.
+ */
+#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO (0x20801123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS {
+    NvHandle hClient;
+    NvHandle hChannelOrTsg;
+    NvU32    tsgId;
+    NvU32    numChannels;
+    NvU32    channelUniqueID[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
+    NvU32    vasUniqueID[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
+    NvU32    veid[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
+} NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID
+ * This command is used query the CID (channel ID) in batch
+ *   hClients
+ *      Input parameter
+ *      Array of Client handles
+ *   hChannels
+ *      Input parameter
+ *      Array of Channel handles
+ *   numChannels
+ *      Indicates the number of input client, channel handle pairs.
+ *   channelUniqueIDs
+ *     Output parameter.
+ *     This parameter returns an array of unique Channel IDs for each input pair.
+ *     channel handles.
+ */
+#define NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID (0x20801124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS {
+    NvHandle hClients[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
+    NvHandle hChannels[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
+    NvU32    numChannels;
+    NvU32    channelUniqueIDs[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
+} NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS;
+/* _ctrl2080fifo_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fla.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fla.h
new file mode 100644
index 0000000..1f0c86a
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fla.h
@@ -0,0 +1,208 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080fla.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX FLA control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_FLA_RANGE
+ *
+ * This command is used to initialize/destroy FLA VAS for a GPU.This is intended
+ * to be used by RM clients that manages the FLA VASpace range. The mode of the
+ * command is decided based on the parameter passed by the client.
+ *
+ *    base
+ *         This parameter specifies the base of the FLA VAS that needs to be allocated
+ *         for this GPU
+ *
+ *    size
+ *         This parameter specifies the size of the FLA VAS that needs to be allocated
+ *         for this GPU
+ *
+ *    mode
+ *         This parameter specifies the functionality of the command.
+ *           MODE_INITIALIZE
+ *             Setting this mode, will initialize the FLA VASpace for the gpu with
+ *             base and size passed as arguments. FLA VASpace will be owned by RM.
+ *             if the client calls the command more than once before destroying
+ *             the FLA VAS, then this command will verify the range exported before and
+ *             return success if it matches. If FLA is not supported for the platform,
+ *             will return NV_ERR_NOT_SUPPORTED.
+ *           MODE_DESTROY (deprecated)
+ *             This command is NOP.
+ *           MODE_HOST_MANAGED_VAS_INITIALIZE
+ *             This mode will initialize the FLA VASpace for the gpu with hVASpace
+ *             handle in addition to base and size arguments. FLA VASpace will be initiated 
+ *             and owned by guest RM. Used only in virtualization platforms by internal clients.
+ *           MODE_HOST_MANAGED_VAS_DESTROY
+ *              This mode will destroy the FLA VAS associated with the device. It will destruct
+ *              only the resources associated with host RM side. Used only in virtualization platforms
+ *              by internal clients.
+ *
+ *    hVASpace 
+ *         This paramete specifies the FLA VAspace that needs to be associated with 
+ *         device. This parameter takes effect only for internal client in virtualization
+ *         platforms. For any other platform and external clients, this parameter has no effect.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_IN_USE
+ *   NV_ERR_INVALID_OWNER
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_FLA_RANGE (0x20803501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_FLA_RANGE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32    mode;
+    NvHandle hVASpace;
+} NV2080_CTRL_FLA_RANGE_PARAMS;
+
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE 0x00000000
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE                         NVBIT(0)
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY                            NVBIT(1)
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE        NVBIT(2)
+#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY           NVBIT(3)
+
+
+/*
+ * NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK
+ *
+ * This command is used to (un)bind FLA Instance Memory Block(IMB) with MMU.
+ * This control call is created for vGPU platform, when a FLA VAS is created/destroyed
+ * by Guest RM. Guest RM doesn't have privilege to (un)bind the IMB with MMU, hence
+ * need to be RPC-ed to Host RM to (un)bind
+ * The mode of the command is decided based on the actionParam passed by the client.
+ *
+ *    imbPhysAddr
+ *         This parameter specifies the FLA Instance Memory Block PA to be programmed
+ *         to MMU. IMB address should be 4k aligned. This parameter is needed only
+ *         for ACTION_BIND.
+ *
+ *    addrSpace
+ *         This parameter specifies the address space of FLA Instance Memory Block. This
+ *         parmater is needed only for ACTION_BIND.
+ *         Available options are:
+ *           NV2080_CTRL_FLA_ADDRSPACE_SYSMEM
+ *               Clients need to use this address space if the IMB is located in sysmem
+ *           NV2080_CTRL_FLA_ADDRSPACE_FBMEM
+ *               Clients need to use this address space if the IMB is located in FB
+ *
+ *    actionParam
+ *         This parameter specifies the functionality of the command.
+ *           NV2080_CTRL_FLA_ACTION_BIND
+ *             Setting this type, will call busBindFla helper HAL
+ *           NV2080_CTRL_FLA_ACTION_UNBIND
+ *             Setting this type, will call busUnbindFla helper HAL
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ */
+typedef enum NV2080_CTRL_FLA_ADDRSPACE {
+    NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = 0,
+    NV2080_CTRL_FLA_ADDRSPACE_FBMEM = 1,
+} NV2080_CTRL_FLA_ADDRSPACE;
+
+typedef enum NV2080_CTRL_FLA_ACTION {
+    NV2080_CTRL_FLA_ACTION_BIND = 0,
+    NV2080_CTRL_FLA_ACTION_UNBIND = 1,
+} NV2080_CTRL_FLA_ACTION;
+
+#define NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK (0x20803502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 imbPhysAddr, 8);
+    NV2080_CTRL_FLA_ADDRSPACE addrSpace;
+    NV2080_CTRL_FLA_ACTION    flaAction;
+} NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_FLA_GET_RANGE
+ *
+ * This command is used to query the FLA base and size from plugin to return as static info to Guest RM. 
+ *
+ *    base
+ *         This parameter returns the base address of FLA range registered to the subdevice. 
+ *    size
+ *         This parameter returns the size of FLA range registered to the subdevice. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FLA_GET_RANGE (0x20803503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_FLA_GET_RANGE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+} NV2080_CTRL_FLA_GET_RANGE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS
+ *
+ * This command returns the total size and the free size of the fabric vaspace.
+ * Note: This returns the information for the FABRIC_VASPACE_A class.
+ *
+ *   totalSize[OUT]
+ *      - Total fabric vaspace.
+ *
+ *   freeSize [OUT]
+ *      - Available fabric vaspace.
+ *
+ * Possible status values returned are:
+ *
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS (0x20803504) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 freeSize, 8);
+} NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS;
+
+// _ctrl2080fla_h_
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080flcn.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080flcn.h
new file mode 100644
index 0000000..9dd4266
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080flcn.h
@@ -0,0 +1,454 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080flcn.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+
+
+
+//
+// XAPICHK/XAPI_TEST breaks on including "nvmisc.h". Workaround: don't include
+// the header in that case and just redefine the macros we need.
+//
+#include "nvmisc.h"
+/*
+ * Obsolete Falcon ID type. Use NV2080_ENGINE_TYPE_ instead
+ */
+#define FALCON_ID_PMU           (NV2080_ENGINE_TYPE_PMU)
+#define FALCON_ID_DPU           (NV2080_ENGINE_TYPE_DPU)
+#define FALCON_ID_SEC2          (NV2080_ENGINE_TYPE_SEC2)
+#define FALCON_ID_FBFLCN        (NV2080_ENGINE_TYPE_FBFLCN)
+
+/*
+ * NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE
+ *
+ * This command returns total heap size and free heap size of a falcon engine
+ *
+ *  flcnID
+ *    The falcon ID
+ *
+ *  heapSize
+ *    Total heap size in byte
+ *
+ *  heapFree
+ *    Total free heap size in byte
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_NOT_SUPPORTED
+ *    NV_ERR_INVALID_ARGUMENT
+ *    NV_ERR_INVALID_OBJECT
+ */
+#define NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE (0x20803101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS {
+    NvU32 flcnID;
+    NvU32 heapSize;
+    NvU32 heapFree;
+} NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS;
+
+/*!
+ * @defgroup NVOS_INST_EVT Instrumentation event types.
+ * @{
+ */
+
+//! Reserved for uStreamer internal use.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE    0x00U
+
+//! RTOS CTXSW includes next taskID and number of ODP for previous task.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END          0x01U
+
+//! Begin of a HW IRQ.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN       0x02U
+
+//! End of a HW IRQ, before stack pinning etc is performed.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END         0x03U
+
+//! RTOS Timer tick slip. (Only for # tick processed > 1).
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK         0x04U
+
+//! Task start processing an event, includes taskId, eventType and unitId (optional).
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN   0x05U
+
+//! Task finished processing an event, incldues taskId.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END     0x06U
+
+//! Latency for inserting response into RM queue.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY   0x07U
+
+//! Special / multi-purpose event, see field definition below.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT 0x08U
+
+//! Unused, recycle
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0           0x09U
+
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END            0x0AU
+
+//! Begin/end for arbitrary block of code. The payload contains a sub-ID for each location profiled.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN      0x0BU
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END        0x0CU
+
+//! Queueing time for the most recent event.
+#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY 0x0DU
+/*!@}*/
+
+#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID        0xFFU
+
+/*
+ * NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH
+ *
+ * Get the egine arch i.e FALCON, RISCV etc given the NV2080_ENGINE_TYPE_*.
+ *
+ */
+#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH              (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
+    //! The engine type, from NV2080_ENGINE_TYPE_*
+    NvU32 engine;
+
+    //! The engine architecture - FALCON or RISC-V
+    NvU32 engineArch;
+} NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS;
+
+/*!
+ * @defgroup Engine Arch types
+ * @{
+ */
+#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT                         0x0
+#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON                          0x1
+#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV                           0x2
+#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB                        0x3
+/*!@}*/
+
+
+/* ----------------------- uStreamer (INST v2) ------------------------------ */
+/*!
+ * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT uStreamer event fields.
+ *
+ * This is a binary-packed representation of uStreamer events. There are
+ * three main types of entry: Head, Payload, and Tail. COMM here is used
+ * when a field is shared among multiple event types.
+ *
+ * @{
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG                         31:31
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD                         30:30
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE                     29:29
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND                       28:28
+
+/*!
+ * Below DRF's need constants assigned to start and end so they can be represented in FINN properly
+ * This is because FINN v1 will not have the ability to represent DRF's and bit fields yet.
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT         (27)
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE           (20)
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID \
+    (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT) : \
+    (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE)
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT  (28)
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE    (24)
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT \
+    (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT) : \
+    (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE)
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH                        19:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD                        7:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT                23:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME                          29:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD                       30:0
+/*!@}*/
+
+
+/*!
+ * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_BREAKDOWN
+ *
+ * These DRFs define breakdown of the compact payload for various event IDs.
+ *
+ * @{
+ */
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID                               7:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON                               10:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD                          0x0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0                           0x1
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK                     0x2
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK                    0x3
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED                  0x4
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT                      23:11
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP                           23:0
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID                        7:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID                       15:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE                   23:16
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID                          7:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID                     15:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC                        15:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE          0xF0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID                       23:16
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT                          10U
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID                      7:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID                          23:8
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED             0x000000
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL      0x000001
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT                         6U
+
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID                                     11:0
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID                            0x000
+#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL                    0x001
+
+/*!@}*/
+
+
+/*!
+ * @defgroup NV2080_CTRL_FLCN_USTREAMER_FEATURE
+ *
+ * This defines all the features currently supported by uStreamer. For a new
+ * usecase of uStreamer, a feature should be defined here describing the usecase.
+ * This value should be unique for each queue.
+ *
+ * @{
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT                       0U
+#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT                        1U
+/*!@}*/
+
+/*!
+ * @defgroup NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY
+ *
+ * This defines the DRF used for ustreamer queue policy
+ *
+ * @{
+ */
+
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH                   0:0
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED      0U
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED       1U
+
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH                   1:1
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED      0U
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED       1U
+
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH              2:2
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED 0U
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED  1U
+
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD              31:8
+
+/*!@}*/
+
+/*!
+ * The maximum number of compact event types, calculated from the number of bits
+ * in the event structure.
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT                 (0x20U) /* finn: Evaluated from "(1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE + 1))" */
+
+/*!
+ * The maximum number of event types, calculated from the number of bits in the
+ * event structure.
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES                         (0x120U) /* finn: Evaluated from "((1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE + 1)) + NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT)" */
+
+/*!
+ * The number of bytes required in the event mask to contain all event types.
+ */
+#define NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES                       (0x24U) /* finn: Evaluated from "((NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES + 7) / 8)" */
+
+/*!
+ * uStreamer Event Filter type, stored as a bitmask.
+ */
+typedef struct NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER {
+    NvU8 mask[NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES];
+} NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER;
+
+/*!
+ * NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO
+ * Get queue info for mapping / unmapping
+ */
+#define NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO (0x20803120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS {
+    //! The engine type, from NV2080_ENGINE_TYPE_*
+    NvU32 engine;
+
+    //!
+    // The page size of the requested queue in bytes.
+    //
+    NvU32 pageSize;
+
+    //! Offset of the queue buffer in FB.
+    NV_DECLARE_ALIGNED(NvUPtr offset, 8);
+
+    //!
+    // The size of the user-mapped instrumentation buffer. Measured in bytes.
+    //
+    NvU32 size;
+
+    //!
+    // The feature ID of the queue.
+    //
+    NvU8  queueFeatureId;
+} NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET/SET
+ *
+ * Get/set the event bitmask for the default queue.
+ */
+#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS {
+    //! The engine type, from NV2080_ENGINE_TYPE_*
+    NvU32                                   engine;
+
+    /*!
+     * The bitmask of which event types to log. An event type corresponding to
+     * a bit with a zero will be ignored at the log site, which prevents it
+     * from filling up the resident buffer in the PMU. In general, set this to
+     * only log the event types you actually want to use.
+     * Refer to NVOS_BM_* in nvos_utility.h for usage.
+     */
+    NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER eventFilter;
+
+    //! The queueId of the queue whose eventFilter we want to interact with
+    NvU8                                    queueId;
+} NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS;
+
+#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID (0x22U)
+
+typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS;
+
+#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID (0x23U)
+
+typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO
+ *
+ * This command provides the attributes of the falcon engine context buffer
+ *
+ *   hUserClient [IN]
+ *     This parameter specifies the client handle that owns this channel.
+ *   hChannel [IN]
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *   alignment
+ *     Specifies the alignment requirement for each context buffer
+ *   size
+ *     Aligned size of context buffer
+ *   bufferHandle
+ *     Opaque pointer to memdesc. Used by kernel clients for tracking purpose only.
+ *   pageCount
+ *     allocation size in the form of pageCount
+ *   physAddr
+ *     Physical address of the buffer first page
+ *   aperture
+ *     allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN
+ *   kind
+ *     PTE kind of this allocation.
+ *   pageSize
+ *     Page size of the buffer.
+ *   bIsContigous
+ *     States if physical allocation for this buffer is contiguous. PageSize will
+ *     have no meaning if this flag is set.
+ *   bDeviceDescendant
+ *     TRUE if the allocation is a constructed under a Device or Subdevice.
+ *   uuid
+ *     SHA1 UUID of the Device or Subdevice. Valid when bDeviceDescendant is TRUE.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO (0x20803124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS {
+    NvHandle hUserClient;
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 alignment, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8);
+    NV_DECLARE_ALIGNED(NvU64 pageCount, 8);
+    NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
+    NvU32    aperture;
+    NvU32    kind;
+    NvU32    pageSize;
+    NvBool   bIsContigous;
+    NvBool   bDeviceDescendant;
+    NvU8     uuid[16];
+} NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS;
+
+// Aperture flags
+#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN
+#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM
+#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM
+
+/*
+ * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE
+ *
+ * This command provides the size of the falcon engine context buffer
+ *
+ *   hChannel [IN]
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *   totalBufferSize [OUT]
+ *     This parameter returns the total context buffers size.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE (0x20803125) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS {
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8);
+} NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS;
+
+
+
+/* _ctrl2080flcn_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fuse.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fuse.h
new file mode 100644
index 0000000..7ea0b05
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fuse.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080fuse.finn
+//
+
+
+
+/* _ctrl2080fuse_h_ */
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpio.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpio.h
new file mode 100644
index 0000000..fd0e349
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpio.h
@@ -0,0 +1,74 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080gpio.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+
+
+#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION (0x20802300) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID (0x00U)
+
+typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS {
+    NvU32  gpioPin; // in
+    NvBool bInput; // in
+} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT (0x20802301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID (0x01U)
+
+typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS {
+    NvU32 gpioPin; // in
+    NvU32 value; // in
+} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT (0x20802302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID (0x02U)
+
+typedef struct NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS {
+    NvU32 gpioPin; // in
+    NvU32 value; // out
+} NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION (0x20802303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID (0x03U)
+
+typedef struct NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS {
+    NvU32 function; // in
+    NvU32 pin; // in
+} NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS;
+
+/* _ctrl2080gpio_h_ */
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpu.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpu.h
new file mode 100644
index 0000000..bdc35e5
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpu.h
@@ -0,0 +1,5026 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080gpu.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080gr.h"
+#include "ctrl/ctrl0000/ctrl0000system.h"
+#include "nvcfg_sdk.h"
+#include "nvstatus.h"
+
+#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128)
+
+/* License info strings for vGPU products */
+#define NV_GRID_LICENSE_FEATURE_VPC_EDITION                 "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
+#define NV_GRID_LICENSE_FEATURE_VAPPS_EDITION               "GRID-Virtual-Apps,3.0"
+#define NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
+#define NV_GRID_LICENSE_FEATURE_GAMING_EDITION              "GRID-vGaming,8.0"
+#define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION             "NVIDIA-vComputeServer,9.0"
+
+#define NV_GRID_LICENSED_PRODUCT_VWS                "NVIDIA RTX Virtual Workstation"
+#define NV_GRID_LICENSED_PRODUCT_GAMING             "NVIDIA Cloud Gaming"
+#define NV_GRID_LICENSED_PRODUCT_VPC                "NVIDIA Virtual PC"
+#define NV_GRID_LICENSED_PRODUCT_VAPPS              "NVIDIA Virtual Applications"
+#define NV_GRID_LICENSED_PRODUCT_COMPUTE            "NVIDIA Virtual Compute Server"
+#define NV_GRID_LICENSED_PRODUCT_VGPU_FOR_COMPUTE   "NVIDIA vGPU for Compute"
+
+
+
+/* NV20_SUBDEVICE_XX gpu control commands and parameters */
+
+
+
+typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
+
+/* valid gpu info index values */
+
+#define NV2080_CTRL_GPU_INFO_INDEX_INDEX                   23:0
+
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32                                      (0x00000001U)
+#define NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32                                      (0x00000002U)
+#define NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT                             (0x00000004U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0                                   (0x00000012U)
+#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1                                   (0x00000013U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED                                  (0x0000001bU)
+#define NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS                                  (0x0000001fU)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD                                   (0x00000022U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE                      (0x00000025U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED                     (0x00000027U)
+#define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED                        (0x00000028U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT                                 (0x00000029U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE                                   (0x0000002aU)
+#define NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM                (0x0000002bU)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION                                 (0x0000002cU)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY                             (0x0000002dU)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM                        (0x0000002fU)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY                             (0x00000030U)
+#define NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE                    (0x00000031U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED                                (0x00000034U)
+#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED                          (0x00000035U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY                       (0x00000036U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY                       (0x00000037U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY                       (0x0000003aU)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY                     (0x0000003bU)
+#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU                                        (0x0000003cU)
+#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY                              (0x0000003dU)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED                     (0x0000003fU)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED                      (0x00000041U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY                   (0x00000042U)
+
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_SYSMEM_CAPABILITY                      (0x00000043U)
+
+
+#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE                       (0x00000044U)
+
+#define NV2080_CTRL_GPU_INFO_INDEX_COMPR_BIT_BACKING_COPY_TYPE                    (0x00000045U)
+
+#define NV2080_CTRL_GPU_INFO_INDEX_CPU_COHERENT_CACHING_GPU_MEMORY_CAPABILITY     (0x00000046U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_COHERENT_CACHING_CPU_MEMORY_CAPABILITY     (0x00000047U)
+
+#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE                                        (0x00000048U)
+
+#define NV2080_CTRL_GPU_INFO_INDEX_TYPE                    30:28
+#define NV2080_CTRL_GPU_INFO_INDEX_TYPE_SPECIFIC_ID        27:24
+#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED                31:31
+
+/* valid minor revision extended values */
+#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE                              (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P                                 (0x00000001U)
+#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V                                 (0x00000002U)
+#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV                                (0x00000003U)
+
+
+
+/* valid system memory access capability values */
+#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO                                     (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES                                    (0x00000001U)
+
+
+
+/* valid gemini board values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO                                (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES                               (0x00000001U)
+
+/* valid surprise removal values */
+#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO                   (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES                  (0x00000001U)
+
+/* valid poison fuse capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO                  (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES                 (0x00000001U)
+
+/* valid nvswitch proxy detected values */
+#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO                           (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES                          (0x00000001U)
+
+/* valid NVSR GPU support info values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO                              (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES                             (0x00000001U)
+
+/* valid SMC mode values */
+#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED                             (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED                                 (0x00000001U)
+#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED                                (0x00000002U)
+#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING                          (0x00000003U)
+#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING                         (0x00000004U)
+
+/* valid split VAS mode values */
+#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO                   (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES                  (0x00000001U)
+
+/* valid grid capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO                          (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES                         (0x00000001U)
+
+/* valid per runlist channel ram capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED               (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED                (0x00000001U)
+
+/* valid ATS capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO                          (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES                         (0x00000001U)
+
+/* valid Nvenc Session Stats reporting state values */
+#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED                 (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED                  (0x00000001U)
+#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED            (0x00000002U)
+
+/* valid display enabled values */
+#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO                                   (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES                                  (0x00000001U)
+
+/* valid mobile config enabled values */
+#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO                       (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES                      (0x00000001U)
+
+
+/* valid profiling capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED              (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED               (0x00000001U)
+
+/* valid debugging capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED              (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED               (0x00000001U)
+
+
+
+/* valid local EGM supported values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO                    (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES                   (0x00000001U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID                          31:1
+
+/* valid self hosted values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO                  (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES                 (0x00000001U)
+
+/* valid CMP (Crypto Mining Processor) SKU values */
+#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO                                     (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES                                    (0x00000001U)
+
+
+/* valid dma-buf suport values */
+#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO                           (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES                          (0x00000001U)
+
+/* valid resetless MIG device supported values */
+#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO                  (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES                 (0x00000001U)
+
+/* valid localization supported values */
+#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_NO                   (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_YES                  (0x00000001U)
+
+/* valid Non-PASID ATS capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY_NO                (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY_YES               (0x00000001U)
+
+/* valid fla sysmem capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_SYSMEM_CAPABILITY_NO                   (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_SYSMEM_CAPABILITY_YES                  (0x00000001U)
+
+
+
+/* valid coherent GPU memory mode capability values */
+#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NONE                  (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NUMA                  (0x00000001U)
+#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_DRIVER                (0x00000002U)
+
+/* valid compression bit backing copy type values */
+#define NV2080_CTRL_GPU_INFO_INDEX_COMP_BIT_BACKING_COPY_TYPE_PHYSICAL            (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_COMP_BIT_BACKING_COPY_TYPE_VIRTUAL             (0x00000001U)
+
+#define NV2080_CTRL_GPU_INFO_INDEX_CPU_COHERENT_CACHING_GPU_MEMORY_CAPABILITY_NO  (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_CPU_COHERENT_CACHING_GPU_MEMORY_CAPABILITY_YES (0x00000001U)
+
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_COHERENT_CACHING_CPU_MEMORY_CAPABILITY_NO  (0x00000000U)
+#define NV2080_CTRL_GPU_INFO_INDEX_GPU_COHERENT_CACHING_CPU_MEMORY_CAPABILITY_YES (0x00000001U)
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_INFO
+ *
+ * This command returns gpu information for the associated GPU.  Requests
+ * to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO
+ * structures.
+ *
+ *   gpuInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     gpuInfoList.
+ *   gpuInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the gpu information is to be returned.
+ *     This buffer must be at least as big as gpuInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_GPU_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_GPU_GET_INFO                                              (0x20800101U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS {
+    NvU32 gpuInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8);
+} NV2080_CTRL_GPU_GET_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS {
+    NvU32                gpuInfoListSize;
+    NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE];
+} NV2080_CTRL_GPU_GET_INFO_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_NAME_STRING
+ *
+ * This command returns the name of the GPU in string form in ASCII format.
+ *
+ *   gpuNameStringFlags
+ *     Ignored, to be removed. Callers should not be setting it at all.
+ *   gpuNameString
+ *     This field contains the buffer into which the name string should be
+ *     returned.  The length of the returned string will be no more than
+ *     NV2080_CTRL_GPU_MAX_NAME_STRING_LENGTH bytes in size.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_GPU_GET_NAME_STRING              (0x20800110U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_GPU_MAX_NAME_STRING_LENGTH                (0x0000040U)
+
+// This field is deprecated - 'gpuNameStringFlags' is now a simple scalar.
+// Field maintained (and extended from 0:0) for compile-time compatibility.
+#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE                    31:0
+
+/* valid gpu name string flags - deprecated, should not set anything */
+#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII (0x00000000U)
+
+#define NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS {
+    NvU32 gpuNameStringFlags;
+    struct {
+        NvU8 ascii[NV2080_GPU_MAX_NAME_STRING_LENGTH];
+    } gpuNameString;
+} NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING
+ *
+ * This command returns the short name of the GPU in ASCII string form.
+ *
+ *   gpuShortNameString
+ *     This field contains the buffer into which the short name string should
+ *     be returned.  The length of the returned string will be no more than
+ *     NV2080_MAX_NAME_STRING_LENGTH bytes in size.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING (0x20800111U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS {
+    NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
+} NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_POWER
+ *
+ * This command sets the power state for the GPU as a whole, various engines,
+ * or clocks.
+ *
+ *   target
+ *     One of NV2080_CTRL_GPU_SET_POWER_TARGET_*
+ *
+ *   newLevel
+ *     One of NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_*
+ *            NV2080_CTRL_GPU_SET_POWER_STATE_ENGINE_LEVEL_*
+ *            NV2080_CTRL_GPU_SET_POWER_STATE_CLOCK_LEVEL_*
+ *     depending on the target above.
+ *
+ *   oldLevel
+ *     Previous level as appropriate.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GPU_SET_POWER (0x20800112U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_GPU_SET_POWER_PARAMS {
+    NvU32 target;
+    NvU32 newLevel;
+    NvU32 oldLevel;
+} NV2080_CTRL_GPU_SET_POWER_PARAMS;
+
+
+
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0            (0x00000000U)
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1            (0x00000001U)
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2            (0x00000002U)
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3            (0x00000003U)
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4            (0x00000004U)
+#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7            (0x00000007U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_SDM
+ *
+ * This command returns the subdevice mask value for the associated subdevice.
+ * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction
+ * provided by the NV36_CHANNEL_DMA and newer channel dma classes.
+ *
+ *   subdeviceMask [out]
+ *     This field return the subdevice mask value.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_SDM                            (0x20800118U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_GPU_GET_SDM_PARAMS {
+    NvU32 subdeviceMask;
+} NV2080_CTRL_GPU_GET_SDM_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_SDM
+ *
+ * This command sets the subdevice instance and mask value for the associated subdevice.
+ * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction
+ * provided by the NV36_CHANNEL_DMA and newer channel dma classes.
+ * It must be called before the GPU HW is initialized otherwise
+ * NV_ERR_INVALID_STATE is being returned.
+ *
+ *   subdeviceMask [in]
+ *     This field configures the subdevice mask value for the GPU/Subdevice
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_DATA
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_SET_SDM (0x20800120U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_GPU_SET_SDM_PARAMS {
+    NvU32 subdeviceMask;
+} NV2080_CTRL_GPU_SET_SDM_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO
+ *
+ * This command returns the associated subdevices' simulation information.
+ *
+ *   type
+ *     This field returns the simulation type.
+ *     One of NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_*
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO (0x20800119U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS {
+    NvU32 type;
+} NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE          (0x00000000U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL   (0x00000001U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL   (0x00000002U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL        (0x00000003U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL           (0x00000004U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU           (0x00000005U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER (0x00000006U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA         (0x00000007U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL     (0x00000008U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL  (0x00000009U)
+#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN       (0xFFFFFFFFU)
+
+/*
+ * NV2080_CTRL_GPU_REG_OP
+ *
+ * This structure describes register operation information for use with
+ * the NV2080_CTRL_CMD_GPU_EXEC_REG_OPS command.  The structure describes
+ * a single register operation.  The operation can be a read or write and
+ * can involve either 32bits or 64bits of data.
+ *
+ * For 32bit read operations, the operation takes the following form:
+ *
+ *   regValueLo = read(bar0 + regOffset)
+ *   regValueHi = 0
+ *
+ * For 64bit read operations, the operation takes the following form:
+ *
+ *   regValueLo = read(bar0 + regOffset)
+ *   regValueHi = read(bar0 + regOffset + 4)
+ *
+ * For 32bit write operations, the operation takes the following form:
+ *
+ *   new = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo)
+ *   write(bar0 + regOffset, new)
+ *
+ * For 64bit write operations, the operation takes the following form:
+ *
+ *   new_lo = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo)
+ *   new_hi = ((read(bar0 + regOffset + 4) &  ~regAndNMaskHi) | regValueHi)
+ *   write(bar0 + regOffset, new_lo)
+ *   write(bar0 + regOffset + 4, new_hi)
+ *
+ * Details on the parameters follow:
+ *
+ *   regOp
+ *     This field specifies the operation to be applied to the register
+ *     specified by the regOffset parameter.  Valid values for this
+ *     parameter are:
+  *      NV2080_CTRL_GPU_REG_OP_READ_08
+ *         The register operation should be a 8bit global privileged register read.
+ *       NV2080_CTRL_GPU_REG_OP_WRITE_08
+ *         The register operation should be a 8bit global privileged register write.
+ *       NV2080_CTRL_GPU_REG_OP_READ_32
+ *         The register operation should be a 32bit register read.
+ *       NV2080_CTRL_GPU_REG_OP_WRITE_32
+ *         The register operation should be a 32bit register write.
+ *       NV2080_CTRL_GPU_REG_OP_READ_64
+ *         The register operation should be a 64bit register read.
+ *       NV2080_CTRL_GPU_REG_OP_WRITE_64
+ *         The register operation should be a 64bit register write.
+ *   regType
+ *     This field specifies the type of the register specified by the
+ *     regOffset parameter.  Valid values for this parameter are:
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL
+ *         The register is a global privileged register.  Read operations
+ *         return the current value from the associated global register.
+ *         Write operations for registers of this type take effect immediately.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX
+ *         The register is a graphics context register.  Read operations
+ *         return the current value from the associated global register.
+ *         Write operations are applied to all existing graphics engine
+ *         contexts.  Any newly created graphics engine contexts will also
+ *         be modified.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC
+ *         This is a graphics context TPC register group. Write operations are
+ *         applied to TPC group(s) specified by regGroupMask.
+ *         This field is ignored for read operations.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM
+ *         This is a graphics context SM register group that is inside TPC
+ *         group.  Write operations are applied to SM group(s) specified by
+ *         regGroupMask (TPC) and regSubGroupMask (SM). This field is ignored
+ *         for read operations.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP
+ *         This is a graphics context CROP register group. Write operations
+ *         are applied to registers specified by regGroupMask. This field is
+ *         ignored for read operations.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP
+ *         This is a graphics context ZROP register group. Write operations
+ *         are applied to registers specified by regGroupMask. This field is
+ *         ignored for read operations.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_FB
+ *         This is a fb register group. Write operations are applied to
+ *         registers specified by regGroupMask. This field is
+ *         ignored for read operations.
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD
+ *         This is a graphics context QUAD register group. Operations
+ *         are applied to registers specified by regQuad value.
+ *   regQuad
+ *     This field specifies the quad to be accessed for register regOffsetwhen
+ *     the regType specified is NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD.
+ *   regGroupMask
+ *     This field specifies which registers inside an array should be updated.
+ *     This field is used when regType is one of below:
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_FB
+ *     When regGroupMask is used, the regOffset MUST be the first register in
+ *     an array.
+ *   regSubGroupMask
+ *     This field specifies which registers inside a group should be updated.
+ *     This field is used for updating SM registers when regType is:
+ *       NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC
+ *     When regSubGroupMask is used, regOffset MUST be the first register in an
+ *     array AND also the first one in sub array.  regGroupMask specifies
+ *     TPC(X) and regSubGroupMask specifies SM_CTX_N(Y)
+ *   regStatus
+ *     This field returns the completion status for the associated register
+ *     operation in the form of a bitmask.  Possible status values for this
+ *     field are:
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS
+ *         This value indicates the operation completed successfully.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP
+ *         This bit value indicates that the regOp value is not valid.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE
+ *         This bit value indicates that the regType value is not valid.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET
+ *         This bit value indicates that the regOffset value is invalid.
+ *         The regOffset value must be within the legal BAR0 range for the
+ *         associated GPU and must target a supported register with a
+ *         supported operation.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OFFSET
+ *         This bit value indicates that the operation to the register
+ *         specified by the regOffset value is not supported for the
+ *         associated GPU.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK
+ *         This bit value indicates that the regTpcMask value is invalid.
+ *         The regTpcMask must be a subset of TPCs that are enabled on the
+ *         associated GPU.
+ *       NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS
+ *         The caller does not have access to the register at given offset
+ *   regOffset
+ *     This field specifies the register offset to access.  The specified
+ *     offset must be a valid BAR0 offset for the associated GPU.
+ *   regValueLo
+ *     This field contains the low 32bits of the register value.
+ *     For read operations, this value returns the current value of the
+ *     register specified by regOffset.  For write operations, this field
+ *     specifies the logical OR value applied to the current value
+ *     contained in the register specified by regOffset.
+ *   regValueHi
+ *     This field contains the high 32bits of the register value.
+ *     For read operations, this value returns the current value of the
+ *     register specified by regOffset + 4.  For write operations, this field
+ *     specifies the logical OR value applied to the current value
+ *     contained in the register specified by regOffset + 4.
+ *   regAndNMaskLo
+ *     This field contains the mask used to clear a desired field from
+ *     the current value contained in the register specified by regOffsetLo.
+ *     This field is negated and ANDed to this current register value.
+ *     This field is only used for write operations.  This field is ignored
+ *     for read operations.
+ *   regAndNMaskHi
+ *     This field contains the mask used to clear a desired field from
+ *     the current value contained in the register specified by regOffsetHi.
+ *     This field is negated and ANDed to this current register value.
+ *     This field is only used for write operations.  This field is ignored
+ *     for read operations.
+ */
+typedef struct NV2080_CTRL_GPU_REG_OP {
+    NvU8  regOp;
+    NvU8  regType;
+    NvU8  regStatus;
+    NvU8  regQuad;
+    NvU32 regGroupMask;
+    NvU32 regSubGroupMask;
+    NvU32 regOffset;
+    NvU32 regValueHi;
+    NvU32 regValueLo;
+    NvU32 regAndNMaskHi;
+    NvU32 regAndNMaskLo;
+} NV2080_CTRL_GPU_REG_OP;
+
+/* valid regOp values */
+#define NV2080_CTRL_GPU_REG_OP_READ_32               (0x00000000U)
+#define NV2080_CTRL_GPU_REG_OP_WRITE_32              (0x00000001U)
+#define NV2080_CTRL_GPU_REG_OP_READ_64               (0x00000002U)
+#define NV2080_CTRL_GPU_REG_OP_WRITE_64              (0x00000003U)
+#define NV2080_CTRL_GPU_REG_OP_READ_08               (0x00000004U)
+#define NV2080_CTRL_GPU_REG_OP_WRITE_08              (0x00000005U)
+
+/* valid regType values */
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL           (0x00000000U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX           (0x00000001U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC       (0x00000002U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM        (0x00000004U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP      (0x00000008U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP      (0x00000010U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_FB               (0x00000020U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD      (0x00000040U)
+#define NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE           (0x00000080U)
+
+/* valid regStatus values (note: NvU8 ie, 1 byte) */
+#define NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS        (0x00U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP     (0x01U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE   (0x02U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET (0x04U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x08U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK   (0x10U)
+#define NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS       (0x20U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS
+ *
+ * This command is used to submit a buffer containing one or more
+ * NV2080_CTRL_GPU_REG_OP structures for processing.  Each entry in the
+ * buffer specifies a single read or write operation.  Each entry is checked
+ * for validity in an initial pass over the buffer with the results for
+ * each operation stored in the corresponding regStatus field. Unless
+ * bNonTransactional flag is set to true, if any invalid entries are found
+ * during this initial pass then none of the operations are executed. Entries
+ * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL
+ * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries.
+ *
+ *   hClientTarget
+ *     This parameter specifies the handle of the client that owns the channel
+ *     specified by hChannelTarget. If this parameter is set to 0 then the set
+ *     of channel-specific register operations are applied to all current and
+ *     future channels.
+ *   hChannelTarget
+ *     This parameter specifies the handle of the target channel (or channel
+ *     group) object instance to which channel-specific register operations are
+ *     to be directed. If hClientTarget is set to 0 then this parameter must
+ *     also be set to 0.
+ *   bNonTransactional
+ *     This field specifies if command is non-transactional i.e. if set to
+ *     true, all the valid operations will be executed.
+ *   reserved00
+ *     This parameter is reserved for future use.  It should be initialized to
+ *     zero for correct operation.
+ *   regOpCount
+ *     This field specifies the number of entries on the caller's regOps
+ *     list.
+ *   regOps
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer from which the desired register information is to be
+ *     retrieved.  This buffer must be at least as big as regInfoCount
+ *     multiplied by the size of the NV2080_CTRL_GPU_REG_OP structure.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine. When SMC is enabled, this
+ *     is a mandatory parameter.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS             (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS {
+    NvHandle hClientTarget;
+    NvHandle hChannelTarget;
+    NvU32    bNonTransactional;
+    NvU32    reserved00[2];
+    NvU32    regOpCount;
+    NV_DECLARE_ALIGNED(NvP64 regOps, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINES
+ *
+ * Returns a list of supported engine types along with the number of instances
+ * of each type. Querying with engineList NULL returns engineCount.
+ *
+ *   engineCount
+ *     This field specifies the number of entries on the caller's engineList
+ *     field.
+ *   engineList
+ *     This field is a pointer to a buffer of NvU32 values representing the
+ *     set of engines supported by the associated subdevice.  Refer to cl2080.h
+ *     for the complete set of supported engine types.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ENGINES (0x20800123U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS {
+    NvU32 engineCount;
+    NV_DECLARE_ALIGNED(NvP64 engineList, 8);
+} NV2080_CTRL_GPU_GET_ENGINES_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */
+
+/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
+#define NV2080_GPU_MAX_ENGINES_LIST_SIZE   0x54U
+
+#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS {
+    NvU32 engineCount;
+    NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+} NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST
+ *
+ * Returns a list of classes supported by a given engine type.
+ *
+ *   engineType
+ *     This field specifies the engine type being queried.
+ *     NV2080_CTRL_ENGINE_TYPE_ALLENGINES will return  classes
+ *     supported by all engines.
+ *
+ *   numClasses
+ *     This field specifies the number of classes supported by
+ *     engineType.
+ *
+ *   classList
+ *     This field is an array containing the list of supported
+ *     classes. Is of type (NvU32*)
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST (0x20800124U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS {
+    NvU32 engineType;
+    NvU32 numClasses;
+    NV_DECLARE_ALIGNED(NvP64 classList, 8);
+} NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO
+ *
+ * This command returns the fault properties of the specified engine type.
+ *
+ *   engineType
+ *     Input parameter.
+ *     This field specifies the engine type being queried.
+ *     Engine type is specified using the NV2080_ENGINE_TYPE_* defines in cl2080.h.
+ *     The list of engines supported by a chip can be got using the
+ *     NV2080_CTRL_CMD_GPU_GET_ENGINES ctrl call.
+ *
+ *   mmuFaultId
+ *     Output parameter.
+ *     This field returns the MMU fault ID for the specified engine.
+ *     If the engine supports subcontext, this field provides the base fault id.
+ *
+ *   bSubcontextSupported
+ *     Output parameter.
+ *     Returns TRUE if subcontext faulting is supported by the engine.
+ *     Engine that support subcontext use fault IDs in the range [mmuFaultId, mmuFaultId + maxSubCtx).
+ *     "maxSubctx" can be found using the NV2080_CTRL_FIFO_INFO ctrl call with
+ *     NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP as the index.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO (0x20800125U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS {
+    NvU32  engineType;
+    NvU32  mmuFaultId;
+    NvBool bSubcontextSupported;
+} NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS;
+
+
+
+/*!
+ * NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY
+ * Data block describing a virtual context buffer to be promoted
+ *
+ *  gpuPhysAddr [IN]
+ *    GPU Physical Address for the buffer
+ *  gpuVirtAddr [IN]
+ *    GPU Virtual Address for the buffer
+ *   size[IN]
+ *    Size of this virtual context buffer
+ *  physAttr [IN]
+ *    Physical memory attributes (aperture, cacheable)
+ *  bufferId [IN]
+ *    Virtual context buffer type, data type NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_*
+ *  bInitialize [IN]
+ *   Flag indicating that this virtual context buffer should be initialized prior to promotion.
+ *   The client must clear (memset) the buffer to 0x0 prior to initialization.
+ *   Following buffers need initialization:
+ *    1. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN
+ *    2. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH
+ *    3. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP
+ *    4. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP
+ *  bNonmapped [IN]
+ *   Flag indicating that the virtual address is not to be promoted with this
+ *   call. It is illegal to set this flag and not set bInitialize.
+ */
+typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY {
+    NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32 physAttr;
+    NvU16 bufferId;
+    NvU8  bInitialize;
+    NvU8  bNonmapped;
+} NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY;
+
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN                         0U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM                           1U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH                        2U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB             3U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL                     4U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB                 5U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL                6U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL                    7U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK                8U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT                   9U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP              10U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U
+#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP       12U
+
+#define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES                        16U
+
+/*
+ * NV2080_CTRL_CMD_GPU_PROMOTE_CTX
+ *
+ * This command is used to promote a Virtual Context
+ *
+ *   engineType
+ *     Engine Virtual Context is for
+ *   hClient
+ *     Client Handle for hVirtMemory
+ *   ChID
+ *     Hw Channel -- Actually hw index for channel (deprecated)
+ *   hChanClient
+ *     The client handle for hObject
+ *   hObject
+ *     Passed in object handle for either a single channel or a channel group
+ *   hVirtMemory
+ *     Virtual Address handle to map Virtual Context to
+ *   virtAddress
+ *     Virtual Address to map Virtual Context to
+ *   size
+ *     size of the Virtual Context
+ *   entryCount
+ *     Number of valid entries in the promotion entry list
+ *   promoteEntry
+ *     List of context buffer entries to issue promotions for.
+ *
+ *   When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be
+ *   specified, the code cases based on hVirtMemory(NULL vs non-NULL) so
+ *   if both are specified, hVirtMemory has precedence.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED    - The Class does not support version info retrieval
+ *   NV_ERR_INVALID_DEVICE   - The Class/Device is not yet ready to provide this info.
+ *   NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified.
+ */
+#define NV2080_CTRL_CMD_GPU_PROMOTE_CTX                                    (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID (0x2BU)
+
+typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS {
+    NvU32    engineType;
+    NvHandle hClient;
+    NvU32    ChID;
+    NvHandle hChanClient;
+    NvHandle hObject;
+    NvHandle hVirtMemory;
+    NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NvU32    entryCount;
+    // C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8);
+} NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS;
+typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_EVICT_CTX
+ *
+ * This command is used to evict a Virtual Context
+ *
+ *   engineType
+ *     Engine Virtual Context is for
+ *   hClient
+ *     Client Handle
+ *   ChID
+ *     Hw Channel -- Actually hw index for channel (deprecated)
+ *   hChanClient
+ *     Client handle for hObject
+ *   hObject
+ *     Passed in object handle for either a single channel or a channel group
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED    - The Class does not support version info retrieval
+ *   NV_ERR_INVALID_DEVICE   - The Class/Device is not yet ready to provide this info.
+ *   NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified.
+ */
+#define NV2080_CTRL_CMD_GPU_EVICT_CTX (0x2080012cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID (0x2CU)
+
+typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS {
+    NvU32    engineType;
+    NvHandle hClient;
+    NvU32    ChID;
+    NvHandle hChanClient;
+    NvHandle hObject;
+} NV2080_CTRL_GPU_EVICT_CTX_PARAMS;
+typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS *PNV2080_CTRL_GPU_EVICT_CTX_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_INITIALIZE_CTX
+ *
+ * This command is used to initialize a Virtual Context. The ctx buffer must be
+ * cleared (zerod) by the caller prior to invoking this method.
+ *
+ *   engineType
+ *     Engine Virtual Context is for
+ *   hClient
+ *     Client Handle for the hVirtMemory
+ *   ChID
+ *      Hw channel -- Actually channel index (deprecated)
+ *   hChanClient
+ *     The client handle for hObject
+ *   hObject
+ *     Passed in object handle for either a single channel or a channel group
+ *   hVirtMemory
+ *     Virtual Address where to map Virtual Context to
+ *   physAddress
+ *     Physical offset in FB to use as Virtual Context
+ *   physAttr
+ *     Physical memory attributes
+ *   hDmaHandle
+ *     Dma Handle when using discontiguous context buffers
+ *   index
+ *     Start offset in Virtual DMA Context
+ *   size
+ *     Size of the Virtual Context
+ *
+ *   Only hVirtMemory or size should be specified, the code cases based on hVirtMemory
+ *   (NULL vs non-NULL) so if both are specified, hVirtMemory has precedence.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED    - The Class does not support version info retrieval
+ *   NV_ERR_INVALID_DEVICE   - The Class/Device is not yet ready to provide this info.
+ *   NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified.
+ */
+#define NV2080_CTRL_CMD_GPU_INITIALIZE_CTX (0x2080012dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID (0x2DU)
+
+typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS {
+    NvU32    engineType;
+    NvHandle hClient;
+    NvU32    ChID;
+    NvHandle hChanClient;
+    NvHandle hObject;
+    NvHandle hVirtMemory;
+    NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
+    NvU32    physAttr;
+    NvHandle hDmaHandle;
+    NvU32    index;
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+} NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS;
+typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS;
+
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE              1:0
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM   (0x00000000U)
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS  (0x00000001U)
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS (0x00000002U)
+
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE         2:2
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES (0x00000000U)
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO  (0x00000001U)
+
+/*
+ * NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX - Tells RM Whether this Ctx buffer needs to
+ * do a full initialization (Load the golden image). When a context is promoted on a different
+ * channel than it was originally inited, the client can use this flag to tell RM
+ * that this is an already inited Context. In such cases RM will update the internal state
+ * to update the context address and state variables.
+ */
+
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX              3:3
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO   (0x00000000U)
+#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES  (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_CPU_QUERY_ECC_INTR
+ * Queries the top level ECC PMC PRI register
+ * TODO remove these parameters, tracked in bug #1975721
+ */
+#define NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR               (0x2080012eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2E" */
+
+typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS {
+    NvU32 eccIntrStatus;
+} NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS
+ *
+ * This command is used to query the ECC status of a GPU by a subdevice
+ * handle.  Please see the NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS
+ * data structure description below for details on the data reported
+ * per hardware unit.
+ *
+ *   units
+ *     Array of structures used to describe per-unit state
+ *
+ *   flags
+ *     See interface flag definitions below.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+
+
+#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS                   (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */
+
+
+#define NV2080_CTRL_GPU_ECC_UNIT_GSP                           (0x0000001DU)
+
+
+#define NV2080_CTRL_GPU_ECC_UNIT_COUNT                         (0x00000029U)
+
+
+
+// Deprecated do not use
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE             0:0
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED   (0x00000000U)
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW        (0x00000001U)
+
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE         0U
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE          1U
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE 2U
+
+/*
+ * NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS
+ *
+ * This structure represents the exception status of a class of per-unit
+ * exceptions
+ *
+ *   count
+ *     number of exceptions that have occurred since boot
+ */
+typedef struct NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS {
+    NV_DECLARE_ALIGNED(NvU64 count, 8);
+} NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS;
+
+/*
+ * NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS
+ *
+ * This structure represents the per-unit ECC exception status
+ *
+ *   enabled
+ *     ECC enabled yes/no for this unit
+ *   scrubComplete
+ *     Scrub has completed yes/no. A scrub is performed for some units to ensure
+ *     the checkbits are consistent with the protected data.
+ *   supported
+ *     Whether HW supports ECC in this unit for this GPU
+ *   dbe
+ *     Double bit error (DBE) status. The value returned reflects a counter
+ *     that is monotonic, but can be reset by clients.
+ *   dbeNonResettable (deprecated do not use)
+ *     Double bit error (DBE) status, not client resettable.
+ *   sbe
+ *     Single bit error (SBE) status. The value returned reflects a counter
+ *     that is monotonic, but can be reset by clients.
+ *   sbeNonResettable (deprecated do not use)
+ *     Single bit error (SBE) status, not client resettable.
+ *
+ */
+typedef struct NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS {
+    NvBool enabled;
+    NvBool scrubComplete;
+    NvBool supported;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbe, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbeNonResettable, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbe, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbeNonResettable, 8);
+} NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS;
+
+/*
+ * NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
+ *
+ * This structure returns ECC exception status and GPU Fatal Poison for all units
+ *
+ *   units
+ *     This structure represents ECC exception status for all Units.
+ *   bFatalPoisonError
+ *     Whether GPU Fatal poison error occurred in this GPU. This will be set for Ampere_and_later
+ *   uncorrectableError
+ *     Indicates whether any uncorrectable GR ECC errors have occurred. When
+ *     SMC is enabled, uncorrectableError is only valid when the client is
+ *     subscribed to a partition. Check QUERY_ECC_STATUS_UNC_ERR_*
+ *   flags
+ *     Flags passed by caller. Refer  NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_* for details.
+ *   grRouteInfo
+ *     SMC partition information. This input is only valid when SMC is
+ *     enabled on Ampere_and_later.
+ *
+ */
+#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID (0x2FU)
+
+typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS units[NV2080_CTRL_GPU_ECC_UNIT_COUNT], 8);
+    NvBool bFatalPoisonError;
+    NvU8   uncorrectableError;
+    NvU32  flags;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES
+ *
+ * This command sets the compute mode rules for the associated subdevice.  The
+ * default mode is equivalent to NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE.  This
+ * command is available to clients with administrator privileges only.  An
+ * attempt to use this command by a client without administrator privileged
+ * results in the return of an NV_ERR_INSUFFICIENT_PERMISSIONS status.
+ *
+ *   rules
+ *     This parameter is used to specify the rules that govern the GPU with
+ *     respect to NV50_COMPUTE objects. Legal values for this parameter include:
+ *
+ *       NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE
+ *         This mode indicate that no special restrictions apply to the
+ *         allocation of NV50_COMPUTE objects.
+ *
+ *       NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE
+ *         This mode means that only one instance of NV50_COMPUTE will be
+ *         allowed at a time. This restriction is enforced at each subsequent
+ *         NV50_COMPUTE allocation attempt. Setting this mode will not affect
+ *         any existing compute programs that may be running. For example,
+ *         if this mode is set while three compute programs are running, then
+ *         all of those programs will be allowed to continue running. However,
+ *         until they all finish running, no new NV50_COMPUTE objects may be
+ *         allocated. User-mode clients should treat this as restricting access
+ *         to a NV50_COMPUTE object to a single thread within a process.
+ *
+ *       NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED
+ *         This mode means that that GPU is not ever allowed to instantiate an
+ *         NV50_COMPUTE object, and thus cannot run any new compute programs.
+ *         This restriction is enforced at each subsequent NV50_COMPUTE object
+ *         allocation attempt. Setting this mode will not affect any existing
+ *         compute programs that may be running. For example, if this mode is
+ *         set while three compute programs are running, then all of those
+ *         programs will be allowed to continue running. However, no new
+ *         NV50_COMPUTE objects may be allocated.
+ *
+ *
+ *       NV2080_CTRL_GPU_COMPUTE_MODE_EXCLUSIVE_COMPUTE_PROCESS
+ *         This mode is identical to EXCLUSIVE_COMPUTE, where only one instance
+ *         of NV50_COMPUTE will be allowed at a time. It is separate from
+ *         EXCLUSIVE_COMPUTE to allow user-mode clients to differentiate
+ *         exclusive access to a compute object from a single thread of a
+ *         process from exclusive access to a compute object from all threads
+ *         of a process. User-mode clients should not limit access to a
+ *         NV50_COMPUTE object to a single thread when the GPU is set to
+ *         EXCLUSIVE_COMPUTE_PROCESS.
+ *
+ *     An invalid rules parameter value results in the return of an
+ *     NV_ERR_INVALID_ARGUMENT status.
+ *
+ *   flags
+ *     Reserved. Caller should set this field to zero.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT (if an invalid rule number is provided)
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS (if the user is not the Administrator or superuser)
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES                   (0x20800130U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */
+
+/* valid rules parameter values */
+#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE                      (0x00000000U)
+#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE         (0x00000001U)
+#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED        (0x00000002U)
+#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS (0x00000003U)
+
+#define NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x30U)
+
+typedef struct NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS {
+    NvU32 rules;
+    NvU32 flags;
+} NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES
+ *
+ * This command queries the compute mode rules for the associated subdevice.
+ * Please see the NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES command, above, for
+ * details as to what the rules mean.
+ *
+ *   rules
+ *     Specifies the rules that govern the GPU, with respect to NV50_COMPUTE
+ *     objects.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES (0x20800131U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x31U)
+
+typedef struct NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS {
+    NvU32 rules;
+} NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION
+ *
+ * This command returns the current ECC configuration setting for
+ * a GPU given its subdevice handle.  The value returned is
+ * the current ECC setting for the GPU stored in non-volatile
+ * memory on the board.
+ *
+ *   currentConfiguration
+ *      The current ECC configuration setting.
+ *
+ *   defaultConfiguration
+ *      The factory default ECC configuration setting.
+ *
+ * Please see the NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS command if
+ * you wish to determine if ECC is currently enabled.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION (0x20800133U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED  (0x00000000U)
+#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED   (0x00000001U)
+
+#define NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x33U)
+
+typedef struct NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS {
+    NvU32 currentConfiguration;
+    NvU32 defaultConfiguration;
+} NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION
+ *
+ * This command changes the ECC configuration setting for a GPU
+ * given its subdevice handle.  The value specified is
+ * stored in non-volatile memory on the board and will take
+ * effect with the next GPU reset
+ *
+ *   newConfiguration
+ *     The new configuration setting to take effect with
+ *     the next GPU reset.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION (0x20800134U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE (0x00000000U)
+#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE  (0x00000001U)
+
+#define NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x34U)
+
+typedef struct NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS {
+    NvU32 newConfiguration;
+} NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS
+ *
+ * This command resets volatile and/or persistent ECC error
+ * status information for a GPU given its subdevice
+ * handle.
+ *
+ *   statuses
+ *     The ECC error statuses (the current, volatile
+ *     and/or the persistent error counter(s)) to
+ *     be reset by the command.
+ *   flags
+ *     FORCE_PURGE
+ *          Forcibly clean all the ECC InfoROM state if this flag is set
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS                     (0x20800136U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE                          (0x00000000U)
+#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE                      (0x00000001U)
+#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE                     (0x00000002U)
+
+#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE           0:0
+#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE 0U
+#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE  1U
+
+#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID (0x36U)
+
+typedef struct NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS {
+    NvU32 statuses;
+    NvU8  flags;
+} NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO
+ *
+ * This command returns a mask of enabled GPCs for the associated GPU.
+ *
+ *    gpcMask
+ *      This parameter returns a mask of enabled GPCs. Each GPC has an ID
+ *      that's equivalent to the corresponding bit position in the mask.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO (0x20800137U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID (0x37U)
+
+typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS {
+    NvU32 gpcMask;
+} NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO
+ *
+ * This command returns a mask of enabled TPCs for a specified GPC.
+ *
+ *    gpcId
+ *      This parameter specifies the GPC for which TPC information is
+ *      to be retrieved. If the GPC with this ID is not enabled this command
+ *      will return an tpcMask value of zero.
+ *
+ *    tpcMask
+ *      This parameter returns a mask of enabled TPCs for the specified GPC.
+ *      Each TPC has an ID that's equivalent to the corresponding bit
+ *      position in the mask.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO (0x20800138U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID (0x38U)
+
+typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS {
+    NvU32 gpcId;
+    NvU32 tpcMask;
+} NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO
+ *
+ * This command returns a mask of enabled ZCULLs for a specified GPC.
+ *
+ *    gpcId
+ *      This parameter specifies the GPC for which ZCULL information is to be
+ *      retrieved. If the GPC with this ID is not enabled this command will
+ *      return an zcullMask value of zero.
+ *
+ *    zcullMask
+ *      This parameter returns a mask of enabled ZCULLs for the specified GPC.
+ *      Each ZCULL has an ID that's equivalent to the corresponding bit
+ *      position in the mask.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *
+ * Deprecated: Please use GR based control call
+ * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO (0x20800139U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID (0x39U)
+
+typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS {
+    NvU32 gpcId;
+    NvU32 zcullMask;
+} NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO
+ *
+ * If an InfoROM with a valid OEM Board Object is present, this
+ * command returns relevant information from the object to the
+ * caller.
+ *
+ * The following data are currently reported:
+ *
+ * buildDate
+ *   The board's build date (8 digit BCD in format YYYYMMDD).
+ *
+ * marketingName
+ *   The board's marketing name (24 ASCII letters e.g. "Quadro FX5800").
+ *
+ * boardSerialNumber
+ *   The board's serial number.
+ *
+ * memoryManufacturer
+ *   The board's memory manufacturer ('S'amsung/'H'ynix/'I'nfineon).
+ *
+ * memoryDateCode
+ *   The board's memory datecode (LSB justified ASCII field with 0x00
+ *   denoting empty space).
+ *
+ * productPartNumber
+ *   The board's 900 product part number (LSB justified ASCII field with 0x00
+ *   denoting empty space e.g. "900-21228-0208-200").
+ *
+ * boardRevision
+ *   The board's revision (for e.g. A02, B01)
+ *
+ * boardType
+ *   The board's type ('E'ngineering/'P'roduction)
+ *
+ * board699PartNumber
+ *   The board's 699 product part number (LSB justified ASCII field with 0x00
+ *   denoting empty space e.g. "699-21228-0208-200").
+ *
+ * board965PartNumber
+ *   The board's 965 product part number (LSB justified ASCII field with 0x00
+ *   denoting empty space e.g. "965-21228-0208-200").
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO    (0x2080013fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_GPU_MAX_MARKETING_NAME_LENGTH      (0x00000018U)
+#define NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH       (0x00000010U)
+#define NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH      (0x00000014U)
+#define NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH    (0x00000006U)
+#define NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH (0x00000014U)
+
+#define NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID (0x3FU)
+
+typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS {
+    NvU32 buildDate;
+    NvU8  marketingName[NV2080_GPU_MAX_MARKETING_NAME_LENGTH];
+    NvU8  serialNumber[NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH];
+    NvU8  memoryManufacturer;
+    NvU8  memoryPartID[NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH];
+    NvU8  memoryDateCode[NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH];
+    NvU8  productPartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH];
+    NvU8  boardRevision[3];
+    NvU8  boardType;
+    NvU8  board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH];
+    NvU8  board965PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH];
+} NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ID
+ *
+ * This command returns the gpuId of the associated object.
+ *
+ *   gpuId
+ *     This field return the gpuId.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ID (0x20800142U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID (0x42U)
+
+typedef struct NV2080_CTRL_GPU_GET_ID_PARAMS {
+    NvU32 gpuId;
+} NV2080_CTRL_GPU_GET_ID_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE
+ *
+ * This command is used to enable or disable GPU debug mode. While this mode
+ * is enabled,  some client RM calls that can potentially timeout return
+ * NV_ERR_BUSY_RETRY, signalling the client to try again once GPU
+ * debug mode is disabled.
+ *
+ * mode
+ *   This parameter specifies whether GPU debug mode is to be enabled or
+ *   disabled. Possible values are:
+ *
+ *     NV2080_CTRL_GPU_DEBUG_MODE_ENABLED
+ *     NV2080_CTRL_GPU_DEBUG_MODE_DISABLED
+ *
+ * Possible return status values are
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE (0x20800143U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x43U)
+
+typedef struct NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS {
+    NvU32 mode;
+} NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS;
+
+#define NV2080_CTRL_GPU_DEBUG_MODE_ENABLED     (0x00000001U)
+#define NV2080_CTRL_GPU_DEBUG_MODE_DISABLED    (0x00000002U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE
+ *
+ * This command is used to query whether debug mode is enabled on the current
+ * GPU. Please see the description of NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE
+ * for more details on GPU debug mode.
+ *
+ * currentMode
+ *   This parameter returns the state of GPU debug mode for the current GPU.
+ *   Possible values are:
+ *
+ *     NV2080_CTRL_GPU_DEBUG_MODE_ENABLED
+ *     NV2080_CTRL_GPU_DEBUG_MODE_DISABLED
+ *
+ * Possible return status values are
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE (0x20800144U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x44U)
+
+typedef struct NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS {
+    NvU32 currentMode;
+} NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST
+ *
+ * Returns a list of engines that can partner or coexist
+ * when using the target channel or partnership class.
+ * This list may include all engines (pre-Kepler), or as few
+ * as 1 engine (Kepler and beyond).
+ *
+ *   engineType
+ *     This field specifies the target engine type.
+ *     See cl2080.h for a list of valid engines.
+ *
+ *   partnershipClassId
+ *     This field specifies the target channel
+ *     or partnership class ID.
+ *     An example of such a class is GF100_CHANNEL_GPFIFO.
+ *
+ *   runqueue
+ *     This field is an index which indicates the runqueue to
+ *     return the list of supported engines for. This is the
+ *     same field as what NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE
+ *     specifies. This is only valid for TSG.
+ *
+ *   numPartners;
+ *     This field returns the number of
+ *     valid entries in the partnersList array
+ *
+ *   partnerList
+ *     This field is an array containing the list of supported
+ *     partner engines types, in no particular order, and
+ *     may even be empty (numPartners = 0).
+ *     See cl2080.h for a list of possible engines.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST           (0x20800147U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID" */
+
+/* this macro specifies the maximum number of partner entries */
+#define NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS                  (0x00000020U)
+
+#define NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID (0x47U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS {
+    NvU32 engineType;
+    NvU32 partnershipClassId;
+    NvU32 runqueue;
+    NvU32 numPartners;
+    // C form: NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS];
+    NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS];
+} NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_GID_INFO
+ *
+ * This command returns the GPU ID (GID) string for the associated
+ * GPU.  This value can be useful for GPU identification and security
+ * system validation.
+ *
+ * The GPU ID is a SHA-1 based 16 byte ID, formatted as a 32 character
+ *      hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the
+ *      canonical format of a UUID)
+ *
+ * The GPU IDs are generated using the ECID, PMC_BOOT_0, and
+ * PMC_BOOT_42 of the GPU as the hash message.
+ *
+ *   index
+ *     Index is ignored for GPU UUID. If MODE_UGPU is set in flags, index specifies
+ *     the which uGPU ID should be returned.
+ *
+ *   flags (Input) The _FORMAT* flags designate ascii or binary format. Binary
+ *     format returns the raw bytes of either the 16-byte SHA-1 ID or the
+ *     32-byte SHA-256 ID.
+ *
+ *     The _TYPE* flags needs to specify the _SHA1 type.
+ *
+ *     The _MODE* flags specify what type of GID to produce.
+ *
+ *   length
+ *     (Output) Actual GID length, in bytes.
+ *
+ *   data[NV2080_BUS_MAX_GID_LENGTH]
+ *     (Output) Result buffer: the GID itself, in a format that is determined by
+ *     the "flags" field (described above).
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_PARAMETER
+ *   NV_ERR_INVALID_INDEX
+ */
+#define NV2080_CTRL_CMD_GPU_GET_GID_INFO      (0x2080014aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID" */
+
+/* maximum possible number of bytes of GID information returned */
+#define NV2080_GPU_MAX_GID_LENGTH             (0x000000100ULL)
+
+/* maximum possible number of bytes of GID information returned if given the BINARY and SHA1 flags */
+#define NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH (0x000000010ULL)
+
+#define NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID (0x4AU)
+
+typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS {
+    NvU32 index;
+    NvU32 flags;
+    NvU32 length;
+    NvU8  data[NV2080_GPU_MAX_GID_LENGTH];
+} NV2080_CTRL_GPU_GET_GID_INFO_PARAMS;
+
+/* valid flags values */
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT                  1:0
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII  (0x00000000U)
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY (0x00000002U)
+
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE                    2:2
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1     (0x00000000U)
+
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_MODE                    5:3
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_MODE_GPU      (0x00000000U)
+#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_MODE_UGPU     (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION
+ *
+ * This command can be used by clients to retrieve the version of an
+ * InfoROM object.
+ *
+ *   objectType
+ *     This parameter specifies the name of the InfoROM object whose version
+ *     should be queried.
+ *
+ *   version
+ *     This parameter returns the version of the InfoROM object specified by
+ *     the objectType parameter.
+ *
+ *   subversion
+ *     This parameter returns the subversion of the InfoROM object specified
+ *     by the objectType parameter.
+ *
+ * Possible return status values:
+ *   NV_OK
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION (0x2080014bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN           3U
+
+#define NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID (0x4BU)
+
+typedef struct NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS {
+    char objectType[NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN];
+    NvU8 version;
+    NvU8 subversion;
+} NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO
+ *
+ * This command will specify that system is Optimus enabled.
+ *
+ * isOptimusEnabled
+ *     Set NV_TRUE if system is Optimus enabled.
+ *
+ * Possible status return values are:
+ *      NV_OK
+ */
+#define NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO (0x2080014cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID (0x4CU)
+
+typedef struct NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS {
+    NvBool isOptimusEnabled;
+} NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_IP_VERSION
+ *
+ * Will return the IP VERSION on the given engine for engines that support
+ * this capability.
+ *
+ *   targetEngine
+ *     This parameter specifies the target engine type to query for IP_VERSION.
+ *
+ *   ipVersion
+ *     This parameter returns the IP VERSION read from the unit's IP_VER
+ *     register.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_IP_VERSION (0x2080014dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4DU)
+
+typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS {
+    NvU32 targetEngine;
+    NvU32 ipVersion;
+} NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY       (0x00000001U)
+#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC      (0x00000002U)
+#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR          (0x00000003U)
+#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU      (0x00000004U)
+#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON   (0x00000005U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_ID_ILLUM_SUPPORT
+ *
+ * This command returns an indicator which reports if the specified Illumination control
+ * attribute is supported
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS 0U
+#define NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS  1U
+#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT      (0x20800153U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID (0x53U)
+
+typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS {
+    NvU32  attribute;
+    NvBool bSupported;
+} NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ID_ILLUM
+ *
+ * This command returns the current value of the specified Illumination control attribute.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS {
+    NvU32 attribute;
+    NvU32 value;
+} NV2080_CTRL_CMD_GPU_ILLUM_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID (0x54U)
+
+typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_GET_ILLUM_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_ID_ILLUM
+ *
+ * This command sets a new valuefor the specified Illumination control attribute.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0x55U)
+
+typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_SET_ILLUM_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION
+ *
+ * This command can be used by clients to retrieve the version of the entire
+ * InfoROM image.
+ *
+ *   version
+ *      This parameter returns the version of the InfoROM image as a NULL-
+ *      terminated character string of the form "XXXX.XXXX.XX.XX" where each
+ *      'X' is an integer character.
+ *
+ * Possible status return values are:
+ *   NVOS_STATUS_SUCCES
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_DATA
+ */
+#define NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION (0x20800156U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN     16U
+
+#define NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID (0x56U)
+
+typedef struct NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS {
+    NvU8 version[NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN];
+} NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT
+ *
+ * This command returns whether or not ECC is supported via the InfoROM.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT (0x20800157U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x57" */
+
+/*
+ * NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION
+ *
+ * This structure contains information about a single physical bridge.
+ *
+ *   fwVersion
+ *     This field specifies Firmware Version of the bridge stored in
+ *     bridge EEPROM.
+ *   oemVersion
+ *     This field specifies Oem Version of the firmware stored in
+ *     bridge EEPROM.
+ *   siliconRevision
+ *     This field contains the silicon revision of the bridge hardware.
+ *     It is set by the chip manufacturer.
+ *   hwbcResourceType
+ *     This field specifies the hardware broadcast resource type.
+ *     Value denotes the kind of bridge - PLX or BR04
+ *
+ */
+
+typedef struct NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS {
+    NvU32 fwVersion;
+    NvU8  oemVersion;
+    NvU8  siliconRevision;
+    NvU8  hwbcResourceType;
+} NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO
+ *
+ * This command returns physical bridge information in the system.
+ * Information consists of bridgeCount and a list of bridgeId's.
+ * The bridge Id's are used by NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION
+ * to get firmware version, oem version and silicon revision info.
+ *
+ *   bridgeCount
+ *     This field specifies the number of physical brides present
+ *     in the system.
+ *   hPhysicalBridges
+ *     This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE.
+ *     In this array, the bridge Id's are stored.
+ *   bridgeList
+ *     This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE.
+ *     In this array, the bridge version details are stored.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO (0x2080015aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MAX_PHYSICAL_BRIDGE                      (100U)
+#define NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID (0x5AU)
+
+typedef struct NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS {
+    NvU8                                           bridgeCount;
+    NvHandle                                       hPhysicalBridges[NV2080_CTRL_MAX_PHYSICAL_BRIDGE];
+    NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE];
+} NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_GPU_BRIDGE_VERSION
+ *
+ * This structure contains information about a single physical bridge.
+ *
+ *   bus
+ *     This field specifies the bus id of the bridge.
+ *   device
+ *     This field specifies the device id of the bridge.
+ *   func
+ *     This field specifies the function id of the bridge.
+ *   oemVersion
+ *     This field specifies Oem Version of the firmware stored in
+ *     bridge EEPROM.
+ *   siliconRevision
+ *     This field contains the silicon revision of the bridge hardware.
+ *     It is set by the chip manufacturer.
+ *   hwbcResourceType
+ *     This field specifies the hardware broadcast resource type.
+ *     Value denotes the kind of bridge - PLX or BR04
+ *   domain
+ *     This field specifies the respective domain of the PCI device.
+ *   fwVersion
+ *     This field specifies Firmware Version of the bridge stored in
+ *     bridge EEPROM.
+ *
+ *   If (fwVersion, oemVersion, siliconRevision) == 0, it would mean that RM
+ *   was unable to fetch the value from the bridge device.
+ *
+ */
+
+typedef struct NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS {
+    NvU8  bus;
+    NvU8  device;
+    NvU8  func;
+    NvU8  oemVersion;
+    NvU8  siliconRevision;
+    NvU8  hwbcResourceType;
+    NvU32 domain;
+    NvU32 fwVersion;
+} NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU
+ *
+ * This command returns information about all the upstream bridges of the GPU.
+ * Information consists of bridge firmware version and its bus topology.
+ *
+ *   bridgeCount
+ *     This field specifies the number of physical brides present
+ *     in the system.
+ *   physicalBridgeIds
+ *     This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE.
+ *     In this array, the bridge Ids are stored.
+ *   bridgeList
+ *     This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE.
+ *     In this array, the bridge version details are stored.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU (0x2080015bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID (0x5BU)
+
+typedef struct NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS {
+    NvU8                                  bridgeCount;
+    NvU32                                 physicalBridgeIds[NV2080_CTRL_MAX_PHYSICAL_BRIDGE];
+    NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE];
+} NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS
+ *
+ * This command is used to query the status of the HW scrubber. If a scrub is
+ * in progress then the range which is being scrubbed is also reported back.
+ *
+ *   scrubberStatus
+ *     Reports the status of the scrubber unit - running/idle.
+ *
+ *   remainingtimeMs
+ *     If scrubbing is going on, reports the remaining time in milliseconds
+ *     required to finish the scrub.
+ *
+ *   scrubStartAddr
+ *     This parameter reports the start address of the ongoing scrub if scrub
+ *     is going on, otherwise reports the start addr of the last finished scrub
+ *
+ *   scrubEndAddr
+ *     This parameter reports the end address of the ongoing scrub if scrub
+ *     is going on, otherwise reports the end addr of the last finished scrub.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS (0x2080015fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID (0x5FU)
+
+typedef struct NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS {
+    NvU32 scrubberStatus;
+    NvU32 remainingTimeMs;
+    NV_DECLARE_ALIGNED(NvU64 scrubStartAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 scrubEndAddr, 8);
+} NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS;
+
+/* valid values for scrubber status */
+#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING (0x00000000U)
+#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE    (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_VPR_CAPS
+ *
+ * This command is used to query the VPR capability information for a
+ * GPU. If VPR is supported, the parameters are filled accordingly.
+ * The addresses returned are all physical addresses.
+ *
+ *   minStartAddr
+ *     Returns the minimum start address that can be possible for VPR.
+ *
+ *   maxEndAddr
+ *     Returns the maximum end   address that can be possible for VPR.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_VPR_CAPS                       (0x20800160U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID (0x60U)
+
+typedef struct NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 minStartAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 maxEndAddr, 8);
+} NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR
+ *
+ * Communicates to RM to handle GPU Surprise Removal
+ * Called from client when it receives SR IRP from OS
+ * Possible status values returned are:
+ *   NVOS_STATUS_SUCCESS
+ */
+#define NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR                      (0x20800167U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x67" */
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_PES_INFO
+ *
+ * This command provides the PES count and mask of enabled PES for a
+ * specified GPC. It also returns the TPC to PES mapping information
+ * for a given GPU.
+ *
+ *   gpcId[IN]
+ *     This parameter specifies the GPC for which PES information is to be
+ *     retrieved. If the GPC with this ID is not enabled this command will
+ *     return an activePesMask of zero
+ *
+ *   numPesInGpc[OUT]
+ *     This parameter returns the number of PES in this GPC.
+ *
+ *   activePesMask[OUT]
+ *     This parameter returns a mask of enabled PESs for the specified GPC.
+ *     Each PES has an ID that is equivalent to the corresponding bit position
+ *     in the mask.
+ *
+ *   maxTpcPerGpcCount[OUT]
+ *     This parameter returns the max number of TPCs in a GPC.
+ *
+ *   tpcToPesMap[OUT]
+ *     This array stores the TPC to PES mappings. The value at tpcToPesMap[tpcIndex]
+ *     is the index of the PES it belongs to.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_PES_INFO                       (0x20800168U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT 10U
+
+#define NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID (0x68U)
+
+typedef struct NV2080_CTRL_GPU_GET_PES_INFO_PARAMS {
+    NvU32 gpcId;
+    NvU32 numPesInGpc;
+    NvU32 activePesMask;
+    NvU32 maxTpcPerGpcCount;
+    NvU32 tpcToPesMap[NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT];
+} NV2080_CTRL_GPU_GET_PES_INFO_PARAMS;
+
+/* NV2080_CTRL_CMD_GPU_GET_OEM_INFO
+ *
+ * If an InfoROM with a valid OEM Object is present, this
+ * command returns relevant information from the object to the
+ * caller.
+ *
+ * oemInfo
+ *  This array stores information specifically for OEM use
+ *  (e.g. "their own serial number", "lot codes", etc)
+ *  "The byte definition is up to the OEM"
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_OEM_INFO (0x20800169U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_GPU_MAX_OEM_INFO_LENGTH   (0x000001F8U)
+
+#define NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID (0x69U)
+
+typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS {
+    NvU8 oemInfo[NV2080_GPU_MAX_OEM_INFO_LENGTH];
+} NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_VPR_INFO
+ *
+ * This command is used to query the VPR information for a GPU.
+ * The following VPR related information can be queried by selecting the queryType:
+ *   1. The current VPR range.
+ *   2. The max VPR range ever possible on this GPU.
+ *
+ *   queryType [in]
+ *     This input parameter is used to select the type of information to query.
+ *     Possible values for this parameter are:
+ *       1. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS: Use this to query the
+ *              max VPR range ever possible on this GPU.
+ *       2. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE: Use this to query
+ *              the current VPR range on this GPU.
+ *
+ *   bVprEnabled [out]
+ *     For query type "NV2080_CTRL_GPU_GET_VPR_INFO_CUR_RANGE", this parameter
+ *     returns if VPR is currently enabled or not.
+ *
+ *   vprStartAddress [out]
+ *     For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns minimum allowed VPR start address.
+ *     For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR start address.
+ *
+ *   vprEndAddress [out]
+ *     For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns maximum allowed VPR end address.
+ *     For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR end address.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */
+
+
+typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE {
+    NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = 0,
+    NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = 1,
+} NV2080_CTRL_VPR_INFO_QUERY_TYPE;
+
+#define NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID (0x6BU)
+
+typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS {
+    NV2080_CTRL_VPR_INFO_QUERY_TYPE queryType;
+    NvBool                          bIsVprEnabled;
+    NV_DECLARE_ALIGNED(NvU64 vprStartAddressInBytes, 8);
+    NV_DECLARE_ALIGNED(NvU64 vprEndAddressInBytes, 8);
+} NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY
+ *
+ * This command is used to query the encoder capacity of the GPU.
+ *
+ *   queryType [in]
+ *     This input parameter is used to select the type of information to query.
+ *     Possible values for this parameter are:
+ *       1. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264: Use this to query the
+ *              H.264 encoding capacity on this GPU.
+ *       2. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC: Use this to query the
+ *              H.265/HEVC encoding capacity on this GPU.
+ *       3. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1: Use this to query the
+ *              AV1 encoding capacity on this GPU.
+ *
+ *   encoderCapacity [out]
+ *     Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance
+ *     may be minimal for this GPU and software should fall back to CPU-based encode.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY (0x2080016cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE {
+    NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0,
+    NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1,
+    NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = 2,
+} NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE;
+
+#define NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x6CU)
+
+typedef struct NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS {
+    NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE queryType;
+    NvU32                                   encoderCapacity;
+} NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS;
+
+/*
+ * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS
+ *
+ * This command is used to retrieve the GPU's count of encoder sessions,
+ * trailing average FPS and encode latency over all active sessions.
+ *
+ *   encoderSessionCount
+ *     This field specifies count of all active encoder sessions on this GPU.
+ *
+ *   averageEncodeFps
+ *     This field specifies the average encode FPS for this GPU.
+ *
+ *   averageEncodeLatency
+ *     This field specifies the average encode latency in microseconds for this GPU.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS (0x2080016dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x6DU)
+
+typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS {
+    NvU32 encoderSessionCount;
+    NvU32 averageEncodeFps;
+    NvU32 averageEncodeLatency;
+} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS;
+
+#define NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES 0x200U  // 512 entries.
+
+/*
+ * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO
+ *
+ * This command returns NVENC software sessions information for the associate GPU.
+ * Request to retrieve session information use a list of one or more
+ * NV2080_CTRL_NVENC_SW_SESSION_INFO structures.
+ *
+ *   sessionInfoTblEntry
+ *     This field specifies the number of entries on the that are filled inside
+ *     sessionInfoTbl. Max value of this field once returned from RM would be
+ *     NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES,
+ *
+ *   sessionInfoTbl
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the NVENC session information is to be returned.
+ *     When buffer is NULL, RM assume that client is querying sessions count value
+ *     and return the current encoder session counts in sessionInfoTblEntry field.
+ *     To get actual buffer data, client should allocate sessionInfoTbl of size
+ *     NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES  multiplied by the
+ *     size of the NV2080_CTRL_NVENC_SW_SESSION_INFO structure. RM will fill the
+ *     current session data in sessionInfoTbl buffer and then update the
+ *     sessionInfoTblEntry to reflect current session count value.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NO_MEMORY
+ *   NV_ERR_INVALID_LOCK_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+typedef struct NV2080_CTRL_NVENC_SW_SESSION_INFO {
+    NvU32 processId;
+    NvU32 subProcessId;
+    NvU32 sessionId;
+    NvU32 codecType;
+    NvU32 hResolution;
+    NvU32 vResolution;
+    NvU32 averageEncodeFps;
+    NvU32 averageEncodeLatency;
+} NV2080_CTRL_NVENC_SW_SESSION_INFO;
+
+#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x6EU)
+
+typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS {
+    NvU32 sessionInfoTblEntry;
+    NV_DECLARE_ALIGNED(NvP64 sessionInfoTbl, 8);
+} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO (0x2080016eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR
+ *
+ * The command sets fabric base address which represents top N bits of a
+ * peer memory address. These N bits will be used to index NvSwitch routing
+ * tables to forward peer memory accesses to associated GPUs.
+ *
+ * The command is available to clients with administrator privileges only.
+ * An attempt to use this command by a client without administrator privileged
+ * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status.
+ *
+ * The command allows to set fabricAddr once in a lifetime of a GPU. A GPU must
+ * be destroyed in order to re-assign a different fabricAddr. An attempt to
+ * re-assign address without destroying a GPU would result in the return of
+ * NV_ERR_STATE_IN_USE status.
+ *
+ *   fabricBaseAddr[IN]
+ *      - An address with at least 32GB alignment.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_STATE_IN_USE
+ */
+
+#define NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x6FU)
+
+typedef struct NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 fabricBaseAddr, 8);
+} NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT
+ *
+ * The command will trigger the specified interrupt on the host from a guest.
+ *
+ *   handle[IN]
+ *      - An opaque handle that will be passed in along with the interrupt
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID (0x72U)
+
+typedef struct NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS {
+    NvU32 handle;
+} NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT                                      (0x20800172U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS
+ *
+ * This control call is to query the status of gpu function registers
+ *
+ *    statusMask[IN]
+ *        - Input mask of required status registers
+ *    xusbData[OUT]
+ *        - data from querying XUSB status register
+ *    ppcData[OUT]
+ *        - data from querying PPC status register
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+
+
+#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID (0x73U)
+
+typedef struct NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS {
+    NvU32 statusMask;
+    NvU32 xusbData;
+    NvU32 ppcData;
+} NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS (0x20800173U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_GPU_PARTITION_SPAN
+ *
+ * This struct represents the span of a memory partition, which represents the
+ * slices a given partition occupies (or may occupy) within a fixed range which
+ * is defined per-chip. A partition containing more resources will cover more
+ * GPU slices and therefore cover a larger span.
+ *
+ *   lo
+ *      - The starting unit of this span, inclusive
+ *
+ *   hi
+ *      - The ending unit of this span, inclusive
+ *
+ */
+typedef struct NV2080_CTRL_GPU_PARTITION_SPAN {
+    NV_DECLARE_ALIGNED(NvU64 lo, 8);
+    NV_DECLARE_ALIGNED(NvU64 hi, 8);
+} NV2080_CTRL_GPU_PARTITION_SPAN;
+
+/*
+ * NV2080_CTRL_EXEC_PARTITION_SPAN
+ *
+ * This struct represents the span of a compute partition, which represents the
+ * slices a given partition occupies (or may occupy) within a fixed range which
+ * is defined memory partition. A partition containing more resources will cover
+ * more GPU instance slices and therefore cover a larger span.
+ *
+ *   lo
+ *      - The starting unit of this span, inclusive
+ *
+ *   hi
+ *      - The ending unit of this span, inclusive
+ *
+ */
+typedef struct NV2080_CTRL_EXEC_PARTITION_SPAN {
+    NV_DECLARE_ALIGNED(NvU64 lo, 8);
+    NV_DECLARE_ALIGNED(NvU64 hi, 8);
+} NV2080_CTRL_EXEC_PARTITION_SPAN;
+
+#define NV_GI_UUID_LEN 16U
+
+/*
+ * NV2080_CTRL_GPU_SET_PARTITION_INFO
+ *
+ * This command partitions a GPU into different SMC-Memory partitions.
+ * The command will configure HW partition table to create work and memory
+ * isolation.
+ *
+ * The command is available to clients with administrator privileges only.
+ * An attempt to use this command by a client without administrator privileged
+ * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status.
+ *
+ * The command allows partitioning an invalid partition only. An attempt to
+ * re-partition a valid partition will resule in NV_ERR_STATE_IN_USE.
+ * Repartitioning can be done only if a partition has been destroyed/invalidated
+ * before re-partitioning.
+ *
+ *   swizzId[IN/OUT]
+ *      - PartitionID associated with a newly created partition. Input in case
+ *        of partition invalidation.
+ *
+ *   uuid[OUT]
+ *      - Uuid of a newly created partition.
+ *
+ *   partitionFlag[IN]
+ *      - Flags to determine if GPU is requested to be partitioned in FULL,
+ *        HALF, QUARTER or ONE_EIGHTHED and whether the partition requires
+ *        any additional resources.
+ *        When flags include NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA
+ *        partition will be created with at least one video decode, jpeg and
+ *        optical flow engines. This flag is valid only for partitions with
+ *        a single GPC.
+ *
+ *   bValid[IN]
+ *      - NV_TRUE if creating a partition. NV_FALSE if destroying a partition.
+ *
+ *   placement[IN]
+ *      - Optional placement span to allocate the partition into. Valid
+ *        placements are returned from NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY.
+ *        The partition flag NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN must
+ *        be set for this parameter to be used. If the flag is set and the given
+ *        placement is not valid, an error will be returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_STATE_IN_USE
+ */
+typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
+    NvU32  swizzId;
+    NvU8   uuid[NV_GI_UUID_LEN];
+    NvU32  partitionFlag;
+    NvBool bValid;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8);
+} NV2080_CTRL_GPU_SET_PARTITION_INFO;
+
+#define PARTITIONID_INVALID                                                          NV2080_CTRL_GPU_PARTITION_ID_INVALID
+#define NV2080_CTRL_GPU_PARTITION_ID_INVALID                                         0xFFFFFFFFU
+#define NV2080_CTRL_GPU_MAX_PARTITIONS                                               0x00000008U
+#define NV2080_CTRL_GPU_MAX_PARTITION_IDS                                            0x00000009U
+#define NV2080_CTRL_GPU_MAX_SMC_IDS                                                  0x00000008U
+#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC                                              0x00000040U
+#define NV2080_CTRL_GPU_MAX_CE_PER_SMC                                               0x00000008U
+
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE              1:0
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL                              0x00000000U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF                              0x00000001U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER                           0x00000002U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH                            0x00000003U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE                             4U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE             4:2
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL                             0x00000000U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF                             0x00000001U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF                        0x00000002U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER                          0x00000003U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER                     0x00000004U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH                           0x00000005U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06             0x00000006U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07             0x00000007U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE                            8U
+
+
+
+#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE                7:5
+#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL                                 0x00000001U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF                                 0x00000002U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF                            0x00000003U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER                              0x00000004U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH                               0x00000005U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06                 0x00000006U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07                 0x00000007U
+
+#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE                                 0x00000000U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE                                8U
+
+
+#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES                                          90U
+
+#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA          29:28
+#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DEFAULT                         0U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DISABLE                         1U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_ENABLE                          2U
+
+
+#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA          30:30
+#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE                       0U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE                        1U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN            31:31
+#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE                         0U
+#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE                          1U
+
+// TODO XXX Bug 2657907 Remove these once clients update
+#define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU                 (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL)    | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL))
+#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU             (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF)    | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF))
+#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU        (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF)    | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF))
+#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU          (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER))
+#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU     (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_QUARTER))
+#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU         (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH)  | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH))
+
+#define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U)
+
+typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS {
+    NvU32 partitionCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_SET_PARTITION_INFO partitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
+} NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_SET_PARTITIONS (0x20800174U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_GPU_GET_PARTITION_INFO
+ *
+ * This command gets the partition information for requested partitions.
+ * If GPU is not partitioned, the control call will return NV_ERR_NOT_SUPPORTED.
+ *
+ * The command will can return global partition information as well as single
+ * partition information if global flag is not set.
+ * In bare-metal user-mode can request all partition info while in virtualization
+ * plugin should make an RPC with swizzId which is assigned to the requesting
+ * VM.
+ *
+ *   swizzId[IN]
+ *      - HW Partition ID associated with the requested partition.
+ *
+ *   partitionFlag[OUT]
+ *      - partitionFlag that was provided during partition creation.
+ *
+ *   grEngCount[OUT]
+ *      - Number of SMC engines/GR engines allocated in partition
+ *        GrIDs in a partition will always start from 0 and end at grEngCount-1
+ *
+ *   veidCount[OUT]
+ *      - VEID Count assigned to a partition. These will be divided across
+ *        SMC engines once CONFIGURE_PARTITION call has been made. The current
+ *        algorithm is to assign veidPerGpc * gpcCountPerSmc to a SMC engine.
+ *
+ *   smCount[OUT]
+ *      - SMs assigned to a partition.
+ *
+ *   ceCount[OUT]
+ *      - Copy Engines assigned to a partition.
+ *
+ *   nvEncCount[OUT]
+ *      - NvEnc Engines assigned to a partition.
+ *
+ *   nvDecCount[OUT]
+ *      - NvDec Engines assigned to a partition.
+ *
+ *   nvJpgCount[OUT]
+ *      - NvJpg Engines assigned to a partition.
+ *
+ *   gpcCount[OUT]
+ *      - Max GPCs assigned to a partition, including the GfxCapable ones.
+ *
+ *   virtualGpcCount[OUT]
+ *      - Virtualized GPC count assigned to partition
+ *
+ *   gfxGpcCount[OUT]
+ *      - Max GFX GPCs assigned to a partition. This is a subset of the GPCs incuded in gpcCount.
+ *
+ *   gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
+ *      - GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX
+ *
+ *   virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
+ *      - Virtualized GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX
+ *
+ *   gfxGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
+ *      - GFX GPC count associated with every valid SMC/Gr. This is a subset of the GPCs included in gfxGpcCount
+ *
+ *   veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT]
+ *      - VEID count associated with every valid SMC. VEIDs within this SMC
+ *        will start from 0 and go till veidCount[SMC_ID] - 1.
+ *
+ *   span[OUT]
+ *      - The span covered by this partition
+ *
+ *   bValid[OUT]
+ *      - NV_TRUE if partition is valid else NV_FALSE.
+ *
+ *   bPartitionError[OUT]
+ *      - NV_TRUE if partition had poison error which requires drain and reset
+ *        else NV_FALSE.
+ *
+ *   validCTSIdMask[OUT]
+ *      - Mask of CTS IDs usable by this partition, not reflecting current allocations
+ *
+ *   validGfxCTSIdMask[OUT]
+ *      - Mask of CTS IDs that contain Gfx capable Grs usable by this partition, not reflecting current allocations
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_NOT_SUPPORTED
+ */
+typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO {
+    NvU32  swizzId;
+    NvU32  partitionFlag;
+    NvU32  grEngCount;
+    NvU32  veidCount;
+    NvU32  smCount;
+    NvU32  ceCount;
+    NvU32  nvEncCount;
+    NvU32  nvDecCount;
+    NvU32  nvJpgCount;
+    NvU32  nvOfaCount;
+    NvU32  gpcCount;
+    NvU32  virtualGpcCount;
+    NvU32  gfxGpcCount;
+    NvU32  gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
+    NvU32  virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
+    NvU32  gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
+    NvU32  veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
+    NV_DECLARE_ALIGNED(NvU64 memSize, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN span, 8);
+    NvBool bValid;
+    NvBool bPartitionError;
+    NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8);
+    NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8);
+} NV2080_CTRL_GPU_GET_PARTITION_INFO;
+
+/*
+ * NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS
+ *
+ *   queryPartitionInfo[IN]
+ *      - Max sized array of NV2080_CTRL_GPU_GET_PARTITION_INFO to get partition
+ *       Info
+ *
+ *   bGetAllPartitionInfo[In]
+ *      - Flag to get all partitions info. Only root client will receive all
+ *        partition's info. Non-Root clients should not use this flag
+ *
+ *   validPartitionCount[Out]
+ *      - Valid partition count which has been filled by RM as part of the call
+ *
+ */
+#define NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID (0x75U)
+
+typedef struct NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_GET_PARTITION_INFO queryPartitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
+    NvU32  validPartitionCount;
+    NvBool bGetAllPartitionInfo;
+} NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_PARTITIONS      (0x20800175U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_GPU_CONFIGURE_PARTITION
+ *
+ * This command configures a partition by associating GPCs with SMC Engines
+ * available in that partition. Engines which are to have GPCs assigned to them
+ * shall not already have any GPCs assigned to them. It is not valid to both
+ * assign GPCs and remove GPCs as part of a single call to this function.
+ *
+ *   swizzId[IN]
+ *      - PartitionID for configuring partition. If partition has a valid
+ *        context created, then configuration is not allowed.
+ *
+ *   gpcCountPerSmcEng[IN]
+ *      - Number of GPCs expected to be configured per SMC. Supported
+ *        configurations are 0, 1, 2, 4 or 8. "0" means a particular SMC
+ *        engine will be disabled with no GPC connected to it.
+ *
+ *   updateSmcEngMask[IN]
+ *      - Mask tracking valid entries of gpcCountPerSmcEng. A value of
+ *        0 in bit index i indicates that engine i will keep its current
+ *        configuration.
+ *
+ *   bUseAllGPCs[IN]
+ *      - Flag specifying alternate configuration mode, indicating that in
+ *        swizzid 0 only, all non-floorswept GPCs should be connected to the
+ *        engine indicated by a raised bit in updateSmcEngMask. Only a single
+ *        engine may be targeted by this operation. The gpcCountPerSmcEng
+ *        parameter should not be used with this flag.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_INSUFFICIENT_RESOURCES
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_STATE_IN_USE
+ */
+#define NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION (0x20800176U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID (0x76U)
+
+typedef struct NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS {
+    NvU32  swizzId;
+    NvU32  gpcCountPerSmcEng[NV2080_CTRL_GPU_MAX_SMC_IDS];
+    NvU32  updateSmcEngMask;
+    NvBool bUseAllGPCs;
+} NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS;
+
+
+/*
+ * NV2080_CTRL_GPU_FAULT_PACKET
+ *
+ * This struct represents a GMMU fault packet.
+ *
+ */
+#define NV2080_CTRL_GPU_FAULT_PACKET_SIZE 32U
+typedef struct NV2080_CTRL_GPU_FAULT_PACKET {
+    NvU8 data[NV2080_CTRL_GPU_FAULT_PACKET_SIZE];
+} NV2080_CTRL_GPU_FAULT_PACKET;
+
+/*
+ * NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT
+ *
+ * This command reports a nonreplayable fault packet to RM.
+ * It is only used by UVM.
+ *
+ *   pFaultPacket[IN]
+ *      - A fault packet that will be later cast to GMMU_FAULT_PACKET *.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT (0x20800177U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID (0x77U)
+
+typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS {
+    NV2080_CTRL_GPU_FAULT_PACKET faultPacket;
+} NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU
+ *
+ *  This command is similar to NV2080_CTRL_CMD_GPU_EXEC_REG_OPS, except it is used
+ *  by the VGPU plugin client only. This command provides access to the subset of
+ *  privileged registers.
+ *
+ *  See confluence page "vGPU UMED Security" for details.
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID (0x78U)
+
+typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE
+ *
+ * This command returns the runlist pri base of the specified engine(s).
+ *
+ *   engineList
+ *     Input array.
+ *     This array specifies the engines being queried for information.
+ *     The list of engines supported by a chip can be fetched using the
+ *     NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call.
+ *
+ *   runlistPriBase
+ *     Output array.
+ *     Returns the runlist pri base for the specified engines
+ *     Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL
+ *     and will return _ERROR when the control call fails due to an invalid argument
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE (0x20800179U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID (0x79U)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS {
+    NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+    NvU32 runlistPriBase[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+    NvU32 runlistId[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+} NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL  (0xFFFFFFFFU)
+#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFBU)
+#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID        (0xFFFFFFFFU)
+#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR          (0xFFFFFFFBU)
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID
+ *
+ * This command returns the host hardware defined engine ID of the specified engine(s).
+ *
+ *   engineList
+ *     Input array.
+ *     This array specifies the engines being queried for information.
+ *     The list of engines supported by a chip can be fetched using the
+ *     NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call.
+ *
+ *   hwEngineID
+ *     Output array.
+ *     Returns the host hardware engine ID(s) for the specified engines
+ *     Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL
+ *     and will return _ERROR when the control call fails due to an invalid argument
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID              (0x2080017aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID (0x7AU)
+
+typedef struct NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS {
+    NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+    NvU32 hwEngineID[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
+} NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL      (0xFFFFFFFFU)
+#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR     (0xFFFFFFFBU)
+
+/*
+ * NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS
+ *
+ * This command is used to retrieve the GPU's count of FBC sessions,
+ * average FBC calls and FBC latency over all active sessions.
+ *
+ *   sessionCount
+ *     This field specifies count of all active fbc sessions on this GPU.
+ *
+ *   averageFPS
+ *     This field specifies the average frames captured.
+ *
+ *   averageLatency
+ *     This field specifies the average FBC latency in microseconds.
+ *
+ * Possible status values returned are :
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+*/
+#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS (0x2080017bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x7BU)
+
+typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS {
+    NvU32 sessionCount;
+    NvU32 averageFPS;
+    NvU32 averageLatency;
+} NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS;
+
+/*
+* NV2080_CTRL_NVFBC_SW_SESSION_INFO
+*
+*   processId[OUT]
+*           Process id of the process owning the NvFBC session.
+*           On VGX host, this will specify the vGPU plugin process id.
+*   subProcessId[OUT]
+*           Process id of the process owning the NvFBC session if the
+*           session is on VGX guest, else the value is zero.
+*   vgpuInstanceId[OUT]
+*           vGPU on which the process owning the NvFBC session
+*           is running if session is on VGX guest, else
+*           the value is zero.
+*   sessionId[OUT]
+*           Unique session id of the NvFBC session.
+*   sessionType[OUT]
+*           Type of NvFBC session.
+*   displayOrdinal[OUT]
+*           Display identifier associated with the NvFBC session.
+*   sessionFlags[OUT]
+*           One or more of NV2080_CTRL_NVFBC_SESSION_FLAG_xxx.
+*   hMaxResolution[OUT]
+*           Max horizontal resolution supported by the NvFBC session.
+*   vMaxResolution[OUT]
+*           Max vertical resolution supported by the NvFBC session.
+*   hResolution[OUT]
+*           Horizontal resolution requested by caller in grab call.
+*   vResolution[OUT]
+*           Vertical resolution requested by caller in grab call.
+*   averageFPS[OUT]
+*           Average no. of frames captured per second.
+*   averageLatency[OUT]
+*           Average frame capture latency in microseconds.
+*/
+
+#define NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED            0x00000001U
+#define NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED  0x00000002U
+#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT  0x00000004U
+#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008U
+#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT  0x00000010U
+
+typedef struct NV2080_CTRL_NVFBC_SW_SESSION_INFO {
+    NvU32 processId;
+    NvU32 subProcessId;
+    NvU32 vgpuInstanceId;
+    NvU32 sessionId;
+    NvU32 sessionType;
+    NvU32 displayOrdinal;
+    NvU32 sessionFlags;
+    NvU32 hMaxResolution;
+    NvU32 vMaxResolution;
+    NvU32 hResolution;
+    NvU32 vResolution;
+    NvU32 averageFPS;
+    NvU32 averageLatency;
+} NV2080_CTRL_NVFBC_SW_SESSION_INFO;
+
+/*
+* NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO
+*
+* This command returns NVFBC software sessions information for the associate GPU.
+*
+*   sessionInfoCount
+*     This field specifies the number of entries that are filled inside
+*     sessionInfoTbl. Max value of this field once returned from RM would be
+*     NV2080_GPU_NVFBC_MAX_COUNT.
+*
+*   sessionInfoTbl
+*     This field specifies the array in which the NVFBC session information is to
+*     be returned. RM will fill the current session data in sessionInfoTbl array
+*     and then update the sessionInfoCount to reflect current session count value.
+*
+* Possible status values returned are:
+*   NV_OK
+*   NV_ERR_NO_MEMORY
+*   NV_ERR_INVALID_LOCK_STATE
+*   NV_ERR_INVALID_ARGUMENT
+*/
+
+#define NV2080_GPU_NVFBC_MAX_SESSION_COUNT 256U
+
+#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x7CU)
+
+typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS {
+    NvU32                             sessionInfoCount;
+    NV2080_CTRL_NVFBC_SW_SESSION_INFO sessionInfoTbl[NV2080_GPU_NVFBC_MAX_SESSION_COUNT];
+} NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX
+ *
+ * This command returns the first async ce index
+ *
+ *   CE Index
+ *     Output parameter.
+ *     Returns the first async ce index
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID (0xe6U)
+
+typedef struct NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS {
+    NvU32 firstAsyncCEIdx;
+} NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS;
+#define NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX (0x208001e6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID" */
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE
+ *
+ * This command returns the VMMU page size
+ *
+ *   vmmuSegmentSize
+ *     Output parameter.
+ *     Returns the VMMU segment size (in bytes)
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE  (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID (0x7EU)
+
+typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 vmmuSegmentSize, 8);
+} NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS;
+
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB     0x02000000U
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB     0x04000000U
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB    0x08000000U
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB    0x10000000U
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB    0x20000000U
+#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_1024MB   0x40000000U
+
+/*
+ * NV2080_CTRL_GPU_GET_PARTITION_CAPACITY
+ *
+ * This command returns the count of partitions of given size (represented by
+ * NV2080_CTRL_GPU_PARTITION_FLAG_*) which can be requested via
+ * NV2080_CTRL_GPU_SET_PARTITIONS ctrl call.
+ * Note that this API does not "reserve" any partitions, and there is no
+ * guarantee that the reported count of available partitions of a given size
+ * will remain consistent following creation of partitions of different size
+ * through NV2080_CTRL_GPU_SET_PARTITIONS.
+ * Note that this API is unsupported if SMC is feature-disabled.
+ *
+ *   partitionFlag[IN]
+ *      - Partition flag indicating size of requested partitions
+ *
+ *   partitionCount[OUT]
+ *      - Available number of partitions of the given size which can currently be created.
+ *
+ *   availableSpans[OUT]
+ *      - For each partition able to be created of the specified size, the span
+ *        it could occupy.
+ *
+ *   availableSpansCount[OUT]
+ *      - Number of valid entries in availableSpans.
+ *
+ *   totalPartitionCount[OUT]
+ *      - Total number of partitions of the given size which can be created.
+ *
+ *   totalSpans[OUT]
+ *      - List of spans which can possibly be occupied by partitions of the
+ *        given type.
+ *
+ *   totalSpansCount[OUT]
+ *      - Number of valid entries in totalSpans.
+ *
+ *   bStaticInfo[IN]
+ *      - Flag indicating that client requests only the information from
+ *        totalPartitionCount and totalSpans.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY (0x20800181U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID (0x81U)
+
+typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS {
+    NvU32  partitionFlag;
+    NvU32  partitionCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN availableSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
+    NvU32  availableSpansCount;
+    NvU32  totalPartitionCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
+    NvU32  totalSpansCount;
+    NvBool bStaticInfo;
+} NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_CACHED_INFO
+ *
+ * This command returns cached(SW only) gpu information for the associated GPU.
+ * Requests to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO
+ * structures.
+ * The gpuInfoList is aligned with NV2080_CTRL_GPU_GET_INFO_V2_PARAMS for security concern
+ *
+ *   gpuInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     gpuInfoList.
+ *   gpuInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the gpu information is to be returned.
+ *     This buffer must be at least as big as gpuInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_GPU_INFO structure.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID (0x82U)
+
+typedef NV2080_CTRL_GPU_GET_INFO_V2_PARAMS NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_GPU_SET_PARTITIONING_MODE
+ *
+ * This command configures this GPU to control global mode for partitioning.
+ * This command may not be sent to a GPU with any active partitions.
+ * This command may be used to set the following modes:
+ *
+ * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING
+ *  NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY
+ *      This is the default mode. While this GPU is in this mode, no partitions
+ *      will be allowed to be created via SET_PARTITIONS - a client must set one
+ *      of the below modes prior to partitioning the GPU. When a client sets a
+ *      GPU into this mode, any performance changes resulting from partitions
+ *      made while in either of the below modes will be cleared. A
+ *      physical-function-level reset is required after setting this mode.
+ *
+ *  NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF
+ *      In this mode, when the GPU is partitioned, each partition will have the
+ *      maximum possible performance which can be evenly distributed among all
+ *      partitions. The total performance of the GPU, taking into account all
+ *      partitions created in this mode, may be less than that of a GPU running
+ *      in legacy non-SMC mode. Partitions created while in this mode require a
+ *      physical-function-level reset before the partitioning may take full
+ *      effect.  Destroying all partitions while in this mode may be
+ *      insufficient to restore full performance to the GPU - only by setting
+ *      the mode to _LEGACY can this be achieved. A physical-function-level
+ *      reset is NOT required after setting this mode.
+ *
+ *  NV2080_CTRL_GPU_SET_PARTIITONING_MODE_REPARTITIONING_FAST_RECONFIG
+ *      By setting this mode, the performance of the GPU will be restricted such
+ *      that all partitions will have a consistent fraction of the total
+ *      available performance, which may be less than the maximum possible
+ *      performance available to each partition. Creating or destroying
+ *      partitions on this GPU while in this mode will not require a
+ *      physical-function-level reset, and will not affect other active
+ *      partitions. Destroying all partitions while in this mode may be
+ *      insufficient to restore full performance to the GPU - only by setting
+ *      the mode to _LEGACY can this be achieved. A physical-function-level
+ *      reset is required after setting this mode.
+ *
+ * Parameters:
+ *   partitioningMode[IN]
+ *      - Partitioning Mode to set for this GPU.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE                          (0x20800183U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING                1:0
+#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY        0U
+#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF      1U
+#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG 2U
+
+#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0x83U)
+
+typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS {
+    NvU32 partitioningMode;
+} NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS;
+
+
+
+/* NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO
+ *
+ * This structure describes resources available in a partition requested of a
+ * given type.
+ *
+ * [OUT] partitionFlag
+ *      - Flags to specify in NV2080_CTRL_CMD_GPU_SET_PARTITIONS to request this
+ *        partition
+ *
+ * [OUT] grCount
+ *      - Total Number of SMC engines/GR engines (including GFX capable ones in this parition)
+ *
+ * [OUT] gfxGrCount
+ *      - Number of SMC engines/GR engines capable of GFX. This is a subset of the engines included in grCount
+ *
+ * [OUT] gpcCount
+ *      - Number of GPCs in this partition, including the GFX Capable ones.
+ *
+ * [OUT] virtualGpcCount
+ *      - Number of virtualized GPCs in this partition, including the GFX Capable ones.
+ *
+ * [OUT] gfxGpcCount
+ *      - Number of GFX Capable GPCs in this partition. This is a subset of the GPCs included in gpcCount.
+ *
+ * [OUT] veidCount
+ *      - Number of VEIDS in this partition
+ *
+ * [OUT] smCount
+ *      - Number of SMs in this partition
+ *
+ * [OUT] ceCount
+ *      - Copy Engines in this partition
+ *
+ * [OUT] nvEncCount
+ *      - Encoder Engines in this partition
+ *
+ * [OUT] nvDecCount
+ *      - Decoder Engines in this partition
+ *
+ * [OUT] nvJpgCount
+ *      - Jpg Engines in this partition
+ *
+ * [OUT] nvOfaCount
+ *      - Ofa engines in this partition
+ * [OUT] memorySize
+ *      - Total available memory within this partition
+ */
+typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO {
+    NvU32 partitionFlag;
+    NvU32 grCount;
+    NvU32 gfxGrCount;
+    NvU32 gpcCount;
+    NvU32 virtualGpcCount;
+    NvU32 gfxGpcCount;
+    NvU32 veidCount;
+    NvU32 smCount;
+    NvU32 ceCount;
+    NvU32 nvEncCount;
+    NvU32 nvDecCount;
+    NvU32 nvJpgCount;
+    NvU32 nvOfaCount;
+    NV_DECLARE_ALIGNED(NvU64 memorySize, 8);
+} NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO;
+
+/*
+ * NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS
+ *
+ * This command returns information regarding GPU partitions which can be
+ * requested via NV2080_CTRL_CMD_GPU_SET_PARTITIONS.
+ *
+ * [OUT] descCount
+ *      - Number of valid partition types
+ *
+ * [OUT] partitionDescs
+ *      - Information describing available partitions
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID (0x85U)
+
+typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS {
+    NvU32 descCount;
+    // C form: NV2080_CTRL_GPU_DESCRIBE_PARTITION_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES], 8);
+} NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS (0x20800185U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID" */
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE
+ *
+ * This command returns information regarding maximum page size supported
+ * by GMMU on the platform on which RM is running.
+ *
+ * [OUT] maxSupportedPageSize
+ *      - Maximum local vidmem page size supported by GMMU of a given GPU (HW)
+ *        on a given platform (OS)
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE (0x20800188U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U)
+
+typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 maxSupportedPageSize, 8);
+} NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC
+ *
+ * This command returns the max number of MMUs per GPC
+ *
+ *   gpcId [IN]
+ *     Logical GPC id
+ *   count [OUT]
+ *     The number of MMUs per GPC
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine. When SMC is enabled, this
+ *     is a mandatory parameter.
+ */
+#define NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID (0x8AU)
+
+typedef struct NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS {
+    NvU32 gpcId;
+    NvU32 count;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC (0x2080018aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS
+ *
+ * This command returns the GPU partition IDs for all active partitions
+ * If GPU is not partitioned, the control call will return partition count as "0"
+ *
+ *   swizzId[OUT]
+ *      - HW Partition ID associated with the active partitions
+ *
+ *   partitionCount[OUT]
+ *      - Number of active partitions in system
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID (0x8BU)
+
+typedef struct NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS {
+    NvU32 swizzId[NV2080_CTRL_GPU_MAX_PARTITION_IDS];
+    NvU32 partitionCount;
+} NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS               (0x2080018bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID" */
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_PIDS
+ *
+ * Given a resource identifier and its type, this command returns a set of
+ * process identifiers (PIDs) of processes that have instantiated this resource.
+ * For example, given a class number, this command returns a list of all
+ * processes with clients that have matching object allocations.
+ * This is a SMC aware call and the scope of the information gets restricted
+ * based on partition subscription.
+ * The call enforces partition subscription if SMC is enabled, and client is not
+ * a monitoring client.
+ * Monitoring clients get global information without any scope based filtering.
+ * Monitoring clients are also not expected to subscribe to a partition when
+ * SMC is enabled.
+ *
+ *   idType
+ *     Type of the resource identifier. See below for a list of valid types.
+ *   id
+ *     Resource identifier.
+ *   pidTblCount
+ *      Number of entries in the PID table.
+ *   pidTbl
+ *     Table which will contain the PIDs. Each table entry is of type NvU32.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_PIDS       (0x2080018dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID" */
+
+/* max size of pidTable */
+#define NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT 950U
+
+#define NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID (0x8DU)
+
+typedef struct NV2080_CTRL_GPU_GET_PIDS_PARAMS {
+    NvU32 idType;
+    NvU32 id;
+    NvU32 pidTblCount;
+    NvU32 pidTbl[NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT];
+} NV2080_CTRL_GPU_GET_PIDS_PARAMS;
+
+/*
+ * Use class NV20_SUBDEVICE_0 with NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS to query
+ * PIDs with or without GPU contexts. For any other class id, PIDs only with GPU
+ * contexts are returned.
+ */
+#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS      (0x00000000U)
+#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST (0x00000001U)
+
+/*
+ * NV2080_CTRL_SMC_SUBSCRIPTION_INFO
+ *
+ * This structure contains information about the SMC subscription type.
+ * If MIG is enabled a valid ID is returned, it is set to PARTITIONID_INVALID otherwise.
+ *
+ *  computeInstanceId
+ *      This parameter returns a valid compute instance ID
+ *  gpuInstanceId
+ *      This parameter returns a valid GPU instance ID
+ */
+typedef struct NV2080_CTRL_SMC_SUBSCRIPTION_INFO {
+    NvU32 computeInstanceId;
+    NvU32 gpuInstanceId;
+} NV2080_CTRL_SMC_SUBSCRIPTION_INFO;
+
+/*
+ * NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA
+ *
+ * This structure contains the video memory usage information.
+ *
+ *   memPrivate
+ *     This parameter returns the amount of memory exclusively owned
+ *     (i.e. private) to the client
+ *   memSharedOwned
+ *     This parameter returns the amount of shared memory owned by the client
+ *   memSharedDuped
+ *     This parameter returns the amount of shared memory duped by the client
+ *   protectedMemPrivate
+ *     This parameter returns the amount of protected memory exclusively owned
+ *     (i.e. private) to the client whenever memory protection is enabled
+ *   protectedMemSharedOwned
+ *     This parameter returns the amount of shared protected memory owned by the
+ *     client whenever memory protection is enabled
+ *   protectedMemSharedDuped
+ *     This parameter returns the amount of shared protected memory duped by the
+ *     client whenever memory protection is enabled
+ */
+typedef struct NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA {
+    NV_DECLARE_ALIGNED(NvU64 memPrivate, 8);
+    NV_DECLARE_ALIGNED(NvU64 memSharedOwned, 8);
+    NV_DECLARE_ALIGNED(NvU64 memSharedDuped, 8);
+    NV_DECLARE_ALIGNED(NvU64 protectedMemPrivate, 8);
+    NV_DECLARE_ALIGNED(NvU64 protectedMemSharedOwned, 8);
+    NV_DECLARE_ALIGNED(NvU64 protectedMemSharedDuped, 8);
+} NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA;
+
+#define NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE (0x00000000U)
+
+#define NV2080_CTRL_GPU_PID_INFO_INDEX_MAX                NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE
+
+typedef union NV2080_CTRL_GPU_PID_INFO_DATA {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA vidMemUsage, 8);
+} NV2080_CTRL_GPU_PID_INFO_DATA;
+
+
+/*
+ * NV2080_CTRL_GPU_PID_INFO
+ *
+ * This structure contains the per pid information. Each type of information
+ * retrievable via NV2080_CTRL_CMD_GET_PID_INFO is assigned a unique index
+ * below. In addition the process for which the lookup is for is also defined.
+ * This is a SMC aware call and the scope of the information gets restricted
+ * based on partition subscription.
+ * The call enforces partition subscription if SMC is enabled, and client is not
+ * a monitoring client.
+ * Monitoring clients get global information without any scope based filtering.
+ * Monitoring clients are also not expected to subscribe to a partition when
+ * SMC is enabled.
+ *
+ *   pid
+ *     This parameter specifies the PID of the process for which information is
+ *     to be queried.
+ *   index
+ *     This parameter specifies the type of information being queried for the
+ *     process of interest.
+ *   result
+ *     This parameter returns the result of the instruction's execution.
+ *   data
+ *     This parameter returns the data corresponding to the information which is
+ *     being queried.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *
+ * Valid PID information indices are:
+ *
+ *   NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE
+ *     This index is used to request the amount of video memory on this GPU
+ *     allocated to the process.
+ */
+typedef struct NV2080_CTRL_GPU_PID_INFO {
+    NvU32                             pid;
+    NvU32                             index;
+    NvU32                             result;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_DATA data, 8);
+    NV2080_CTRL_SMC_SUBSCRIPTION_INFO smcSubscription;
+} NV2080_CTRL_GPU_PID_INFO;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_PID_INFO
+ *
+ * This command allows querying per-process information from the RM. Clients
+ * request information by specifying a unique informational index and the
+ * Process ID of the process in question. The result is set to indicate success
+ * and the information queried (if available) is returned in the data parameter.
+ *
+ *   pidInfoListCount
+ *     The number of valid entries in the pidInfoList array.
+ *   pidInfoList
+ *     An array of NV2080_CTRL_GPU_PID_INFO of maximum length
+ *     NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GPU_GET_PID_INFO       (0x2080018eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID" */
+
+/* max size of pidInfoList */
+#define NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT 200U
+
+#define NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID (0x8EU)
+
+typedef struct NV2080_CTRL_GPU_GET_PID_INFO_PARAMS {
+    NvU32 pidInfoListCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO pidInfoList[NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT], 8);
+} NV2080_CTRL_GPU_GET_PID_INFO_PARAMS;
+
+
+
+/*!
+ * NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT
+ *
+ * @brief Handle VF PRI faults
+ *
+ *   faultType
+ *     BAR1, BAR2, PHYSICAL or UNBOUND_INSTANCE
+ *
+ * Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_NOT_SUPPORTED
+ *
+ */
+
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT                       (0x20800192U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID          0U
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1             1U
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2             2U
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL         3U
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE 4U
+
+#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID (0x92U)
+
+typedef struct NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS {
+    NvU32 faultType;
+} NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS;
+
+
+/*!
+ * Compute policy types to be specified by callers to set a config.
+ *
+ * _TIMESLICE
+ *     Set the timeslice config for the requested GPU.
+ *     Check @ref NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE for
+ *     permissible timeslice values.
+ */
+#define NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE      0U
+#define NV2080_CTRL_GPU_COMPUTE_POLICY_MAX            1U
+
+/*!
+ * Enum consisting of permissible timeslice options that can configured
+ * for a GPU. These can be queried by compute clients and the exact
+ * timeslice values can be chosen appropriately as per GPU support
+ */
+typedef enum NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE {
+    NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = 0,
+    NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = 1,
+    NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = 2,
+    NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = 3,
+    NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = 4,
+} NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE;
+
+typedef struct NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG {
+    /*!
+     * NV2080_CTRL_GPU_COMPUTE_POLICY_<xyz>
+     */
+    NvU32 type;
+
+    /*!
+     * Union of type-specific data
+     */
+    union {
+        NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE timeslice;
+    } data;
+} NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG;
+
+#define NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x94U)
+
+typedef struct NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS {
+    NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG config;
+} NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG
+ *
+ * This command retrieves all compute policies configs for the associated gpu.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG  (0x20800195U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID" */
+
+/*!
+ * This define limits the max number of policy configs that can be handled by
+ * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG command.
+ *
+ * @note Needs to be in sync (greater or equal) to NV2080_CTRL_GPU_COMPUTE_POLICY_MAX.
+ */
+
+#define NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX 32U
+
+#define NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x95U)
+
+typedef struct NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS {
+    NvU32                                 numConfigs;
+
+    /*!
+     * C form:
+     * NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX];
+     */
+    NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX];
+} NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_GFID
+ *
+ * This command returns the GFID (GPU Function ID) for a given SR-IOV
+ * Virtual Function (VF) of the physical GPU.
+ *
+ *   domain [IN]
+ *     This field specifies the respective domain of the PCI device.
+ *   bus [IN]
+ *     This field specifies the bus id for a given VF.
+ *   device [IN]
+ *     This field specifies the device id for a given VF.
+ *   func [IN]
+ *     This field specifies the function id for a given VF.
+ *   gfid[OUT]
+ *      - This field returns GFID for a given VF BDF.
+ *   gfidMask[OUT]
+ *      - This field returns GFID mask value.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_GFID (0x20800196U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID (0x96U)
+
+typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS {
+    NvU32 domain;
+    NvU8  bus;
+    NvU8  device;
+    NvU8  func;
+    NvU32 gfid;
+    NvU32 gfidMask;
+} NV2080_CTRL_GPU_GET_GFID_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY
+ *
+ * This command informs the GPU driver that the GPU partition associated with
+ * a given GFID has been activated or will be deactivated.
+ *
+ *   gfid[IN]
+ *      - The GPU function identifier for a given VF BDF
+ *   bEnable [IN]
+ *      - Set to NV_TRUE if the GPU partition has been activated.
+ *      - Set to NV_FALSE if the GPU partition will be deactivated.
+ *   fabricPartitionId [IN]
+ *      - Set the fabric manager partition ID dring partition activation.
+ *      - Ignored during partition deactivation.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_OPERATING_SYSTEM
+ */
+
+#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY (0x20800197U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID (0x97U)
+
+typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS {
+    NvU32  gfid;
+    NvBool bEnable;
+    NvU32  fabricPartitionId;
+} NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST
+ *
+ * @brief Validate the address range for memory map request by comparing the
+ *        user supplied address range with GPU BAR0/BAR1 range.
+ *
+ * @param[in]   addressStart    Start address for memory map request
+ * @param[in]   addressLength   Length for for memory map request
+ * @param[out]  protection      NV_PROTECT_READ_WRITE, if both read/write is allowed
+ *                              NV_PROTECT_READABLE, if only read is allowed
+ *
+ * Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_PROTECTION_FAULT
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST (0x20800198U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID (0x98U)
+
+typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 addressStart, 8);
+    NV_DECLARE_ALIGNED(NvU64 addressLength, 8);
+    NvU32 protection;
+} NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES
+ *
+ * This command is used to retrieve the load time (latency) of each engine.
+ *
+ *   engineCount
+ *     This field specifies the number of entries of the following
+ *     three arrays.
+ *
+ *   engineList[NV2080_GPU_MAX_ENGINE_OBJECTS]
+ *     An array of NvU32 which stores each engine's descriptor.
+ *
+ *   engineStateLoadTime[NV2080_GPU_MAX_ENGINE_OBJECTS]
+ *     A array of NvU64 which stores each engine's load time.
+ *
+ *   engineIsInit[NV2080_GPU_MAX_ENGINE_OBJECTS]
+ *     A array of NvBool which stores each engine's initialization status.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS        0xC8U
+
+#define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU)
+
+typedef struct NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS {
+    NvU32  engineCount;
+    NvU32  engineList[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS];
+    NV_DECLARE_ALIGNED(NvU64 engineStateLoadTime[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS], 8);
+    NvBool engineIsInit[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS];
+} NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING
+ *
+ * This command is used to retrieve the mapping of engine ID and engine Name.
+ *
+ *   engineCount
+ *     This field specifies the size of the mapping.
+ *
+ *   engineID
+ *     An array of NvU32 which stores each engine's descriptor.
+ *
+ *   engineName
+ *     An array of char[100] which stores each engine's name.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING (0x2080019cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID (0x9CU)
+
+typedef struct NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS {
+    NvU32 engineCount;
+    NvU32 engineID[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS];
+    char  engineName[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS][100];
+} NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS
+ *
+ * Same as above NV2080_CTRL_CMD_GPU_EXEC_REG_OPS except that this CTRL CMD will
+ * not allow any embedded pointers. The regOps array is inlined as part of the
+ * struct.
+ * NOTE: This intended for gsp plugin only as it may override regOp access
+ *       restrictions
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS (0x2080019dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID" */
+
+/* setting this to 100 keeps it right below 4k in size */
+#define NV2080_CTRL_REG_OPS_ARRAY_MAX           100U
+#define NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID (0x9DU)
+
+typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS {
+    NvHandle               hClientTarget;
+    NvHandle               hChannelTarget;
+    NvU32                  bNonTransactional;
+    NvU32                  reserved00[2];
+    NvU32                  regOpCount;
+    NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_REG_OPS_ARRAY_MAX];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS;
+
+#define NV2080_CTRL_GPU_SKYLINE_INFO_MAX_SKYLINES            9U
+#define NV2080_CTRL_GPU_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 64U
+/*!
+ * NV2080_CTRL_GPU_SKYLINE_INFO
+ * skylineVgpcSize[OUT]
+ *      - TPC count of non-singleton VGPCs
+ * singletonVgpcMask[OUT]
+ *      - Mask of active Singletons
+ * maxInstances[OUT]
+ *      - Max allowed instances of this skyline concurrently on a GPU
+ * computeSizeFlag
+ *      - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline
+ */
+typedef struct NV2080_CTRL_GPU_SKYLINE_INFO {
+    NvU8  skylineVgpcSize[NV2080_CTRL_GPU_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS];
+    NvU32 singletonVgpcMask;
+    NvU32 maxInstances;
+    NvU32 computeSizeFlag;
+} NV2080_CTRL_GPU_SKYLINE_INFO;
+
+/*!
+ * NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS
+ * skylineTable[OUT]
+ *      - TPC count of non-singleton VGPCs
+ *      - Mask of singleton vGPC IDs active
+ *      - Max Instances of this skyline possible concurrently
+ *      - Associated compute size with the indexed skyline
+ * validEntries[OUT]
+ *      - Number of entries which contain valid info in skylineInfo
+ */
+#define NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0x9FU)
+
+typedef struct NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS {
+    NV2080_CTRL_GPU_SKYLINE_INFO skylineTable[NV2080_CTRL_GPU_SKYLINE_INFO_MAX_SKYLINES];
+    NvU32                        validEntries;
+} NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_SKYLINE_INFO
+ *
+ * Retrieves skyline information about the GPU. Params are sized to currently known max
+ * values, but will need to be modified in the future should that change.
+ */
+#define NV2080_CTRL_CMD_GPU_GET_SKYLINE_INFO (0x2080019fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO
+ *
+ * [in/out] gpuId
+ *   GPU ID for which the capabilities are queried.
+ *   For the NV2080_CTRL_CMD_GET_P2P_CAPS control:
+ *     If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to
+ *     the GPU ID of an attached GPU.
+ *     If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester
+ *     should set it to the ID of the GPU that needs to be queried from.
+ * [in] gpuUuid
+ *   Alternative to gpuId; used to identify target GPU for which caps are being queried.
+ *   Option only available for Guest RPCs.
+ *     If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU.
+ *     If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default.
+ *     If bAllCaps == NV_TRUE, gpuUuid is ignored.
+ * [out] p2pCaps
+ *   Peer to peer capabilities discovered between the GPUs.
+ *   See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values.
+ * [out] p2pOptimalReadCEs
+ *   Mask of CEs to use for p2p reads over Nvlink.
+ * [out] p2pOptimalWriteCEs
+ *   Mask of CEs to use for p2p writes over Nvlink.
+ * [out] p2pCapsStatus
+ *   Status of all supported p2p capabilities.
+ *   See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values.
+ * [out] busPeerId
+ *   Bus peer ID. For an invalid or a non-existent peer this field
+ *   has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
+ * [out] busEgmPeerId
+ *   Bus EGM peer ID. For an invalid or a non-existent peer this field
+ *   has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
+ */
+#define NV2080_GET_P2P_CAPS_UUID_LEN         16U
+
+typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO {
+    NvU32 gpuId;
+    NvU8  gpuUuid[NV2080_GET_P2P_CAPS_UUID_LEN];
+    NvU32 p2pCaps;
+    NvU32 p2pOptimalReadCEs;
+    NvU32 p2pOptimalWriteCEs;
+    NvU8  p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
+    NvU32 busPeerId;
+    NvU32 busEgmPeerId;
+} NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO;
+
+/*!
+ * NV2080_CTRL_CMD_GET_P2P_CAPS
+ *
+ * Returns peer to peer capabilities present between GPUs.
+ * The caller must either specify bAllCaps to query the capabilities for
+ * all the attached GPUs or they must pass a valid list of GPU IDs.
+ *
+ *   [in] bAllCaps
+ *     Set to NV_TRUE to query the capabilities for all the attached GPUs.
+ *     Set to NV_FALSE and specify peerGpuCount and peerGpuCaps[].gpuId
+ *     to retrieve the capabilities only for the specified GPUs.
+ *   [in] bUseUuid
+ *     Option only available for Guest RPCs.
+ *     Set to NV_TRUE to use gpuUuid in lieu of gpuId to identify target GPU.
+ *     If bAllCaps == NV_TRUE, bUseUuid is ignored.
+ *   [in/out] peerGpuCount
+ *     The number of the peerGpuCaps entries.
+ *     If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to
+ *     the total number of the attached GPUs.
+ *     If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester
+ *     should set it to the number of the peerGpuCaps entries.
+ *   [in/out] peerGpuCaps
+ *     The array of NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO entries, describing
+ *     the peer to peer capabilities of the GPUs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount
+ *   NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuCaps[].gpuId
+ */
+#define NV2080_CTRL_CMD_GET_P2P_CAPS (0x208001a0U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0xA0U)
+
+typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS {
+    NvBool                                  bAllCaps;
+    NvBool                                  bUseUuid;
+    NvU32                                   peerGpuCount;
+    NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
+} NV2080_CTRL_GET_P2P_CAPS_PARAMS;
+
+
+
+/*!
+ * NV2080_CTRL_GPU_COMPUTE_PROFILE
+ *
+ * This structure specifies resources in an execution partition
+ *
+ *  computeSize[OUT]
+ *      - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile
+ *
+ *  flags[OUT]
+ *      - Bitmap of flags describing the profile NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG*
+ *
+ *  gfxGpcCount[OUT]
+ *      - Total Number of GFX Supporting GPCs in this partition
+ *
+ *  gpcCount[OUT]
+ *      - Total Number of GPCs in this partition (including GFX Supported GPCs)
+ *
+ *  veidCount[OUT]
+ *      - Number of VEIDs allocated to this profile
+ *
+ *  smCount[OUT]
+ *      - Number of SMs usable in this profile
+ */
+typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE {
+    NvU8  computeSize;
+    NvU16 flags;
+    NvU32 gfxGpcCount;
+    NvU32 gpcCount;
+    NvU32 veidCount;
+    NvU32 smCount;
+} NV2080_CTRL_GPU_COMPUTE_PROFILE;
+
+// Indicates that the profile spans over multiple dielets
+#define NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG_MULTIDIE   0:0
+#define NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG_MULTIDIE_FALSE 0U
+#define NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG_MULTIDIE_TRUE  1U
+
+/*!
+ * NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
+ *
+ * This structure specifies resources in an execution partition
+ *
+ *  partitionFlag[IN]
+ *      - GPU instance profile flags for which to query compute profiles
+ *        Ignored, if subdevice is subscribed to a GPU instance
+ *
+ *  profileCount[OUT]
+ *      - Total Number of profiles filled
+ *
+ *  profiles[OUT]
+ *      - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
+ */
+#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U)
+
+typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
+    NvU32                           partitionFlag;
+    NvU32                           profileCount;
+    NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
+} NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES       (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED 0U
+#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED 1U
+#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS 2U
+#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE    3U
+
+#define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN             16U
+
+#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED           NVBIT64(0)
+
+#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED NVBIT64(1)
+
+
+
+#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_UC_LOOPBACK_SUPPORTED  NVBIT64(2)
+
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW                    1:0
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED      0
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE               1
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE              2
+
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE               3:2
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED 0
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE          1
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE         2
+
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY               5:4
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED 0
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE          1
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE         2
+
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY               7:6
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED 0
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE          1
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE         2
+
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION                      11:8
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NOT_SUPPORTED        0
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NONE                 1
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_SYSGUID    2
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_CHASSIS_SN 3
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NO_PARTITION         4
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INSUFFICIENT_NVLINKS 5
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCOMPATIBLE_GPU_FW  6
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INVALID_LOCATION     7
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_GPU_STATE_INVALID    8
+
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED 13:12
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_NOT_SUPPORTED 0
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_TRUE          1
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_FALSE         2
+
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_NOT_SUPPORTED 0
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_HEALTHY 1
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_UNHEALTHY 2
+#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_LIMITED_CAPACITY 3
+
+/*!
+ * NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
+ *
+ * This structure provides the GPU<-->FM probe state info on NVSwitch based
+ * systems
+ *
+ *  state[OUT]
+ *      - Current state of GPU<-->FM probe req/rsp
+ *        Following values can be returned
+ *        _UNSUPPORTED - system does not support this feature
+ *        _NOT_STARTED - probe request is not yet sent to the FM
+ *        _IN_PROGRESS - probe response is not yet received
+ *        _COMPLETE    - probe response is received
+ *        When state is NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE
+ *        status has to be checked for probe response success/failure
+ *  status[OUT]
+ *      - Inband Probe response status
+ *        A GPU which returns NV_OK status upon receiving the probe response
+ *        can participate in P2P
+ *  clusterUuid[OUT]
+ *      - Uuid of the cluster to which this node belongs
+ *  fabricPartitionId[OUT]
+ *      - Fabric partition Id
+ *  fabricCaps[OUT]
+ *      - Summary of fabric capabilities received from probe resp
+ *        Possible values are
+ *            NV2080_CTRL_GPU_FABRIC_PROBE_CAP_*
+ *  fabricCliqueId[OUT]
+ *      - Unique ID of a set of GPUs within a fabric partition that can perform P2P
+ *  fabricHealthMask[OUT]
+ *      - Mask where bits indicate different status about the health of the fabric
+ *  fabricHealthSummary[OUT]
+ *      - Summary of the Fabric Health
+ */
+#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U)
+
+typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
+    NvU8      state;
+    NV_STATUS status;
+    NvU8      clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN];
+    NvU16     fabricPartitionId;
+    NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8);
+    NvU32     fabricCliqueId;
+    NvU32     fabricHealthMask;
+    NvU8      fabricHealthSummary;
+} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS
+ *
+ * This command retrieves and constructs the GPU partnumber from the VBIOS.
+ *
+ * The following data are currently supported:
+ *
+ * pciDevId
+ *    The PCI device ID
+ *
+ * chipSku
+ *    The chip SKU information
+ *
+ * chipMajor
+ *    The chip major number
+ *
+ * chipMinor
+ *    The chip minor number
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS      (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */
+
+/*
+ * The string format for a GPU part number
+ * The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string,
+ * the chip major number, and then the chip minor number.
+ * Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS
+ * struct fields.
+ */
+#define GPU_PART_NUMBER_FMT "%04X-%s-%X%X"
+
+/* The maximum length for the chip sku */
+#define NV2080_MAX_CHIP_SKU_LENGTH                0x00000004U
+
+#define NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID (0xA4U)
+
+typedef struct NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS {
+    NvU32 pciDevId;
+    NvU8  chipSku[NV2080_MAX_CHIP_SKU_LENGTH];
+    NvU32 chipMajor;
+    NvU32 chipMinor;
+} NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP
+ *
+ * This command returns the host hardware defined engine ID of the specified engine(s).
+ *
+ *   swizzId[IN]
+ *       - HW Partition ID associated with the requested partition.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP (0x208001a5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID (0xA5U)
+
+typedef struct NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS {
+    NvU32 swizzId;
+} NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS;
+
+#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS      (0x208001a6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP  (0x208001a7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU (0x208001a8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID" */
+
+/* setting this to 100 keeps it right below 4k in size */
+#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX    50U
+typedef struct NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS {
+    NvHandle               hClientTarget;
+    NvHandle               hChannelTarget;
+    NvU32                  bNonTransactional;
+    NvU32                  regOpCount;
+    NvU32                  smIds[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX];
+    NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS;
+
+#define NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID (0xA6U)
+
+typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS;
+#define NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID (0xA7U)
+
+typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS;
+#define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U)
+
+typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET
+ *
+ * INTERNAL DEBUG/TESTING USE ONLY
+ *
+ * Marks the device for reset.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET   (0x208001a9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xA9" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET
+ *
+ * INTERNAL DEBUG/TESTING USE ONLY
+ *
+ * Unmarks the device for reset.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET (0x208001aaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAA" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_RESET_STATUS
+ *
+ * Gets the current reset status of the device.
+ *
+ * bResetNeeded
+ *   Set to NV_TRUE if the device needs to be reset.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_RESET_STATUS        (0x208001abU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID (0xABU)
+
+typedef struct NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS {
+    NvBool bResetRequired;
+} NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET
+ *
+ * INTERNAL DEBUG/TESTING USE ONLY
+ *
+ * Marks the device for drain and reset.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET   (0x208001acU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAC" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET
+ *
+ * INTERNAL DEBUG/TESTING USE ONLY
+ *
+ * Unmarks the device for drain and reset.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001adU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAD" */
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS
+ *
+ * Gets the current drain and reset status of the device. Drain and reset is used only SMC configs.
+ *
+ * bDrainRecommended
+ *   Set to NV_TRUE if a drain and reset is recommended for the device.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS        (0x208001aeU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID (0xAEU)
+
+typedef struct NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS {
+    NvBool bDrainRecommended;
+} NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2
+ *
+ * This command returns NVENC software sessions information for the associate GPU.
+ * This command is similar to NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO but doesn't have
+ * embedded pointers.
+ *
+ * Check NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO for detailed information.
+ */
+
+#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID (0xAFU)
+
+typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS {
+    NvU32                             sessionInfoTblEntry;
+    NV2080_CTRL_NVENC_SW_SESSION_INFO sessionInfoTbl[NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES];
+} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO {
+    NvU32 engDesc;
+    NvU32 ctxAttr;
+    NvU32 ctxBufferSize;
+    NvU32 addrSpaceList;
+    NvU32 registerBase;
+} NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO;
+#define NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS         0x40
+
+#define NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO (0x208001b0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0xB0U)
+
+typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
+    NvU32                                   numConstructedFalcons;
+    NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS];
+} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_VF_CAPS
+ *
+ * This command will return the MSIX capabilities for virtual function
+ * Parameters:
+ *
+ * gfid [IN]
+ *   The GPU function identifier for a given VF BDF
+ *
+ * vfMsixCap [out]
+ *   This field returns the VF MSIX cap values
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+typedef struct NV2080_VF_MSIX_CAPS {
+    NvU32 msix_header;
+    NvU32 msix_table;
+    NvU32 msix_pba;
+} NV2080_VF_MSIX_CAPS;
+
+#define NV2080_CTRL_CMD_GPU_GET_VF_CAPS (0x208001b1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID (0xB1U)
+
+typedef struct NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS {
+    NvU32               gfid;
+    NV2080_VF_MSIX_CAPS vfMsixCap;
+} NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION
+ *
+ * Gets the recovery action needed for the device after a failure.
+ *
+ * action [OUT]
+ *   Returns the recovery action needed.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION (0x208001b2U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_GPU_RECOVERY_ACTION {
+    NV2080_CTRL_GPU_RECOVERY_ACTION_NONE = 0,
+    NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_PF_FLR = 1,
+    NV2080_CTRL_GPU_RECOVERY_ACTION_OS_REBOOT = 2,
+    NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = 3,
+    NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET = 4,
+    NV2080_CTRL_GPU_RECOVERY_ACTION_RECOVER_IMEX_DOMAIN = 5,
+    NV2080_CTRL_GPU_RECOVERY_ACTION_BUS_RESET = 6,
+    NV2080_CTRL_GPU_RECOVERY_ACTION_SYSTEM_REBOOT = 7,
+} NV2080_CTRL_GPU_RECOVERY_ACTION;
+
+#define NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET   NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_PF_FLR
+#define NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT NV2080_CTRL_GPU_RECOVERY_ACTION_OS_REBOOT
+
+#define NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID (0xB2U)
+
+typedef struct NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS {
+    NV2080_CTRL_GPU_RECOVERY_ACTION action;
+} NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS;
+
+/*
+ * NV2080_CTRL_GPU_GET_FIPS_STATUS
+ *
+ * @brief get FIPS status (enabled/disabled) from GSP-RM
+ *
+ *
+ * @return NV_OK on success
+ * @return NV_ERR_ otherwise
+ */
+#define NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID (0xe4U)
+
+typedef struct NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS {
+    NvBool bFipsEnabled;
+} NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS;
+#define NV2080_CTRL_GPU_GET_FIPS_STATUS (0x208001e4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_GPU_GET_RAFTS_FS_MASK
+ *
+ * @brief Get floorsweeping mask for given skyline configuration.
+ *
+ * tpcCountMatrix [IN]
+ *   TPC per GPC distribution for which user require floorsweeping mask.
+ *
+ * gfxGpcCount [IN]
+ *   Number of GFX capable GPC required.
+ *
+ * gfxTpcCount [IN]
+ *   Number of GFX capable TPC required.
+ *
+ * floorSweepConfig [OUT]
+ *   MODS floorsweeping mask.
+ *
+ * bValid [OUT]
+ *   If entries in floorSweepConfig are valid or not.
+ *
+ * @return NV_OK                      : on success
+ * @return NV_ERR_INVALID_PARAMETER   : Parameters in pParams are incompatible with each other
+ * @return NV_ERR_NOT_SUPPORTED       : Requested skyline not supported by current chip but can be supported by a chip
+ *                                       with fewer defects
+ */
+typedef enum NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE {
+    NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID = 0,
+    NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC = 1,
+    NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC = 2,
+} NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE;
+
+typedef struct NV2080_RAFTS_FLOORSWEEP_INFO {
+    NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE unitType;
+    NvU32                                  parentId;
+    NvU32                                  mask;
+} NV2080_RAFTS_FLOORSWEEP_INFO;
+
+#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU         0x2
+#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU 0xC
+#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC      (0x18) /* finn: Evaluated from "NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU * NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU" */
+#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT      (0x1a) /* finn: Evaluated from "NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC + 2" */
+
+#define NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID (0xB3U)
+
+typedef struct NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS {
+    NvU8                         tpcCountMatrix[NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU][NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU];
+    NvBool                       bValid;
+    NV2080_RAFTS_FLOORSWEEP_INFO floorSweepConfig[NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT];
+    NvU8                         gfxGpcCount;
+    NvU8                         gfxTpcPerGpcCount;
+    NvU8                         maxUgpuTpcDiff;
+} NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS;
+
+#define NV2080_CTRL_GPU_GET_RAFTS_FS_MASK                (0x208001b3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS
+ *
+ * This structure specifies resources in an execution partition
+ *
+ *  partitionFlag[IN]
+ *      - If GPU instance profile flag for which to query specified
+ *        compute profile
+ *
+ *  computeSize[IN]
+ *      - Size specifying compute profile whose info to query
+ *
+ *  totalProfileCount[OUT]
+ *      - Total Number of profiles possible to create in instance of specified GPU
+ *        profile
+ *
+ *  totalSpans[OUT]
+ *      - List of spans which can possibly be occupied by partitions of the
+ *        given type.
+ *
+ *  totalSpansCount[OUT]
+ *      - Number of entries filled in totalSpans
+ *
+ */
+#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY (0x208001e5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID (0xe5U)
+
+typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS {
+    NvU32 partitionFlag;
+    NvU32 computeSize;
+    NvU32 totalProfileCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_EXEC_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
+    NvU32 totalSpansCount;
+} NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK
+ *
+ * This command returns the TPC reconfig mask for a specific GPC
+ *
+ *  gpc[IN]
+ *      The GPC for which the TPC reconfig mask needs to be queried.
+ *      The GPC should be specified as a logical index.
+ *
+ *  tpcReconfigMask[OUT]
+ *     Mask of reconfigurable TPCs in the specified GPC
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK (0x208001e7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID (0xe7U)
+
+typedef struct NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS {
+    NvU32 gpc;
+    NvU32 tpcReconfigMask;
+} NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_RPC_GSP_TEST
+ *
+ * This command checks a variable sized RPC for a known pattern, then
+ * fills the data field with another pattern. It also records the timestamp
+ * before and after the RPC is sent to GSP.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ */
+#define NV2080_CTRL_CMD_GPU_RPC_GSP_TEST (0x208001e8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID (0xe8U)
+
+typedef struct NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS {
+    NvU8  test;
+    NvU32 dataSize;
+    NV_DECLARE_ALIGNED(NvU64 startTimestamp, 8);
+    NV_DECLARE_ALIGNED(NvU64 stopTimestamp, 8);
+    NV_DECLARE_ALIGNED(NvP64 data, 8);
+} NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS;
+
+#define NV2080_CTRL_GPU_RPC_GSP_TEST_SERIALIZED_INTEGRITY 0x1
+#define NV2080_CTRL_GPU_RPC_GSP_TEST_UNSERIALIZED 0x2
+#define NV2080_CTRL_GPU_RPC_GSP_TEST_SERIALIZED_NOP 0x3
+#define NV2080_CTRL_GPU_RPC_GSP_TEST_TIMEOUT 0x4
+
+/*
+ * NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES
+ *
+ * This command returns information necessary for GSP RPC integrity tests
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ */
+#define NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES (0x208001e9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID (0xe9U)
+
+typedef struct NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS {
+    NvU32 maxRpcSize;
+    NvU32 finnRmapiSize;
+    NvU32 rpcGspControlSize;
+    NvU32 rpcMessageHeaderSize;
+    NV_DECLARE_ALIGNED(NvU64 timestampFreq, 8);
+} NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS;
+
+/*
+ * RUSD features.
+ * Each feature definition equates to a bit in the supportedFeatures bitmask.
+ */
+#define RUSD_FEATURE_NON_POLLING 0x1
+#define RUSD_FEATURE_POLLING     0x2
+
+/*
+ * NV2080_CTRL_CMD_GPU_RUSD_GET_SUPPORTED_FEATURES
+ *
+ * @brief Returns bitmask of supported RUSD features.
+ *
+ * @param[out]  supportedFeatures Bitmask of supported RUSD features
+ *
+ * @return NV_OK
+ */
+#define NV2080_CTRL_CMD_RUSD_GET_SUPPORTED_FEATURES (0x208001eaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID (0xeaU)
+
+typedef struct NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS {
+    NvU32 supportedFeatures;
+} NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_RUSD_SET_FEATURES
+ *
+ * @brief Set RUSD featuress
+ *
+ * permanentPolledDataMask
+ *     When a permanent polling data mask is set, RUSD will start polling the
+ *     set of specified polling data as long as there's an active userspace
+ *     channel, even if there's no active RUSD clients.
+ *     This field specifies which data to poll in permanent RUSD polling.
+ *
+ * @return NV_OK
+ */
+#define NV2080_CTRL_CMD_GPU_RUSD_SET_FEATURES (0x208001ebU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS_MESSAGE_ID (0xebU)
+
+typedef struct NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 permanentPolledDataMask, 8);
+} NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_FORCE_GSP_UNLOAD
+ *
+ * This command is used to trigger GSP Unload
+ *
+ *  flags[IN]
+ *     Flags passed by caller - For future use.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_FORCE_GSP_UNLOAD (0x208001ecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS_MESSAGE_ID (0xecU)
+
+typedef struct NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS {
+    NvU32 flags;
+} NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_VGA_SR_READ_WRITE
+ *
+ * This control is supported only on MODS.
+ *
+ *  bRead[IN]
+ *  head[IN]
+ *  index[IN]
+ *  data[IN/OUT]
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_GPU_VGA_SR_READ_WRITE (0x208001edU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS_MESSAGE_ID (0xedU)
+
+typedef struct NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS {
+    NvBool bWrite;
+    NvU32  head;
+    NvU8   index;
+    NvU8   data;
+} NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_ERROR_INJECTION_CONTROL
+ *
+ * @brief Injects an error for testing purposes
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+
+typedef enum NV2080_CTRL_GPU_INJECT_ERROR_TYPE {
+    NV2080_CTRL_GPU_INJECT_ERROR_MESSAGE_QUEUE = 0,
+    NV2080_CTRL_GPU_INJECT_ERROR__COUNT = 1,
+} NV2080_CTRL_GPU_INJECT_ERROR_TYPE;
+
+#define NV2080_CTRL_CMD_GPU_ERROR_INJECTION_CONTROL (0x208001efU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS_MESSAGE_ID (0xefU)
+
+typedef struct NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS {
+    NvU32 errorType;
+} NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_CHECK_MEM_SUBSYS_ERROR
+ *
+ * @brief Detect if there is a memory subsystem HW error
+ *
+ *  flags[IN]
+ *     Flags passed by caller - For future use.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_MEMORY_ERROR
+ */
+#define NV2080_CTRL_CMD_GPU_CHECK_MEM_SUBSYS_ERROR (0x208001f0U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS_MESSAGE_ID (0xf0U)
+
+typedef struct NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS {
+    NvU32 flags;
+} NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS;
+
+/* 
+ * NV2080_CTRL_CMD_GPU_GET_DEFAULT_TIMEOUT
+ *
+ * @brief Returns the RM default timeout in ms
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_GENERIC
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_DEFAULT_TIMEOUT (0x208001f1U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS_MESSAGE_ID (0xf1U)
+
+typedef struct NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS {
+    NvU32 defaultTimeout;
+} NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL
+ *
+ * This control is used to set up and perform various GSP crypto operations
+ *
+ */
+#define NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL (0x208001f2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_TYPE {
+    NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RSA_DECRYPTION = 0,
+    NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_ECDSA = 1,
+    NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RNG = 2,
+    NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_SHA = 3,
+} NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_TYPE;
+
+#define NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RSA_EXPONENT_SIZE 4
+#define NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_NONCE_SIZE        48
+
+#define NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS_MESSAGE_ID (0xf2U)
+
+typedef struct NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS {
+    NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_TYPE opcode;
+    NvU32                                   inputMessageSize;
+    NV_DECLARE_ALIGNED(NvP64 inputMessage, 8);
+    NvU32                                   outputMessageSize;
+    NV_DECLARE_ALIGNED(NvP64 outputMessage, 8);
+    NvU32                                   modulusSize;
+    NV_DECLARE_ALIGNED(NvP64 modulus, 8);
+    NvU8                                    exponent[NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RSA_EXPONENT_SIZE];
+    NvBool                                  usePresetKey;
+    NvU32                                   keySize;
+    NV_DECLARE_ALIGNED(NvP64 key, 8);
+    NvU8                                    nonce[NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_NONCE_SIZE];
+} NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED
+ *
+ * Identifies whether the GPU reset is coupled.
+ *
+ *   isResetCoupled[OUT]
+ *     This field is written with the value TRUE if the reset is coupled.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED (0x208081f3U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS_MESSAGE_ID (0xf3U)
+
+typedef struct NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS {
+    NvBool isResetCoupled;
+} NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_DIELET_INFO
+ *
+ * Returns a list of dielet type/physical mask pairs.
+ * 
+ * If a given dielet type may be present on a given arch but all instances are floorswept, a mask of 0x0 will be returned. 
+ * If a given dielet type cannot exist on a given arch, no record for the dielet should be returned.
+ *
+ *   dieletPairs[OUT]
+ *     This field returns a series of key-value pairs of the format <dielet type, dielet mask>
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+
+typedef enum NV2080_CTRL_GPU_DIELET_TYPE {
+    NV2080_CTRL_GPU_DIELET_TYPE_UGD = 0,
+    NV2080_CTRL_GPU_DIELET_TYPE_IODN = 1,
+    NV2080_CTRL_GPU_DIELET_TYPE_IODS = 2,
+    NV2080_CTRL_GPU_DIELET_TYPE_LAST = 3,
+} NV2080_CTRL_GPU_DIELET_TYPE;
+
+typedef struct NV2080_CTRL_GPU_GET_DIELET_INFO {
+    NV2080_CTRL_GPU_DIELET_TYPE dieletType;
+    NvU32                       typeSpecificId;
+} NV2080_CTRL_GPU_GET_DIELET_INFO;
+
+#define NV2080_CTRL_GPU_GET_DIELET_INFO_MAX_SIZE (256U)
+
+#define NV2080_CTRL_CMD_GPU_GET_DIELET_INFO      (0x208081f4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS_MESSAGE_ID (0xf4U)
+
+typedef struct NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS {
+    NvU32                           dieletListSize;
+    NV2080_CTRL_GPU_GET_DIELET_INFO dielets[NV2080_CTRL_GPU_GET_DIELET_INFO_MAX_SIZE];
+} NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GPU_GET_UNIT_INFO_FROM_DIELET
+ *
+ * Returns a floorswept mask of a HW unit given a dielet type, dielet index, and HW unit.
+ * 
+ *   dieletType [IN]
+ *     One of the types defined in NV2080_CTRL_GPU_DIELET_TYPE.
+ *   dieletIndex [IN]
+ *     Index of dielet used to query FS info.
+ *   unitType [IN]
+ *     One of the types defined in NV2080_CTRL_GPU_UNIT_TYPE.
+ *   unitMask[OUT]
+ *     This field returns a floorswept mask for a given HW unit type.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_GPU_GET_UNIT_FS_INFO_FROM_DIELET (0x208081f5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_GPU_UNIT_TYPE {
+    NV2080_CTRL_GPU_UNIT_TYPE_SYSLTC = 0,
+    NV2080_CTRL_GPU_UNIT_TYPE_SYSLTS = 1,
+    NV2080_CTRL_GPU_UNIT_TYPE_HSHUBCHI = 2,
+    NV2080_CTRL_GPU_UNIT_TYPE_HSHUBNVL = 3,
+    NV2080_CTRL_GPU_UNIT_TYPE_LAST = 4,
+} NV2080_CTRL_GPU_UNIT_TYPE;
+
+#define NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS_MESSAGE_ID (0xf5U)
+
+typedef struct NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS {
+    NV2080_CTRL_GPU_DIELET_TYPE dieletType;
+    NvU32                       dieletTypeSpecificId;
+    NV2080_CTRL_GPU_UNIT_TYPE   unitType;
+    NvU32                       unitMask;
+} NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GPU_SET_MIGRATION_BLOCK
+ *
+ * This command allows devtools processes to notify the Resource Manager when
+ * they enter or exit critical sections that cannot survive vGPU live migration.
+ * This enables selective migration blocking only during devtools critical
+ * operations, rather than blanket disabling migration when devtools are active.
+ *
+ *   bIsDevtoolInUse
+ *     This boolean parameter indicates whether the devtools is entering or
+ *     exiting a critical section:
+ *       NV_TRUE  - Devtools is entering a critical section (block migration)
+ *       NV_FALSE - Devtools is exiting a critical section (may allow migration)
+ */
+#define NV2080_CTRL_CMD_GPU_SET_MIGRATION_BLOCK (0x208001faU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS_MESSAGE_ID (0xfaU)
+
+typedef struct NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS {
+    NvBool bIsDevtoolInUse;
+} NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS;
+
+/* _ctrl2080gpu_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpumon.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpumon.h
new file mode 100644
index 0000000..2398a0c
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpumon.h
@@ -0,0 +1,96 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080gpumon.finn
+//
+
+
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/*!
+ *  This structure represents base class of GPU monitoring sample.
+ */
+typedef struct NV2080_CTRL_GPUMON_SAMPLE {
+    /*!
+    * Timestamps in nano-seconds. 
+    */
+    NV_DECLARE_ALIGNED(NvU64 timeStamp, 8);
+} NV2080_CTRL_GPUMON_SAMPLE;
+
+/*!
+ *  This structure represents base GPU monitoring sample.
+ */
+typedef struct NV2080_CTRL_GPUMON_SAMPLES {
+    /*!
+    * Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference. 
+    */
+    NvU8  type;
+    /*!
+    * Size of the buffer, this should be
+    * bufSize ==  NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_*
+    *    sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE).
+    */
+    NvU32 bufSize;
+    /*!
+    * Number of samples in ring buffer.
+    */
+    NvU32 count;
+    /*!
+    * tracks the offset of the tail in the circular queue array pSamples.
+    */
+    NvU32 tracker;
+    /*!
+    * Pointer to a circular queue based on array of NV2080_CTRL_GPUMON_SAMPLE
+    * or its derived types structs with size == bufSize.
+    *
+    * @note This circular queue wraps around after 10 seconds of sampling,
+    * and it is clients' responsibility to query within this time frame in
+    * order to avoid losing samples.
+    * @note With one exception, this queue contains last 10 seconds of samples
+    * with tracker poiniting to oldest entry and entry before tracker as the
+    * newest entry. Exception is when queue is not full (i.e. tracker is
+    * pointing to a zeroed out entry), in that case valid entries are between 0
+    * and tracker.
+    * @note Clients can store tracker from previous query in order to provide
+    * samples since last read.
+    */
+    NV_DECLARE_ALIGNED(NvP64 pSamples, 8);
+} NV2080_CTRL_GPUMON_SAMPLES;
+
+/*!
+ * Enumeration of GPU monitoring sample types.
+ */
+#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS 0x00000001
+#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL       0x00000002
+
+/*!
+ * Macro for invalid PID.
+ */
+#define NV2080_GPUMON_PID_INVALID         ((NvU32)(~0))
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gr.h
new file mode 100644
index 0000000..93172ac
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gr.h
@@ -0,0 +1,2034 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080gr.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+#include "ctrl/ctrl0080/ctrl0080gr.h"        /* 2080 is partially derivative of 0080 */
+#include "nvcfg_sdk.h"
+
+/*
+ * NV2080_CTRL_GR_ROUTE_INFO
+ *
+ * This structure specifies the routing information used to
+ * disambiguate the target GR engine.
+ *
+ *   flags
+ *     This field decides how the route field is interpreted
+ *
+ *   route
+ *     This field has the data to identify target GR engine
+ *
+ */
+#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE                 1:0
+#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE    0x0U
+#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID   0x1U
+#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL 0x2U
+
+#define NV2080_CTRL_GR_ROUTE_INFO_DATA_CHANNEL_HANDLE      31:0
+#define NV2080_CTRL_GR_ROUTE_INFO_DATA_ENGID               31:0
+
+typedef NV0080_CTRL_GR_ROUTE_INFO NV2080_CTRL_GR_ROUTE_INFO;
+
+/* NV20_SUBDEVICE_XX gr control commands and parameters */
+
+/*
+ * NV2080_CTRL_GR_INFO
+ *
+ * This structure represents a single 32bit gr engine value.  Clients
+ * request a particular gr engine value by specifying a unique gr
+ * information index.
+ *
+ * Legal gr information index values are:
+ *   NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT
+ *     This index is used to request the surface buffer alignment (in bytes)
+ *     required by the associated subdevice.  The return value is GPU
+ *     implementation-dependent.
+ *   NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT
+ *     This index is used to request the required swizzled surface alignment
+ *     (in bytes) supported by the associated subdevice.  The return value
+ *     is GPU implementation-dependent.  A return value of 0 indicates the GPU
+ *     does not support swizzled surfaces.
+ *   NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE
+ *     This index is used to request the vertex cache size (in entries)
+ *     supported by the associated subdevice.  The return value is GPU
+ *     implementation-dependent.  A value of 0 indicates the GPU does
+ *     have a vertex cache.
+ *   NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT
+ *     This index is used to request the number of VPE units supported by the
+ *     associated subdevice.  The return value is GPU implementation-dependent.
+ *     A return value of 0 indicates the GPU does not contain VPE units.
+ *   NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT
+ *     This index is used to request the number of shader pipes supported by
+ *     the associated subdevice.  The return value is GPU
+ *     implementation-dependent.  A return value of 0 indicates the GPU does
+ *     not contain dedicated shader units.
+ *     For tesla: this value is the number of enabled TPCs
+ *   NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT
+ *     This index is used to request the number of sub units per
+ *     shader pipes supported by the associated subdevice.  The return
+ *     value is GPU implementation-dependent.  A return value of 0 indicates
+ *     the GPU does not contain dedicated shader units.
+ *     For tesla: this value is the number of enabled SMs (per TPC)
+ *   NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR
+ *     This index is used to request the scaling factor for thread stack
+ *     memory.
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT
+ *     This index is used to request the number of SM register banks supported.
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT
+ *     This index is used to request the number of registers per SM register
+ *     bank. A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_SM_VERSION
+ *     This index is used to determine the SM version.
+ *     A value of 0 indicates the GPU does not support this function.
+ *     Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*.
+ *   NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM
+ *     This index is used to determine the maximum number of warps
+ *     (thread groups) per SM.
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP
+ *     This index is used to determine the maximum number of threads
+ *     in each warp (thread group).
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY
+ *     This index is used to request the default fb memory read/write request
+ *     size in bytes (typically based on the memory configuration/controller).
+ *     Smaller memory requests are likely to take as long as a full one.
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY
+ *     This index is used to request the default host memory read/write request
+ *     size in bytes (typically based on the memory configuration/controller).
+ *     Smaller memory requests are likely to take as long as a full one.
+ *     A value of 0 indicates the GPU does not support this function.
+ *   NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM
+ *     This index is used to request the maximum number of streaming processors
+ *     per SM.
+ *   NV2080_CTRL_GR_INFO_INDEX_LITTER_*
+ *     This index is used to query the various LITTER size information from
+ *     the chip.
+ *   NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED
+ *     This index is used to query whether the chip has timeslice mode enabled.
+ *   NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT
+ *     This index is used to return the number of "GPU Cores"
+ *     supported by the graphics pipeline
+ *   NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT
+ *     This index is used to return the number of "Ray Tracing Cores"
+ *     supported by the graphics pipeline
+ *    NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
+ *     This index is used to return the number of "Tensor Cores"
+ *     supported by the graphics pipeline
+ *    NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
+ *     This index is used to return the Graphics capabilities
+ *     supported by the graphics pipeline
+ */
+typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
+
+/*
+ * Valid GR info index values
+ * These indices are offset from supporting the 0080 version of this call
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS                              NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
+#define NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894                  NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
+#define NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK                     NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK
+/**
+ * This index is used to request the surface buffer alignment (in bytes)
+ * required by the associated subdevice.  The return value is GPU
+ * implementation-dependent.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT                      NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT
+#define NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT                     NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT
+#define NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE                     NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE
+/**
+ * This index is used to request the number of VPE units supported by the
+ * associated subdevice.  The return value is GPU implementation-dependent.
+ * A return value of 0 indicates the GPU does not contain VPE units.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT                             NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT
+/**
+ * This index is used to request the number of shader pipes supported by
+ * the associated subdevice.  The return value is GPU
+ * implementation-dependent.  A return value of 0 indicates the GPU does
+ * not contain dedicated shader units.
+ * For tesla: this value is the number of enabled TPCs
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT                     NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT
+/**
+ * This index is used to request the scaling factor for thread stack
+ * memory.
+ * A value of 0 indicates the GPU does not support this function.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR           NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR
+/**
+ * This index is used to request the number of sub units per
+ * shader pipes supported by the associated subdevice.  The return
+ * value is GPU implementation-dependent.  A return value of 0 indicates
+ * the GPU does not contain dedicated shader units.
+ * For tesla: this value is the number of enabled SMs (per TPC)
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT                 NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT                     NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT                 NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT
+/**
+ * This index is used to determine the SM version.
+ * A value of 0 indicates the GPU does not support this function.
+ * Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_SM_VERSION                            NV0080_CTRL_GR_INFO_INDEX_SM_VERSION
+/**
+ * This index is used to determine the maximum number of warps
+ * (thread groups) per SM.
+ * A value of 0 indicates the GPU does not support this function.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM                      NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM
+/**
+ * This index is used to determine the maximum number of threads
+ * in each warp (thread group).
+ * A value of 0 indicates the GPU does not support this function.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP                  NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP
+#define NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES                  NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES
+#define NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES                     NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES
+#define NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY         NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY
+#define NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY       NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM                         NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS                       NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS                       NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS                NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC                NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS                   NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS            NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS
+#define NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED                     NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS                      NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC                NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT                        NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES               NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS            NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC                 NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS            NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS
+/**
+ * This index is used to return the number of "Ray Tracing Cores"
+ * supported by the graphics pipeline
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT                         NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT                     NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS                        NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS                       NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES                 NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC             NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP                NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC                NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC                NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP               NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT                  NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT           NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT       NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS             NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS                  NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC     NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC             NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
+
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES           NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES
+
+
+#define NV2080_CTRL_GR_INFO_INDEX_RESERVED                              NV0080_CTRL_GR_INFO_INDEX_RESERVED
+#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES                      NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES                       NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES
+#define NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS                NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG         NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET            NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_CPC_PER_GPC                NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_CPC_PER_GPC
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_NVLINK_MASK              NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_NVLINK_MASK
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_C2C_MASK                 NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_C2C_MASK
+#define NV2080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_PCIE_MASK                NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_PCIE_MASK
+
+
+#define NV2080_CTRL_GR_INFO_INDEX_RESERVED1                             NV0080_CTRL_GR_INFO_INDEX_RESERVED1
+
+/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly
+ * NOTE: 0080 functionality is merged with 2080 functionality, so this max size
+ * reflects that.
+ */
+#define NV2080_CTRL_GR_INFO_INDEX_MAX                                   NV0080_CTRL_GR_INFO_INDEX_MAX
+#define NV2080_CTRL_GR_INFO_MAX_SIZE                                    NV0080_CTRL_GR_INFO_MAX_SIZE
+
+/* valid SM version return values */
+
+#define NV2080_CTRL_GR_INFO_SM_VERSION_NONE                             (0x00000000U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_05                             (0x00000105U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_1                              (0x00000110U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_2                              (0x00000120U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_3                              (0x00000130U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_4                              (0x00000140U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_1_5                              (0x00000150U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_2_0                              (0x00000200U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_2_1                              (0x00000210U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_2_2                              (0x00000220U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_0                              (0x00000300U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_1                              (0x00000310U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_2                              (0x00000320U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_3                              (0x00000330U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_5                              (0x00000350U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_6                              (0x00000360U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_8                              (0x00000380U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_3_9                              (0x00000390U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_4_0                              (0x00000400U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_5_0                              (0x00000500U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_5_02                             (0x00000502U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_5_03                             (0x00000503U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_6_0                              (0x00000600U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_6_01                             (0x00000601U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_6_02                             (0x00000602U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_0                              (0x00000700U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_01                             (0x00000701U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_02                             (0x00000702U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_03                             (0x00000703U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_05                             (0x00000705U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_02                             (0x00000802U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_06                             (0x00000806U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_07                             (0x00000807U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08                             (0x00000808U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09                             (0x00000809U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00                             (0x00000900U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_10_00                            (0x00000A00U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01                            (0x00000A01U)
+
+#define NV2080_CTRL_GR_INFO_SM_VERSION_10_03                            (0x00000A03U)
+
+
+/*
+ * TODO Bug 4333440 is introducing versions 12_*.
+ * Eventually once 12_* is tested and validated, another
+ * follow up change will be needed to remove 10_04 support.
+ */
+#define NV2080_CTRL_GR_INFO_SM_VERSION_10_04                            (0x00000A04U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_12_00                            (0x00000C00U)
+
+
+#define NV2080_CTRL_GR_INFO_SM_VERSION_12_01                            (0x00000C01U)
+
+
+#define NV2080_CTRL_GR_INFO_SM_VERSION_10_05                            (0x00000A05U)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_13_00                            (0x00000D00U)
+
+
+
+/* compatibility SM versions to match the official names in the ISA (e.g., SM5.2)  */
+#define NV2080_CTRL_GR_INFO_SM_VERSION_5_2                              (NV2080_CTRL_GR_INFO_SM_VERSION_5_02)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_5_3                              (NV2080_CTRL_GR_INFO_SM_VERSION_5_03)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_6_1                              (NV2080_CTRL_GR_INFO_SM_VERSION_6_01)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_6_2                              (NV2080_CTRL_GR_INFO_SM_VERSION_6_02)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_1                              (NV2080_CTRL_GR_INFO_SM_VERSION_7_01)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_2                              (NV2080_CTRL_GR_INFO_SM_VERSION_7_02)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_3                              (NV2080_CTRL_GR_INFO_SM_VERSION_7_03)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_7_5                              (NV2080_CTRL_GR_INFO_SM_VERSION_7_05)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_2                              (NV2080_CTRL_GR_INFO_SM_VERSION_8_02)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_6                              (NV2080_CTRL_GR_INFO_SM_VERSION_8_06)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_7                              (NV2080_CTRL_GR_INFO_SM_VERSION_8_07)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8                              (NV2080_CTRL_GR_INFO_SM_VERSION_8_08)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9                              (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0                              (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_10_0                             (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1                             (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
+
+#define NV2080_CTRL_GR_INFO_SM_VERSION_10_3                             (NV2080_CTRL_GR_INFO_SM_VERSION_10_03)
+
+
+#define NV2080_CTRL_GR_INFO_SM_VERSION_10_4                             (NV2080_CTRL_GR_INFO_SM_VERSION_10_04)
+
+
+#define NV2080_CTRL_GR_INFO_SM_VERSION_10_5                             (NV2080_CTRL_GR_INFO_SM_VERSION_10_05)
+#define NV2080_CTRL_GR_INFO_SM_VERSION_13_0                             (NV2080_CTRL_GR_INFO_SM_VERSION_13_00)
+
+
+
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D            0:0
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE                   0x0U
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE                    0x1U
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D            1:1
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE                   0x0U
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE                    0x1U
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE       2:2
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE              0x0U
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE               0x1U
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M           3:3
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE                  0x0U
+#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE                   0x1U
+
+/**
+ * NV2080_CTRL_CMD_GR_GET_INFO
+ *
+ * This command returns gr engine information for the associated GPU.
+ * Requests to retrieve gr information use a list of one or more
+ * NV2080_CTRL_GR_INFO structures.
+ *
+ *   grInfoListSize
+ *     This field specifies the number of entries on the caller's
+ *     grInfoList.
+ *   grInfoList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the gr information is to be returned.
+ *     This buffer must be at least as big as grInfoListSize multiplied
+ *     by the size of the NV2080_CTRL_GR_INFO structure.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine. When MIG is enabled, this
+ *     is a mandatory parameter.
+ */
+#define NV2080_CTRL_CMD_GR_GET_INFO                                     (0x20801201U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_GR_GET_INFO_PARAMS {
+    NvU32 grInfoListSize;
+    NV_DECLARE_ALIGNED(NvP64 grInfoList, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_GET_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE
+ *
+ * This command is used to set the zcull context switch mode for the specified
+ * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the
+ * target channel does not support zcull context switch mode changes.
+ *
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have it's zcull context switch mode changed.
+ *   hShareClient
+ *     Support for sharing zcull buffers across RM clients is no longer
+ *     supported.  To maintain API compatibility, this field must match
+ *     the hClient used in the control call.
+ *   hShareChannel
+ *     This parameter specifies the channel handle of
+ *     the channel with which the zcull context buffer is to be shared.  This
+ *     parameter is valid when zcullMode is set to SEPARATE_BUFFER.  This
+ *     parameter should be set to the same value as hChannel if no
+ *     sharing is intended.
+ *   zcullMode
+ *     This parameter specifies the new zcull context switch mode.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_GLOBAL
+ *         This mode is the normal zcull operation where it is not
+ *         context switched and there is one set of globally shared
+ *         zcull memory and tables.  This mode is only supported as
+ *         long as all channels use this mode.
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_NO_CTXSW
+ *         This mode causes the zcull tables to be reset on a context
+ *         switch, but the zcull buffer will not be saved/restored.
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_SEPARATE_BUFFER
+ *         This mode will cause the zcull buffers and tables to be
+ *         saved/restored on context switches.  If a share channel
+ *         ID is given (shareChID), then the 2 channels will share
+ *         the zcull context buffers.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS {
+    NvHandle hChannel;
+    NvHandle hShareClient;
+    NvHandle hShareChannel;
+    NvU32    zcullMode;
+} NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS;
+/* valid zcullMode values */
+#define NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL          (0x00000000U)
+#define NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW        (0x00000001U)
+#define NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER (0x00000002U)
+
+/**
+ * NV2080_CTRL_CMD_GR_GET_ZCULL_INFO
+ *
+ * This command is used to query the RM for zcull information that the
+ * driver will need to allocate and manage the zcull regions.
+ *
+ *   widthAlignPixels
+ *     This parameter returns the width alignment restrictions in pixels
+ *     used to adjust a surface for proper aliquot coverage (typically
+ *     #TPC's * 16).
+ *
+ *   heightAlignPixels
+ *     This parameter returns the height alignment restrictions in pixels
+ *     used to adjust a surface for proper aliquot coverage (typically 32).
+ *
+ *   pixelSquaresByAliquots
+ *     This parameter returns the pixel area covered by an aliquot
+ *     (typically #Zcull_banks * 16 * 16).
+ *
+ *   aliquotTotal
+ *     This parameter returns the total aliquot pool available in HW.
+ *
+ *   zcullRegionByteMultiplier
+ *     This parameter returns multiplier used to convert aliquots in a region
+ *     to the number of bytes required to save/restore them.
+ *
+ *   zcullRegionHeaderSize
+ *     This parameter returns the region header size which is required to be
+ *     allocated and accounted for in any save/restore operation on a region.
+ *
+ *   zcullSubregionHeaderSize
+ *     This parameter returns the subregion header size which is required to be
+ *     allocated and accounted for in any save/restore operation on a region.
+ *
+ *   subregionCount
+ *     This parameter returns the subregion count.
+ *
+ *   subregionWidthAlignPixels
+ *     This parameter returns the subregion width alignment restrictions in
+ *     pixels used to adjust a surface for proper aliquot coverage
+ *     (typically #TPC's * 16).
+ *
+ *   subregionHeightAlignPixels
+ *     This parameter returns the subregion height alignment restrictions in
+ *     pixels used to adjust a surface for proper aliquot coverage
+ *     (typically 62).
+ *
+ *   The callee should compute the size of a zcull region as follows.
+ *     (numBytes = aliquots * zcullRegionByteMultiplier +
+ *                 zcullRegionHeaderSize + zcullSubregionHeaderSize)
+ */
+#define NV2080_CTRL_CMD_GR_GET_ZCULL_INFO            (0x20801206U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED
+#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS {
+    NvU32 widthAlignPixels;
+    NvU32 heightAlignPixels;
+    NvU32 pixelSquaresByAliquots;
+    NvU32 aliquotTotal;
+    NvU32 zcullRegionByteMultiplier;
+    NvU32 zcullRegionHeaderSize;
+    NvU32 zcullSubregionHeaderSize;
+    NvU32 subregionCount;
+    NvU32 subregionWidthAlignPixels;
+    NvU32 subregionHeightAlignPixels;
+} NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_PM_MODE
+ *
+ * This command is used to set the pm context switch mode for the specified
+ * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the
+ * target channel does not support pm context switch mode changes.
+ *
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have its pm context switch mode changed.
+ *   pmMode
+ *     This parameter specifies the new pm context switch mode.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW
+ *         This mode says that the pms are not to be context switched.
+ *       NV2080_CTRL_CTXSW_PM_MODE_CTXSW
+ *         This mode says that the pms in Mode-B are to be context switched.
+ *       NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW
+ *         This mode says that the pms in Mode-E (stream out) are to be context switched.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS {
+    NvHandle hChannel;
+    NvU32    pmMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS;
+
+/* valid pmMode values */
+#define NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW         (0x00000000U)
+#define NV2080_CTRL_CTXSW_PM_MODE_CTXSW            (0x00000001U)
+#define NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW (0x00000002U)
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND
+ *
+ * This command is used to set the zcull context switch mode and virtual address
+ * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is
+ * returned if the target channel does not support zcull context switch mode
+ * changes.
+ *
+ *   hClient
+ *     This parameter specifies the client handle of
+ *     that owns the zcull context buffer. This field must match
+ *     the hClient used in the control call for non-kernel clients.
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have its zcull context switch mode changed.
+ *   vMemPtr
+ *     This parameter specifies the 64 bit virtual address
+ *     for the allocated zcull context buffer.
+ *   zcullMode
+ *     This parameter specifies the new zcull context switch mode.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_GLOBAL
+ *         This mode is the normal zcull operation where it is not
+ *         context switched and there is one set of globally shared
+ *         zcull memory and tables.  This mode is only supported as
+ *         long as all channels use this mode.
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_NO_CTXSW
+ *         This mode causes the zcull tables to be reset on a context
+ *         switch, but the zcull buffer will not be saved/restored.
+ *       NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_SEPARATE_BUFFER
+ *         This mode will cause the zcull buffers and tables to be
+ *         saved/restored on context switches.  If a share channel
+ *         ID is given (shareChID), then the 2 channels will share
+ *         the zcull context buffers.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND        (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS {
+    NvHandle hClient;
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8);
+    NvU32    zcullMode;
+} NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS;
+/* valid zcullMode values same as above NV2080_CTRL_CTXSW_ZCULL_MODE */
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_PM_BIND
+ *
+ * This command is used to set the PM context switch mode and virtual address
+ * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is
+ * returned if the target channel does not support PM context switch mode
+ * changes.
+ *
+ *   hClient
+ *     This parameter specifies the client handle of
+ *     that owns the PM context buffer.
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have its PM context switch mode changed.
+ *   vMemPtr
+ *     This parameter specifies the 64 bit virtual address
+ *     for the allocated PM context buffer.
+ *   pmMode
+ *     This parameter specifies the new PM context switch mode.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_GR_SET_CTXSW_PM_MODE_NO_CTXSW
+ *         This mode says that the pms are not to be context switched
+ *       NV2080_CTRL_GR_SET_CTXSW_PM_MODE_CTXSW
+ *         This mode says that the pms are to be context switched
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS {
+    NvHandle hClient;
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8);
+    NvU32    pmMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS;
+/* valid pmMode values same as above NV2080_CTRL_CTXSW_PM_MODE */
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND
+ *
+ * This command is used to set the Setup context switch mode and virtual address
+ * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is
+ * returned if the target channel does not support setup context switch mode
+ * changes.
+ *
+ *   hClient
+ *     This parameter specifies the client handle of
+ *     that owns the Setup context buffer. This field must match
+ *     the hClient used in the control call for non-kernel clients.
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have its Setup context switch mode changed.
+ *   vMemPtr
+ *     This parameter specifies the 64 bit virtual address
+ *     for the allocated Setup context buffer.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND (0x2080123aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0x3AU)
+
+typedef struct NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS {
+    NvHandle hClient;
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8);
+} NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP
+ *
+ * Send a list of values used to describe GPC/TPC tile mapping tables.
+ *
+ *   mapValueCount
+ *     This field specifies the number of actual map entries.  This count
+ *     should equal the number of TPCs in the system.
+ *   mapValues
+ *     This field is a pointer to a buffer of NvU08 values representing map
+ *     data.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES 128U
+#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP        (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS {
+    NvU32 mapValueCount;
+    NvU8  mapValues[NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE
+ *
+ * This command is used to set the SMPC context switch mode for the specified
+ * channel or channel group (TSG). A value of NV_ERR_NOT_SUPPORTED
+ * is returned if the target channel/TSG does not support SMPC context switch
+ * mode changes.  If a channel is part of a TSG, the user must send in the TSG
+ * handle and not an individual channel handle, an error will be returned if a
+ * channel handle is used in this case.
+ *
+ * SMPC = SM Performance Counters
+ *
+ *   hChannel
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *     that is to have its SMPC context switch mode changed.
+ *     If this parameter is set to 0, then the mode below applies to all current
+ *     and future channels (i.e. we will be enabling/disabling global mode)
+ *   smpcMode
+ *     This parameter specifies the new SMPC context switch mode.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_GR_SET_CTXSW_SMPC_MODE_NO_CTXSW
+ *         This mode says that the SMPC data is not to be context switched.
+ *       NV2080_CTRL_GR_SET_CTXSW_SMPC_MODE_CTXSW
+ *         This mode says that the SMPC data is to be context switched.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS {
+    NvHandle hChannel;
+    NvU32    smpcMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS;
+
+/* valid smpcMode values */
+#define NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW                   (0x00000000U)
+#define NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW                      (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
+ *
+ * This command returns an array of the mappings between SMs and GPC/TPCs.
+ *
+ *   smId
+ *     An array of the mappings between SMs and GPC/TPCs.
+ *   smCount
+ *     Returns the number of valid mappings in the array.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS          (0x2080120fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT 512U
+#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS {
+    struct {
+        NvU32 gpcId;
+        NvU32 tpcId;
+    } smId[NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT];
+    NvU32 smCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE
+ *
+ * This command is used to set the preemption context switch mode for the specified
+ * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the
+ * target channel does not support preemption context switch mode changes.
+ *
+ *   flags
+ *     This field specifies flags for the preemption mode changes.
+ *     These flags can tell callee which mode is valid in the call
+ *     since we handle graphics and/or compute
+ *   hChannel
+ *     This parameter specifies the channel handle of the channel
+ *     that is to have it's preemption context switch mode set.
+ *   gfxpPreemptMode
+ *     This parameter specifies the new Graphics preemption context switch
+ *     mode. Legal values for this parameter include:
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI
+ *         This mode is the normal wait-for-idle context switch mode.
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP
+ *         This mode causes the graphics engine to allow preempting the
+ *         channel mid-triangle.
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL
+ *         This mode causes the graphics engine to use a shared pool of buffers
+ *         to support GfxP with lower memory overhead
+ *   cilpPreemptMode
+ *     This parameter specifies the new Compute preemption context switch
+ *     mode. Legal values for this parameter include:
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI
+ *         This mode is the normal wait-for-idle context switch mode.
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA
+ *         This mode causes the compute engine to allow preempting the channel
+ *         at the instruction level.
+ *       NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP
+ *         This mode causes the compute engine to allow preempting the channel
+ *         at the instruction level.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS {
+    NvU32    flags;
+    NvHandle hChannel;
+    NvU32    gfxpPreemptMode;
+    NvU32    cilpPreemptMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS;
+
+/* valid preemption flags */
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP                0:0
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE (0x00000000U)
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET    (0x00000001U)
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP                1:1
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE (0x00000000U)
+#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET    (0x00000001U)
+
+/* valid Graphics mode values */
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI              (0x00000000U)
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP             (0x00000001U)
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL        (0x00000002U)
+
+/* valid Compute mode values */
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI          (0x00000000U)
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA          (0x00000001U)
+#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP         (0x00000002U)
+
+/* valid preemption buffers */
+typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS {
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = 0,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = 1,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = 2,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = 3,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = 4,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP = 8,
+    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 9,
+} NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS;
+
+/*
+ * NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND
+ *
+ * This command is used to set the preemption context switch mode and virtual
+ * addresses of the preemption buffers for the specified channel. A value of
+ * NV_ERR_NOT_SUPPORTED is returned if the target channel does not
+ * support preemption context switch mode changes.
+ *
+ *   flags
+ *     This field specifies flags for the preemption mode changes.
+ *     These flags can tell callee which mode is valid in the call
+ *     since we handle graphics and/or compute
+ *   hClient
+ *     This parameter specifies the client handle of
+ *     that owns the preemption context buffer.
+ *   hChannel
+ *     This parameter specifies the channel handle of the channel
+ *     that is to have its preemption context switch mode set.
+ *   vMemPtr
+ *     This parameter specifies the 64 bit virtual address
+ *     for the allocated preemption context buffer.
+ *   gfxpPreemptMode
+ *     This parameter specifies the new Graphics preemption context switch
+ *     mode. Legal values for this parameter include:
+ *       NV2080_CTRL_CTXSW_PREEMPTION_MODE_GFX_WFI
+ *         This mode is the normal wait-for-idle context switch mode.
+ *       NV2080_CTRL_CTXSW_PREEMPTION_MODE_GFX_GFXP
+ *         This mode causes the graphics engine to allow preempting the
+ *         channel mid-triangle.
+ *   cilpPreemptMode
+ *     This parameter specifies the new Compute preemption context switch
+ *     mode. Legal values for this parameter include:
+ *       NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_WFI
+ *         This mode is the normal wait-for-idle context switch mode.
+ *       NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_CTA
+ *         This mode causes the compute engine to allow preempting the channel
+ *         at the instruction level.
+ *       NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_CILP
+ *         This mode causes the compute engine to allow preempting the channel
+ *         at the instruction level.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS {
+    NvU32    flags;
+    NvHandle hClient;
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 vMemPtrs[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END], 8);
+    NvU32    gfxpPreemptMode;
+    NvU32    cilpPreemptMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS;
+/* valid mode and flag values same as above NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE */
+
+/*
+ * NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE
+ *
+ * This command is used to apply the WAR for PC sampling to avoid hang in
+ * multi-ctx scenario.
+ *
+ *   hChannel
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *     that is to have its PC Sampling mode changed.
+ *   samplingMode
+ *     This parameter specifies whether sampling is turned ON or OFF.
+ *     Legal values for this parameter include:
+ *       NV2080_CTRL_GR_SET_PC_SAMPLING_MODE_DISABLED
+ *         This mode says that PC sampling is disabled for current context.
+ *       NV2080_CTRL_GR_SET_PC_SAMPLING_MODE_ENABLED
+ *         This mode says that PC sampling is disabled for current context.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS {
+    NvHandle hChannel;
+    NvU32    samplingMode;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS;
+
+/* valid samplingMode values */
+#define NV2080_CTRL_PC_SAMPLING_MODE_DISABLED (0x00000000U)
+#define NV2080_CTRL_PC_SAMPLING_MODE_ENABLED  (0x00000001U)
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_ROP_INFO
+ *
+ * Gets information about ROPs including the ROP unit count and information
+ * about ROP operations per clock.
+ *
+ *   ropUnitCount
+ *     The count of active ROP units.
+ *   ropOperationsFactor.
+ *     The number of ROP operations per clock for a single ROP unit.
+ *   ropOperationsCount
+ *     The number of ROP operations per clock across all active ROP units.
+ */
+#define NV2080_CTRL_CMD_GR_GET_ROP_INFO       (0x20801213U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_GR_GET_ROP_INFO_PARAMS {
+    NvU32 ropUnitCount;
+    NvU32 ropOperationsFactor;
+    NvU32 ropOperationsCount;
+} NV2080_CTRL_GR_GET_ROP_INFO_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_CTXSW_STATS
+ *
+ * This command is used to get the context switch statistics.  The user can
+ * also add a flag to tell RM to reset the stats counters back to 0.
+ *
+ *   hChannel
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *     that is to have the stats returned.  Note, must be the TSG handle if
+ *     channel is part of a TSG.
+ *   flags
+ *     This parameter specifies processing flags. See possible flags below.
+ *   saveCnt
+ *     This parameter returns the number of saves on the channel.
+ *   restoreCnt
+ *     This parameter returns the number of restores on the channel.
+ *   wfiSaveCnt
+ *     This parameter returns the number of WFI saves on the channel.
+ *   ctaSaveCnt
+ *     This parameter returns the number of CTA saves on the channel.
+ *   cilpSaveCnt
+ *     This parameter returns the number of CILP saves on the channel.
+ *   gfxpSaveCnt
+ *     This parameter returns the number of GfxP saves on the channel.
+ */
+#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS {
+    NvHandle hChannel;
+    NvU32    flags;
+    NvU32    saveCnt;
+    NvU32    restoreCnt;
+    NvU32    wfiSaveCnt;
+    NvU32    ctaSaveCnt;
+    NvU32    cilpSaveCnt;
+    NvU32    gfxpSaveCnt;
+} NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS;
+/* valid GET_CTXSW_STATS flags settings */
+#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET                      0:0
+#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE (0x00000000U)
+#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE  (0x00000001U)
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE
+ *
+ * This command provides the size, alignment of all context buffers including global and
+ * local context buffers which has been created & will be mapped on a context
+ *
+ *   hChannel [IN]
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *   totalBufferSize [OUT]
+ *     This parameter returns the total context buffers size.
+ */
+#define NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE (0x20801218U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS {
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8);
+} NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS;
+
+/*
+ * NV2080_CTRL_GR_CTX_BUFFER_INFO
+ *   alignment
+ *     Specifies the alignment requirement for each context buffer
+ *   size
+ *     Aligned size of context buffer
+ *   bufferHandle [deprecated]
+ *     Opaque pointer to memdesc. Used by kernel clients for tracking purpose only.
+ *   pageCount
+ *     allocation size in the form of pageCount
+ *   physAddr
+ *     Physical address of the buffer first page
+ *   bufferType
+ *     NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID type of this buffer
+ *   aperture
+ *     allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN
+ *   kind
+ *     PTE kind of this allocation.
+ *   pageSize
+ *     Page size of the buffer.
+ *   bIsContigous
+ *     States if physical allocation for this buffer is contiguous. PageSize will
+ *     have no meaning if this flag is set.
+ *   bGlobalBuffer
+ *     States if a defined buffer is global as global buffers need to be mapped
+ *     only once in TSG.
+ *   bLocalBuffer
+ *     States if a buffer is local to a channel.
+ *   bDeviceDescendant
+ *     TRUE if the allocation is a constructed under a Device or Subdevice.
+ *   uuid
+ *     SHA1 UUID of the Device or Subdevice. Valid when deviceDescendant is TRUE.
+ */
+typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO {
+    NV_DECLARE_ALIGNED(NvU64 alignment, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8);
+    NV_DECLARE_ALIGNED(NvU64 pageCount, 8);
+    NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
+    NvU32  bufferType;
+    NvU32  aperture;
+    NvU32  kind;
+    NvU32  pageSize;
+    NvBool bIsContigous;
+    NvBool bGlobalBuffer;
+    NvBool bLocalBuffer;
+    NvBool bDeviceDescendant;
+    NvU8   uuid[16];
+} NV2080_CTRL_GR_CTX_BUFFER_INFO;
+typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO *PNV2080_CTRL_GR_CTX_BUFFER_INFO;
+
+#define NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT    64U
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO
+ *
+ * This command provides the size, alignment of all context buffers including global and
+ * local context buffers which has been created & will be mapped on a context.
+ * If the client invoking the command is a kernel client, the buffers are retained.
+ *
+ *   hUserClient [IN]
+ *     This parameter specifies the client handle that owns this channel.
+ *   hChannel [IN]
+ *     This parameter specifies the channel or channel group (TSG) handle
+ *   bufferCount [OUT]
+ *     This parameter specifies the number of entries in ctxBufferInfo filled
+ *     by the command.
+ *   ctxBufferInfo [OUT]
+ *     Array of context buffer info containing alignment, size etc.
+ */
+#define NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO (0x20801219U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x19U)
+
+typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS {
+    NvHandle hUserClient;
+    NvHandle hChannel;
+    NvU32    bufferCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTX_BUFFER_INFO ctxBufferInfo[NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT], 8);
+} NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS;
+
+// Aperture flags. The defines should match the defines in mem_desc.h
+#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN 0
+#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM  1
+#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM   2
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
+ *     This command returns the global logical ordering of SM w.r.t GPCs/TPCs.
+ *
+ * NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS
+ *     This structure holds the TPC/SM ordering info.
+ *
+ *     gpcId
+ *         Logical GPC Id.
+ *         This is the ordering of enabled GPCs post floor sweeping.
+ *         The GPCs are numbered from 0 to N-1, where N is the enabled GPC count.
+ *
+ *     localTpcId
+ *         Local Logical TPC Id.
+ *         This is the ordering of enabled TPCs within a GPC post floor sweeping.
+ *         This ID is used in conjunction with the gpcId.
+ *         The TPCs are numbered from 0 to N-1, where N is the enabled TPC count for the given GPC.
+ *
+ *     localSmId
+ *         Local Logical SM Id.
+ *         This is the ordering of enabled SMs within a TPC post floor sweeping.
+ *         This ID is used in conjunction with the localTpcId.
+ *         The SMs are numbered from 0 to N-1, where N is the enabled SM count for the given TPC.
+ *
+ *     globalTpcId
+ *         Global Logical TPC Id.
+ *         This is the ordering of all enabled TPCs in the GPU post floor sweeping.
+ *         The TPCs are numbered from 0 to N-1, where N is the enabled TPC count across all GPCs
+ *
+ *     globalSmId
+ *         Global Logical SM Id array.
+ *         This is the global ordering of all enabled SMs in the GPU post floor sweeping.
+ *         The SMs are numbered from 0 to N-1, where N is the enabled SM count across all GPCs.
+ *
+ *     virtualGpcId
+ *         Virtual GPC Id.
+ *         This is the ordering of enabled GPCs post floor sweeping (ordered in increasing
+ *         number of TPC counts) The GPCs are numbered from 0 to N-1, where N is the
+ *         enabled GPC count and 8-23 for singleton TPC holders.
+ *
+ *     migratableTpcId
+ *         Migratable TPC Id.
+ *         This is the same as the Local Tpc Id for virtual GPC 0-8 (true physical gpcs) and 0 for
+ *         virtual gpcs 8-23 that represent singleton tpcs.
+ *
+ *     numSm
+ *         Enabled SM count across all GPCs.
+ *         This represent the valid entries in the globalSmId array
+ *
+ *     numTpc
+ *         Enabled TPC count across all GPCs.
+ *
+ *     grRouteInfo
+ *         This parameter specifies the routing information used to
+ *         disambiguate the target GR engine.
+ *
+ *     ugpuId
+ *         Specifies the uGPU ID on Hopper+.
+ *
+ */
+#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER              (0x2080121bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT 512U
+
+#define NV2080_CTRL_GR_DISABLED_SM_VGPC_ID                  0xFFU
+
+#define NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x1BU)
+
+typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS {
+    struct {
+        NvU16 gpcId;
+        NvU16 localTpcId;
+        NvU16 localSmId;
+        NvU16 globalTpcId;
+        NvU16 virtualGpcId;
+        NvU16 migratableTpcId;
+        NvU16 ugpuId;
+        NvU16 physicalCpcId;
+        NvU16 virtualTpcId;
+    } globalSmId[NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT];
+
+    NvU16 numSm;
+    NvU16 numTpc;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS;
+
+/*
+* NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL
+*
+* This command gives current resident channel on GR engine
+*
+*   chID [OUT]
+*       RM returns current resident channel on GR engine
+*   grRouteInfo [IN]
+*       This parameter specifies the routing information used to
+*       disambiguate the target GR engine.
+*/
+#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID (0x1CU)
+
+typedef struct NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS {
+    NvU32 chID;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE
+ *
+ * This command provides the size of GR attribute buffer.
+ *
+ *   attribBufferSize [OUT]
+ *     This parameter returns the attribute buffer size.
+ */
+#define NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE (0x2080121eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x1EU)
+
+typedef struct NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS {
+    NvU32 attribBufferSize;
+} NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE
+ *
+ * This API queries size parameters for a request maximum graphics preemption
+ * pool size.  It is only available to kernel callers
+ *
+ * NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS
+ *   struct to return the size parameters
+ *
+ *   maxSlots
+ *     Input specifying the maximum number of slots, RM will calculate the output
+ *     parameters based on this.  Must be non-zero
+ *   ctrlStructSize
+ *     Output indicating the required size in bytes of the control structure to
+ *     support a pool of maxSlots size.
+ *   ctrlStructAlign
+ *     Output indicating the required alignment of the control structure
+ *   poolSize
+ *     Output indicating the required size in bytes of the GfxP Pool.
+ *   poolAlign
+ *     Output indicating the required alignment of the GfxP Pool
+ *   slotStride
+ *     The number of bytes in each slot, i * slotStride gives the offset from the
+ *     base of the pool to a given slot
+ */
+#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID (0x1FU)
+
+typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS {
+    NvU32 maxSlots;
+    NvU32 slotStride;
+    NV_DECLARE_ALIGNED(NvU64 ctrlStructSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 ctrlStructAlign, 8);
+    NV_DECLARE_ALIGNED(NvU64 poolSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 poolAlign, 8);
+} NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE
+ *
+ * This API takes a CPU pointer to a GFxP Pool Control Structure and does the
+ * required onetime initialization.  It should be called once and only once
+ * before a pool is used.  It is only accessible to kernel callers.
+ *
+ * NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS
+ *   struct to hand in the required info to RM
+ *
+ *   maxSlots
+ *      Max pool slots
+ *   hMemory
+ *      Handle to GFX Pool memory
+ *   offset
+ *      Offset of the control structure in GFX Pool memory
+ *   size
+ *      Size of the control structure
+ */
+#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS {
+    NvU32    maxSlots;
+    NvHandle hMemory;
+    NvU32    offset;
+    NvU32    size;
+} NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS;
+
+#define NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS     64U
+
+/*
+ * NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS
+ *
+ * This API adds a list of buffer slots to a given control structure.  It can
+ * only be called when no channel using the given pool is running or may become
+ * running for the duration of this call.  If more slots are added than there
+ * is room for in the control structure the behavior is undefined. It is only
+ * accessible to kernel callers.
+ *
+ * NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS
+ *
+ *   numSlots
+ *     This input indicates how many slots are being added and are contained in the slots parameter
+ *   slots
+ *     This input contains an array of the slots to be added to the control structure
+ *   hMemory
+ *      Handle to GFX Pool memory
+ *   offset
+ *      Offset of the control structure in GFX Pool memory
+ *   size
+ *      Size of the control structure
+ */
+#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
+    NvU32    numSlots;
+    NvU32    slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
+    NvHandle hMemory;
+    NvU32    offset;
+    NvU32    size;
+} NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS
+ *
+ * This API removes buffer slots from a given control structure.  It can
+ * only be called when no channel using the given pool is running or may become
+ * running for the duration of this call. It can operate in two modes, either
+ * it will a specified number of slots, or a specified list of slots.
+ *
+ * It is only accessible to kernel callers.
+ *
+ * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS_PARAMS
+ *
+ *   numSlots
+ *     This input indicates how many slots are being removed.  if
+ *     bRemoveSpecificSlots is true, then it also indicates how many entries in
+ *     the slots array are populated.
+ *   slots
+ *     This array is either an input or output.  If bRemoveSpecificSlots is true,
+ *     then this will contain the list of slots to remove.  If it is false, then
+ *     it will be populated by RM with the indexes of the slots that were
+ *     removed.
+ *   bRemoveSpecificSlots
+ *     This input determines which mode the call will run in.  If true the caller
+ *     will specify the list of slots they want removed, if any of those slots
+ *     are not on the freelist, the call will fail.  If false they only specify
+ *     the number of slots they want removed and RM will pick up to that
+ *     many.  If there are not enough slots on the freelist to remove the
+ *     requested amount, RM will return the number it was able to remove.
+ *   hMemory
+ *      Handle to GFX Pool memory
+ *   offset
+ *      Offset of the control structure in GFX Pool memory
+ *   size
+ *      Size of the control structure
+ */
+#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID (0x22U)
+
+typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS {
+    NvU32    numSlots;
+    NvU32    slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
+    NvBool   bRemoveSpecificSlots;
+    NvHandle hMemory;
+    NvU32    offset;
+    NvU32    size;
+} NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS;
+
+
+
+#define NV2080_CTRL_CMD_GR_GET_CAPS_V2 (0x20801227U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x27U)
+
+typedef NV0080_CTRL_GR_GET_CAPS_V2_PARAMS NV2080_CTRL_GR_GET_CAPS_V2_PARAMS;
+
+#define NV2080_CTRL_CMD_GR_GET_INFO_V2 (0x20801228U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x28U)
+
+typedef NV0080_CTRL_GR_GET_INFO_V2_PARAMS NV2080_CTRL_GR_GET_INFO_V2_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_GPC_MASK
+ *
+ * This command returns a mask of enabled GPCs for the associated subdevice.
+ *
+ *    grRouteInfo[IN]
+ *      This parameter specifies the routing information used to
+ *      disambiguate the target GR engine.
+ *
+ *    gpcMask[OUT]
+ *      This parameter returns a mask of enabled GPCs. Each GPC has an ID
+ *      that's equivalent to the corresponding bit position in the mask.
+ */
+#define NV2080_CTRL_CMD_GR_GET_GPC_MASK (0x2080122aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID (0x2AU)
+
+typedef struct NV2080_CTRL_GR_GET_GPC_MASK_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32 gpcMask;
+} NV2080_CTRL_GR_GET_GPC_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_TPC_MASK
+ *
+ * This command returns a mask of enabled TPCs for a specified GPC.
+ *
+ *    grRouteInfo[IN]
+ *      This parameter specifies the routing information used to
+ *      disambiguate the target GR engine.
+ *
+ *    gpcId[IN]
+ *      This parameter specifies the GPC for which TPC information is
+ *      to be retrieved. If the GPC with this ID is not enabled this command
+ *      will return an tpcMask value of zero.
+ *
+ *    tpcMask[OUT]
+ *      This parameter returns a mask of enabled TPCs for the specified GPC.
+ *      Each TPC has an ID that's equivalent to the corresponding bit
+ *      position in the mask.
+ */
+#define NV2080_CTRL_CMD_GR_GET_TPC_MASK (0x2080122bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID (0x2BU)
+
+typedef struct NV2080_CTRL_GR_GET_TPC_MASK_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32 gpcId;
+    NvU32 tpcMask;
+} NV2080_CTRL_GR_GET_TPC_MASK_PARAMS;
+
+#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x2CU)
+
+typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES
+ *
+ * This command is used to provide the caller with the alignment and size
+ * of the context save region for an engine
+ *
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ *   engineId
+ *     This parameter is an input parameter specifying the engineId for which
+ *     the alignment/size is requested.
+ *   alignment
+ *     This parameter is an output parameter which will be filled in with the
+ *     minimum alignment requirement.
+ *   size
+ *     This parameter is an output parameter which will be filled in with the
+ *     minimum size of the context save region for the engine.
+ *   bInfoPopulated
+ *     This parameter will be set if alignment and size are already set with
+ *     valid values from a previous call.
+ */
+
+#define NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES (0x2080122dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x2DU)
+
+typedef struct NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32  engineId;
+    NvU32  alignment;
+    NvU32  size;
+    NvBool bInfoPopulated;
+} NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER
+ *
+ * This command provides an interface to retrieve the speed select values of
+ * various instruction types.
+ *
+ *    grRouteInfo[IN]
+ *      This parameter specifies the routing information used to
+ *      disambiguate the target GR engine.
+ *
+ *    imla0[OUT]
+ *       The current speed select for IMLA0.
+ *
+ *    fmla16[OUT]
+ *       The current speed select for FMLA16.
+ *
+ *    dp[OUT]
+ *       The current speed select for DP.
+ *
+ *    fmla32[OUT]
+ *       The current speed select for FMLA32.
+ *
+ *    ffma[OUT]
+ *       The current speed select for FFMA.
+ *
+ *    imla1[OUT]
+ *       The current speed select for IMLA1.
+ *
+ *    imla2[OUT]
+ *       The current speed select for IMLA2.
+ *
+ *    imla3[OUT]
+ *       The current speed select for IMLA3.
+ *
+ *    imla4[OUT]
+ *       The current speed select for IMLA4.
+ */
+#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER                       (0x20801230U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED          (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2   (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4   (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8   (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16  (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32  (0x5U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64  (0x6U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED         (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2  (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4  (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8  (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 (0x5U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED             (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED          (0x1U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED         (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2  (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4  (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8  (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 (0x5U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED           (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2    (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4    (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8    (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16   (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32   (0x5U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED          (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2   (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4   (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8   (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16  (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32  (0x5U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64  (0x6U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED          (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2   (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4   (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8   (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16  (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32  (0x5U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64  (0x6U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED          (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2   (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4   (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8   (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16  (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32  (0x5U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64  (0x6U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED          (0x0U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2   (0x1U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4   (0x2U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8   (0x3U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16  (0x4U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32  (0x5U)
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64  (0x6U)
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x30U)
+
+typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU8 imla0;
+    NvU8 fmla16;
+    NvU8 dp;
+    NvU8 fmla32;
+    NvU8 ffma;
+    NvU8 imla1;
+    NvU8 imla2;
+    NvU8 imla3;
+    NvU8 imla4;
+} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
+
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE (0xFFU)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA16        (0x0U)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DP            (0x1U)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA32        (0x2U)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FFMA          (0x3U)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA0         (0x4U)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA1         (0x5U)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA2         (0x6U)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA3         (0x7U)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA4         (0x8U)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP16          (0x9U)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP32          (0xAU)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DFMA          (0xBU)
+#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DMLA          (0xCU)
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2
+ *
+ * This command provides an interface to retrieve the speed select values of
+ * various instruction types.
+ *
+ *   smIssueRateModifierListSize
+ *     This field specifies the number of entries on the caller's
+ *     smIssueRateModifierList.
+ *     When caller passes smIssueRateModifierListSize = 0, all fuse
+ *     values are returned.
+ *   smIssueRateModifierList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the speed select values are to be returned.
+ */
+#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2       (0x2080123cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID" */
+
+typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2;
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x3CU)
+
+typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS {
+    NvU32                                    smIssueRateModifierListSize;
+    NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE];
+} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
+
+#define NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE (0xFFU)
+#define NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MASK          (0x0U)
+#define NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_CREDIT        (0x1U)
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_SM_ISSUE_THROTTLE_CTRL
+ *
+ * This command provides an interface to retrieve the throttle contol values of
+ * various instruction types for a GR engine.
+ *
+ *   smIssueThrottleCtrlListSize
+ *     This field specifies the number of entries on the caller's
+ *     smIssueThrottleCtrlList.
+ *     When caller passes smIssueThrottleCtrlListSize = 0, all fuse
+ *     values are returned.
+ *   smIssueThrottleCtrlList
+ *     This field specifies a pointer in the caller's address space
+ *     to the buffer into which the throttle control values are to be returned.
+ */
+#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_THROTTLE_CTRL       (0x2080123dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID" */
+
+typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL;
+
+#define NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID (0x3DU)
+
+typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS {
+    NvU32                                 smIssueThrottleCtrlListSize;
+    NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL smIssueThrottleCtrlList[NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE];
+} NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID
+ *
+ * *DEPRECATED* Use NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 instead
+ *
+ * This command is used to create a FECS bind-point to an event buffer that
+ * is filtered by UID.
+ *
+ *  hEventBuffer[IN]
+ *      The event buffer to bind to
+ *
+ *  recordSize[IN]
+ *      The size of the FECS record in bytes
+ *
+ *  levelOfDetail[IN]
+ *      One of NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_:
+ *          FULL: Report all CtxSw events
+ *          SIMPLE: Report ACTIVE_REGION_START and ACTIVE_REGION_END only
+ *          COMPAT: Events that KMD is interested in (for backwards compatibility)
+ *          CUSTOM: Report events in the eventFilter field
+ *      NOTE: RM may override the level-of-detail depending on the caller
+ *
+ *  eventFilter[IN]
+ *      Bitmask of events to report if levelOfDetail is CUSTOM
+ *
+ *  bAllUsers[IN]
+ *     Only report FECS CtxSw data for the current user if false, for all users if true
+ */
+
+#define NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID (0x20801231U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD {
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL = 0,
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE = 1,
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT = 2,
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM = 3,
+} NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD;
+
+#define NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID (0x31U)
+
+typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS {
+    NvHandle                            hEventBuffer;
+    NvU32                               recordSize;
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail;
+    NvU32                               eventFilter;
+    NvBool                              bAllUsers;
+} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK
+ *
+ * This command returns a mask of physical GPC Ids for the associated syspipe
+ *
+ *    physSyspipeId[IN]
+ *      This parameter specifies syspipe for which phys GPC mask is requested
+ *
+ *    gpcMask[OUT]
+ *      This parameter returns a mask of mapped GPCs to provided syspipe.
+ *      Each GPC-ID has a corresponding bit position in the mask.
+ */
+#define NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK (0x20801232U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID (0x32U)
+
+typedef struct NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS {
+    NvU32 physSyspipeId;
+    NvU32 gpcMask;
+} NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_PPC_MASK
+ *
+ * This command returns a mask of enabled PPCs for a specified GPC.
+ *
+ *    grRouteInfo[IN]
+ *      This parameter specifies the routing information used to
+ *      disambiguate the target GR engine.
+ *
+ *    gpcId[IN]
+ *      This parameter specifies the GPC for which TPC information is
+ *      to be retrieved. If the GPC with this ID is not enabled this command
+ *      will return an ppcMask value of zero.
+ *
+ *    ppcMask[OUT]
+ *      This parameter returns a mask of enabled PPCs for the specified GPC.
+ *      Each PPC has an ID that's equivalent to the corresponding bit
+ *      position in the mask.
+ */
+#define NV2080_CTRL_CMD_GR_GET_PPC_MASK (0x20801233U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID (0x33U)
+
+typedef struct NV2080_CTRL_GR_GET_PPC_MASK_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32 gpcId;
+    NvU32 ppcMask;
+} NV2080_CTRL_GR_GET_PPC_MASK_PARAMS;
+
+#define NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC (0x20801234U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID (0x34U)
+
+typedef struct NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS {
+    NvU32 gpcId;
+    NvU32 numTpcs;
+} NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_CTXSW_MODES
+ *
+ * This command is used to get context switch modes for the specified
+ * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the
+ * target channel does not support context switch mode changes.
+ *
+ *   hChannel
+ *     This parameter specifies the channel handle of
+ *     the channel that is to have its context switch modes retrieved.
+ *   zcullMode
+ *     See NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE for possible return values
+ *   pmMode
+ *     See NV2080_CTRL_CMD_GR_CTXSW_PM_MODE for possible return values
+ *   smpcMode
+ *     See NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE for possible return values
+ *   cilpPreemptMode
+ *     See NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE for possible return values
+ *   gfxpPreemptMode
+ *     See NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE for possible return values
+ */
+#define NV2080_CTRL_CMD_GR_GET_CTXSW_MODES (0x20801235U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x35U)
+
+typedef struct NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS {
+    NvHandle hChannel;
+    NvU32    zcullMode;
+    NvU32    pmMode;
+    NvU32    smpcMode;
+    NvU32    cilpPreemptMode;
+    NvU32    gfxpPreemptMode;
+} NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP
+ *
+ * Get a list of values used to describe GPC/TPC tile mapping tables.
+ *
+ *   mapValueCount
+ *     This field specifies the number of actual map entries.  This count
+ *     should equal the number of TPCs in the system.
+ *   mapValues
+ *     This field is a pointer to a buffer of NvU08 values representing map
+ *     data.
+ *   grRouteInfo
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0x36U)
+
+typedef NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK
+ *
+ * This command returns a mask of enabled ZCULLs for a specified GPC.
+ *
+ *    gpcId[IN]
+ *      This parameter, physical GPC index, specifies the GPC for which ZCULL
+ *      information is to be retrieved. If the GPC with this ID is not enabled
+ *      this command will return a zcullMask value of zero.
+ *
+ *    zcullMask[OUT]
+ *      This parameter returns a mask of enabled ZCULLs for the specified GPC.
+ *      Each ZCULL has an ID that's equivalent to the corresponding bit
+ *      position in the mask.
+ */
+
+#define NV2080_CTRL_CMD_GR_GET_ZCULL_MASK (0x20801237U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID (0x37U)
+
+typedef struct NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS {
+    NvU32 gpcId;
+    NvU32 zcullMask;
+} NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2
+ *
+ * This command is used to create a FECS bind-point to an event buffer that
+ * is filtered by UID.
+ *
+ *  hEventBuffer[IN]
+ *      The event buffer to bind to
+ *
+ *  recordSize[IN]
+ *      The size of the FECS record in bytes
+ *
+ *  levelOfDetail[IN]
+ *      One of NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_:
+ *          FULL: Report all CtxSw events
+ *          SIMPLE: Report ACTIVE_REGION_START and ACTIVE_REGION_END only
+ *          COMPAT: Events that KMD is interested in (for backwards compatibility)
+ *          CUSTOM: Report events in the eventFilter field
+ *      NOTE: RM may override the level-of-detail depending on the caller
+ *
+ *  eventFilter[IN]
+ *      Bitmask of events to report if levelOfDetail is CUSTOM
+ *
+ *  bAllUsers[IN]
+ *     Only report FECS CtxSw data for the current user if false, for all users if true
+ *
+ *  reasonCode [OUT]
+ *     Reason for failure
+ */
+#define NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 (0x20801238U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE {
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE = 0,
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD = 1,
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU = 2,
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED = 3,
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN = 4,
+    NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY = 5,
+} NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE;
+
+#define NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID (0x38U)
+
+typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS {
+    NvHandle                            hEventBuffer;
+    NvU32                               recordSize;
+    NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail;
+    NvU32                               eventFilter;
+    NvBool                              bAllUsers;
+    NvU32                               reasonCode;
+} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO
+ *
+ * This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine
+ *
+ *  grRouteInfo[IN]
+ *      This parameter specifies the routing information used to
+ *      disambiguate the target GR engine.
+ *
+ *  physGfxGpcMask [OUT]
+ *     Physical mask of Gfx capable GPC's
+ *
+ *  numGfxTpc [OUT]
+ *     Total number of Gfx capable TPC's
+ */
+#define NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO (0x20801239U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID (0x39U)
+
+typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32 physGfxGpcMask;
+    NvU32 numGfxTpc;
+} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK
+ *
+ * This command returns the TPC reconfig mask for a specific GPC
+ *
+ *  gpc[IN]
+ *      The GPC for which the TPC reconfig mask needs to be queried.
+ *      The GPC should be specified as a logical index.
+ *
+ *  tpcReconfigMask[OUT]
+ *     Mask of reconfigurable TPCs in the specified GPC
+ *
+ *  grRouteInfo[IN]
+ *     This parameter specifies the routing information used to
+ *     disambiguate the target GR engine.
+ */
+#define NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK (0x2080123bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID (0x3bU)
+
+typedef struct NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS {
+    NvU32 gpc;
+    NvU32 tpcReconfigMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+} NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GR_TEST_CTXSW_ERROR_LOGS
+ *
+ * This command provides an interface to test CTXSW print logs from
+ * the context switch microcode. This is test only interface.
+ *
+ *    expectedCharCount[IN]
+ *      This parameter specifies the number of characters to retrieve
+ *      and print.
+ *    bUseInterrupt[IN]
+ *      This flag is used to indicate if an interrupt is to be issued prior to 
+ *      ctxsw ucode dumping its prints to the buffer. 
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GR_TEST_CTXSW_ERROR_LOGS (0x2080123eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS_MESSAGE_ID (0x3EU)
+
+typedef struct NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS {
+    NvU32  expectedCharCount;
+    NvBool bUseInterrupt;
+} NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS;
+
+/* _ctrl2080gr_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080grmgr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080grmgr.h
new file mode 100644
index 0000000..8d41d3a
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080grmgr.h
@@ -0,0 +1,299 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080grmgr.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX grmgr control commands and parameters */
+
+//
+// NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO
+//
+// This control call works as a batched query interface where we
+// have multiple different queries that can be passed in
+// and RM will return the associated data and status type
+// If there is any error in NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS,
+// we will immediately fail the call.
+// However, if there is an error in the query-specific calls, we will
+// log the error and march on.
+//
+// NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS
+//  numQueries[in]
+//      - Specifies the number of valid queries that the caller will be passing in
+//
+// Possible status values returned are:
+//   NV_OK
+//   NV_ERR_INVALID_ARGUMENT
+//   NV_ERR_INVALID_STATE
+//
+#define NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO        (0x20803801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID << 8) | NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID" */
+
+// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES    96
+
+//
+// Preference is to keep max.size of union at 24 bytes (i.e. 6 32-bit members)
+// so that the size of entire query struct is maintained at 32 bytes, to ensure
+// that overall params struct does not exceed 4kB
+//
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE 32
+#define NV2080_CTRL_GRMGR_MAX_SMC_IDS               8
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS
+ *  gpcCount[out]
+ *      - No. of logical/local GPCs which client can use to create the
+ *        logical/local mask respectively
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS {
+    NvU32 gpcCount;         // param[out] - logical/local GPC mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS
+ *  gpcId[in]
+ *      - Logical/local GPC ID
+ *  chipletGpcMap[out]
+ *      - Returns chiplet GPC ID for legacy case and device monitoring client
+ *      - Returns local GPC ID (== input gpcId) for SMC client
+ *      - Does not support DM attribution case
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS {
+    NvU32 gpcId;            // param[in] - logical/local GPC ID
+    NvU32 chipletGpcMap;    // param[out] - chiplet GPC ID
+} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS
+ *  gpcId[in]
+ *      - Logical/local GPC ID
+ *  tpcMask[out]
+ *      - Returns physical TPC mask for legacy, DM client and SMC cases
+ *      - Does not support DM attribution case
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS {
+    NvU32 gpcId;            // param[in] - logical/local GPC ID
+    NvU32 tpcMask;          // param[out] - physical TPC mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS
+ *  gpcId[in]
+ *      - Logical/local GPC ID
+ *  ppcMask[out]
+ *      - Returns physical PPC mask for legacy, DM client and SMC cases
+ *      - Does not support DM attribution case
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS {
+    NvU32 gpcId;            // param[in] - logical/local GPC ID
+    NvU32 ppcMask;          // param[out] - physical PPC mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS;
+
+/*!
+ *  !!! DEPRECATED - This query will return NV_ERR_NOT_SUPPORTED since deleting
+ *               it would break driver compatibility !!!
+ *
+ *  NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS
+ *  swizzId[in]
+ *      - Swizz ID of partition
+ *      - A DM client with an invalid swizz ID, will fail this call
+ *      - This parameter is not compulsory for an SMC client; the subscription
+ *        itself will do the necessary validation.
+ *  gpcId[in]
+ *      - Logical/local GPC ID
+ *  chipletGpcMap[out]
+ *      - Returns chiplet GPC ID for legacy case and device monitoring client
+ *      - Returns local GPC ID (== input gpcId) for SMC client
+ *      - Does not support non-attribution case for DM client
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS {
+    NvU32 swizzId;          // param[in]  - swizz ID of partition
+    NvU32 gpcId;            // param[in]  - logical/local GPC ID
+    NvU32 chipletGpcMap;    // param[out] - chiplet GPC ID
+} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS
+ *  gpcId[in]
+ *      - Logical/local GPC ID
+ *  ropMask[out]
+ *      - Returns physical ROP mask for legacy, DM client
+ *      - Returns logical ROP mask for SMC
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS {
+    NvU32 gpcId;            // param[in] - logical/local GPC ID
+    NvU32 ropMask;          // param[out] - physical ROP mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS;
+
+/*!
+ *  NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS
+ *  chipletSyspipeMask [out]
+ *      - Mask of chiplet SMC-IDs for DM client attribution case
+ *      - Mask of local SMC-IDs for SMC client
+ *      - Legacy case returns 1 GR
+ *      - Does not support attribution case for DM client
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS {
+    NvU32 chipletSyspipeMask;   // param[out] - Mask of chiplet SMC IDs
+} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS;
+
+/*!
+ *  NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS
+ *  swizzId[in]
+ *      - Swizz ID of partition
+ *      - A DM client with an invalid swizz ID, will fail this call
+ *  physSyspipeId[GRMGR_MAX_SMC_IDS] [out]
+ *      - Physical SMC-IDs mapped to partition local idx for DM client attribution case
+ *      - Does not support non-attribution case for DM client, SMC clients, legacy case
+ *  physSyspipeIdCount[out]
+ *      - Valid count of physSmcIds which has been populated in above array.
+ *      - Failure case will return 0
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS {
+    NvU16 swizzId;                                          // param[in]  - swizz ID of partition
+    NvU16 physSyspipeIdCount;                               // param[out] - Count of physSmcIds in above array
+    NvU8  physSyspipeId[NV2080_CTRL_GRMGR_MAX_SMC_IDS];      // param[out] - physical/local SMC IDs
+} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS
+ * swizzId[in]
+ *      - Swizz ID of partition
+ *      - Mandatory parameter
+ *      - A DM client with an invalid swizz ID, will fail this call
+ * grIdx[in]
+ *      - Local grIdx for a partition
+ *      - Mandatory parameter
+ * gpcEnMask[out]
+ *      - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask
+ *      - These Ids should be used as input further
+ *      - Does not support non-attribution case for DM client, SMC clients, legacy case
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS {
+    NvU32 swizzId;      // param[in]  - swizz ID of partition
+    NvU32 grIdx;        // param[in]  - partition local GR ID
+    NvU32 gpcEnMask;    // param[out] - logical enabled GPC mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID
+ * syspipeId[out]
+ *      - Partition-local GR idx for client subscribed to exec partition
+ *      - Does not support legacy case, DM client, or SMC client subscribed only to partition
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS {
+    NvU32 syspipeId;    // param[out] - partition-local Gr idx
+} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS;
+
+/*!
+ *  NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS
+ *  chipletSyspipeMask [out]
+ *      - Mask of chiplet GFX capable SMC-IDs for DM client attribution case
+ *      - Mask of local GFX capable SMC-IDs for SMC client
+ *      - Legacy case returns GR0 if GFX capable, else 0
+ *      - Does not support attribution case for DM client
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS {
+    NvU32 chipletSyspipeMask;   // param[out] - Mask of chiplet SMC IDs
+} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS;
+
+/*!
+ * NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS
+ * swizzId[in]
+ *      - Swizz ID of partition
+ *      - Mandatory parameter
+ *      - A DM client with an invalid swizz ID, will fail this call
+ * grIdx[in]
+ *      - Local grIdx for a partition
+ *      - Mandatory parameter
+ * gpcEnMask[out]
+ *      - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask
+ *      - These Ids should be used as input further
+ *      - Does not support non-attribution case for DM client, SMC clients, legacy case
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS {
+    NvU32 swizzId;      // param[in]  - swizz ID of partition
+    NvU32 grIdx;      // param[in]  - partition local GR ID
+    NvU32 gpcEnMask;      // param[out] - logical enabled GPC mask
+} NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS;
+
+/*!
+ * queryType[in]
+ *  - Use queryType defines to specify what information is being requested
+ * status[out]
+ *  - Possible status values returned are:
+ *      NV_OK
+ *      NV_ERR_INVALID_ARGUMENT
+ *      NV_ERR_INVALID_STATE
+ */
+typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS {
+    NvU16 queryType;
+    NvU8  reserved[2]; // To keep the struct aligned for now and available for future use (if needed)
+    NvU32 status;
+    union {
+        NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS                     gpcCountData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS               chipletGpcMapData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS                      tpcMaskData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS                      ppcMaskData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS     partitionGpcMapData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS          syspipeMaskData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS partitionChipletSyspipeData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS         dmGpcMaskData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS          partitionSyspipeIdData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS                      ropMaskData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS gfxSyspipeMaskData;
+        NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS          gfxGpcMaskData;
+    } queryData;
+} NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS;
+
+#define NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS {
+    NvU16                                     numQueries;
+    NvU8                                      reserved[6]; // To keep the struct aligned for now and available for future use (if needed)
+    NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS queries[NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES];
+} NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS;
+
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID                       0
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT                     1
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP               2
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK                      3
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK                      4
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP     5   /* deprecated */
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK          6
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS 7
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK         8
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID          9
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK                      10
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GRAPHICS_SYSPIPE_MASK 11
+#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GFX_CAPABLE_GPC_MASK          12
+
+/* _ctrl2080grmgr_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gsp.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gsp.h
new file mode 100644
index 0000000..404c988
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gsp.h
@@ -0,0 +1,273 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080gsp.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX GSP control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_GSP_GET_FEATURES
+ *
+ * This command is used to determine which GSP features are
+ * supported on this GPU.
+ *
+ *   gspFeatures
+ *     Bit mask that specifies GSP features supported.
+ *   bValid
+ *     If this field is set to NV_TRUE, then above bit mask is
+ *     considered valid. Otherwise, bit mask should be ignored
+ *     as invalid. bValid will be set to NV_TRUE when RM is a
+ *     GSP client with GPU support offloaded to GSP firmware.
+ *   bDefaultGspRmGpu
+ *     If this field is set to NV_TRUE, it indicates that the
+ *     underlying GPU has GSP-RM enabled by default. If set to NV_FALSE,
+ *     it indicates that the GPU has GSP-RM disabled by default.
+ *   firmwareVersion
+ *     This field contains the buffer into which the firmware build version
+ *     should be returned, if GPU is offloaded. Otherwise, the buffer
+ *     will remain untouched.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_GSP_GET_FEATURES    (0x20803601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_GSP_MAX_BUILD_VERSION_LENGTH (0x0000040)
+
+#define NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
+    NvU32  gspFeatures;
+    NvBool bValid;
+    NvBool bDefaultGspRmGpu;
+    NvU8   firmwareVersion[NV2080_GSP_MAX_BUILD_VERSION_LENGTH];
+} NV2080_CTRL_GSP_GET_FEATURES_PARAMS;
+
+/* Valid feature values */
+#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0
+#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE                      (0x00000000)
+#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE                       (0x00000001)
+#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED 1:1
+#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE (0x00000000)
+#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE  (0x00000001)
+
+/*
+ * NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS
+ *
+ * This command reports the current GSP-RM heap usage statistics.
+ *
+ *  gfid
+ *    The gfid that's under query: When gfid = 0, it will report the stats of PF.
+ *    Otherwise, it will report stats for RM task's memory consumption associated
+ *    with a given gfid.
+ *  managedSize
+ *    The total size in bytes of the underlying heap. Note that not all memory
+ *    will be allocatable, due to fragmentation and memory allocator/tracking
+ *    overhead.
+ *  current
+ *    An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to
+ *    GSP-RM heap usage at the time this command is called.
+ *  peak
+ *    An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to
+ *    the "high water mark" of heap usage since GSP-RM was started.
+ */
+#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS                               (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT
+ *
+ * This record represents a set of heap measurements at a given point in time.
+ *
+ *  allocatedSize
+ *    Allocated memory size, in bytes. This value does not include overhead used
+ *    by the underlying allocator for padding/metadata, but does include the
+ *    NvPort memory tracking overhead.
+ *  usableSize
+ *    Allocated memory size excluding all metadata, in bytes. This value does
+ *    not include the NvPort memory tracking overhead.
+ *  memTrackOverhead
+ *    Allocated memory size used for NvPort memory tracking.
+ */
+typedef struct NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT {
+    NV_DECLARE_ALIGNED(NvU64 allocatedSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 usableSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 memTrackOverhead, 8);
+    NvU32 allocationCount;
+} NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT;
+
+#define NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS {
+    NvU32 gfid;
+    NV_DECLARE_ALIGNED(NvU64 managedSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 largestFreeChunkSize, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT current, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT peak, 8);
+} NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS
+ *
+ * This command reports the current partition's VGPU-GSP plugin's heap usage statistics.
+ *
+ *  managedSize
+ *    The total size in bytes of the underlying heap. Note that not all memory
+ *    will be allocatable, due to fragmentation and memory allocator/tracking
+ *    overhead.
+ *  allocatedSize
+ *    Allocated memory size, in bytes. This value does not include overhead used
+ *    by the underlying allocator for padding/metadata.
+ *  allocationCount
+ *    The number of active allocations. This count reflects the current number of
+ *    memory blocks that have been allocated but not yet freed.
+ *  peakAllocatedSize
+ *    The highest recorded allocated memory size, in bytes. This value represents the
+ *    maximum amount of memory that has been allocated at any point in time. When a new
+ *    highest allocated size is recorded, the peakAllocatedSize is updated.
+ *  peakAllocationCount
+ *    The number of active allocations corresponding to the highest recorded peakAllocatedSize.
+ */
+
+#define NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS (0x20803603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 allocatedSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 peakAllocatedSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 managedSize, 8);
+    NvU32 allocationCount;
+    NvU32 peakAllocationCount;
+    NV_DECLARE_ALIGNED(NvU64 largestFreeChunkSize, 8);
+} NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS;
+
+#define NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS (0x20803604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX     64
+
+typedef struct NV2080_CTRL_GSP_LIBOS_POOL_STATS {
+    NvU32 allocations;
+    NvU32 peakAllocations;
+    NV_DECLARE_ALIGNED(NvU64 objectSize, 8);
+} NV2080_CTRL_GSP_LIBOS_POOL_STATS;
+
+
+#define NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_LIBOS_POOL_STATS poolStats[NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX], 8);
+    NV_DECLARE_ALIGNED(NvU64 totalHeapSize, 8);
+    NvU8 poolCount;
+} NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST
+ *
+ * This control spams GDMA requests of random size, location, and source memory.
+ *
+ * iters
+ *     Number of DMA requests to send. Large values should be paired with RmDefaultTimeout
+ *     increase in order to avoid XID 119.
+ *
+ * pSysmemPA
+ *     Internal param
+ *
+ */
+#define NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST (0x20803605) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 iters, 8);
+    NV_DECLARE_ALIGNED(NvU64 pSysmemPA, 8);
+} NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS;
+
+#define NV2080_CTRL_CMD_GSP_CORE_TEST (0x20803606) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_GSP_CORE_TEST_OP {
+    NV2080_CTRL_GSP_CORE_TEST_OP_WRITE_LATENCY = 0,
+    NV2080_CTRL_GSP_CORE_TEST_OP_READ_LATENCY = 1,
+    NV2080_CTRL_GSP_CORE_TEST_OP_WRITE_BLOCK = 2,
+    NV2080_CTRL_GSP_CORE_TEST_OP_READ_BLOCK = 3,
+    NV2080_CTRL_GSP_CORE_TEST_SYSMEM_TO_FB_OP_COPY_NAIVE = 4,
+    NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_COPY_NAIVE = 5,
+    NV2080_CTRL_GSP_CORE_TEST_DMEM_TO_FB_OP_PORT_MEM_COPY = 6,
+    NV2080_CTRL_GSP_CORE_TEST_FB_TO_DMEM_OP_PORT_MEM_COPY = 7,
+    NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_PORT_MEM_COPY = 8,
+    NV2080_CTRL_GSP_CORE_TEST_DMEM_TO_FB_OP_DMA = 9,
+    NV2080_CTRL_GSP_CORE_TEST_FB_TO_DMEM_OP_DMA = 10,
+    NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_DMA = 11,
+    NV2080_CTRL_GSP_CORE_TEST_L1D_INVAL_TIME = 12,
+} NV2080_CTRL_GSP_CORE_TEST_OP;
+
+typedef enum NV2080_CTRL_GSP_CORE_TEST_MEM {
+    NV2080_CTRL_GSP_CORE_TEST_MEM_DMEM = 0,
+    NV2080_CTRL_GSP_CORE_TEST_MEM_FB = 1,
+    NV2080_CTRL_GSP_CORE_TEST_MEM_SYSMEM = 2,
+} NV2080_CTRL_GSP_CORE_TEST_MEM;
+
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L1_LIBOS 0:0
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L1_LIBOS_YES (0x00000001)
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L1_LIBOS_NO  (0x00000000)
+
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_EVICT_L2 1:1
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_EVICT_L2_YES       (0x00000001)
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_EVICT_L2_NO        (0x00000000)
+
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L2 2:2
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L2_YES       (0x00000001)
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L2_NO        (0x00000000)
+
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_UNCACHED 3:3
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_UNCACHED_YES       (0x00000001)
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_UNCACHED_NO        (0x00000000)
+
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_FENCE 4:4
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_FENCE_YES          (0x00000001)
+#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_FENCE_NO           (0x00000000)
+
+#define NV2080_CTRL_GSP_CORE_TEST_SIZE_MAX                 (0x400000)  // 4MiB
+#define NV2080_CTRL_GSP_CORE_TEST_ITERS_MAX                (10000)
+
+#define NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS {
+    NV2080_CTRL_GSP_CORE_TEST_OP  op;
+    NV2080_CTRL_GSP_CORE_TEST_MEM mem;
+    NV_DECLARE_ALIGNED(NvU64 flags, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NV_DECLARE_ALIGNED(NvU64 iters, 8);
+    NV_DECLARE_ALIGNED(NvU64 timeNs, 8);
+    NV_DECLARE_ALIGNED(NvU64 cycles, 8);
+} NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS;
+
+// _ctrl2080gsp_h_
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080hshub.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080hshub.h
new file mode 100644
index 0000000..0160705
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080hshub.h
@@ -0,0 +1,73 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080hshub.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/*
+ * NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK
+ *
+ * This command get active HSHUB masks.
+ *
+ *   hshubNcisocMask
+ *     NCISOC enabled active HSHUBs
+ *   hshubNvlMask
+ *     NVLINK capable active HSHUBs.
+ */
+
+#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS {
+    NvU32 hshubNcisocMask;
+    NvU32 hshubNvlMask;
+} NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS;
+
+#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK (0x20804101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE
+ *
+ * This command sets EC throttle mode registers
+ *
+ *  ecMode
+ *    EC Mode 0-7 to write to mode register
+ *  status
+ *    return status
+ */
+#define NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS {
+    NvU32 ecMode;
+    NvU32 status;
+} NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS;
+
+#define NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE (0x20804102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID" */
+/* _ctrl2080hshub_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080i2c.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080i2c.h
new file mode 100644
index 0000000..99e78c2
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080i2c.h
@@ -0,0 +1,372 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080i2c.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX i2c-related control commands and parameters */
+
+/*
+ * NV2080_CTRL_I2C_VERSION
+ *   
+ *   NV2080_CTRL_I2C_VERSION_0_0: 
+ *       This return state specifies that support is only available 
+ *       for single subAddr reads.
+ *
+ */
+#define NV2080_CTRL_I2C_VERSION_0                         0x00
+
+/* maximum number of i2c entries support */
+#define NV2080_CTRL_I2C_MAX_ENTRIES                       256
+#define NV2080_CTRL_I2C_MAX_REG_LEN                       8
+#define NV2080_CTRL_I2C_MAX_ADDR_ENTRIES                  20
+
+/*
+ * NV2080_CTRL_I2C_FLAGS
+ *
+ *   NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: 
+ *       This option specified that non-compliant i2c for SI1930UC is required
+ *
+ *   NV2080_CTRL_I2C_FLAGS_PRIVILEGE
+ *       This option specified that the i2c access is privileged
+ *
+ *   NV2080_CTRL_I2C_FLAGS_PX3540
+ *       This option specified that the i2c device -PX3540/3544- is accessed
+ */
+#define NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC             (0x00000001)
+#define NV2080_CTRL_I2C_FLAGS_PRIVILEGE                   (0x00000002)
+#define NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED              (0x00000004)
+#define NV2080_CTRL_I2C_FLAGS_PX3540                      (0x00000010)
+#define NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED (0x00000008)
+
+/*
+ * NV2080_CTRL_CMD_I2C_READ_BUFFER
+ *
+ * This command allocates video memory for a particular subset of microcode.
+ *
+ *   version
+ *       This field is returned to the client and indicates the current
+ *       supported I2C controls available.  
+ *
+ *   port
+ *       This field must be specified by the client to indicate which port/bus
+ *       in which i2c access is desired.
+ *
+ *   flags
+ *       This field is specified by the client to request additional options
+ *       as provided by NV2080_CTRL_I2C_FLAGS.
+ *
+ *   inputCount
+ *       This field specifies the total # of elements contained in inputBuffer
+ *
+ *   inputBuffer
+ *       This should contain the chipaddr as the first element, followed by
+ *       the each subAddress in which to access the first element of data
+ *       Eg. <chipAddr> <subAddr1> ... <subAddrX> 
+ *       In general, client will only have 2 elements <chipAddr> <subAddr>
+ *
+ *   outputCount
+ *       This field specifies how many registers from the start register index.
+ *       The maximum values allow are NV2080_CTRL_I2C_MAX_ENTRIES.
+ *
+ *   outputBuffer
+ *       This buffer is returned to the client with the data read from
+ *       the start register index.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_NOT_SUPPORTED
+ *
+ */
+#define NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_I2C_READ_BUFFER_PARAMS {
+    NvU32 version;
+    NvU32 port;
+    NvU32 flags;
+    NvU32 inputCount;
+    // C form: NvU8    inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+    NvU8  inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+    NvU32 outputCount;
+    // C form: NvU8    outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+    NvU8  outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+} NV2080_CTRL_I2C_READ_BUFFER_PARAMS;
+
+#define NV2080_CTRL_CMD_I2C_READ_BUFFER (0x20800601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_I2C_WRITE_BUFFER
+ *
+ * This command allocates video memory for a particular subset of microcode.
+ *
+ *   version
+ *       This field is returned to the client and indicates the current
+ *       supported I2C controls available.  
+ *
+ *   port
+ *       This field must be specified by the client to indicate which port/bus
+ *       in which i2c access is desired.
+ *
+ *   flags
+ *       This field is specified by the client to request additional options.
+ *       NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: 
+ *       - Specifies that non-compliant i2c access for SI1930UC is required
+ *
+ *   inputCount
+ *       This field specifies the total # of elements contained in inputBuffer
+ *
+ *   inputBuffer
+ *       This should contain the chipaddr as the first element, followed by
+ *       the each subAddress in which to access the first element of data,
+ *       and finally the data to be programmed.
+ *       Eg. <chipAddr> <subAddr1> ... <subAddrX> <data1> ... <dataX>
+ *       In general, client will have 2 elements + data to be programmed.
+ *       <chipAddr> <subAddr> <data1> ... <dataX>
+ *
+ *   encrClientID
+ *      This field is specified by client, which is used to uniquely access
+ *      the client's encryption context
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_STATE
+ *
+ */
+
+#define NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS {
+    NvU32 version;
+    NvU32 port;
+    NvU32 flags;
+    NvU32 inputCount;
+    // C form: NvU8    inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+    NvU8  inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
+    NvU32 encrClientID;
+} NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS;
+
+#define NV2080_CTRL_CMD_I2C_WRITE_BUFFER (0x20800602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID" */
+
+
+/*
+ * NV2080_CTRL_CMD_I2C_READ_REG
+ *
+ * This command allocates video memory for a particular subset of microcode.
+ *
+ *   version
+ *       This field is returned to the client and indicates the current
+ *       supported I2C controls available.  
+ *
+ *   port
+ *       This field must be specified by the client to indicate which port/bus
+ *       in which i2c access is desired.
+ *
+ *   flags
+ *       This field is specified by the client to request additional options.
+ *       NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: 
+ *       - Specifies that non-compliant i2c access for SI1930UC is required
+ *   addr
+ *       This field is specified by the client to target address.
+ *   reg
+ *       This field is specified by the client to target register address.
+ *
+ *   bufsize
+ *       This field specifies the total bytes # of register size
+ *
+ *   buffer
+ *       when used for read, it used as buffer that store returned register content
+ *       when used for write, It include data that will be written.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_STATE
+ *
+ */
+typedef struct NV2080_CTRL_I2C_RW_REG_PARAMS {
+    NvU32 version;
+    NvU32 port;
+    NvU32 flags;
+    NvU32 addr;
+    NvU8  reg;
+    NvU8  bufsize;
+    // C form: NvU8    buffer[NV2080_CTRL_I2C_MAX_ENTRIES - 1];
+    NvU8  buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)];
+} NV2080_CTRL_I2C_RW_REG_PARAMS;
+
+#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID" */
+
+// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name
+#define NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID (0x3U)
+
+typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS;
+
+#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID (0x4U)
+
+typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_WRITE_REG_PARAMS;
+
+/*
+ * NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS
+ *
+ * This command allows Clients to read and write data using the I2C ports
+ * 
+ *   token [IN]
+ *      This used in i2cAcquirePort
+ *
+ *   cmd [IN]
+ *      The I2CAccess command
+ *     
+ *   port [IN]
+ *       The port ID of the concerned display
+ *     
+ *   flags [IN]
+ *      The I2CAccess Flags such ack,start,stop
+ *   
+ *   data  [OUT/IN]
+ *      Data that needs to be pass or read out
+ *
+ *   dataBuffSize [IN]
+ *       Size of the data buffer.
+ *   
+ *   speed [IN]
+ *      Speed of transaction.
+ *
+ *   status [OUT]
+ *      The I2CAccess Status returned
+ *
+ *   encrClientID [IN]
+ *      This field is specified by client, which is used to uniquely access
+ *      the client's encryption context
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_I2C_ACCESS_PARAMS {
+    NvU32 token;
+    NvU32 cmd;
+    NvU32 port;
+    NvU32 flags;
+    NV_DECLARE_ALIGNED(NvP64 data, 8);
+    NvU32 status;
+    NvU32 dataBuffSize;
+    NvU32 speed;
+    NvU32 encrClientID;
+} NV2080_CTRL_I2C_ACCESS_PARAMS;
+
+// commands
+#define NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE                   0x1
+#define NV2080_CTRL_I2C_ACCESS_CMD_RELEASE                   0x2
+#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE                0x3
+#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE                 0x4
+#define NV2080_CTRL_I2C_ACCESS_CMD_NULL                      0x5
+#define NV2080_CTRL_I2C_ACCESS_CMD_RESET                     0x6
+#define NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT                 0x11
+#define NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE             0x12
+#define NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE           0x13
+#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER              0x14
+#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER               0x15
+#define NV2080_CTRL_I2C_ACCESS_CMD_START                     0x17
+#define NV2080_CTRL_I2C_ACCESS_CMD_STOP                      0x18
+#define NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE             0x20
+
+// flags
+#define NV2080_CTRL_I2C_ACCESS_FLAG_START                    0x1
+#define NV2080_CTRL_I2C_ACCESS_FLAG_STOP                     0x2
+#define NV2080_CTRL_I2C_ACCESS_FLAG_ACK                      0x4
+#define NV2080_CTRL_I2C_ACCESS_FLAG_RAB                      0x8
+#define NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS              0x10
+#define NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE                0x20
+#define NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED           0x40
+#define NV2080_CTRL_I2C_ACCESS_FLAG_RESTART                  0x80
+#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT       0x100
+#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT          0x200
+#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT          0x400
+#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT        0x800
+#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT           0x1000
+
+// port
+#define NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC                  0x0
+#define NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY                  0x1
+#define NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY                0x2
+#define NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY                 0x3
+#define NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY                0x4
+
+// Alternate numeric port designators
+#define NV2080_CTRL_I2C_ACCESS_PORT_1                        0x1
+#define NV2080_CTRL_I2C_ACCESS_PORT_2                        0x2
+#define NV2080_CTRL_I2C_ACCESS_PORT_3                        0x3
+#define NV2080_CTRL_I2C_ACCESS_PORT_4                        0x4
+#define NV2080_CTRL_I2C_ACCESS_PORT_5                        0x5
+#define NV2080_CTRL_I2C_ACCESS_PORT_6                        0x6
+#define NV2080_CTRL_I2C_ACCESS_PORT_7                        0x7
+#define NV2080_CTRL_I2C_ACCESS_PORT_8                        0x8
+#define NV2080_CTRL_I2C_ACCESS_PORT_9                        0x9
+#define NV2080_CTRL_I2C_ACCESS_PORT_10                       0x10
+
+// Total ports count
+#define NV2080_CTRL_I2C_ACCESS_NUM_PORTS                     NV2080_CTRL_I2C_ACCESS_PORT_10
+
+// status
+#define NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS                0x0
+#define NV2080_CTRL_I2C_ACCESS_STATUS_ERROR                  0x1
+#define NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR         0x2
+#define NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY            0x3
+#define NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND        0x4
+#define NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING 0x5
+
+#define NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE           (0x20800620) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS {
+    NvU32 head;
+    NvU32 authType;
+    NvU32 status;
+} NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS;
+
+/* _ctrl2080i2c_h_ */
+
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080illum.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080illum.h
new file mode 100644
index 0000000..ee2ada8
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080illum.h
@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080illum.finn
+//
+
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080internal.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080internal.h
new file mode 100644
index 0000000..da90d5d
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080internal.h
@@ -0,0 +1,5589 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080internal.finn
+//
+
+#include "nvimpshared.h"
+#include "cc_drv.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+#include "ctrl/ctrl2080/ctrl2080gpu.h"
+#include "ctrl/ctrl2080/ctrl2080gr.h"               /* Some controls derivative of 2080gr */
+#include "ctrl/ctrl0080/ctrl0080nvenc.h"            /* NV0080_CTRL_NVENC_CAPS_TBL_SIZE    */
+#include "ctrl/ctrl0080/ctrl0080nvdec.h"            /* NV0080_CTRL_NVDEC_CAPS_TBL_SIZE      */
+#include "ctrl/ctrl2080/ctrl2080fifo.h"             /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */
+#include "ctrl/ctrl2080/ctrl2080mc.h"               /* NV2080_INTR_* */
+#include "ctrl/ctrl0073/ctrl0073system.h"           /* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS */
+#include "ctrl/ctrl0000/ctrl0000system.h"
+#include "ctrl/ctrl2080/ctrl2080nvlink_common.h"   /* NV2080_CTRL_NVLINK_LINK_MASK */
+#include "ctrl/ctrl2080/ctrl2080nvlink.h"         /* NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS */
+#include "ctrl/ctrl90f1.h"
+#include "ctrl/ctrl30f1.h"
+#include "nvcfg_sdk.h"
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO
+ *
+ *    This command obtains information from physical RM for use by CPU-RM.
+ *
+ *   feHwSysCap
+ *     Display IP v03_00 and later.
+ *     Contents of capability register.
+ *
+ *   windowPresentMask
+ *     Display IP v03_00 and later.
+ *     Mask for the present WINDOWs actually on the current chip.
+ *   numHeads
+ *     Display IP v02_01 and later.
+ *     Provides the number of heads HW support.
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
+    NvU32  feHwSysCap;
+    NvU32  windowPresentMask;
+    NvU32  numHeads;
+    NvU32  i2cPort;
+    NvU32  internalDispActiveMask;
+    NvU32  embeddedDisplayPortMask;
+    NvBool bExternalMuxSupported;
+    NvBool bInternalMuxSupported;
+    NvU32  numDispChannels;
+} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS;
+
+
+
+//
+// MemorySystem settings that are static after GPU state init/load is finished.
+//
+// Fields are shared between the VGPU guest/GSP Client as well as the VGPU
+// host/GSP-RM.
+//
+#define NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID (0x1CU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
+    /*! Determines if RM should use 1 to 1 Comptagline allocation policy */
+    NvBool bOneToOneComptagLineAllocation;
+
+    /*! Determines if RM should use 1 to 4 Comptagline allocation policy */
+    NvBool bUseOneToFourComptagLineAllocation;
+
+    /*! Determines if RM should use raw Comptagline allocation policy */
+    NvBool bUseRawModeComptaglineAllocation;
+
+    /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */
+    NvBool bDisableCompbitBacking;
+
+    /*! Determine if we need to disable post L2 compression */
+    NvBool bDisablePostL2Compression;
+
+    /*! Is ECC DRAM feature supported? */
+    NvBool bEnabledEccFBPA;
+
+    NvBool bL2PreFill;
+
+    /*! L2 cache size */
+    NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8);
+
+    /*! Indicate whether fpba is present or not */
+    NvBool bFbpaPresent;
+
+    /*! Size covered by one comptag */
+    NvU32  comprPageSize;
+
+    /*! log32(comprPageSize) */
+    NvU32  comprPageShift;
+
+    /*! RAM type */
+    NvU32  ramType;
+
+    /*! LTC count */
+    NvU32  ltcCount;
+
+    /*! LTS per LTC count */
+    NvU32  ltsPerLtcCount;
+} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS;
+
+/*!
+ * Retrieve Memory System Static data.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG        (0x20800a1c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_REGISTER_UVM_ACCESS_CNTR_BUFFER
+ *
+ * This command sends access counter buffer pages allocated by CPU-RM
+ * to be setup and enabled in physical RM.
+ *
+ * accessCounterIndex
+ *   Index of access counter buffer to register.
+ *
+ * bufferSize
+ *   Size of the access counter buffer to register.
+ *
+ * bufferPteArray
+ *   Pages of access counter buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER (0x20800a1d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES    64
+#define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU)
+
+typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS {
+    NvU32 accessCounterIndex;
+    NvU32 bufferSize;
+    NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8);
+} NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER
+ *
+ * This command requests physical RM to disable the access counter buffer.
+ *
+ * accessCounterIndex
+ *   Index of access counter buffer to unregister.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1EU)
+
+typedef struct NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS {
+    NvU32 accessCounterIndex;
+} NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES         8
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2
+ */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS {
+    NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE];
+} NV2080_CTRL_INTERNAL_STATIC_GR_CAPS;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
+ * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
+ */
+
+
+
+#define NV2080_CTRL_INTERNAL_GR_MAX_SM                         512
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
+    struct {
+        NvU16 gpcId;
+        NvU16 localTpcId;
+        NvU16 localSmId;
+        NvU16 globalTpcId;
+        NvU16 virtualGpcId;
+        NvU16 migratableTpcId;
+        NvU16 ugpuId;
+        NvU16 physicalCpcId;
+        NvU16 virtualTpcId;
+    } globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM];
+
+    NvU16 numSm;
+    NvU16 numTpc;
+} NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS;
+
+/*!
+ * NVDEC Static data.
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_MAX_NVDECS 8
+#define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS NV2080_CTRL_CMD_INTERNAL_MAX_NVDECS
+
+typedef struct NV2080_CTRL_INTERNAL_NVDEC_CAPS {
+    NvU8 capsTbl[NV0080_CTRL_NVDEC_CAPS_TBL_SIZE];
+} NV2080_CTRL_INTERNAL_NVDEC_CAPS;
+#define NV2080_CTRL_INTERNAL_BSP_CAPS NV2080_CTRL_INTERNAL_NVDEC_CAPS
+
+typedef struct NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS {
+    NV2080_CTRL_INTERNAL_NVDEC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_NVDECS];
+    NvBool                          valid[NV2080_CTRL_CMD_INTERNAL_MAX_NVDECS];
+} NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS;
+#define NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS
+
+/*!
+ * NVENC Static data.
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_MAX_NVENCS 8
+#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS NV2080_CTRL_CMD_INTERNAL_MAX_NVENCS
+
+typedef struct NV2080_CTRL_INTERNAL_NVENC_CAPS {
+    NvU8 capsTbl[NV0080_CTRL_NVENC_CAPS_TBL_SIZE];
+} NV2080_CTRL_INTERNAL_NVENC_CAPS;
+#define NV2080_CTRL_INTERNAL_MSENC_CAPS NV2080_CTRL_INTERNAL_NVENC_CAPS
+
+typedef struct NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS {
+    NV2080_CTRL_INTERNAL_NVENC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_NVENCS];
+    NvBool                          valid[NV2080_CTRL_CMD_INTERNAL_MAX_NVENCS];
+} NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS;
+#define NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS
+
+
+#define NV2080_CTRL_INTERNAL_GR_MAX_GPC                            64
+#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT                 10
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK
+ * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK
+ * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK
+ */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS {
+    NvU32 gpcMask;
+
+    /*!
+     * tpcMask is indexed by logical GPC ID for MIG case
+     * and indexed by physical GPC ID for non-MIG case
+     */
+    NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+
+    /*!
+     * tpcCount is always indexed by logical GPC ID
+     */
+    NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+    NvU32 physGpcMask;
+    NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+
+    NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT];
+    NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+
+    /*!
+     * zcullMask is always indexed by physical GPC ID
+     */
+    NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+
+    NvU32 physGfxGpcMask;
+    NvU32 numGfxTpc;
+} NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS {
+    /*!
+     * floorsweeping masks which are indexed via local GR index
+     */
+    NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES
+ *
+ * This command returns physical addresses of specified context buffer.
+ * To obtain addresses of whole buffer firstPage has to be advanced on
+ * subsequent invocations of the control until whole buffer is probed.
+ * If the buffer is contiguous, only single address will be returned by
+ * this control.
+ *
+ *    bufferType[IN]
+ *      Buffer type as returned by GET_CTX_BUFFER_INFO.
+ *
+ *    firstPage[IN]
+ *      Index of the first page to return in 'physAddrs' array.
+ *
+ *    numPages[OUT]
+ *      Number of entries filled in 'physAddrs' array. This will be 0
+ *      if firstPage is greater or equal to number of pages managed by 'hBuffer'.
+ *
+ *    physAddrs[OUT]
+ *      Physical addresses of pages comprising specified buffer.
+ *
+ *    bNoMorePages[OUT]
+ *      End of buffer reached. Either 'physAddrs' contains last page of the
+ *      buffer or 'firstPage' specifies index past the buffer.
+ */
+#define NV2080_CTRL_KGR_MAX_BUFFER_PTES         128
+#define NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES (0x20800a28) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID (0x28U)
+
+typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS {
+    NvHandle hUserClient;
+    NvHandle hChannel;
+    NvU32    bufferType;
+    NvU32    firstPage;
+    NvU32    numPages;
+    NV_DECLARE_ALIGNED(NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES], 8);
+    NvBool   bNoMorePages;
+} NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS;
+
+/*!
+ * NV2080_CTRL_INTERNAL_MEMDESC_INFO
+ *
+ * A generic container structure representing a memory region to be used as a
+ * component of other control call parameters.
+ *
+ */
+typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO {
+    NV_DECLARE_ALIGNED(NvU64 base, 8);
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+    NV_DECLARE_ALIGNED(NvU64 alignment, 8);
+    NvU32 addressSpace;
+    NvU32 cpuCacheAttrib;
+} NV2080_CTRL_INTERNAL_MEMDESC_INFO;
+
+/*!
+ * @ref NV0080_CTRL_CMD_GR_GET_INFO
+ * @ref NV0080_CTRL_CMD_GR_GET_INFO_V2
+ * @ref NV2080_CTRL_CMD_GR_GET_INFO
+ * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2
+ */
+
+
+
+/*!
+ * @ref NV2080_CTRL_GR_INFO
+ */
+typedef struct NV2080_CTRL_INTERNAL_GR_INFO {
+    NvU32 index;
+    NvU32 data;
+} NV2080_CTRL_INTERNAL_GR_INFO;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO {
+    NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE];
+} NV2080_CTRL_INTERNAL_STATIC_GR_INFO;
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO
+ */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO {
+    NvU32 widthAlignPixels;
+    NvU32 heightAlignPixels;
+    NvU32 pixelSquaresByAliquots;
+    NvU32 aliquotTotal;
+    NvU32 zcullRegionByteMultiplier;
+    NvU32 zcullRegionHeaderSize;
+    NvU32 zcullSubregionHeaderSize;
+    NvU32 subregionCount;
+    NvU32 subregionWidthAlignPixels;
+    NvU32 subregionHeightAlignPixels;
+} NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO
+ */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO {
+    NvU32 ropUnitCount;
+    NvU32 ropOperationsFactor;
+    NvU32 ropOperationsCount;
+} NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK
+ */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS {
+    NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
+} NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES
+ * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE
+ */
+
+
+
+#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x1a
+
+typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO {
+    NvU32 size;
+    NvU32 alignment;
+} NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO;
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO {
+    NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT];
+} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER
+ */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER {
+    NvU8 imla0;
+    NvU8 fmla16;
+    NvU8 dp;
+    NvU8 fmla32;
+    NvU8 ffma;
+    NvU8 imla1;
+    NvU8 imla2;
+    NvU8 imla3;
+    NvU8 imla4;
+} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
+
+/*
+ * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS
+ *
+ * This command obtains information from physical RM for use by CPU-RM.
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO      (0x20800a36) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * Maximum number of register bases to return.
+ * These are indexed by NV_REG_BASE_* constants from gpu.h, and this value needs
+ * to be updated if NV_REG_BASE_LAST ever goes over it. See the ct_assert() in gpu.h
+ */
+#define NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX 16
+#define NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID (0x36U)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS {
+    NvU8   chipSubRev;
+    NvU32  emulationRev1;
+    NvBool isCmpSku;
+    NvU32  pciDeviceId;
+    NvU32  pciSubDeviceId;
+    NvU32  pciRevisionId;
+    NvU32  regBases[NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX];
+} NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE
+ *
+ * Set whether or not context switch logging is enabled
+ *
+ * bEnable
+ *    Enable/Disable status for context switch logging
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE (0x20800a37) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE
+ *
+ * Retrieve whether or not context switch logging is enabled
+ *
+ * bEnable
+ *    Enable/Disable status for context switch logging
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE (0x20800a38) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvBool bEnable;
+} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U)
+
+typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U)
+
+typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET
+ *
+ * Set read offset into FECS context switch trace record
+ *
+ * offset
+ *   Value indicating number of records by which to offset
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET (0x20800a39) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET
+ *
+ * Set write offset into FECS context switch trace record
+ *
+ * offset
+ *   Value indicating number of records by which to offset
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET (0x20800a3a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID" */
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET
+ *
+ * Get read offset into FECS context switch trace record
+ *
+ * offset
+ *   Value indicating number of records by which to offset
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET (0x20800a3b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
+    NvU32 offset;
+} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U)
+
+typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU)
+
+typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU)
+
+typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE
+ *
+ * Get size of FECS record
+ *
+ * fecsRecordSize
+ *   Size of FECS record
+ */
+
+
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE (0x20800a3d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE {
+    NvU32 fecsRecordSize;
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3CU)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES
+ *
+ * Get HW defines used to extract information from FECS records
+ *
+ * fecsRecordSize
+ *  Size of FECS record
+ *
+ * timestampHiTagMask
+ *  Mask for high bits of raw timestamp to extract tag
+ *
+ * timestampHiTagShift
+ *  Shift for high bits of raw timestamp to extract tag
+ *
+ * timestampVMask
+ *  Mask to extract timestamp from raw timestamp
+ *
+ * numLowerBitsZeroShift
+ *  Number of bits timestamp is shifted by
+ */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES {
+    NvU32 fecsRecordSize;
+    NvU32 timestampHiTagMask;
+    NvU8  timestampHiTagShift;
+    NV_DECLARE_ALIGNED(NvU64 timestampVMask, 8);
+    NvU8  numLowerBitsZeroShift;
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8);
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS;
+
+/**
+ * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE
+ *
+ * Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel.
+ */
+typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO {
+    NvU32 faultId;
+    NvU32 instanceId;
+    NvU32 typeEnum;
+    NvU32 resetId;
+    NvU32 devicePriBase;
+    NvU32 isEngine;
+    NvU32 rlEngId;
+    NvU32 runlistPriBase;
+    NvU32 groupId;
+    NvU32 ginTargetId;
+    NvU32 deviceBroadcastPriBase;
+    NvU32 groupLocalInstanceId;
+} NV2080_CTRL_INTERNAL_DEVICE_INFO;
+#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 512
+
+#define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE   (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x40U)
+
+typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS {
+    NvU32                            numEntries;
+    NV2080_CTRL_INTERNAL_DEVICE_INFO deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES];
+} NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP              (0x20800a41) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE  16384
+#define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES 4096
+
+#define NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID (0x41U)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS {
+    NvU32 userRegisterAccessMapSize;
+    NvU32 compressedSize;
+    NvU8  compressedData[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE];
+    NvU32 profilingRangesSize;
+    NvU8  profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES];
+} NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS;
+
+/**
+ * Get GR PDB properties synchronized between Kernel and Physical
+ *
+ * bPerSubCtxheaderSupported
+ *   @ref PDB_PROP_GR_SUPPORTS_PER_SUBCONTEXT_CONTEXT_HEADER
+ */
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
+    NV_DECLARE_ALIGNED(NvU64 lo, 8);
+    NV_DECLARE_ALIGNED(NvU64 hi, 8);
+} NV2080_CTRL_INTERNAL_NV_RANGE;
+
+/*!
+ * NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
+ *
+ * This structure specifies a target swizz-id and mem_range to update
+ *
+ *  swizzId[IN]
+ *      - Targeted swizz-id for which the memRange is being set
+ *
+ *  memAddrRange[IN]
+ *      - Memory Range for given GPU instance
+ */
+#define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U)
+
+typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS {
+    NvU32 swizzId;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8);
+} NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U)
+
+typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
+    NvBool bPerSubCtxheaderSupported;
+} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GPU_CHECK_CTS_ID_VALID
+ *
+ * This command validates whether a given CTS ID can be used within a GPU Instance by checking
+ * if the required GPCs can be allocated from the GPU Instance.
+ *
+ *   ctsId [in]
+ *     The CTS ID to validate
+ *
+ *   bCheckClientGI [in]
+ *     Validate the CTS ID against the GPU Instance owned by the client.
+ *
+ *   giComputeSize [in]
+ *     The compute size for the GPU Instance, which determines the number of GPCs in the GPU Instance.
+ *
+ *   bCtsIdValid [out]
+ *     Returns whether the CTS ID is valid within the specified GPU Instance.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GPU_CHECK_CTS_ID_VALID (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS_MESSAGE_ID (0x46U)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS {
+    NvU32  ctsId;
+    NvBool bCheckClientGI;
+    NvU32  giComputeSize;
+    NvBool bCtsIdValid;
+} NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM
+ *
+ *   This command writes instance memory information in the display hardware registers.
+ *
+ *   instMemPhysAddr
+ *     GPU physical address or IOVA address of the display instance memory.
+ *
+ *   instMemSize
+ *     Size of the display instance memory.
+ *
+ *   instMemAddrSpace
+ *     Address space of the display instance memory.
+ *
+ *   instMemCpuCacheAttr
+ *     Cache attribute of the display instance memory.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID (0x49U)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 instMemSize, 8);
+    NvU32 instMemAddrSpace;
+    NvU32 instMemCpuCacheAttr;
+} NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS;
+
+/*
+ * NV2080_CTRL_INTERNAL_GPU_RECOVER_ALL_COMPUTE_CONTEXTS
+ *
+ * This command issues RC recovery for all compute contexts running on the given GPU.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS (0x20800a4a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4A" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION
+ *
+ *    This command obtains IP version of display engine for use by Kernel RM.
+ *
+ *   ipVersion
+ *     IP Version of display engine.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED - DISP has been disabled
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION       (0x20800a4b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4BU)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS {
+    NvU32 ipVersion;
+} NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE
+ *
+ *  This command determines the current status of MIG MODE from Physical RM.
+ *
+ *  smcMode [OUT]
+ *     Current MIG MODE of the GPU. Values range NV2080_CTRL_GPU_INFO_GPU_SMC_MODE*
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE (0x20800a4c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID (0x4CU)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS {
+    NvU32 smcMode;
+} NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR
+ *
+ *   head
+ *     This parameter specifies the head for which the callback is to be registered/unregistered. This value must be
+ *     less than the maximum number of heads supported by the GPU subdevice.
+ *
+ *   rgLineNum
+ *     This indicates the RG scanout line number on which the callback will be executed.
+ *
+ *   intrLine
+ *     Enable: [out] Which interrupt line was allocated for this head.
+ *     Disable: [in] Which interrupt line to deallocate.
+ *
+ *   bEnable
+ *     Should we allocate or deallocate an interrupt line?
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC - There was no available interrupt to allocate.
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR (0x20800a4d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID (0x4DU)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
+    NvU32  head;
+    NvU32  rgLineNum;
+    NvU32  intrLine;
+    NvBool bEnable;
+} NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS;
+
+/*!
+ * NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO
+ *
+ * Description of a supported GPU instance.
+ *
+ *   partitionFlag [OUT]
+ *     Allocation flag to be used to allocate a partition with this profile.
+ *
+ *   grCount [OUT]
+ *     # GR engines, including the GFX capable ones.
+ *
+ *   gfxGrCount [OUT]
+ *     # GR engines capable of Gfx, which is a subset of the GR engines included in grCount
+ *
+ *   gpcCount [OUT]
+ *     # total gpcs, including the GFX capable ones.
+ *
+ *   virtualGpcCount [OUT]
+ *     # virtualized gpcs, including the GFX capable ones.
+ *
+ *   gfxGpcCount [OUT]
+ *     # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount.
+ *
+ *   veidCount [OUT]
+ *     # total veids
+ *
+ *   smCount [OUT]
+ *     # total SMs
+ *
+ *   ceCount [OUT]
+ *     # CE engines
+ *
+ *   nvEncCount [OUT]
+ *     # NVENC engines
+ *
+ *   nvDecCount [OUT]
+ *     # NVDEC engines
+ *
+ *   nvJpgCount [OUT]
+ *     # NVJPG engines
+ *
+ *   nvOfaCount [OUT]
+ *     # NVOFA engines
+ *
+ *   validCTSIdMask [OUT]
+ *     # mask of CTS IDs which can be assigned under this profile
+ *
+ *   validGfxCTSIdMask [OUT]
+ *     # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile
+ */
+#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES      90
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO {
+    NvU32 partitionFlag;
+    NvU32 grCount;
+    NvU32 gfxGrCount;
+    NvU32 gpcCount;
+    NvU32 virtualGpcCount;
+    NvU32 gfxGpcCount;
+    NvU32 veidCount;
+    NvU32 smCount;
+    NvU32 ceCount;
+    NvU32 nvEncCount;
+    NvU32 nvDecCount;
+    NvU32 nvJpgCount;
+    NvU32 nvOfaCount;
+    NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8);
+    NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8);
+} NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO;
+
+/*!
+ * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS
+ *
+ * Returns the list of supported GPU instance profiles.
+ *
+ *   count [OUT]
+ *     Number of supported profiles.
+ *
+ *   table [OUT]
+ *     Supported profiles.
+ */
+#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS {
+    NvU32 count;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8);
+} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM
+ *
+ *  This command instructs the physical MemorySystem to set up memory partitioning
+ *  exterior boundaries in hardware.
+ *
+ *  partitionableMemSize [input]
+ *      Size of the partitionable memory in bytes
+ *
+ *  bottomRsvdSize [input]
+ *      Size of the reserved region below partitionable memory in bytes
+ *
+ *  topRsvdSize [input]
+ *      Size of the reserved region above partitionable memory in bytes
+ *
+ *  partitionableStartAddr [output]
+ *      Start address of the partitionable memory, aligned to HW constraints
+ *
+ *  partitionableEndAddr [output]
+ *      End address of the partitionable memory, aligned to HW constraints
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM (0x20800a51) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID (0x51U)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 partitionableMemSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 bottomRsvdSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 topRsvdSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 partitionableStartAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 partitionableEndAddr, 8);
+} NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS;
+
+
+
+#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE 4
+
+#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 engineMask[NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE], 8);
+} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS         2
+#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID              64
+/*!
+ * NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS
+ *
+ * Promote a single partition's runlist buffers allocated by kernel Client RM to Physical RM
+ *
+ *   rlBuffers [IN]
+ *     2D array of runlist buffers for a single partition
+ *
+ *   runlistIdMask [IN]
+ *     Mask of runlists belonging to partition
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS (0x20800a53) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID (0x53U)
+
+typedef struct NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO rlBuffers[NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID][NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS], 8);
+    NV_DECLARE_ALIGNED(NvU64 runlistIdMask, 8);
+    NvU32 swizzId;
+} NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO (0x20800a54) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID (0x54U)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS {
+    TEGRA_IMP_IMPORT_DATA tegraImpImportData;
+} NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO (0x20800a55) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID (0x55U)
+
+typedef struct NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS {
+    NvU16  pciDeviceId;
+    NvU16  pciSubDeviceId;
+    NvBool iseGPUBridge;
+    NvU8   approvedBusType;
+} NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE              (0x00000000)
+#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM            (0x00000001)
+#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2               (0x00000002)
+#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3               (0x00000003)
+
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR
+ *
+ * This command triggers a sysmembar to flush VIDMEM writes.
+ * This command accepts no parameters.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR    (0x20800a70) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x70" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL
+ *
+ * Setup local PCIE P2P Mailbox
+ *
+ * local2Remote[IN]
+ *   Local peer ID of remote gpu on local gpu
+ *
+ * remote2Local[IN]
+ *   Remote peer ID of local gpu on remote gpu
+ *
+ * localP2PDomainRemoteAddr[IN]
+ *   P2P domain remote address on local gpu
+ *
+ * remoteP2PDomainLocalAddr[IN]
+ *   P2P domain local address on remote gpu
+ *
+ * remoteWMBoxLocalAddr[IN]
+ *   Local mailbox address on remote gpu
+ *
+ * p2pWmbTag[OUT]
+ *   Tag for mailbox to transport from local to remote GPU
+ *
+ * bNeedWarBug999673[IN]
+ *   Set to true if WAR for bug 999673 is required
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL (0x20800a71) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID (0x71U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS {
+    NvU32  local2Remote;
+    NvU32  remote2Local;
+    NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 remoteWMBoxLocalAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8);
+    NvBool bNeedWarBug999673;
+} NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS;
+
+ /*
+ * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE
+ *
+ * Setup remote PCIE P2P Mailbox
+ *
+ * local2Remote[IN]
+ *   Local peer ID of remote gpu on local gpu
+ *
+ * remote2Local[IN]
+ *   Remote peer ID of local gpu on remote gpu
+ *
+ * localP2PDomainRemoteAddr[IN]
+ *   P2P domain remote address on local gpu
+ *
+ * remoteP2PDomainLocalAddr[IN]
+ *   P2P domain local address on remote gpu
+ *
+ * remoteWMBoxAddrU64[IN]
+ *   Mailbox address on remote gpu
+ *
+ * p2pWmbTag[IN]
+ *   Tag for mailbox to transport from local to remote GPU
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE (0x20800a72) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID (0x72U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS {
+    NvU32 local2Remote;
+    NvU32 remote2Local;
+    NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 remoteWMBoxAddrU64, 8);
+    NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8);
+} NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX
+ *
+ * Destroy PCIE P2P Mailbox
+ *
+ * peerIdx[IN]
+ *   Peer ID of the P2P destination GPU
+ *
+ * bNeedWarBug999673[IN]
+ *   Set to true if WAR for bug 999673 is required
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX (0x20800a73) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID (0x73U)
+
+typedef struct NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS {
+    NvU32  peerIdx;
+    NvBool bNeedWarBug999673;
+} NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING
+ *
+ * Create C2C mapping to a given peer GPU
+ *
+ * peerId[IN]
+ *   Peer ID for local to remote GPU
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING (0x20800a74) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x74U)
+
+typedef struct NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS {
+    NvU32 peerId;
+} NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING
+ *
+ * Remove C2C mapping to a given peer GPU
+ *
+ * peerId[IN]
+ *   Peer ID for local to remote GPU
+ *
+ * Possible status values returned are:
+ *  NV_OK
+ *  NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING (0x20800a75) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x75U)
+
+typedef struct NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS {
+    NvU32 peerId;
+} NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES
+ *
+ * Retrieves the corresponding SPAs (per the given GFID's VMMU mappings)
+ * for the given array of GPAs.
+ *
+ *   gfid [IN]
+ *     GFID to translate GPAs for
+ *
+ *   numEntries [IN]
+ *     Number of entries (<= NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES)
+ *     to translate (i.e. number of elements in gpaEntries)
+ *
+ *   gpaEntries [IN]
+ *     Array of GPAs to translate
+ *
+ *   spaEntries [OUT]
+ *     Resulting array of SPAs
+ */
+#define NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES (0x20800a57) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES     128
+
+#define NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID (0x57U)
+
+typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS {
+    NvU32 gfid;
+    NvU32 numEntries;
+    NV_DECLARE_ALIGNED(NvU64 gpaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8);
+    NV_DECLARE_ALIGNED(NvU64 spaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8);
+} NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER
+ *
+ * Pass required pushbuffer parameters from kernel RM to Physical RM
+ *
+ *   addressSpace [IN]
+ *     Address space of pushbuffer whtether it is ADDR_SYSMEM or ADDR_FBMEM
+ *
+ *   physicalAddr [IN]
+ *     Physical address of pushbuffer
+ *
+ *   addressSpace [IN]
+ *     Limit of the pushbuffer address, it should be less than 4K
+ *
+ *   cacheSnoop [IN]
+ *     Cachesnoop supported or not
+ *
+ *   channelInstance [IN]
+ *     Channel instance pass by the client to get corresponding dispchannel
+ *
+ *   hclass [IN]
+ *     External class ID pass by the client to get the channel class
+ *
+ *   valid [IN]
+ *     This bit indicates whether pushbuffer parameters are valid or not
+ *
+ *   pbTargetAperture [IN]
+ *     Indicates the PushBuffer Target Aperture type (IOVA, PCI, PCI_COHERENT or NVM)
+ *
+ *   channelPBSize [IN]
+ *     Indicates the PushBuffer size requested by client
+ *
+ *   subDeviceId [IN]
+ *     One-hot encoded subDeviceId (i.e. SDM) that will be used to address the channel
+ *     in the pushbuffer stream (via SSDM method)
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID (0x58U)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
+    NvU32  addressSpace;
+    NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 limit, 8);
+    NvU32  cacheSnoop;
+    NvU32  hclass;
+    NvU32  channelInstance;
+    NvBool valid;
+    NvU32  pbTargetAperture;
+    NvU32  channelPBSize;
+    NvU32  subDeviceId;
+} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO
+ *
+ *   This command obtains information from physical RM for use by CPU-RM.
+ *
+ *   replayableFaultBufferSize
+ *     Default size of replayable fault buffer
+ *
+ *   nonReplayableFaultBufferSize
+ *     Default size of non-replayable fault buffer
+ *
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO (0x20800a59) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x59U)
+
+typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS {
+    NvU32 replayableFaultBufferSize;
+    NvU32 replayableShadowFaultBufferMetadataSize;
+    NvU32 nonReplayableFaultBufferSize;
+    NvU32 nonReplayableShadowFaultBufferMetadataSize;
+} NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU)
+
+typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE
+ *
+ * Get heap reservation size needed by different module
+ */
+#define NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE (0x20800a5b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID (0x5BU)
+
+typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS {
+    NvU32 moduleIndex;
+    NvU32 size;
+} NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE
+ *
+ *   tableLen   [OUT]
+ *     Number of valid records in table field.
+ *
+ *   table      [OUT]
+ *     Interrupt table for Kernel RM.
+ *
+ *   subtreeMap [OUT]
+ *     Subtree mask for each NV2080_INTR_CATEGORY.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE       128
+
+typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
+    NvU16 engineIdx;
+    NvU32 pmcIntrMask;
+    NvU32 vectorStall;
+    NvU32 vectorNonStall;
+} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY;
+
+#define NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID (0x5CU)
+
+typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
+    NvU32                                            tableLen;
+    NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];
+    NV_DECLARE_ALIGNED(NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT], 8);
+} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
+
+/* Index to retrieve the needed heap space for specific module */
+#define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR           (0x00000000)
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK
+ *
+ * Checking if the reservation / release of the PERFMON HW is possible
+ *
+ *   bReservation [IN]
+ *     NV_TRUE -> request for reservation, NV_FALSE -> request for release
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK (0x20800a98) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID" */
+
+
+#define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID (0x98U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS {
+    NvBool bReservation;
+} NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET
+ *
+ * Reserving / Releasing PERFMON HW
+ *
+ *   bReservation [IN]
+ *     NV_TRUE -> request for reservation, NV_FALSE -> request for release
+ *
+ *   bClientHandlesGrGating [IN]
+ *     DM-TODO: Add comment for this
+ *
+ *   bRmHandlesIdleSlow [IN]
+ *     If the IDLE slowdown is required
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET (0x20800a99) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID (0x99U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS {
+    NvBool bReservation;
+    NvBool bClientHandlesGrGating;
+    NvBool bRmHandlesIdleSlow;
+} NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES
+ *
+ * Get active display devices
+ *
+ *   displayMask [OUT]
+ *     Get the mask of the active display devices in VBIOS
+ *
+ *   numHeads [OUT]
+ *     Number of heads display supported.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (0x20800a5d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID (0x5DU)
+
+typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS {
+
+    NvU32 displayMask;
+    NvU32 numHeads;
+} NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
+ *
+ * Get FB Mem page ranges for all possible swizzIds
+ *
+ *   fbMemPageRanges [OUT]
+ *      Mem page ranges for each swizzId in the form of {lo, hi}
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a60) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID                                      15
+
+#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE fbMemPageRanges[NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID], 8);
+} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to get number of channels for a given runlist ID
+ *
+ *   runlistId   [IN]
+ *   numChannels [OUT]
+ */
+#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS (0x20800a61) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID (0x61U)
+
+typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
+    NvU32 runlistId;
+    NvU32 numChannels;
+} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES
+ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG
+ * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG
+ *
+ * This command retrieves memory config from HW
+ *
+ *   memBoundaryCfgA [OUT]
+ *      Memory boundary config A (4KB aligned)
+ *
+ *   memBoundaryCfgB [OUT]
+ *      Memory boundary config B (4KB aligned)
+ *
+ *   memBoundaryCfgC [OUT]
+ *      Memory boundary config C (64KB aligned)
+ *
+ *   memBoundaryCfg [OUT]
+ *      Memory boundary config (64KB aligned)
+ *
+ *   memBoundaryCfgValInit [OUT]
+ *      Memory boundary config initial value (64KB aligned)
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8);
+    NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgB, 8);
+    NvU32 memBoundaryCfgC;
+    NvU32 memBoundaryCfg;
+    NvU32 memBoundaryCfgValInit;
+} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U)
+
+typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE  (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x6BU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS {
+    NvU32 data[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE];
+} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT
+ *
+ * Invoke RC recovery after watchdog timeout is hit.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT      (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */
+
+/* !
+ *  This command is used to get the current AUX power state of the sub-device.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE (0x20800a81) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x81U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS {
+    NvU32 powerState;
+} NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS;
+
+/*!
+ * This command can be used to boost P-State up one level or to the highest for a limited
+ * duration for the associated subdevice. Boosts from different clients are being tracked
+ * independently. Note that there are other factors that can limit P-States so the resulting
+ * P-State may differ from expectation.
+ *
+ *   flags
+ *     This parameter specifies the actual command. _CLEAR is to clear existing boost.
+ *     _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost
+ *     to the highest P-State.
+ *   duration
+ *     This parameter specifies the duration of the boost in seconds. This has to be less
+ *     than NV2080_CTRL_PERF_BOOST_DURATION_MAX.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID (0x9AU)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X {
+
+    NvBool flags;
+    NvU32  duration;
+} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X;
+
+#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE   0U
+#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK   1U
+#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST     NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK
+#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM      (0x2U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST + 1" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL
+ *
+ * Activate/Deactivate GPU Boost Sync algorithm
+ *
+ *   bActivate [IN]
+ *     GPU Boost Sync algorithm:
+ *      NV_TRUE  -> activate
+ *      NV_FALSE -> deactivate
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL (0x20800a7e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7EU)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS {
+    NvBool bActivate;
+} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS
+ *
+ * Apply given limits to a specific subdevice
+ *
+ *   flags [IN]
+ *     DM-TODO: write description here
+ *
+ *   bBridgeless [IN]
+ *     Bridgeless information, for now supporting only MIO bridges
+ *
+ *   currLimits
+ *     Array of limits that will be applied
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS (0x20800a7f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID (0x7FU)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS {
+    NvU32  flags;
+    NvBool bBridgeless;
+    NvU32  currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM];
+} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO
+ *
+ * Data for GPU Boost Sync structure initialization
+ *
+ *   hysteresisus [OUT]
+ *     Hysteresis value for GPU Boost synchronization hysteresis algorithm.
+ *
+ *   bHystersisEnable [OUT]
+ *     hysteresis algorithm for SLI GPU Boost synchronization:
+ *      NV_TRUE  -> enabled,
+ *      NV_FALSE -> disabled
+ *
+ *   bSliGpuBoostSyncEnable [OUT]
+ *     SLI GPU Boost feature is:
+ *      NV_TRUE  -> enabled,
+ *      NV_FALSE -> disabled
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO (0x20800a80) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID (0x80U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 hysteresisus, 8);
+    NvBool bHystersisEnable;
+    NvBool bSliGpuBoostSyncEnable;
+} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER
+ *
+ * This command sends replayable fault buffer pages allocated by CPU-RM
+ * to be setup and enabled in physical RM.
+ *
+ * hClient
+ *   Client handle.
+ *
+ * hObject
+ *   Object handle.
+ *
+ * faultBufferSize
+ *   Size of the replayable fault buffer to register.
+ *
+ * faultBufferPteArray
+ *   Pages of replayable fault buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER (0x20800a9b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES    256
+#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9BU)
+
+typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS {
+    NvHandle hClient;
+    NvHandle hObject;
+    NvU32    faultBufferSize;
+    NV_DECLARE_ALIGNED(NvU64 faultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES], 8);
+} NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER
+ *
+ * This command requests physical RM to disable the replayable fault buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER             (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */
+
+// Valid fault buffer types
+#define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE                           (0x00000000)
+#define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE                               (0x00000001)
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER
+ *
+ * This command sends client shadow fault buffer pages allocated by CPU-RM
+ * to be setup and enabled in physical RM.
+ *
+ * shadowFaultBufferQueuePhysAddr
+ *   Physical address of shadow fault buffer queue.
+ *
+ * faultBufferSize
+ *   Size of the client shadow fault buffer to register.
+ *
+ * shadowFaultBufferPteArray
+ *   Pages of client shadow fault buffer.
+ *
+ * shadowFaultBufferType
+ *   Replayable or non-replayable fault buffer
+ *
+ * faultBufferSharedMemoryPhysAddr
+ *   Fault buffer shared memory address. Used only by the Replayable fault buffer.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES    3000
+#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU)
+
+typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8);
+    NvU32 shadowFaultBufferSize;
+    NvU32 shadowFaultBufferMetadataSize;
+    NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8);
+    NvU32 shadowFaultBufferType;
+    NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8);
+} NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER
+ *
+ * This command requests physical RM to disable the client shadow fault buffer.
+ *
+ * shadowFaultBufferType
+ *   Replayable or non-replayable fault buffer
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU)
+
+typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS {
+    NvU32 shadowFaultBufferType;
+} NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER
+ *
+ * Pin PDEs for  Global VA range on the server RM and then mirror the client's page
+ * directory/tables in the server.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER (0x20800a9f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID (0x9FU)
+
+typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS {
+    NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8);
+} NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X
+ *
+ * This command can be used to boost P-State the highest for a limited
+ * duration for the associated subdevice. Boosts from different clients are being tracked
+ * independently. Note that there are other factors that can limit P-States so the resulting
+ * P-State may differ from expectation.
+ *
+ *   flags [IN]
+ *     This parameter specifies the actual command. _CLEAR is to clear existing boost.
+ *     and _BOOST_TO_MAX is to boost to the highest P-State.
+ *
+ *   boostDuration [IN]
+ *     This parameter specifies the duration of the boost in seconds. This has to be less
+ *     than NV2080_CTRL_PERF_BOOST_DURATION_MAX.
+ *
+ *   gfId [IN]
+ *     This specifies Id of the Kernel RM that is requesting the Boost
+ *
+ *   bOverrideInfinite[IN]
+ *      This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM.
+ *      This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM
+ *      and setting the boost duration to a next maximum duration registered for the Kernel RM in question.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X {
+    NvU32  flags;
+    NvU32  boostDuration;
+    NvU32  gfId;
+    NvBool bOverrideInfinite;
+} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X
+ *
+ * Clear the boost for specific Kernel RM
+ *
+ *   bIsCudaClient [IN]
+ *     Specifies if the request is for clearing the CUDA boost or regular boost
+ *     NV_TRUE -> CUDA boost, NV_FALSE otherwise
+ *
+ *   gfId [IN]
+ *     Specifies Id of the Kernel RM that is requesting Boost clear
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X (0x20800aa1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID (0xA1U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X {
+
+    NvBool bIsCudaClient;
+    NvU32  gfId;
+} NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO
+ *
+ * Retrieves skyline information about the GPU. Params are sized to currently known max
+ * values, but will need to be modified in the future should that change.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO          (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES            9
+#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 64
+/*!
+ * NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO
+ * skylineVgpcSize[OUT]
+ *      - TPC count of non-singleton VGPCs
+ * singletonVgpcMask[OUT]
+ *      - Mask of active Singletons
+ * maxInstances[OUT]
+ *      - Max allowed instances of this skyline concurrently on a GPU
+ * computeSizeFlag
+ *      - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline
+ * numNonSingletonVgpcs
+ *      - Number of VGPCs with non-zero TPC counts which are not singletons
+ */
+typedef struct NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO {
+    NvU8  skylineVgpcSize[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS];
+    NvU32 singletonVgpcMask;
+    NvU32 maxInstances;
+    NvU32 computeSizeFlag;
+    NvU32 numNonSingletonVgpcs;
+} NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO;
+
+/*!
+ * NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS
+ * skylineTable[OUT]
+ *      - TPC count of non-singleton VGPCs
+ *      - Mask of singleton vGPC IDs active
+ *      - Max Instances of this skyline possible concurrently
+ *      - Associated compute size with the indexed skyline
+ *      - Number of VGPCs with non-zero TPC counts which are not singletons
+ * validEntries[OUT]
+ *      - Number of entries which contain valid info in skylineInfo
+ */
+#define NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0xA2U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS {
+    NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO skylineTable[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES];
+    NvU32                                   validEntries;
+} NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U)
+
+typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U)
+
+typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U)
+
+typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U)
+
+typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED
+ *
+ * Tell Physical RM whether any ZBC-kind surfaces are allocated.
+ * If PF and all VFs report false, ZBC table can be flushed by Physical RM.
+ *
+ *   bZbcReferenced [IN]
+ *     NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
+    NvBool bZbcSurfacesExist;
+} NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE
+ *
+ * Export the resource and placement information about a gpu instance such that a
+ * similar gpu instance can be recreated from scratch in the same position on the
+ * same or similar GPU. Note that different GPUs may have different physical
+ * resources due to floorsweeping, and an imported gpu instance is not guaranteed
+ * to get the exact same resources as the exported gpu instance, but the imported
+ * gpu instance should behave identically with respect to fragmentation and
+ * placement / span positioning.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE                     (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE                      (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE
+ *
+ * Create a gpu instance resembling the exported instance info. Note that
+ * different GPUs may have different physical resources due to floorsweeping,
+ * and an imported gpu instance is not guaranteed to get the exact same resources
+ * as the exported gpu instance, but the imported gpu instance should behave
+ * identically with respect to fragmentation and placement / span positioning.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE                     (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE                      (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4
+typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO {
+    NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8);
+    NvU32 partitionFlags;
+    NvU32 gpcMask;
+    NvU32 virtualGpcCount;
+    NvU32 veidOffset;
+    NvU32 veidCount;
+} NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO;
+
+typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS {
+    NvU32 swizzId;
+    NvU8  uuid[NV_GI_UUID_LEN];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8);
+} NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U)
+
+typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U)
+
+typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U)
+
+typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU)
+
+typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT
+ *
+ * Invalidate and/or evict the L2 cache
+ *
+ *   flags [IN]
+ *     flags that specify required actions
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT (0x20800a6c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID (0x6cU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS {
+    NvU32 flags;
+} NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL          (0x00000001)
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST        (0x00000002)
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST         (0x00000004)
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL       (0x00000008)
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN        (0x00000010)
+#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL (0x00000020)
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES
+ *
+ * Flush all L2 Rams and Caches using the ELPG flush
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES       (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_CLEAN_LTC_PROBE_FILTER
+ *
+ * Set the L2 coherence probe filter to CLEAN state.
+ * This evicts all checked-out lines from the probe filter.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_CLEAN_LTC_PROBE_FILTER             (0x20800ab0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xB0" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO
+ *
+ * This command obtains information from physical RM for use by CPU-RM
+ *
+ * Data fields ->
+ *   bPcieGen4Capable - tells whether PCIe is Gen4 capable
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO                       (0x20800aac) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xacU)
+
+typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS {
+    NvBool bPcieGen4Capable;
+    NvBool bIsC2CLinkUp;
+    NvBool bIsDeviceMultiFunction;
+    NvBool bGcxPmuCfgSpaceRestore;
+} NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_BIF_GET_DATA
+ *
+ * This command is used to redirect calls to physical RM if the info required by various clients is present in physical RM
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BIF_GET_DATA           (0x20800a00) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8)" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG
+ *
+ * Program HSHUB Peer Conn Config space.
+ *
+ *    programPeerMask[IN]
+ *      If nonzero, the peer mask for programming peers based on hshub connectivity.
+ *
+ *    invalidatePeerMask[IN]
+ *      If nonzero, the peer mask for invalidating peers.
+ *
+ *    programPciePeerMask[IN]
+ *      If nonzero, the peer mask for programming peers in pcie case.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_WARN_NOTHING_TO_DO
+ *     If all peer masks are zero.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG (0x20800a88) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID (0x88U)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS {
+    NvU32 programPeerMask;
+    NvU32 invalidatePeerMask;
+    NvU32 programPciePeerMask;
+} NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS
+ *
+ * Get the Hshub Ids connected to the other end of links.
+ *
+ *    linkMask[IN]
+ *      A mask of link ids to query.
+ *
+ *    hshubIds[OUT]
+ *      For each set bit in the link mask, the peer Hshub Id.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_WARN_NOTHING_TO_DO
+ *     If the mask is zero.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS        (0x20800a8a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE 32
+
+#define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID (0x8aU)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS {
+    NvU32 linkMask;
+    NvU8  hshubIds[NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE];
+} NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS
+ *
+ * Return the number of HSHUB units.
+ *
+ *    numHshubs[OUT]
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS (0x20800a8b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID (0x8bU)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS {
+    NvU32 numHshubs;
+} NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID
+ *
+ * Return the next hshubId after the given hshubId.
+ *
+ *    hshubId[IN/OUT]
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID (0x20800a8c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID (0x8cU)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS {
+    NvU8 hshubId;
+} NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG
+ *
+ * Program HSHUB for EGM peer id.
+ *
+ *    egmPeerId[IN]
+ *      EGM peer id to program in the HSHUB registers.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG (0x20800a8d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID (0x8dU)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS {
+    NvU32 egmPeerId;
+} NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR
+ *
+ * Enable compute peer addressing mode
+ * This command accepts no parameters.
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR (0x20800aad) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xad" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR
+ *
+ * Get/Set NVSwitch fabric address for FLA
+ *
+ * [In] bGet
+ *     Whether to get or set the NVSwitch fabric address
+ * [In/Out] addr
+ *     Address that is to be set or retrieved.
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID (0xaeU)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS {
+    NvBool bGet;
+    NV_DECLARE_ALIGNED(NvU64 addr, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR                    (0x20800aae) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT
+ *
+ * Sets number of VM slots that are active in VGPU's scheduler
+ *
+ *   maxActiveVGpuVMCount [IN]
+ *     Number of VM slots that are active in vGPU's scheduler.
+ *
+ * Possible status values returned are:
+ * NV_OK
+ * NV_ERR_OUT_OF_RANGE - Passed value is out of range
+ * NV_ERR_NO_MEMORY    - Out of memory
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT              (0x20800ab1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Maximum value of VM slots that are active in vGPU's scheduler.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE 32
+
+#define NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID (0xB1U)
+
+typedef struct NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS {
+    NvU8 maxActiveVGpuVMCount;
+} NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS
+ *
+ * Disable all NVLINK FB peers
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS         (0x20800a6e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6E" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE
+ *
+ * Program GPU in raw / legacy compression mode
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE (0x20800a6f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID (0x6fU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS {
+    NvBool bRawMode;
+} NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO
+ *
+ * This command gets the CCU samples Info from physical-RM.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO (0x20800ab2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xB2" */
+
+typedef struct NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS {
+    NvU32 ccuSampleSize;
+} NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_CCU_MAP
+ *
+ * This command gets the shared buffer memory descriptor from the CPU-RM and maps to it
+ * in physical-RM.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_ADDRESS
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CCU_MAP              (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1
+
+typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO {
+    NV_DECLARE_ALIGNED(NvU64 phyAddr, 8);
+    NvU32 shrBufSize;
+    NvU32 cntBlkSize;
+} NV2080_CTRL_INTERNAL_CCU_MAP_INFO;
+
+#define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U)
+
+typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_CCU_MAP_INFO mapInfo[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8);
+} NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP
+ *
+ * This command unmaps the shared buffer memory mapping in physical-RM
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID (0xB4U)
+
+typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS {
+    NvBool bDevShrBuf;
+    NvBool bMigShrBuf;
+} NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO
+ *
+ * [in] gpuId
+ *   GPU ID.
+ * [in] gpuInstance
+ *   GPU instance.
+ * [in] p2pCaps
+ *   Peer to peer capabilities discovered between the GPUs.
+ *   See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values.
+ * [in] p2pOptimalReadCEs
+ *   Mask of CEs to use for p2p reads over Nvlink.
+ * [in] p2pOptimalWriteCEs
+ *   Mask of CEs to use for p2p writes over Nvlink.
+ * [in] p2pCapsStatus
+ *   Status of all supported p2p capabilities.
+ *   See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values.
+ * [in] busPeerId
+ *   Bus peer ID. For an invalid or a non-existent peer this field
+ *   has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
+ * [in] busEgmPeerId
+ *   Bus EGM peer ID. For an invalid or a non-existent peer this field
+ *   has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
+ */
+typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO {
+    NvU32 gpuId;
+    NvU32 gpuInstance;
+    NvU32 p2pCaps;
+    NvU32 p2pOptimalReadCEs;
+    NvU32 p2pOptimalWriteCEs;
+    NvU8  p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
+    NvU32 busPeerId;
+    NvU32 busEgmPeerId;
+} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS
+ *
+ * An internal call to propagate the peer to peer capabilities of peer GPUs
+ * to the Physical RM. These capabilities are to be consumed by the vGPU GSP plugin.
+ * This control is used to both add and and update the peer to peer capabilities.
+ * The existing GPU entries will be updated and those which don't exist will be added.
+ * Use NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS to remove the added entries.
+ *
+ *   [in] peerGpuCount
+ *     The number of the peerGpuInfos entries.
+ *   [in] peerGpuInfos
+ *     The array of NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS entries, describing
+ *     the peer to peer capabilities of the specified GPUs.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount
+ *   NV_ERR_INSUFFICIENT_RESOURCES - Total GPU count exceeds the maximum value
+ */
+#define NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS (0x20800ab5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID (0xB5U)
+
+typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS {
+    NvU32                                       peerGpuCount;
+    NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO peerGpuInfos[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
+} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS
+ *
+ * An internal call to remove the cached peer to peer capabilities of peer GPUs
+ * from the Physical RM.
+ *
+ *   [in] peerGpuIdCount
+ *     The number of the peerGpuIds entries.
+ *   [in] peerGpuIds
+ *     The array of GPU IDs, specifying the GPU for which the entries need to be removed.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT - Invalid peerGpuIdCount
+ *   NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuIds[] entry
+ */
+#define NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS (0x20800ab6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB6U)
+
+typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS {
+    NvU32 peerGpuIdCount;
+    NvU32 peerGpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
+} NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS;
+
+
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_BUS_GET_PCIE_P2P_CAPS
+ *
+ * This command returns the GPU's PCIE P2P caps
+ *
+ *   [in]  bCommonPciSwitchFound
+ *     All GPUs are under the same PCI switch
+ *   [out] p2pReadCapsStatus
+ *   [out] p2pWriteCapsStatus
+ *     These members returns status of all supported p2p capabilities. Valid
+ *     status values include:
+ *       NV0000_P2P_CAPS_STATUS_OK
+ *         P2P capability is supported.
+ *       NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED
+ *         Chipset doesn't support p2p capability.
+ *       NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED
+ *         GPU doesn't support p2p capability.
+ *       NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED
+ *         IOH topology isn't supported. For e.g. root ports are on different
+ *         IOH.
+ *       NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY
+ *         P2P Capability is disabled by a regkey.
+ *       NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED
+ *         P2P Capability is not supported.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS (0x20800ab8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB8U)
+
+typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS {
+    NvBool bCommonPciSwitchFound;
+    NvU8   p2pReadCapsStatus;
+    NvU8   p2pWriteCapsStatus;
+} NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO
+ *
+ * Enable/disable PCIe Relaxed Ordering.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xB9U)
+
+typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
+    // Enable/disable PCIe relaxed ordering
+    NvBool enableRo;
+} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE
+ *
+ * An internal call to invoke the sequence VGA register reads & writes to
+ * perform save and restore of VGA
+ *
+ *   [in] bSave
+ *     To indicate whether save or restore needs to be performed.
+ *   [in] bUseVbios
+ *     Primary VGA indication from OS.
+ *   [out] bReturnEarly
+ *     To indicate caller to return after this call.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_OPERATION
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS {
+    NvBool bSave;
+    NvBool bUseVbios;
+    NvBool bReturnEarly;
+} NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE
+ *
+ * To perform save or restore operation from/to saved fonts.
+ *
+ *   [in] bSave
+ *     To indicate whether save or restore needs to be performed.
+ *   [in] bUseVbios
+ *     Primary VGA indication from OS.
+ *   [in] bVbiosCallSuccessful
+ *     Indicates if vbios invocation was successful or not.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x77U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS {
+    NvBool bSave;
+    NvBool bUseVbios;
+    NvBool bVbiosCallSuccessful;
+} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS;
+
+/*!
+ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES
+ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES
+ */
+
+/*!
+ * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE
+ *
+ * This structure specifies resources in an execution partition
+ *
+ *  computeSize[OUT]
+ *      - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile
+ *
+ *  flags[OUT]
+ *      - Bitmap of flags describing the profile NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG*
+ *
+ *  gfxGpcCount[OUT]
+ *      - Total Number of GFX Supporting GPCs in this partition
+ *
+ *  gpcCount[OUT]
+ *      - Total Number of GPCs in this partition (including GFX Supported GPCs)
+ *
+ *  veidCount[OUT]
+ *      - Number of VEIDs allocated to this profile
+ *
+ *  smCount[OUT]
+ *      - Number of SMs usable in this profile
+ */
+typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE {
+    NvU8  computeSize;
+    NvU16 flags;
+    NvU32 gfxGpcCount;
+    NvU32 gpcCount;
+    NvU32 veidCount;
+    NvU32 smCount;
+    NvU32 physicalSlots;
+} NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE;
+
+/*!
+ * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS
+ *
+ * This structure specifies resources in an execution partition
+ *
+ *  profileCount[OUT]
+ *      - Total Number of profiles filled
+ *
+ *  profiles[OUT]
+ *      - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
+ */
+#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS {
+    NvU32                                       profileCount;
+    NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
+} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE
+ *
+ * This command sets the ccu stream to enable/disable state.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE (0x20800abd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID (0xBDU)
+
+typedef struct NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS {
+    NvBool bStreamState;
+} NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT
+ *
+ * Attach GPU to the external device.
+ *
+ *   [in] bExtDevFound
+ *     To enable GPIO interrupts.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT (0x20800abe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID (0xBEU)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS {
+    NvBool bExtDevFound;
+} NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS
+ *
+ * Optimize the Gsync timing parameters
+ *
+ *   [in] timingParameters
+ *     Timing parameters passed by client.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS (0x20800abf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS {
+    NV_DECLARE_ALIGNED(NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters, 8);
+} NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS
+ *
+ * Get displayIDs supported by the display.
+ *
+ *   [out] displayIds
+ *     Associated display ID with head.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS (0x20800ac0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_MAX_NUM_HEADS                           4
+
+#define NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID (0xC0U)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS {
+    NvU32 displayIds[NV2080_MAX_NUM_HEADS];
+} NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC
+ *
+ * Set the Stereo sync for Gsync
+ *
+ *   [in] slave
+ *     Slave GPU head status.
+ *   [in] localSlave
+ *     Slave GPU head status but are not coupled.
+ *   [in] master
+ *     Master GPU head status.
+ *   [in] regstatus
+ *     Register status of status1 register.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC (0x20800ac1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID (0xC1U)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS {
+    NvU32 slave[NV2080_MAX_NUM_HEADS];
+    NvU32 localSlave[NV2080_MAX_NUM_HEADS];
+    NvU32 master[NV2080_MAX_NUM_HEADS];
+    NvU32 regStatus;
+} NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES
+ *
+ * Get vertical active lines for given head.
+ *
+ *   [in] head
+ *     For the headIdx which we need active.
+ *   [out] vActiveLines
+ *     Vertical active lines.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES (0x20800ac4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID (0xC4U)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS {
+    NvU32 headIdx;
+    NvU32 vActiveLines;
+} NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID
+ *
+ * Verifies if this displayId is valid.
+ *
+ *   [in] displays
+ *     Displays given by the client
+ *
+ *   [out] displayId
+ *     DisplayId for the given display
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID (0x20800ac9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID (0xC9U)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS {
+    NvU32 displays;
+    NvU32 displayId;
+} NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC
+ *
+ * Disable the raster sync gpio on the other P2060 GPU
+ * that's connected to master over Video bridge.
+ *
+ *   [in] bEnableMaster
+ *     If it is master gpu.
+ *
+ *   [out] bRasterSyncGpioSaved
+ *     If raster sync GPIO direction is saved or not.
+ *
+ *   [in/out] bRasterSyncGpioDirection
+ *     During save it gets the direction.
+ *     In restores it sets the direction.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC (0x20800aca) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID (0xCAU)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
+    NvBool bEnableMaster;
+    NvBool bRasterSyncGpioSaved;
+    NvU32  bRasterSyncGpioDirection;
+} NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS;
+
+
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_FBSR_INIT
+ *
+ * Initialize FBSR on GSP to prepare for suspend-resume
+ *
+ *   [in] hClient
+ *     Handle to client of SYSMEM memlist object
+ *   [in] hSysMem
+ *     Handle to SYSMEM memlist object
+ *   [in] bEnteringGcoffState
+ *     Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING
+ *   [in] sysmemAddrOfSuspendResumeData
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U)
+
+typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
+    NvHandle hClient;
+    NvHandle hSysMem;
+    NvBool   bEnteringGcoffState;
+    NV_DECLARE_ALIGNED(NvU64 sysmemAddrOfSuspendResumeData, 8);
+} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING
+ *
+ * Disable all the active channels during suspend
+ * Resume FIFO scheduling from GSP after resume on Kernel-RM
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID (0xC3U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS {
+    NvBool bDisableActiveChannels;
+} NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB
+ *
+ * This command is used to get the amount of host reserved FB
+ *
+ *  hostReservedFb [OUT]
+ *      Amount of FB reserved for the host
+ *  vgpuTypeId [IN]
+ *      The Type ID for VGPU profile
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB (0x20800ac5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID (0xC5U)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8);
+    NvU32 vgpuTypeId;
+} NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD
+ *
+ * This command initiates brightc module state load.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_ACPI_DSM_READ_SIZE                   (0x1000) /* finn: Evaluated from "(4 * 1024)" */
+
+#define NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID (0xC6U)
+
+typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS {
+    NvU32 status;
+    NvU16 backLightDataSize;
+    NvU8  backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE];
+} NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS;
+
+/*
+ * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL
+ *
+ * Returns number of active links allowed per IOCTRL
+ *
+ * [Out] numActiveLinksPerIoctrl
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC7U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS {
+    NvU32 numActiveLinksPerIoctrl;
+} NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS;
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ac7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */
+/*
+ * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL
+ *
+ * Returns number of links per IOCTRL
+ *
+ * [Out] numLinksPerIoctrl
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC8U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS {
+    NvU32 numLinksPerIoctrl;
+} NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS;
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ac8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE
+ *
+ * Update the system control capability
+ *
+ *   bIsSysCtrlSupported  [IN]
+        If the system control is supported
+ *   bIsPlatformLegacy [OUT]
+        If the platform is legacy
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE  (0x20800acb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID (0xCBU)
+
+typedef struct NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS {
+    NvBool bIsSysCtrlSupported;
+    NvBool bIsPlatformLegacy;
+} NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS;
+
+/*!
+ * Macros for PFM_REQ_HNDLR_STATE_SYNC data types.
+ */
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR   0x00U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM  0x01U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI 0x02U
+
+/*!
+ * Structure representing static data for a PFM_REQ_HNDLR_STATE_SYNC_SMBPBI.
+ */
+typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI {
+    /*!
+     * PFM sensor ID
+     */
+    NvU32 sensorId;
+
+    /*!
+     * PFM sensor limit value if required
+     */
+    NvU32 limit;
+} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI;
+
+/*!
+ * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC data types.
+ */
+typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA {
+    /*!
+     * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_<xyz>
+     */
+    NvU8 type;
+
+    /*!
+     * Type-specific information.
+     */
+    union {
+        NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI smbpbi;
+    } data;
+} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA;
+
+/*!
+ * Macros for PFM_REQ_HNDLR_STATE_SYNC flags for specific operation.
+ */
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD       0x00U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT      0x01U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR 0x02U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET   0x03U
+
+/*!
+ * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC params.
+ */
+typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
+    /*!
+     * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_<xyz>
+     */
+    NvU8                                               flags;
+
+    /*!
+     * Type-specific information.
+     */
+    NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA syncData;
+} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC
+ *
+ * State sync with platform req handler and SMBPBI
+ *
+ *   flags [IN]
+ *     Flags that needs sync operation between physical and kernel
+ *
+ *   syncData [IN]
+ *     Sync payload data
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU)
+
+typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC
+ *
+ * State sync with platform req handler and SMBPBI
+ *
+ *   flags [IN]
+ *     Flags that needs sync operation between physical and kernel
+ *
+ *   syncData [IN]
+ *     Sync payload data
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU)
+
+typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS;
+
+/*!
+ * Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag
+ */
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS 0x00U
+#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS            0x01U
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE
+ *
+ * Queries PM1 Forced off / PM1 Available status
+ *
+ *   flag        [IN]
+ *     Fetch PM1 Forced off / PM1 Available status based on value.
+ *   bStatus     [OUT]
+ *     PM1 Forced off / PM1 Available is true or false.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMETS
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE    (0x20800ace) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID (0xCEU)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS {
+    /*!
+     * Fetch PM1 Forced off / PM1 Available status based on value.
+     */
+    NvU8   flag;
+
+    /*!
+     * PM1 Forced off / PM1 Available status
+     */
+    NvBool bStatus;
+} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE
+ *
+ * Set PM1 state to enabled / disabled (boost clocks).
+ *
+ *   bEnable   [IN]
+ *     NV_TRUE means enable PM1, NV_FALSE means disable.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE (0x20800acf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID (0xCFU)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS {
+
+    /*!
+     * NV_TRUE means enable PM1, NV_FALSE means disable.
+     */
+    NvBool bEnable;
+} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT
+ *
+ * Updates EDPpeak Limit of GPU
+ *
+ *   bEnable        [IN]
+ *     Enable or Reset the settings
+ *   clientLimit    [IN]
+ *     Client requested limit
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_NOT_READY
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT (0x20800ad0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID (0xD0U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS {
+    NvBool bEnable;
+    NvU32  clientLimit;
+} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT
+ *
+ * Updates Target Temperature of GPU
+ *
+ *   targetTemp        [IN]
+ *     Target Temperature Set from SBIOS
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT (0x20800ad1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID (0xD1U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS {
+    NvS32 targetTemp;
+} NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE
+ *
+ * Enable / disable CTGP MODE
+ *
+ *   bEnable        [IN]
+ *     Enable or Reset the settings
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE (0x20800ad2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID (0xD2U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS {
+    NvBool bEnable;
+} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2
+ *
+ * Configuration of the turbo v2 parameters for NVPCF-Turbo arb control
+ *
+ *   ctgpOffsetmW        [IN]
+ *     TGP MODE Offset in mW
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 (0x20800ad3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID (0xD3U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS {
+    NvU32 ctgpOffsetmW;
+} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO
+ *
+ * Query VPstatese info. Get VPS PS2.0 support / get highest VP State Idx and requested VP State Idx
+ *
+ *   bVpsPs20Supported     [OUT]
+ *     Reflects Vpstates PS20 support
+ *   vPstateIdxHighest     [OUT}
+ *     Reflects Highest VPstate Idx
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO (0x20800ad4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID (0xD4U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS {
+    /*!
+     * Reflects Vpstates PS20 support
+     */
+    NvBool bVpsPs20Supported;
+
+    /*!
+     * Get highest VPState Idx from VBIOS
+     */
+    NvU32  vPstateIdxHighest;
+} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING
+ *
+ * Get vPstate mapping for requested pStateIdx
+ *
+ *   pStateIdx     [IN]
+ *     Requested PState Idx
+ *   vPstateIdx    [OUT}
+ *     Mapped VPstate Idx
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING (0x20800ad5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID (0xD5U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS {
+    /*!
+     * Requested PState Idx
+     */
+    NvU32 pStateIdx;
+
+    /*!
+     * Mapped VPstate Idx
+     */
+    NvU32 vPstateIdxMapping;
+} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE
+ *
+ * Set requested VPstate
+ *
+ *   vPstateIdx   [IN]
+ *     VPstate Idx to be set
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE (0x20800ad6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID (0xD6U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS {
+
+    /*!
+     * NV_TRUE means enable PM1, NV_FALSE means disable.
+     */
+    NvU32 vPstateIdx;
+} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE
+ *
+ * This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3
+ *
+ * Possible status return values are:
+ *   NV_OK     Success
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U)
+
+typedef struct NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS {
+    NvBool bIsGC6Satisfied;
+    NvBool bIsGCOFFSatisfied;
+} NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS;
+
+/*
+ *  This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to get number of secure channels supported on SEC2 and CE
+ *
+ *   maxSec2SecureChannels  [OUT]
+ *   maxCeSecureChannels    [OUT]
+ */
+#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS   (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U)
+
+typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
+    NvU32 maxSec2SecureChannels;
+    NvU32 maxCeSecureChannels;
+} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK
+ *
+ * This command checks if all the dependant modules to PRH have been initialized.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK (0x20800a45) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x45" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to disable the GPU system memory access after quiescing the GPU or
+ * re-enable sysmem access.
+ *
+ *   bDisable   [IN]
+ *     If NV_TRUE the GPU is quiesced and system memory access is disabled .
+ *     If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS    (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU)
+
+typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS {
+    NvBool bDisable;
+} NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU)
+
+typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS {
+    NvU32  pinSetIn; // in
+    NvU32  pinSetOut; // in
+    NvBool bMasterScanLock; // out
+    NvU32  masterScanLockPin; // out
+    NvBool bSlaveScanLock; // out
+    NvU32  slaveScanLockPin; // out
+} NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE            (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */
+
+#define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU)
+
+typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS {
+    NvU32  pinSet; // in
+    NvU32  gpioFunction; // out
+    NvU32  gpioPin; // out
+    NvBool gpioDirection; // out
+} NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS;
+
+/* NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA
+ *
+ * This command sets up ACPI DDC Edid data.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA (0x20800adf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID" */
+
+/* From ACPI6.5 spec., the max size of EDID data from SBIOS(_DDC) is 512B */
+#define MAX_EDID_SIZE_FROM_SBIOS                      512U
+
+typedef struct NV2080_CTRL_INTERNAL_EDID_DATA {
+    NvU32 status;
+    NvU32 acpiId;
+    NvU32 bufferSize;
+    NvU8  edidBuffer[MAX_EDID_SIZE_FROM_SBIOS];
+} NV2080_CTRL_INTERNAL_EDID_DATA;
+
+#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID (0xDFU)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS {
+    NvU32                          tableLen;
+    NV2080_CTRL_INTERNAL_EDID_DATA edidTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
+} NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED
+ *
+ * This command intializes display ACPI child devices.
+ * This command accepts no parameters.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED (0x20800af0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF0" */
+
+/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET              (0x20800af1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF1" */
+
+/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET */
+#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET             (0x20800af2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF2" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS
+ *
+ * This structure provides the params for getting GPU Fabric Probe Internal
+ * Info from GSP to CPU RM
+ *
+ *  numProbes[OUT]
+ *      - Number of probe requests sent
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF4U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 numProbes, 8);
+} NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO
+ *
+ * This command is used to get NV2080_CTRL_CMD_INTERNAL_GPU_FABRIC_PROBE_INFO_PARAMS
+ * from GSP to CPU RM.
+ * This command accepts NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO (0x208001f4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS
+ *
+ * This structure provides the params for starting GPU Fabric Probe
+ *
+ *  bwMode[IN]
+ *      - Nvlink Bandwidth mode
+ *
+ *  bLocalEgmEnabled[IN]
+ *      - EGM Enablement Status that needs to be set in GSP-RM
+ */
+#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS {
+    NvU16  bwMode;
+    NvBool bLocalEgmEnabled;
+} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE
+ *
+ * This command is used to trigger start of GPU FABRIC PROBE PROCESS on GSP.
+ * This command accepts NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE   (0x208001f5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE
+ *
+ * This command is used to trigger stop of GPU FABRIC PROBE PROCESS on GSP.
+ * This command accepts no parameters
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE    (0x208001f6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF6" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE
+ *
+ * This command is used to trigger suspend of GPU FABRIC PROBE PROCESS on GSP.
+ * This command accepts no parameters
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE (0x208001f7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF7" */
+
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS
+ *
+ * This structure provides the params for resuming GPU Fabric Probe
+ *
+ *  bwMode[IN]
+ *      - Nvlink Bandwidth mode
+ */
+#define NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF8U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS {
+    NvU16 bwMode;
+} NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE
+ *
+ * This command is used to trigger resume of GPU FABRIC PROBE PROCESS on GSP.
+ * This command accepts NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE      (0x208001f8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE
+ *
+ * This command is used to invalidate/reset GPU_FABRIC_PROBE_INFO on GSP.
+ * This command accepts no parameters
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE  (0x208001f9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF9" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to get static conf compute info
+ *
+ *      bIsBar1Trusted: [OUT]
+ *          Is BAR1 trusted to access CPR
+ *      bIsPcieTrusted: [OUT]
+ *          Is PCIE trusted to access CPR
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO (0x20800af3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xF3U)
+
+typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
+    NvBool bIsBar1Trusted;
+    NvBool bIsPcieTrusted;
+} NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to derive SWL keys and IV masks for a given engine
+ *
+ *      engineId: [IN]
+ *          NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived
+ *      ivMaskSet: [OUT]
+ *          Set of IV masks for given engine
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS (0x20800ae1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE         3U
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL   0U
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER     1U
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER 2U
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT    3U
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT    6U
+
+typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK {
+    NvU32 ivMask[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE];
+} NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK;
+
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID (0xE1U)
+
+typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS {
+    NvU32                                    engineId;
+    NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT];
+} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to derive LCE keys and IV masks for a given engine
+ *
+ *      engineId: [IN]
+ *          NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived
+ *      ivMaskSet: [OUT]
+ *          Set of IV masks for given engine
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS (0x20800ae2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID (0xE2U)
+
+typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS {
+    NvU32                                    engineId;
+    NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT];
+} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEY
+ *
+ * This command handles key rotation for a given H2D key (and corresponding D2H key)
+ * by deriving new key on GSP and updating the key on relevant SEC2 or LCE.
+ * It also updates IVs for all channels using the key and conditionally re-enables them
+ * and notifies clients of key rotation status at the end.
+ *
+ *      globalH2DKey : [IN]
+ *          global h2d key to be rotated
+ *      updatedEncryptIVMask: [OUT]
+ *          Encrypt IV mask post IV key rotation for a given engine's kernel channel
+ *      updatedDecryptIVMask: [OUT]
+ *          Decrypt IV mask post IV key rotation for a given engine's kernel channel
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS (0x20800ae5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID (0xE5U)
+
+typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS {
+    NvU32 globalH2DKey;
+    NvU32 updatedEncryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD];
+    NvU32 updatedDecryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD];
+} NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION
+ *
+ * This command RCs all channels that use the given key and have not reported
+ * idle via NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION yet.
+ * RM needs to RC such channels before going ahead with key rotation.
+ *
+ *      globalH2DKey : [IN]
+ *          global h2d key whose channels will be RCed
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION (0x20800ae6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0xE6U)
+
+typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS {
+    NvU32 exceptionType;
+    NvU32 globalH2DKey;
+} NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE
+ *
+ * This control call can be used to set gpu state on GSP to accept client requests
+ * or to block client requests.
+ * This is a internal command sent from Kernel RM to Physical RM.
+ *
+ *      bAcceptClientRequest:[IN]
+ *          NV_TRUE : set gpu state to accept client work requests
+ *          NV_FALSE: set gpu state to block client work requests
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE (0x20800ae7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID (0xE7U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS {
+    NvBool bAcceptClientRequest;
+} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY
+ *
+ *    This control call can be used to set CC security policy on GSP.
+ *    This is a internal command sent from Kernel RM to Physical RM.
+ *
+ *    attackerAdvantage [IN]
+ *      The minimum and maximum values for attackerAdvantage.
+ *      The probability of an attacker successfully guessing the contents of
+ *      an encrypted packet go up ("attacker advantage").
+ *
+ *    Possible status values returned are:
+ *     NV_OK
+ *     NV_ERR_INVALID_OBJECT_HANDLE
+ *     NV_ERR_INVALID_STATE
+ *     NV_ERR_INVALID_ARGUMENT
+ *     NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY (0x20800ae8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID (0xE8U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 attackerAdvantage, 8);
+} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS;
+
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to update the logical Uproc Id for the configuration.
+ *
+ *   logicalUprocId  [OUT]
+ */
+#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID (0x20800aef) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID (0xEFU)
+
+typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS {
+    NvU8 logicalUprocId;
+} NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP
+ *
+ * This command is used by CPU-RM to perform memory operations using GSP
+ *
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_TIMEOUT_RETRY
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP (0x20800afa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_MEMMGR_MEMORY_OP {
+    NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0,
+    NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1,
+} NV2080_CTRL_MEMMGR_MEMORY_OP;
+
+typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO {
+    /*!
+     * Base physical address of the surface
+     */
+    NV_DECLARE_ALIGNED(NvU64 baseAddr, 8);
+
+    /*!
+     * Size of the surface in bytes
+     */
+    NV_DECLARE_ALIGNED(NvU64 size, 8);
+
+    /*!
+     * Offset in bytes into the surface where read/write must happen
+     */
+    NV_DECLARE_ALIGNED(NvU64 offset, 8);
+
+    /*!
+     * Aperture where the surface is allocated
+     */
+    NvU32 aperture;
+
+    /*!
+     * CPU caching attribute of the surface
+     */
+    NvU32 cpuCacheAttrib;
+} NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO;
+
+#define CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */
+
+#define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS {
+
+    /*!
+     * Source surface info
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8);
+
+    /*!
+     * Authentication tag if data is encrypted
+     */
+    NvU8                         authTag[CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES];
+
+    /*!
+     * Destination surface info
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO dst, 8);
+
+    /*!
+     * Size of the data to be transferred
+     */
+    NV_DECLARE_ALIGNED(NvU64 transferSize, 8);
+
+    /*!
+     * To be set in case of memset
+     */
+    NvU32                        value;
+
+    /*!
+     * Memory op to be performed
+     */
+    NV2080_CTRL_MEMMGR_MEMORY_OP memop;
+} NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to get local GPU's ATS config
+ *
+ *      addrSysPhys : [OUT]
+ *          System Physical Address
+ *      addrWidth   : [OUT]
+ *          Address width value
+ *      mask        : [OUT]
+ *          Mask value
+ *      maskWidth   : [OUT]
+ *          Mask width value
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG (0x20800afb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFBU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8);
+    NvU32 addrWidth;
+    NvU32 mask;
+    NvU32 maskWidth;
+} NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG
+ *
+ * This command is an internal command sent from Kernel RM to Physical RM
+ * to set peer ATS config using the parameters passed in.
+ *
+ *      peerId      : [IN]
+ *          Peer Id of the peer for which ATS config is to be programmed
+ *      addrSysPhys : [IN]
+ *          System Physical Address
+ *      addrWidth   : [IN]
+ *          Address width value
+ *      mask        : [IN]
+ *          Mask value
+ *      maskWidth   : [IN]
+ *          Mask width value
+ */
+#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG (0x20800afc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFCU)
+
+typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS {
+    NvU32 peerId;
+    NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8);
+    NvU32 addrWidth;
+    NvU32 mask;
+    NvU32 maskWidth;
+} NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO
+ *
+ * Get GPU EDPpeak Limit information
+ *
+ *   limitMin        [OUT]
+ *     Minimum allowed limit value on EDPp policy on both AC and DC
+ *   limitRated      [OUT]
+ *      Rated/default allowed limit value on EDPp policy on AC
+ *   limitMax        [OUT]
+ *     Maximum allowed limit value on EDPp policy on AC
+ *   limitCurr       [OUT]
+ *     Current resultant limit effective on EDPp policy on AC and DC
+ *   limitBattRated  [OUT]
+ *     Default/rated allowed limit on EDPp policy on DC
+ *   limitBattMax    [OUT]
+ *     Maximum allowed limit on EDPp policy on DC
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO (0x20800afd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID (0xFDU)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS {
+    NvU32 limitMin;
+    NvU32 limitRated;
+    NvU32 limitMax;
+    NvU32 limitCurr;
+    NvU32 limitBattRated;
+    NvU32 limitBattMax;
+} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA
+ *
+ * @brief Initialize/Destroy RM User Shared Data memory mapping on physical RM
+ *
+ * @param[in]  bInit    If this is an init or a destroy request
+ * @param[in]  physAddr Physical address of memdesc to link physical to kernel
+ *                      0 to de-initialize
+ *
+ * @return NV_OK on success
+ * @return NV_ERR_ otherwise
+ */
+#define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU)
+
+typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
+    NvBool bInit;
+    NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
+} NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL
+ *
+ * @brief Set mask of data to be polled on physical for RUSD
+ *
+ * @param[in]  polledDataMask Bitmask of data requested, defined in cl00de
+ * @param[in]  pollIntervalMs Requested polling interval, in ms
+ *
+ * @return NV_OK on success
+ * @return NV_ERR_ otherwise
+ */
+#define NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID (0xFFU)
+
+typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8);
+    NvU32 pollIntervalMs;
+} NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS
+ *
+ * This structure provides the params for starting GPU Fabric Probe
+ *
+ *  tracepointMask[IN]
+ *      - tracepoint selection filter
+ *  bufferAddr[IN]
+ *      - physical address of tracing buffer for VGPU
+ *  bufferSize[IN]
+ *      - size of gsp side logging buffer
+ *  bufferWatermark[IN]
+ *      - entry threshold for GSP to issue RPC of logged entries to kernel RM
+ *  flag[IN]
+ *      - indicates which operation to perform
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID (0xE3U)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8);
+    NV_DECLARE_ALIGNED(NvU64 bufferAddr, 8);
+    NvU32 bufferSize;
+    NvU32 bufferWatermark;
+    NvU8  flag;
+} NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS;
+
+/*!
+ * Macros for INTERNAL_CONTROL_GSP_TRACE flags for specific operation.
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST 0x00U
+#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST 0x01U
+#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP              0x02U
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE
+ *
+ * This command is used to start GSP-RM trace tool.
+ * This command accepts NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE                        (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES
+ *
+ * @brief get state (enabled/disabled) of SEC2 classes
+ *
+ *
+ * @return NV_OK on success
+ * @return NV_ERR_ otherwise
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID (0xAFU)
+
+typedef struct NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS {
+    NvBool bMaxwellSec2Enabled;
+    NvBool bNv95A1TsecEnabled;
+    NvBool bHopperSec2WorkLaunchAEnabled;
+} NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES (0x20800aaf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID" */
+
+
+/*!
+ * @ref NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND      (0x20800ae4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0xE4U)
+
+typedef NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS;
+
+/*!
+ * NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER
+ *
+ * @brief Notify the offloaded RM that CPU-RM enters the power management cycle.
+ *
+ *      bInPMTransition : [IN]
+ *      newPMLevel : [IN]
+ *          New PM Level : NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_[0-7]
+ *
+ * @return NV_OK on success
+ * @return NV_ERR_ otherwise
+ */
+#define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID (0xE9U)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS {
+    NvBool bInPMTransition;
+    NvU32  newPMLevel;
+} NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS;
+#define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER      (0x20800ae9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_RECOVERY
+ *
+ * This command is used to perform recovery actions after the fabric has been
+ * idled due to a fatal nvlink error.
+ * This command accepts no parameters.
+ *
+ *   bSuccessful
+ *     NV_TRUE if recovery was successful, NV_FALSE otherwise
+ */
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY (0x20800aea) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID (0xEAU)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS {
+    NvBool bSuccessful;
+} NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP
+ *
+ * @brief To get the free heap size of GSP-RM
+ *
+ *      freeHeapSize : [OUT]
+ *
+ * @return NV_OK
+ */
+#define NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID (0xEBU)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 freeHeapSize, 8);
+} NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP (0x20800aeb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM
+ *
+ * This command sets a new value for the specified Illumination control attribute.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0xECU)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS {
+    NvU32 attribute;
+    NvU32 value;
+} NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM (0x20800aecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR
+ *
+ * @brief NVIDIA RTX 5000 (GP180 SKU500) Windows-specific war
+ * to pull gpio19 (stereo pin) low for bug3362661.
+ *
+ *   [in] bApplyStereoPinAlwaysHiWar
+ *     If need to driver stereo pin(GPIO19) low(_IO_INPUT)
+ *
+ * @return NV_OK on success
+ * @return NV_ERR_ otherwise
+ */
+#define NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID (0xEDU)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS {
+    NvBool bApplyStereoPinAlwaysHiWar;
+} NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR (0x20800aed) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID" */
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM
+ *
+ * Returns the maximum number of HSHUBs in a shim instance.
+ *
+ *  maxHshubs[OUT]
+ *      The maximum number of HSHUBs in a shim instance.
+ *
+ *  @return NV_OK
+ */
+#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM        (0x20800a79) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID (0x79U)
+
+typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS {
+    NvU32 maxHshubs;
+} NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS;
+
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_MODE
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS {
+    NvU32 rasterSyncDecodeMode;
+} NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE (0x20800a14) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS
+ *
+ * This is an internal command sent from kernel-RM to physical-RM to retrieve GPU PF BAR1 SPA
+ * BAR1 SPA is required for BAR1 mapping in Direct NIC case for DMA(Direct Memory Access) of FB.
+ *
+ *  spaValue[OUT]
+ *      - BAR1 SPA of GPU PF
+ */
+#define NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID (0xEEU)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 spaValue, 8);
+} NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA       (0x20800aee) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER
+ *
+ * This command is used to enable RM NVLink enabled peer state.
+ * Note: This just updates the RM state. To reflect the state in the registers,
+ *       use NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER
+ *
+ * [in] peerMask
+ *     Mask of Peer IDs for which USE_NVLINK_PEER needs to be enabled
+ * [in] bEnable
+ *     Whether the bit needs to be set or unset
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the USE_NVLINK_PEER bit was enabled successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip, or
+ *     If unsetting USE_NVLINK_PEER bit is not supported
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER (0x20800a21U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID (0x21U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS {
+    NvU32  peerMask;
+    NvBool bEnable;
+} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS;
+
+/*
+ * NVLINK Link states
+ * These should ALWAYS match the nvlink core library defines in nvlink.h
+ */
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF                      0x00U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS                       0x01U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE                     0x02U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT                    0x03U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY                 0x04U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL                     0x05U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT                   0x06U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET                    0x07U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM                0x08U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM               0x09U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP                    0x0AU
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE               0x0BU
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE            0x0CU
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS                   0x0EU
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT       0x0FU
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE             0x10U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN            0x11U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP            0x12U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1               0x13U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE            0x14U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE       0x15U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE             0x16U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE        0x17U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT        0x18U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN                  0x19U
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL                   0x1AU
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5               0x1BU
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI                      0x1CU
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING           0x1DU
+#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID                  0xFFU
+
+/*
+ * NVLINK TX Sublink states
+ * These should ALWAYS match the nvlink core library defines in nvlink.h
+ */
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS                          0x00U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE                 0x04U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER                   0x04U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN                       0x05U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE                        0x06U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF                         0x07U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE                 0x08U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE         0x09U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY                  0x0AU
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ                          0x0BU
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN                     0x0CU
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS                     0x0DU
+
+/*
+ * NVLINK RX Sublink states
+ * These should ALWAYS match the nvlink core library defines in nvlink.h
+ */
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS                          0x00U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE                 0x04U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER                   0x04U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN                       0x05U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE                        0x06U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF                         0x07U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL                       0x08U
+#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM                   0x09U
+
+/*
+ * Link training seed values
+ * These should ALWAYS match the values defined in nvlink.h
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM                        6U
+#define NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE                (0x7U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM + 1" */
+
+// NVLINK callback types
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE      0x00U
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE      0x01U
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE      0x02U
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE      0x03U
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE   0x04U
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE   0x05U
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE   0x06U
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE   0x07U
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT 0x08U
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT 0x09U
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN 0x0AU
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN  0x0BU
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE     0x0CU
+#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD         0x0DU
+
+/*
+ * Structure to store the GET_DL_MODE callback params.
+ * mode
+ *     The current Nvlink DL mode
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS {
+    NvU32 mode;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS;
+
+/*
+ * Structure to store the SET_DL_LINK_MODE callback OFF params
+ * seedData
+ *     The output seed data
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS {
+    NvU32 seedData[NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE];
+} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS;
+
+/*
+ * Structure to store the SET_DL_LINK_MODE callback PRE_HS params
+ * remoteDeviceType
+ *     The input remote Device Type
+ * ipVerDlPl
+ *     The input DLPL version
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS {
+    NvU32 remoteDeviceType;
+    NvU32 ipVerDlPl;
+} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS;
+
+/*
+ * Structure to store SET_DL_LINK_MODE callback INIT_PHASE1 params
+ * seedData[]
+ *     The input seed data
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS {
+    NvU32 seedData[NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE];
+} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS;
+
+/*
+ * Structure to store the Nvlink Remote and Local SID info
+ * remoteSid
+ *     The output remote SID
+ * remoteDeviceType
+ *     The output remote Device Type
+ * remoteLinkId
+ *     The output remote link ID
+ * localSid
+ *     The output local SID
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO {
+    NV_DECLARE_ALIGNED(NvU64 remoteSid, 8);
+    NvU32 remoteDeviceType;
+    NvU32 remoteLinkId;
+    NV_DECLARE_ALIGNED(NvU64 localSid, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO;
+
+/*
+ * Structure to store the SET_DL_LINK_MODE callback POST_INITNEGOTIATE params
+ * bInitnegotiateConfigGood
+ *     The output bool if the config is good
+ * remoteLocalSidInfo
+ *     The output structure containing the Nvlink Remote/Local SID info
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS {
+    NvBool bInitnegotiateConfigGood;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS;
+
+/*
+ * Structure to store the SET_DL_LINK_MODE callback POST_INITOPTIMIZE params
+ * bPollDone
+ *     The output bool if the polling has finished
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS {
+    NvBool bPollDone;
+} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS;
+
+/*
+ * Structure to store the SET_DL_LINK_MODE callback params
+ * mode
+ *     The input nvlink state to set
+ * bSync
+ *     The input sync boolean
+ * linkMode
+ *     The input link mode to be set for the callback
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 mode, 8);
+    NvBool bSync;
+    NvU32  linkMode;
+    union {
+        NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS               linkModeOffParams;
+        NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS            linkModePreHsParams;
+        NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS       linkModeInitPhase1Params;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS linkModePostInitNegotiateParams, 8);
+        NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS linkModePostInitOptimizeParams;
+    } linkModeParams;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS;
+
+/*
+ * Structure to store the GET_TL_MODE callback params.
+ * mode
+ *     The current Nvlink TL mode
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS {
+    NvU32 mode;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS;
+
+/*
+ * Structure to store the SET_TL_LINK_MODE callback params
+ * mode
+ *     The input nvlink mode to set
+ * bSync
+ *     The input sync boolean
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 mode, 8);
+    NvBool bSync;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS;
+
+/*
+ * Structure to store the GET_RX/TX_SUBLINK_MODE callback params
+ * sublinkMode
+ *     The current Sublink mode
+ * sublinkSubMode
+ *     The current Sublink sub mode
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS {
+    NvU32 sublinkMode;
+    NvU32 sublinkSubMode;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS;
+
+/*
+ * Structure to store the SET_TL_LINK_MODE callback params
+ * mode
+ *     The input nvlink mode to set
+ * bSync
+ *     The input sync boolean
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 mode, 8);
+    NvBool bSync;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS;
+
+/*
+ * Structure to store the SET_RX_SUBLINK_MODE callback params
+ * mode
+ *     The input nvlink mode to set
+ * bSync
+ *     The input sync boolean
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 mode, 8);
+    NvBool bSync;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS;
+
+/*
+ * Structure to store the GET_RX_SUBLINK_DETECT callback params
+ * laneRxdetStatusMask
+ *     The output RXDET per-lane status mask
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS {
+    NvU32 laneRxdetStatusMask;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS;
+
+/*
+ * Structure to store the SET_RX_DETECT callback params
+ * bSync
+ *     The input bSync boolean
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS {
+    NvBool bSync;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS;
+
+/*
+ * Structure to store the RD_WR_DISCOVERY_TOKEN callback params
+ * ipVerDlPl
+ *     The input DLPL version
+ * token
+ *     The output token
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS {
+    NvU32 ipVerDlPl;
+    NV_DECLARE_ALIGNED(NvU64 token, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS;
+
+/*
+ * Structure to store the GET_UPHY_LOAD callback params
+ * bUnlocked
+ *     The output unlocked boolean
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS {
+    NvBool bUnlocked;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS;
+
+/*
+ * Structure to store the Union of Callback params
+ * type
+ *     The input type of callback to be executed
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE {
+    NvU8 type;
+    union {
+        NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS getDlLinkMode;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS setDlLinkMode, 8);
+        NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS getTlLinkMode;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS setTlLinkMode, 8);
+        NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getTxSublinkMode;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS setTxSublinkMode, 8);
+        NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getRxSublinkMode;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS setRxSublinkMode, 8);
+        NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS    getRxSublinkDetect;
+        NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS    setRxSublinkDetect;
+        NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS writeDiscoveryToken, 8);
+        NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS readDiscoveryToken, 8);
+        NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS    getUphyLoad;
+    } callbackParams;
+} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK
+ *
+ * Generic NvLink callback RPC to route commands to GSP
+ *
+ * [In] linkdId
+ *     ID of the link to be used
+ * [In/Out] callBackType
+ *     Callback params
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID (0x24U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS {
+    NvU32 linkId;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE callbackType, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK (0x20800a24U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID
+ *
+ * Update Remote and Local Sid info via GSP
+ *
+ * [In] linkId
+ *     ID of the link to be used
+ * [Out] remoteLocalSidInfo
+ *     The output structure containing the Nvlink Remote/Local SID info
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID (0x25U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS {
+    NvU32 linkId;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID (0x20800a25U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED
+ *
+ * Returns if ALI is enabled
+ *
+ * [Out] bEnableAli
+ *     Output boolean for ALI enablement
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x29U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS {
+    NvBool bEnableAli;
+} NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED           (0x20800a29U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM 0x0U
+#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET   0x1U
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX
+ *
+ * Generic Hshub Mux Update RPC to route commands to GSP
+ *
+ * [In] updateType
+ *     HSHUB Mux update type to program or reset Mux
+ * [In] bSysMem
+ *     Boolean to differentiate between sysmen and peer mem
+ * [In] peerMask
+ *     Mask of peer IDs. Only parsed when bSysMem is false
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID (0x42U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
+    NvBool updateType;
+    NvBool bSysMem;
+    NvU32  peerMask;
+} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX (0x20800a42U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER
+ *
+ * Performs all the necessary actions required before setting a peer on NVLink
+ *
+ * [In] peerId
+ *     Peer ID which will be set on NVLink
+ * [In] peerLinkMask
+ *     Mask of links that connects the given peer
+ * [In] bNvswitchConn
+ *     Is the GPU connected to NVSwitch
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x4EU)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
+    NvU32  peerId;
+    NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
+    NvBool bEgmPeer;
+    NvBool bNvswitchConn;
+} NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER (0x20800a4eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER
+ *
+ * Performs all the necessary actions required after setting a peer on NVLink
+ *
+ * [In] peerMask
+ *     Mask of Peer IDs which has been set on NVLink
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x50U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS {
+    NvU32 peerMask;
+} NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER (0x20800a50U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID
+ *
+ * Log an XID message to OOB.
+ *
+ * xid [in]
+ *   The XID number of the message.
+ *
+ * message [in]
+ *   The text message, including the NULL terminator.
+ *
+ * len [in]
+ *   The length, in bytes, of the text message, excluding the NULL terminator.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID                   (0x20800a56U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID" */
+
+#define NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE            (81U)
+
+#define NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID (0x56U)
+
+typedef struct NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS {
+    NvU32 xid;
+    NvU8  message[NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE];
+    NvU32 len;
+} NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS;
+
+#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U
+#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER   0x2U
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING
+ *
+ * Performs all the necessary actions required to remove NVLink mapping (sysmem or peer or both)
+ *
+ * [In] mapTypeMask
+ *     Remove NVLink mapping for the given map types (sysmem or peer or both)
+ * [In] peerMask
+ *     Mask of Peer IDs which needs to be removed on NVLink
+ *     Only parsed if mapTypeMask accounts peer
+ * [In] bL2Entry
+ *     Is the peer removal happening because links are entering L2 low power state?
+ *     Only parsed if mapTypeMask accounts peer
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID (0x5FU)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS {
+    NvU32  mapTypeMask;
+    NvU32  peerMask;
+    NvBool bL2Entry;
+} NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING (0x20800a5fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE
+ *
+ * Performs all the necessary actions required to save/restore HSHUB state during NVLink L2 entry/exit
+ *
+ * [In] bSave
+ *     Whether this is a save/restore operation
+ * [In] linkMask
+ *     Mask of links for which HSHUB config registers need to be saved/restored
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID (0x62U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS {
+    NvBool bSave;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK linkMask, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE (0x20800a62U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET        (0x00000000)
+#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE       (0x00000001)
+#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE    (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY
+ *
+ * Performs all the necessary actions required to save/restore bufferready state during NVLink L2 entry/exit
+ *
+ * [In] flags
+ *     Whether to set, save or restore bufferready
+ * [In] bSysmem
+ *     Whether to perform the operation for sysmem links or peer links
+ * [In] peerLinkMask
+ *     Mask of peer links for which bufferready state need to be set/saved/restored
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID (0x64U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS {
+    NvU32  flags;
+    NvBool bSysmem;
+    NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY (0x20800a64U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG
+ *
+ * Performs all the necessary actions required to update the current Nvlink configuration
+ *
+ * [out] bNvlinkSysmemEnabled
+ *     Whether sysmem nvlink support was enabled
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID (0x78U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS {
+    NvBool bNvlinkSysmemEnabled;
+} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG (0x20800a78U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK
+ *
+ * Synchronizes the peerLinkMask between CPU-RM and GSP-RM
+ *
+ * [In] gpuInst
+ *     Gpu instance
+ * [In] peerLinkMask
+ *     Mask of links to the given peer GPU
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID (0x7DU)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS {
+    NvU32 gpuInst;
+    NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK (0x20800a7dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION
+ *
+ * Updates the remote connection information for a link
+ *
+ * [In] linkId
+ *     Id of the link to be used
+ * [In] bConnected
+ *     Boolean that tracks whether the link is connected
+ * [In] remoteDeviceType
+ *     Tracks whether the remote device is switch/gpu/ibmnpu/tegra
+ * [In] remoteLinkNumber
+ *     Tracks the link number for the connected remote device
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x82U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8);
+    NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8);
+    NvU32  linkId;
+    NvU32  laneRxdetStatusMask;
+    NvU32  remoteLinkNumber;
+    NvU32  remotePciDeviceId;
+    NvU32  remoteDomain;
+    NvU8   remoteBus;
+    NvU8   remoteDevice;
+    NvU8   remoteFunction;
+    NvBool bConnected;
+} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION (0x20800a82U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY
+ *
+ * Enable links post topology via GSP
+ *
+ * [In]  linkMask
+ *     Mask of links to enable
+ * [Out] initializedLinks
+ *     Mask of links that were initialized
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID (0x83U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS {
+    NvU32 linkMask;
+    NvU32 initializedLinks;
+} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20800a83U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI
+ *
+ * [In] linkMask
+ *     Mask of enabled links to train
+ * [In] bSync
+ *     The input sync boolean
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x84U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS {
+    NvU32  linkMask;
+    NvBool bSync;
+} NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI (0x20800a84U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE           64
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET
+ *
+ * Get link mask post Rx detection
+ *
+ * [Out] postRxDetLinkMask
+ *     Mask of links discovered
+ * [Out] laneRxdetStatusMask
+ *     RXDET per-lane status mask
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID (0x85U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 postRxDetLinkMask, 8);
+    NvU32 laneRxdetStatusMask[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
+} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET (0x20800a85U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI
+ *
+ * [In] linkMask (This field will be deprecated in the future, please use links)
+ *     Mask of enabled links to train
+ * [In] links
+ *     Mask of enabled links to train
+ * [In] bSync
+ *     The input sync boolean
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x86U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS {
+    NvU32  linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NvBool bSync;
+} NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI (0x20800a86U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES {
+    NvBool bValid;
+    NvU8   linkId;
+    NvU32  ioctrlId;
+    NvU8   pllMasterLinkId;
+    NvU8   pllSlaveLinkId;
+    NvU32  ipVerDlPl;
+} NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES;
+
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_INVALID_TIME_MS 0
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO
+ *
+ * [Out] ioctrlMask
+ *    Mask of IOCTRLs discovered from PTOP device info table
+ * [Out] ioctrlNumEntries
+ *    Number of IOCTRL entries in the PTOP device info table
+ * [Out] ioctrlSize
+ *    Maximum number of entries in the PTOP device info table
+ * [Out] discoveredLinks
+ *    Mask of links discovered from all the IOCTRLs
+ * [Out] ipVerNvlink
+ *    IP revision of the NVLink HW
+ * [Out] maxSupportedLinks
+ *    Maximum number of links supported for a given arch
+ * [Out] linkInfo
+ *    Per link information
+ * [Out] probeRequestTimeMs
+ *    nominal time needed for a probe request
+ * [Out] linkStateChangeTimeMs
+ *    max amount of time needed for a link to transition states
+ */
+
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID (0x87U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS {
+    NvU32                                          ioctrlMask;
+    NvU8                                           ioctrlNumEntries;
+    NvU32                                          ioctrlSize;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK discoveredLinks, 8);
+    NvU32                                          ipVerNvlink;
+    NvU32                                          maxSupportedLinks;
+    NvU32                                          probeRequestTimeMs;
+    NvU32                                          linkStateChangeTimeMs;
+    NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS supportedCounterMask, 8);
+} NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO (0x20800a87U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW    6U
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES {
+    NvU32 ipVerIoctrl;
+    NvU32 ipVerMinion;
+} NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO
+ *
+ * [In] ioctrlIdx
+ *    IOCTRL index
+ * [Out] PublicId
+ *    PublicId of the IOCTRL discovered
+ * [Out] localDiscoveredLinks
+ *    Mask of discovered links local to the IOCTRL
+ * [Out] localGlobalLinkOffset
+ *    Global link offsets for the locally discovered links
+ * [Out] ioctrlDiscoverySize
+ *    IOCTRL table size
+ * [Out] numDevices
+ *    Number of devices discovered from the IOCTRL
+ * [Out] deviceIpRevisions
+ *    IP revisions for the devices discovered in the IOCTRL
+ */
+
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x8EU)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS {
+    NvU32                                                 ioctrlIdx;
+    NvU32                                                 PublicId;
+    NvU32                                                 localDiscoveredLinks;
+    NvU32                                                 localGlobalLinkOffset;
+    NvU32                                                 ioctrlDiscoverySize;
+    NvU8                                                  numDevices;
+    NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES ipRevisions;
+} NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO (0x20800a8eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED
+ *
+ * Program NVLink Speed from OS/VBIOS
+ *
+ * [In] bPlatformLinerateDefined
+ *    Whether line rate is defined in the platform
+ * [In] platformLineRate
+ *    Platform defined line rate
+ * [Out] nvlinkLinkSpeed
+ *    The line rate that was programmed for the links
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID (0x8FU)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS {
+    NvBool bPlatformLinerateDefined;
+    NvU32  platformLineRate;
+    NvU32  nvlinkLinkSpeed;
+} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED (0x20800a8fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED
+ *
+ * [In] linkMask
+ *     Mask of links whose state will be checked
+ * [In] bActiveOnly
+ *     The input boolean to check for Link Active state
+ * [Out] bIsLinkActive
+ *     Boolean array to track if the link is trained
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID (0x90U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK linkMask, 8);
+    NvBool bActiveOnly;
+    NvBool bIsLinkActive[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
+} NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED (0x20800a90U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT      (0x00000000)
+#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT    (0x00000001)
+#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE      (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS
+ *
+ * [In] linkMask
+ *     Mask of links which need to be reset
+ * [In] flags
+ *     Whether to assert, de-assert or toggle the Nvlink reset
+ */
+
+#define NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID (0x91U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS {
+    NvU32 linkMask;
+    NvU32 flags;
+} NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS (0x20800a91U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS
+ *
+ * [In] linkMask
+ *     Mask of links for which DL interrrupts need to be disabled
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID (0x92U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS {
+    NvU32 linkMask;
+} NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS (0x20800a92U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID" */
+
+/*
+ * Structure to store the GET_LINK_AND_CLOCK__INFO params
+ *
+ * [Out] bLinkConnectedToSystem
+ *     Boolean indicating sysmem connection of a link
+ * [Out] bLinkConnectedToPeer
+ *     Boolean indicating peer connection of a link
+ * [Out] bLinkReset
+ *     Whether the link is in reset
+ * [Out] subLinkWidth
+ *     Number of lanes per sublink
+ * [Out] linkState
+ *     Mode of the link
+ * [Out] txSublinkState
+ *     Tx sublink state
+ * [Out] rxSublinkState
+ *     Rx sublink state
+ * [Out] bLaneReversal
+ *     Boolean indicating if a link's lanes are reversed
+ * [Out] nvlinkLinkClockKHz
+ *     Link clock value in KHz
+ * [Out] nvlinkLineRateMbps
+ *     Link line rate in Mbps. This is on a per Lane Basis.
+ * [Out] nvlinkLinkClockMhz
+ *     Link clock in MHz
+ * [Out] nvlinkLinkDataRateKiBps
+ *     Link Data rate in KiBps. This is on a per Link Basis.
+ * [Out] nvlinkRefClkType
+ *     Current Nvlink refclk source
+ * [Out] nvlinkReqLinkClockMhz
+ *     Requested link clock value
+ * [Out] nvlinkMinL1Threshold
+ *     Requested link Min L1 Threshold
+ * [Out] nvlinkMaxL1Threshold
+ *     Requested link Max L1 Threshold
+ * [Out] nvlinkL1ThresholdUnits
+ *     Requested link L1 Threshold Units
+ * [Out] nvlpwIdx
+ *     Nvlpw Index for link
+ */
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
+    NvBool bLinkConnectedToSystem;
+    NvBool bLinkConnectedToPeer;
+    NvBool bLinkReset;
+    NvU8   subLinkWidth;
+    NvU32  linkState;
+    NvU32  txSublinkState;
+    NvU32  rxSublinkState;
+    NvBool bLaneReversal;
+    NvU32  nvlinkLinkClockKHz;
+    NvU32  nvlinkLineRateMbps;
+    NvU32  nvlinkLinkClockMhz;
+    NvU32  nvlinkLinkDataRateKiBps;
+    NvU8   nvlinkRefClkType;
+    NvU32  nvlinkReqLinkClockMhz;
+    NvU32  nvlinkMinL1Threshold;
+    NvU32  nvlinkMaxL1Threshold;
+    NvU32  nvlinkL1ThresholdUnits;
+    NvU32  nvlpwIdx;
+} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO
+ *
+ * [In] linkMask
+ *     Mask of enabled links to loop over
+ * [Out] enabledNvlpwMask
+ *     mask of nvlpw indices available
+ * [Out] nvlinkRefClkSpeedKHz
+ *     Ref clock value n KHz
+ * [Out] linkInfo
+ *     Per link information
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID (0x93U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV_DECLARE_ALIGNED(NvU64 enabledNvlpwMask, 8);
+    NvU32                                                 nvlinkRefClkSpeedKHz;
+    NvBool                                                bSublinkStateInst; // whether instantaneous sublink state is needed
+    NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
+} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO (0x20800a93U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM
+ *
+ * Updates the HSHUB sysmem config resgister state to reflect sysmem NVLinks
+ *
+ * [In] sysmemLinkMask
+ *     Mask of discovered sysmem NVLinks
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID (0x94U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS {
+    NvU32 sysmemLinkMask;
+} NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS;
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM (0x20800a94U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS
+ *
+ * Process NVLink forced configurations which includes setting of HSHUB and memory system
+ *
+ * [In] bLegacyForcedConfig
+ *     Tracks whether the forced config is legacy forced config or chiplib config
+ * [Out] bOverrideComputePeerMode
+ *     Whether compute peer mode was enabled
+ * [In] phase
+ *     Only applicable when bLegacyForcedConfig is true
+ *     Tracks the set of registers to program from the NVLink table
+ * [In] linkConnection
+ *     Array of chiplib configurations
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID (0x95U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS {
+    NvBool bLegacyForcedConfig;
+    NvBool bOverrideComputePeerMode;
+    NvU32  phase;
+    NvU32  linkConnection[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
+} NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS (0x20800a95U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS
+ *
+ * Sync the NVLink lane shutdown properties with GSP-RM
+ *
+ * [In] bLaneShutdownOnUnload
+ *     Whether nvlink shutdown should be triggered on driver unload
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID (0x96U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS {
+    NvBool bLaneShutdownOnUnload;
+} NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS (0x20800a96U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS
+ *
+ * Enable ATS functionality related to NVLink sysmem if hardware support is available
+ *
+ * [In] notUsed
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID (0x97U)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS {
+    NvU32 notUsed;
+} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS (0x20800a97U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK
+ *
+ *  Get the mask of Nvlink links connected to system
+ *
+ * [Out] sysmemLinkMask
+ *      Mask of Nvlink links connected to system
+ */
+#define NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID (0xABU)
+
+typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
+    NvU32 sysmemLinkMask;
+} NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20800aabU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO
+ *
+ *  Send CMC gsplite the address and size of log buffer allocated on sysmem
+ *
+ * [In] PublicId
+ *     ID of the gsplite engine
+ * [In] logBufferSize
+ *     Size of the log buffer allocated on sysmem
+ * [In] logBufferAddr
+ *     Start address of the log buffer
+ */
+#define NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID (0x89U)
+
+typedef struct NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS {
+    NvU32 PublicId;
+    NV_DECLARE_ALIGNED(NvU64 logBufferSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 logBufferAddr, 8);
+} NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO (0x20800a89U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_HFRP_INSTANCE_SIZE             5
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GPU_GET_HFRP_INFO
+ *
+ * This command retrives HFRP info from physical RM
+ *
+ * [Out] hfrpPrivBase
+ *      HFRP device PRIV base
+ * [Out] hfrpIntrCtrlReg
+ *      HFRP intr control base
+ *
+ */
+#define NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS_MESSAGE_ID (0x7AU)
+
+typedef struct NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS {
+    NvU32 hfrpPrivBase[NV2080_CTRL_INTERNAL_HFRP_INSTANCE_SIZE];
+    NvU32 hfrpIntrCtrlReg[NV2080_CTRL_INTERNAL_HFRP_INSTANCE_SIZE];
+} NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_HFRP_INFO (0x20800a7aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS
+ *
+ *  Send UMD API operations to CMC
+ *
+ * [in]  opType
+ *     UMD Task construct/destroy operation to perform on CMC
+ * [in]  flags
+ *     Additional flags depending on the operation type.
+ *     TASK_CONSTRUCT: Flags should be passed from CMC_UMD_API_ALLOCATION_PARAMETERS.
+ *     TASK_DESTROY: Currently unused.
+ * [in]  handle
+ *     Handle of CmcUmdApi object for CMC to identify
+ * [in]  ringBufferSize
+ *     Size of ring buffer in bytes
+ * [in]  ringBufferOffset
+ *     Offset of ring buffer
+ * [in]  userdPa
+ *     PA of USERD memory
+ * [in]  userdVa
+ *     VA of USERD memory
+ * [in] instBlkAddr
+ *     Address of instance block holding VASpace PDB info
+ * [in] instBlkAperture
+ *     Aperture of instance block
+ * [in] usermodeGpuVA
+ *     GPU VA offset of the usermode page
+ * [in] inputWorkSubmitToken
+ *     Work submit token for task
+ * [out] cmcWorkSubmitToken
+ *     WorkSubmitToken generated by CMC for UMD_API object
+ *
+ */
+#define NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS_MESSAGE_ID (0x7CU)
+
+typedef struct NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS {
+    NvU32 opType;
+    NvU32 flags;
+    NvU32 ringBufferSize;
+    NV_DECLARE_ALIGNED(NvU64 ringBufferOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 userdPa, 8);
+    NV_DECLARE_ALIGNED(NvU64 userdVa, 8);
+    NV_DECLARE_ALIGNED(NvU64 usermodeGpuVa, 8);
+    NV_DECLARE_ALIGNED(NvU64 instBlkAddr, 8);
+    NvU8  instBlkAperture;
+    NvU8  userdAperture;
+    NvU32 inputWorkSubmitToken;
+    NvU32 cmcWorkSubmitToken;
+    NvU32 cmcHandle;
+} NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS;
+
+#define NV2080_INTERNAL_CMC_UMD_API_TASK_CONSTRUCT                       0x0U
+#define NV2080_INTERNAL_CMC_UMD_API_TASK_DESTROY                         0x1U
+#define NV2080_INTERNAL_CMC_UMD_API_TASK_ADD_QUEUE                       0x2U
+
+#define NV2080_CTRL_CMD_INTERNAL_SEND_CMC_UMD_API_OP                     (0x20800a7cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS_MESSAGE_ID" */
+#include "ctrl/ctrl2080/ctrl2080fifo.h"             /* NV2080_CTRL_CMD_FIFO_ROTATE_KEYS */
+
+/*
+* NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS
+*
+* Request from CPU-RM to proccess supressed errors during boot on GSP
+* This command accepts no parameters.
+*/
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS         (0x20800b01U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x1" */
+
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2
+ */
+
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2 {
+    NvU32                                    smIssueRateModifierListSize;
+    NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE];
+} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x02U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierV2[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2 (0x20800b03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x03U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
+
+
+/*!
+ * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_THROTTLE_CTRL
+ *
+ * This command returns the throttle controls for all the GR engines.
+ *
+ */
+
+
+
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL {
+    NvU32                                 smIssueThrottleCtrlListSize;
+    NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL smIssueThrottleCtrlList[NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE];
+} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL;
+
+#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID (0x04U)
+
+typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS {
+    NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL smIssueThrottleCtrl[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
+} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL (0x20800b05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID (0x05U)
+
+typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY
+ *
+ * Set memory for use by the video event buffer
+ *
+ * memDescInfo
+ *  Information to set up memory descriptor on GSP
+ *
+ * engDesc
+ *  Video engdesc to find correct engine
+ *
+ * bEngineFound
+ *  Bool for whether or not the engine is actually assigned to a video object
+ */
+#define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY (0x20800b11) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO memDescInfo, 8);
+    NvU32  engDesc;
+    NvBool bEngineFound;
+} NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEY
+ *
+ * This command handles key rotation for a given channel
+ * by deriving new key on GSP and updating the key on relevant LCE.
+ * It also updates IVs for the channels using the key and conditionally re-enables them
+ * and notifies clients of key rotation status at the end.
+ *
+ *      pParams : [IN]
+ *          Rotation related information provided by client for triggering key rotation.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS (0x20800b07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS_PARAMS_MESSAGE_ID (0x07U)
+
+typedef NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS_PARAMS;
+
+
+
+/*!
+ * NV2080_CTRL_CMD_INTERNAL_NVLINK_RC_USER_MODE_CHANNELS
+ *
+ * This command is used to perform recovery actions after the fabric has been
+ * idled due to a fatal nvlink error.
+ * This command accepts no parameters.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_NVLINK_RC_USER_MODE_CHANNELS     (0x20800b08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x08" */
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES
+ *
+ * This command queries physical RM for the answers to
+ * NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS.
+ *
+ */
+#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES (0x20800b06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_MESSAGE_ID (0x06U)
+
+typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS {
+    NV_DECLARE_ALIGNED(NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS params, 8);
+} NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE
+ *
+ * Internal control to get instrumentation state from GSP-RM.
+ *
+ *   ucode                 [in]  Numeric ID of the ucode to query
+ *   gfid                  [in]  GFID for vGPU partitions
+ *   bEnabled              [out] Whether instrumentation is enabled
+ *   bClear                [out] Reserved
+ *   instrumentationType   [in]  Type of instrumentation (SanitizerCoverage or BullseyeCoverage)
+ */
+#define NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE (0x20800b12) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS {
+    NvU32  ucode;
+    NvU32  gfid;
+    NvBool bEnabled;
+    NvBool bClear;
+    NvU32  instrumentationType;
+} NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE
+ *
+ * Internal control to set instrumentation state on GSP-RM.
+ *
+ *   ucode                 [in]  Numeric ID of the ucode to control
+ *   gfid                  [in]  GFID for vGPU partitions
+ *   bEnabled              [in]  Whether to enable instrumentation
+ *   bClear                [in]  Whether to clear existing data
+ *   instrumentationType   [in]  Type of instrumentation (SanitizerCoverage or BullseyeCoverage)
+ */
+#define NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE (0x20800b13) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS {
+    NvU32  ucode;
+    NvU32  gfid;
+    NvBool bEnabled;
+    NvBool bClear;
+    NvU32  instrumentationType;
+} NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA
+ *
+ * Internal control to get instrumentation data from GSP-RM.
+ *
+ *   ucode                 [in]  Numeric ID of the ucode to retrieve data from
+ *   gfid                  [in]  GFID for vGPU partitions
+ *   offset                [in]  Byte offset into coverage data stream
+ *   instrumentationType   [in]  Type of instrumentation (SanitizerCoverage or BullseyeCoverage)
+ *   data                  [out] Buffer containing retrieved coverage data
+ *   dataSize              [out] Number of bytes written to data[] in this call
+ *   bComplete             [out] NV_TRUE when all data has been retrieved
+ */
+#define NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_MAX_DATA_SIZE 65536
+
+#define NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA  (0x20800b14) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS {
+    NvU32  ucode;
+    NvU32  gfid;
+    NvU32  offset;
+    NvU32  instrumentationType;
+    NvU8   data[NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_MAX_DATA_SIZE];
+    NvU32  dataSize;
+    NvBool bComplete;
+} NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS;
+
+/* ctrl2080internal_h */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080lpwr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080lpwr.h
new file mode 100644
index 0000000..707a256
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080lpwr.h
@@ -0,0 +1,100 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080lpwr.finn
+//
+
+
+
+/*!
+ * NV2080_CTRL_CMD_LPWR_DIFR_CTRL
+ *
+ * This command is used to control the DIFR
+ * feature behavior.
+ *
+ */
+#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL            (0x20802801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID" */
+
+/*!
+ * @brief Various Values for control
+ */
+// Disable the DIFR
+#define NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE        (0x00000001)
+// Enable the DIFR
+#define NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE         (0x00000002)
+
+// Support status for DIFR
+#define NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS (0x00000003)
+
+/*!
+ * Structure containing DIFR control call Parameters
+ */
+#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS {
+    NvU32 ctrlParamVal;
+} NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS;
+
+// Values for the SUPPORT Control Status
+#define NV2080_CTRL_LPWR_DIFR_SUPPORTED                          (0x00000001)
+#define NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED                      (0x00000002)
+
+/*!
+ * NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE
+ *
+ * This control call is used to send the prefetch response
+ *
+ */
+#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE              (0x20802802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID" */
+
+/*!
+ * @brief Various Values of Reponses for Prefetch Status
+ */
+
+// Prefetch is successfull.
+#define NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS                   (0x00000001)
+// OS Filps are enabled, so prefetch can not be done.
+#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED     (0x00000002)
+// Current Display surface can not fit in L2
+#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE (0x00000003)
+// Fatal and un recoverable Error
+#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR          (0x00000004)
+
+/*!
+ * Structure containing DIFR prefetch response control call Parameters
+ */
+#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS {
+    NvU32 responseVal;
+} NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS;
+
+
+// _ctrl2080lpwr_h_
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080mc.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080mc.h
new file mode 100644
index 0000000..e7339d3
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080mc.h
@@ -0,0 +1,368 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080mc.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "nvcfg_sdk.h"
+
+/* NV20_SUBDEVICE_XX mc control commands and parameters */
+
+/**
+ * NV2080_CTRL_CMD_MC_GET_ARCH_INFO
+ *
+ * This command returns chip architecture information from the
+ * master control engine in the specified GPU.
+ *
+ *   architecture
+ *       This parameter specifies the architecture level for the GPU.
+ *   implementation
+ *       This parameter specifies the implementation of the architecture
+ *       for the GPU.
+ *   revision
+ *       This parameter specifies the revision of the mask used to produce
+ *       the GPU.
+ *   subRevision
+ *       This parameter specific the sub revision of the GPU. Value is one of
+ *       NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_*
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_MC_GET_ARCH_INFO (0x20801701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
+    NvU32 architecture;
+    NvU32 implementation;
+    NvU32 revision;
+    NvU8  subRevision;
+} NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS;
+
+/* valid architecture values */
+
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X          (0xE0000023)
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100         (0x00000160)
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100         (0x00000170)
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100         (0x00000180)
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100         (0x00000190)
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100         (0x000001A0)
+
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200         (0x000001B0)
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GR100         (0x000001C0)
+
+
+
+/* valid ARCHITECTURE_T23X implementation values */
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234        (0x00000004)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D       (0x00000005)
+
+
+/* valid ARCHITECTURE_TU10x implementation values */
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100       (0x00000000)
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102       (0x00000002)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104       (0x00000004)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106       (0x00000006)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116       (0x00000008)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117       (0x00000007)
+
+
+/* valid ARCHITECTURE_GA10x implementation values */
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100       (0x00000000)
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102       (0x00000002)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103       (0x00000003)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104       (0x00000004)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106       (0x00000006)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107       (0x00000007)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B       (0x0000000B)
+
+
+/* valid ARCHITECTURE_GH10x implementation values */
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100       (0x00000000)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC   (0x00000001)
+
+/* valid ARCHITECTURE_AD10x implementation values */
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100       (0x00000000)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000       (0x00000001)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101       (0x00000001)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102       (0x00000002)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103       (0x00000003)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104       (0x00000004)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106       (0x00000006)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107       (0x00000007)
+/* valid ARCHITECTURE_GB10x implementation values */
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100       (0x00000000)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102       (0x00000002)
+
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB110       (0x00000003)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB112       (0x00000004)
+
+
+/* valid ARCHITECTURE_GB20x implementation values */
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200       (0x00000000)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202       (0x00000002)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203       (0x00000003)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205       (0x00000005)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206       (0x00000006)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207       (0x00000007)
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20B       (0x0000000B)
+
+
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20C       (0x0000000C)
+
+
+/* valid ARCHITECTURE_GR10x implementation values */
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GR100       (0x00000000)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GR102       (0x00000002)
+
+
+
+/* Valid Chip sub revisions */
+#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)
+#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P              (0x00000001)
+#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q              (0x00000002)
+#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R              (0x00000003)
+
+/*
+ * NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS
+ *
+ * This command instructs the RM to service interrupts for the specified
+ * engine(s).
+ *
+ *   engines
+ *       This parameter specifies which engines should have their interrupts
+ *       serviced.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS               (0x20801702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_ENGINE_ID_GRAPHICS                   0x00000001
+#define NV2080_CTRL_MC_ENGINE_ID_ALL                        0xFFFFFFFF
+
+#define NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS {
+    NvU32 engines;
+} NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS;
+
+
+/*
+ * NV2080_CTRL_CMD_MC_GET_MANUFACTURER
+ *
+ * This command returns the GPU manufacturer information for the associated
+ * subdevice.
+ *
+ *   manufacturer
+ *       This parameter returns the manufacturer value for the GPU.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_MC_GET_MANUFACTURER (0x20801703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS {
+    NvU32 manufacturer;
+} NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP
+ *
+ * This call will setup RM to either service or ignore the
+ * repayable fault interrupt.
+ * This is a privileged call that can only be called by the UVM driver
+ * when it will take ownership of the repalayable fault interrupt.
+ *
+ * Possible status values returned are:
+ *   NVOS_STATUS_SUCCESS
+ *   NVOS_STATUS_ERROR_INVALID_ARGUMENT
+ *   NVOS_STATUS_ERROR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP          (0x2080170c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS {
+    NvBool bOwnedByRm;
+} NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS
+ *
+ *  This command gets the notification interrupt vectors device for all VGPU engines from Host RM.
+ *
+ *  Parameters:
+ *
+ *    entries [out]
+ *      A buffer to store up to MAX_ENGINES entries of type
+ *      NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY.
+ *
+ *    numEntries [out]
+ *      Number of populated entries in the provided buffer.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ */
+#define NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS         (0x2080170d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES 256
+
+typedef struct NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY {
+    NvU32 nv2080EngineType;
+    NvU32 notificationIntrVector;
+} NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY;
+
+#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS {
+    NvU32                                                numEntries;
+    NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY entries[NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES];
+} NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS;
+
+/*
+ *  NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE
+ *
+ *  This command gets the static interrupts needed by VGPU from Host RM.
+ *
+ *  Parameters:
+ *
+ *    entries [out]
+ *      A buffer to store up to MAX_ENGINES entries of type
+ *      NV2080_CTRL_MC_STATIC_INTR_ENTRY.
+ *
+ *    numEntries [out]
+ *      Number of populated entries in the provided buffer.
+ *
+ *  Possible status values returned are:
+ *    NV_OK
+ */
+#define NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE    (0x2080170e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX    32
+
+// Interface defines for static MC_ENGINE_IDX defines
+#define NV2080_INTR_TYPE_NULL                       (0x00000000)
+#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT       (0x00000001)
+#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR (0x00000002)
+#define NV2080_INTR_TYPE_INFO_FAULT                 (0x00000003)
+#define NV2080_INTR_TYPE_REPLAYABLE_FAULT           (0x00000004)
+#define NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR     (0x00000005)
+#define NV2080_INTR_TYPE_ACCESS_CNTR                (0x00000006)
+#define NV2080_INTR_TYPE_TMR                        (0x00000007)
+#define NV2080_INTR_TYPE_CPU_DOORBELL               (0x00000008)
+#define NV2080_INTR_TYPE_GR0_FECS_LOG               (0x00000009)
+#define NV2080_INTR_TYPE_GR1_FECS_LOG               (0x0000000A)
+#define NV2080_INTR_TYPE_GR2_FECS_LOG               (0x0000000B)
+#define NV2080_INTR_TYPE_GR3_FECS_LOG               (0x0000000C)
+#define NV2080_INTR_TYPE_GR4_FECS_LOG               (0x0000000D)
+#define NV2080_INTR_TYPE_GR5_FECS_LOG               (0x0000000E)
+#define NV2080_INTR_TYPE_GR6_FECS_LOG               (0x0000000F)
+#define NV2080_INTR_TYPE_GR7_FECS_LOG               (0x00000010)
+
+typedef struct NV2080_CTRL_MC_STATIC_INTR_ENTRY {
+    NvU32 nv2080IntrType;
+    NvU32 pmcIntrMask;
+    NvU32 intrVectorStall;
+    NvU32 intrVectorNonStall;
+} NV2080_CTRL_MC_STATIC_INTR_ENTRY;
+
+#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS {
+    NvU32                            numEntries;
+    NV2080_CTRL_MC_STATIC_INTR_ENTRY entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX];
+} NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS;
+
+
+/*!
+ * Categories of interrupts.
+ *
+ * Each of these categories get a separate range of interrupt subtrees (top
+ * level bits) corresponding to a set of interrupt leaves.
+ * Interrupt leaves may overlap between two or more categories.
+ * Interrupt leaves may or may not be contiguous.
+ */
+typedef enum NV2080_INTR_CATEGORY {
+    NV2080_INTR_CATEGORY_DEFAULT = 0,
+    NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
+    NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
+    NV2080_INTR_CATEGORY_RUNLIST = 3,
+    NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
+    NV2080_INTR_CATEGORY_UVM_OWNED = 5,
+    NV2080_INTR_CATEGORY_UVM_SHARED = 6,
+    NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
+} NV2080_INTR_CATEGORY;
+
+#define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX
+
+typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
+    // Maximum possible 64 subtrees, but 16 is enough for any existing silicon.
+    NV_DECLARE_ALIGNED(NvU64 subtreeMask, 8);
+} NV2080_INTR_CATEGORY_SUBTREE_MAP;
+
+/*
+ *  NV2080_CTRL_CMD_MC_GET_INTR_CATEGORY_SUBTREE_MAP
+ *
+ *  This command gets a mapping from every interrupt category -> subtrees used from
+ *  Host RM.
+ */
+#define NV2080_CTRL_CMD_MC_GET_INTR_CATEGORY_SUBTREE_MAP (0x2080170f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT], 8);
+} NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS;
+
+/* _ctrl2080mc_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvd.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvd.h
new file mode 100644
index 0000000..0954acf
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvd.h
@@ -0,0 +1,385 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080nvd.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+#include "ctrl/ctrlxxxx.h"
+/*
+ * NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE
+ *
+ * This command gets the expected dump size of a particular GPU dump component.
+ * Note that events that occur between this command and a later
+ * NV2080_CTRL_CMD_NVD_GET_DUMP command could alter the size of
+ * the buffer required.
+ *
+ *   component
+ *     One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to estimate
+ *     the size of.
+ *   size
+ *     This parameter returns the expected size.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT if component is invalid.
+ *
+ */
+
+#define NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE (0x20802401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS {
+    NvU32 component;
+    NvU32 size;
+} NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVD_GET_DUMP
+ *
+ * This command gets a dump of a particular GPU dump component. If triggers
+ * is non-zero, the command waits for the trigger to occur
+ * before it returns.
+ *
+ *   pBuffer
+ *     This parameter points to the buffer for the data.
+ *  component
+ *     One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to select
+ *     for dumping.
+ *  size
+ *     On entry, this parameter specifies the maximum length for
+ *     the returned data. On exit, it specifies the number of bytes
+ *     returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_ERROR_INVALID_ARGUMENT if component is invalid.
+ *   NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid
+ *   NVOS_ERROR_INVALID_???? if the buffer was too small
+ *
+ *
+ */
+#define NV2080_CTRL_CMD_NVD_GET_DUMP (0x20802402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_NVD_GET_DUMP_PARAMS {
+    NV_DECLARE_ALIGNED(NvP64 pBuffer, 8);
+    NvU32 component;
+    NvU32 size;
+} NV2080_CTRL_NVD_GET_DUMP_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL
+ *
+ * This command returns the contents of the Journal used by  NOCAT, and
+ * optionally clears the data
+ *
+ *   clear:
+ *     [IN] indicates if should the data be cleared after reporting
+ *
+ *   JournalRecords :
+ *     [OUT] an array of Journal records reported.
+ *
+ *   outstandingAssertCount:
+ *     [OUT] number of asserts that remain to be reported on.
+ *
+ *   reportedAssertCount:
+ *     [OUT] the number of asserts contained in the report
+ *
+ *   asserts:
+ *     [OUT] an array of up to NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS assert reports
+ */
+
+
+#define NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL    (0x20802409) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER     1024
+#define NV2080_NOCAT_JOURNAL_MAX_STR_LEN         65
+#define NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS 10
+#define NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS  32
+
+// structure to hold clock details.
+typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS {
+    NvS32 userMinOffset;
+    NvS32 userMaxOffset;
+    NvU32 factoryMinOffset;
+    NvU32 factoryMaxOffset;
+    NvU32 lastActiveClock;
+    NvU32 lastActiveVolt;
+    NvU32 lastActivePoint;
+    NvU32 kappa;
+} NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS;
+
+
+// structure to hold clock configuration & state.
+typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG {
+    NvU32                                  pstateVer;
+    NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS gpcOverclock;
+    NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS mclkOverclock;
+    NvBool                                 bUserOverclocked;
+    NvBool                                 bFactoryOverclocked;
+} NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG;
+
+// structure to hold the GPU context at the time of the report.
+typedef struct NV2080_NOCAT_JOURNAL_GPU_STATE {
+    NvBool                             bValid;
+    NvU32                              strap;
+    NvU16                              deviceId;
+    NvU16                              vendorId;
+    NvU16                              subsystemVendor;
+    NvU16                              subsystemId;
+    NvU16                              revision;
+    NvU16                              type;
+    NvU32                              vbiosVersion;
+    NvBool                             bOptimus;
+    NvBool                             bMsHybrid;
+    NvBool                             bFullPower;
+    NvU32                              vbiosOemVersion;
+    NvU16                              memoryType;
+    NvU8                               tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU8                               vbiosProject[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvBool                             bInFullchipReset;
+    NvBool                             bInSecBusReset;
+    NvBool                             bInGc6Reset;
+    NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG overclockCfg;
+} NV2080_NOCAT_JOURNAL_GPU_STATE;
+
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN  0
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK 1
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE   2
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_TDR      3
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_RC       4
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT   5
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_ANY      6
+
+// this should be relative to the highest type value
+#define NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT    (0x7) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REC_TYPE_ANY + 1" */
+typedef struct NV2080_NOCAT_JOURNAL_ENTRY {
+    NvU8  recType;
+    NvU32 bugcheck;
+    NvU32 tdrBucketId;
+    NvU8  source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU32 subsystem;
+    NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
+    NvU32 diagBufferLen;
+    NvU8  diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER];
+    NvU8  faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU32 mmuFaultType;
+    NvU32 mmuErrorSrc;
+    NvU8  tdrReason[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+} NV2080_NOCAT_JOURNAL_ENTRY;
+
+typedef struct NV2080_NOCAT_JOURNAL_RECORD {
+    NvU32                          GPUTag;
+    NV_DECLARE_ALIGNED(NvU64 loadAddress, 8);
+    NV_DECLARE_ALIGNED(NvU64 timeStamp, 8);
+    NV_DECLARE_ALIGNED(NvU64 stateMask, 8);
+    NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState;
+    NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_ENTRY nocatJournalEntry, 8);
+} NV2080_NOCAT_JOURNAL_RECORD;
+
+// NOCAT activity counter indexes
+// collection activity
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX          0
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX 1
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX            2
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX            3
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX        4
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX    5
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX         6
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX       7
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX   8
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX  9
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX   10
+
+// Journal Lock activity
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX       11
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX 12
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX     13
+
+// lookup activity
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX           14
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX           15
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX          16
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX             17
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX        18
+
+// reporting activity
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX            19
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX             20
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX              21
+
+// update activity
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX           22
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX              23
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX        24
+
+// general errors
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX                 25
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX            26
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX             27
+
+// reserved entries for temporary use.
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX                 28
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX                 29
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX                 30
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX                 31
+
+// this should be relative to the highest counter index
+#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT            (0x20) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX + 1" */
+
+#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY         0:0
+#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES                       1
+#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO                        0
+
+#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS        1:1
+#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES                      1
+#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO                       0
+
+
+#define NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
+    NvU32 flags;
+    NvU32 nocatRecordCount;
+    NvU32 nocatOutstandingRecordCount;
+    NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_RECORD journalRecords[NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS], 8);
+    NvU32 activityCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT];
+    NvU8  reserved[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+} NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS;
+
+ /*
+ * NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA
+ *
+ * This command reports the TDR data collected by KMD to be added to the
+ * nocat record
+ *
+ *   dataType
+ *     [IN] specifies the type of data provided.
+ *  targetRecordType
+ *     [IN] specifies record type the data is intended for.
+ *  nocatJournalData
+ *     [IN] specifies the data to be added.
+ */
+
+#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA     (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */
+
+// data types & structures
+#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY      0
+#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1
+#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG    2
+#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG      3
+
+#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE                0
+#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY              1
+#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP            2
+#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET            3
+#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET           4
+#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL    5
+#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET         6
+#define NV2080_CTRL_NOCAT_TDR_TYPE_GPU_RC_RESET        7
+#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST                8
+
+typedef struct NV2080CtrlNocatJournalDataTdrReason {
+    NvU32 flags;
+    NvU8  source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU32 subsystem;
+    NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
+    NvU32 reasonCode;
+} NV2080CtrlNocatJournalDataTdrReason;
+
+#define NV2080_CTRL_NOCAT_TAG_CLEAR                 0:0
+#define NV2080_CTRL_NOCAT_TAG_CLEAR_YES 1
+#define NV2080_CTRL_NOCAT_TAG_CLEAR_NO  0
+typedef struct NV2080CtrlNocatJournalSetTag {
+    NvU32 flags;
+    NvU8  tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+} NV2080CtrlNocatJournalSetTag;
+
+typedef struct NV2080CtrlNocatJournalRclog {
+    NvU32 flags;
+    NvU32 rclogSize;        // rclog size
+    NvU32 rmGpuId;        // RMGpuId associated with the adapter
+    NvU32 APIType;        // API Type (dx9, dx1x, ogl, etc.)
+    NvU32 contextType;        // Context type (OGL, DX, etc.)
+    NvU32 exceptType;        // ROBUST_CHANNEL_* error identifier
+    NvU8  processImageName[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];    // process image name (without path)
+} NV2080CtrlNocatJournalRclog;
+
+#define NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS {
+    NvU32 dataType;
+    NvU32 targetRecordType;
+    union {
+        NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8);
+        NV2080CtrlNocatJournalSetTag tagData;
+        NV2080CtrlNocatJournalRclog  rclog;
+    } nocatJournalData;
+} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS;
+ /*
+ * NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD
+ *
+ * This command Inserts a NOCAT Journal record from an outside component. 
+ *
+ *  nocatJournalData
+ *     [IN] specifies the data to be added.
+ */
+
+#define NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD (0x2080240c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR         0:0
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES     1
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO      0
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER     1:1
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1
+#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO  0
+
+typedef struct NV2080CtrlNocatJournalInsertRecord {
+    NvU32 flags;
+    NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
+    NvU8  recType;
+    NvU32 bugcheck;
+    char  source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU32 subsystem;
+    NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
+    char  faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
+    NvU32 tdrReason;
+    NvU32 diagBufferLen;
+    NvU8  diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER];
+} NV2080CtrlNocatJournalInsertRecord;
+#define NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord nocatJournalRecord, 8);
+} NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS;
+/* _ctr2080nvd_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink.h
new file mode 100644
index 0000000..ba40f71
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink.h
@@ -0,0 +1,3520 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080nvlink.finn
+//
+
+#include "nvlimits.h"
+#include "nvfixedtypes.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080nvlink_common.h"
+#include "nvcfg_sdk.h"
+
+/* NV20_SUBDEVICE_XX bus control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS
+ *
+ * This command returns the NVLink capabilities supported by the subdevice.
+ *
+ *   capsTbl
+ *     This is bit field for getting different global caps. The individual bitfields are specified by NV2080_CTRL_NVLINK_CAPS_*
+ *   lowestNvlinkVersion
+ *     This field specifies the lowest supported NVLink version for this subdevice.
+ *   highestNvlinkVersion
+ *     This field specifies the highest supported NVLink version for this subdevice.
+ *   lowestNciVersion
+ *     This field specifies the lowest supported NCI version for this subdevice.
+ *   highestNciVersion
+ *     This field specifies the highest supported NCI version for this subdevice.
+ *   discoveredLinkMask // deprecated use discovered links
+ *     This field provides a bitfield mask of NVLink links discovered on this subdevice.
+ *   enabledLinkMask // deprecated use enabled Links
+ *     This field provides a bitfield mask of NVLink links enabled on this subdevice.
+ *   discoveredLinks
+ *     This field provides a bitfield mask of NVLink links discovered on this subdevice.
+ *   enabledLinks
+ *     This field provides a bitfield mask of NVLink links enabled on this subdevice.
+ *
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
+    NvU32 capsTbl;
+
+    NvU8  lowestNvlinkVersion;
+    NvU8  highestNvlinkVersion;
+    NvU8  lowestNciVersion;
+    NvU8  highestNciVersion;
+
+    NvU32 discoveredLinkMask;
+    NvU32 enabledLinkMask;
+
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK discoveredLinks, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK enabledLinks, 8);
+} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS;
+
+/* extract cap bit setting from tbl */
+#define NV2080_CTRL_NVLINK_GET_CAP(tbl,c)              (((NvU8)tbl[(1?c)]) & (0?c))
+
+/*
+ * NV2080_CTRL_NVLINK_CAPS
+ *
+ *   SUPPORTED
+ *     Set if NVLink is present and supported on this subdevice, NV_FALSE otherwise. This field is used for *global* caps only and NOT for per-link caps
+ *   P2P_SUPPORTED
+ *     Set if P2P over NVLink is supported on this subdevice, NV_FALSE otherwise.
+ *   SYSMEM_ACCESS
+ *     Set if sysmem can be accessed over NVLink on this subdevice, NV_FALSE otherwise.
+ *   PEER_ATOMICS
+ *     Set if P2P atomics are supported over NVLink on this subdevice, NV_FALSE otherwise.
+ *   SYSMEM_ATOMICS
+ *     Set if sysmem atomic transcations are supported over NVLink on this subdevice, NV_FALSE otherwise.
+ *   PEX_TUNNELING
+ *     Set if PEX tunneling over NVLink is supported on this subdevice, NV_FALSE otherwise.
+ *   SLI_BRIDGE
+ *     GLOBAL: Set if SLI over NVLink is supported on this subdevice, NV_FALSE otherwise.
+ *     LINK:   Set if SLI over NVLink is supported on a link, NV_FALSE otherwise.
+ *   SLI_BRIDGE_SENSABLE
+ *     GLOBAL: Set if the subdevice is capable of sensing SLI bridges, NV_FALSE otherwise.
+ *     LINK:   Set if the link is capable of sensing an SLI bridge, NV_FALSE otherwise.
+ *   POWER_STATE_L0
+ *     Set if L0 is a supported power state on this subdevice/link, NV_FALSE otherwise.
+ *   POWER_STATE_L1
+ *     Set if L1 is a supported power state on this subdevice/link, NV_FALSE otherwise.
+ *   POWER_STATE_L2
+ *     Set if L2 is a supported power state on this subdevice/link, NV_FALSE otherwise.
+ *   POWER_STATE_L3
+ *     Set if L3 is a supported power state on this subdevice/link, NV_FALSE otherwise.
+ *   VALID
+ *     Set if this link is supported on this subdevice, NV_FALSE otherwise. This field is used for *per-link* caps only and NOT for global caps.
+ *   UNCONTAINED_ERROR_RECOVERY
+ *     Set if this GPU supports resetless recovery from uncontained packet errors.
+ *
+ */
+
+/* caps format is byte_index:bit_mask */
+#define NV2080_CTRL_NVLINK_CAPS_SUPPORTED                          0:0x01
+#define NV2080_CTRL_NVLINK_CAPS_P2P_SUPPORTED                      0:0x02
+#define NV2080_CTRL_NVLINK_CAPS_SYSMEM_ACCESS                      0:0x04
+#define NV2080_CTRL_NVLINK_CAPS_P2P_ATOMICS                        0:0x08
+#define NV2080_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS                     0:0x10
+#define NV2080_CTRL_NVLINK_CAPS_PEX_TUNNELING                      0:0x20
+#define NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE                         0:0x40
+#define NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE_SENSABLE                0:0x80
+#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L0                     1:0x01
+#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L1                     1:0x02
+#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L2                     1:0x04
+#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L3                     1:0x08
+#define NV2080_CTRL_NVLINK_CAPS_VALID                              1:0x10
+#define NV2080_CTRL_NVLINK_CAPS_UNCONTAINED_ERROR_RECOVERY         1:0x20
+
+/*
+ * Size in bytes of nvlink caps table.  This value should be one greater
+ * than the largest byte_index value above.
+ */
+#define NV2080_CTRL_NVLINK_CAPS_TBL_SIZE               2U
+
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0     (0x00000001U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0     (0x00000002U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2     (0x00000004U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0     (0x00000005U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1     (0x00000006U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0     (0x00000007U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0     (0x00000008U)
+#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_6_0     (0x00000009U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID    (0x00000000U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0        (0x00000001U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0        (0x00000002U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2        (0x00000004U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0        (0x00000005U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1        (0x00000006U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0        (0x00000007U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0        (0x00000008U)
+#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_6_0        (0x00000009U)
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS         (0x20803001U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_NVLINK_DEVICE_INFO
+ *
+ * This structure stores information about the device to which this link is associated
+ *
+ *   deviceIdFlags
+ *      Bitmask that specifies which IDs are valid for the device
+ *      Refer NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_* for possible values
+ *      If NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI is set, PCI information is valid
+ *      If NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID is set, UUID is valid
+ *   domain, bus, device, function, pciDeviceId
+ *      PCI information for the device
+ *   deviceType
+ *      Type of the device
+ *      See NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_* for possible values
+ *   deviceUUID
+ *      This field specifies the device UUID of the device. Useful for identifying the device (or version)
+ *   fabricRecoveryStatusMask
+ *      This field contains flags which advertise the current GPU-centric health status of the NVLINKs
+ */
+typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO {
+    // ID Flags
+    NvU32 deviceIdFlags;
+
+    // PCI Information
+    NvU32 domain;
+    NvU16 bus;
+    NvU16 device;
+    NvU16 function;
+    NvU32 pciDeviceId;
+
+    // Device Type
+    NV_DECLARE_ALIGNED(NvU64 deviceType, 8);
+
+    // Device UUID
+    NvU8  deviceUUID[16];
+
+    // GPU-centric fabric health
+    NvU32 fabricRecoveryStatusMask;
+} NV2080_CTRL_NVLINK_DEVICE_INFO;
+
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS        31:0
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE                                            (0x00000000U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI                                             (0x00000001U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID                                            (0x00000002U)
+
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE                                             (0x00000000U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU                                                 (0x00000001U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU                                                 (0x00000002U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH                                              (0x00000003U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA                                               (0x00000004U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE                                                (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID                                             (0xFFFFFFFFU)
+
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED                      0:0
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE                  (0x00000000U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE                   (0x00000001U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY        1:1
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE (0x00000000U)
+#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE   (0x00000001U)
+
+/*
+ * NV2080_CTRL_NVLINK_NVLINK_LINK_STATUS_INFO
+ *
+ * This structure stores the per-link status of different NVLink parameters.
+ *
+ *   capsTbl
+ *     This is bit field for getting different global caps. The individual bitfields
+ *     are specified by NV2080_CTRL_NVLINK_CAPS_*
+ *   phyType
+ *     This field specifies the type of PHY (NVHS or GRS) being used for this link.
+ *   subLinkWidth
+ *     This field specifies the no. of lanes per sublink.
+ *   linkState
+ *     This field specifies the current state of the link.
+ *     See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_LINK_STATE_* for possible values.
+ *   rxSublinkStatus
+ *     This field specifies the current state of RX sublink.
+ *     See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_SUBLINK_RX_STATE_* for possible values.
+ *   txSublinkStatus
+ *     This field specifies the current state of TX sublink.
+ *     See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_SUBLINK_TX_STATE_* for possible values.
+ *   bLaneReversal
+ *     This field indicates that lane reversal is in effect on this link.
+ *   nvlinkVersion
+ *     This field specifies the NVLink version supported by the link.
+ *   nciVersion
+ *     This field specifies the NCI version supported by the link.
+ *   phyVersion
+ *     This field specifies the version of PHY being used by the link.
+ *   nvlinkLineRateMbps
+ *      Bit rate at which bits toggle on wires in megabits per second. This is on
+ *      a per Lane basis.
+ *      NOTE: This value is the full speed line rate, not the instantaneous line rate of the link.
+ *   nvlinkLinkClockMhz
+ *      Clock corresponding to link logic in mega hertz
+ *   nvlinkRefClkType
+ *      This field specifies whether the link clock is taken from NVHS reflck
+ *      or PEX refclk for the current GPU.
+ *   nvlinkLinkDataRateKiBps
+ *      Effective rate available for transactions after subtracting overhead,
+ *      as seen at Data Layer in kibibytes (1024 bytes) per second. This is on a
+ *      per Link basis.
+ *      Only valid in GA100+, reported as 0 otherwise
+ *      NOTE: Because minion calculates these values, it will only be valid if
+ *            links are in ACTIVE state
+ *   nvlinkRefClkSpeedMhz
+ *      The input reference frequency to the PLL
+ *   connected
+ *     This field specifies if any device is connected on the other end of the link
+ *   loopProperty
+ *     This field specifies if the link is a loopback/loopout link. See NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_* for possible values.
+ *   remoteDeviceLinkNumber
+ *     This field specifies the link number on the remote end of the link
+ *   remoteDeviceInfo
+ *     This field stores the device information for the remote end of the link
+ *   nvlinkMinL1Threshold
+ *     This field stores the Min L1 Thresohld of the link
+ *   nvlinkMaxL1Threshold
+ *     This field stores the Max L1 Threshold of the link
+ *   nvlinkL1ThresholdUnits
+ *     This field stores the L1 Threshold Units of the link
+ *   nvlpwIdx
+ *     This field stores the nvlpw index in use
+ *
+ */
+typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
+    // Top level capablilites
+    NvU32  capsTbl;
+
+    NvU8   phyType;
+    NvU8   subLinkWidth;
+
+    // Link and sublink states
+    NvU32  linkState;
+    NvU8   rxSublinkStatus;
+    NvU8   txSublinkStatus;
+
+    // Indicates that lane reversal is in effect on this link.
+    NvBool bLaneReversal;
+
+    NvU8   nvlinkVersion;
+    NvU8   nciVersion;
+    NvU8   phyVersion;
+
+    // Legacy clock information (to be deprecated)
+    NvU32  nvlinkLinkClockKHz;
+    NvU32  nvlinkCommonClockSpeedKHz;
+    NvU32  nvlinkRefClkSpeedKHz;
+
+    NvU32  nvlinkCommonClockSpeedMhz;
+
+    // Clock Speed and Data Rate Reporting
+    NvU32  nvlinkLineRateMbps;
+    NvU32  nvlinkLinkClockMhz;
+    NvU8   nvlinkRefClkType;
+    NvU32  nvlinkLinkDataRateKiBps;
+    NvU32  nvlinkRefClkSpeedMhz;
+
+    // Connection information
+    NvBool connected;
+    NvU8   loopProperty;
+    NvU8   remoteDeviceLinkNumber;
+    NvU8   localDeviceLinkNumber;
+
+    //
+    // Added as part of NvLink 3.0
+    // Note: SID has link info appended to it when provided by minion
+    //
+    NV_DECLARE_ALIGNED(NvU64 remoteLinkSid, 8);
+    NV_DECLARE_ALIGNED(NvU64 localLinkSid, 8);
+
+    // Ampere+ only
+    NvU32  laneRxdetStatusMask;
+
+    // L1 Threshold Info
+    NvU32  nvlinkMinL1Threshold;
+    NvU32  nvlinkMaxL1Threshold;
+    NvU32  nvlinkL1ThresholdUnits;
+
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO remoteDeviceInfo, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO localDeviceInfo, 8);
+
+    NvU32  nvlpwIdx;
+} NV2080_CTRL_NVLINK_LINK_STATUS_INFO;
+
+// NVLink link states
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT               (0x00000000U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG              (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG              (0x00000002U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE             (0x00000003U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT              (0x00000004U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP              (0x00000005U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY           (0x00000006U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC        (0x00000008U)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX        (0x0000000aU)
+#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID            (0xFFFFFFFFU)
+
+// NVLink Rx sublink states
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000U)
+// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE  (0x00000004) // Deprecated
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER    (0x00000004)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING     (0x00000005U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE    (0x00000006U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF          (0x00000007U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST         (0x00000008U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT        (0x0000000eU)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID      (0x000000FFU)
+
+// NVLink Tx sublink states
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000U)
+// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE  (0x00000004) // Deprecated
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER    (0x00000004)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING     (0x00000005U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE    (0x00000006U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF          (0x00000007U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST         (0x00000008U)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT        (0x0000000eU)
+#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID      (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_STATUS_PHY_NVHS                      (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_PHY_GRS                       (0x00000002U)
+#define NV2080_CTRL_NVLINK_STATUS_PHY_INVALID                   (0x000000FFU)
+
+// Version information
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0            (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0            (0x00000002U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2            (0x00000004U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0            (0x00000005U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1            (0x00000006U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0            (0x00000007U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0            (0x00000008U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_6_0            (0x00000009U)
+#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID        (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0               (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0               (0x00000002U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2               (0x00000004U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0               (0x00000005U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1               (0x00000006U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0               (0x00000007U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0               (0x00000008U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_6_0               (0x00000009U)
+#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID           (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0              (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID          (0x000000FFU)
+
+#define NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0               (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID           (0x000000FFU)
+
+// Connection properties
+#define NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE                (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE               (0x00000000U)
+
+#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK        (0x00000001U)
+#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT         (0x00000002U)
+#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE            (0x00000000U)
+
+#define NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID    (0x000000FFU)
+
+// L1 Threshold Units
+typedef enum NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT {
+    NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US = 0,
+    NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US = 1,
+} NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT;
+
+// NVLink REFCLK types
+#define NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U)
+#define NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS    (0x01U)
+#define NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX     (0x02U)
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS {
+    NvU32  enabledLinkMask; // (This field will be deprecated in the future, use enabledLinks)
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK enabledLinks, 8);
+    NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
+    NvBool bNvleModeEnabled; // whether Nvlink Encryption is enabled or not
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
+    NV_DECLARE_ALIGNED(NvU64 enabledNvlpwMask, 8);
+} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS
+ *
+ *   enabledLinkMask
+ *     This field specifies the mask of available links on this subdevice.
+ *   bNvleModeEnabled
+ *     This field indicates if Nvlink Encryption is enabled or not.
+ *   linkInfo
+ *     This structure stores the per-link status of different NVLink parameters. The link is identified using an index.
+ *   enabledNvlpwMask
+ *     This field specifics mask of Nvlpw indices available
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS (0x20803002U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_NVLINK_ERR_INFO
+ *   Error information per link
+ *
+ *   TLErrlog
+ *     Returns the error mask for NVLINK TL errors
+ *     Used in Pascal
+ *
+ *   TLIntrEn
+ *     Returns the intr enable mask for NVLINK TL errors
+ *     Used in Pascal
+ *
+ *   TLCTxErrStatus0
+ *     Returns the TLC Tx Error Mask 0
+ *     Used in Volta and later
+ *
+ *   TLCTxErrStatus1
+ *     Returns the TLC Tx Error Mask 1
+ *     Used in Ampere and later
+ *
+ *   TLCTxSysErrStatus0
+ *     Returns the TLC Tx Sys Error Mask 0
+ *     Used in Ampere and later.
+ *
+ *   TLCRxErrStatus0
+ *     Returns the TLC Rx Error Mask 0
+ *     Used in Volta and later
+ *
+ *   TLCRxErrStatus1
+ *     Returns the TLC Rx Error Mask 1
+ *     Used in Volta and later
+ *
+ *   TLCRxSysErrStatus0
+ *     Returns the TLC Rx Sys Error Mask 0
+ *     Used in Ampere and later.
+ *
+ *   TLCTxErrLogEn0
+ *     Returns the TLC Tx Error Log En 0
+ *     Used in Volta and later
+ *
+ *   TLCTxErrLogEn1
+ *     Returns the TLC Tx Error Log En 1
+ *     Used in Ampere and later
+ *
+ *   TLCTxSysErrLogEn0
+ *     Returns the TLC Tx Sys Error Log En 0
+ *     Used in Ampere and later
+ *
+ *   TLCRxErrLogEn0
+ *     Returns the TLC Rx Error Log En 0
+ *     Used in Volta and later
+ *
+ *   TLCRxErrLogEn1
+ *     Returns the TLC Rx Error Log En 1
+ *     Used in Volta and later
+ *
+ *   TLCRxSysErrLogEn0
+ *     Returns the TLC Rx Sys Error Log En 0
+ *     Used in Ampere and later
+ *
+ *   MIFTxErrStatus0
+ *     Returns the MIF Rx Error Mask 0
+ *     Used in Volta and Turing
+ *
+ *   MIFRxErrStatus0
+ *     Returns the MIF Tx Error Mask 0
+ *     Used in Volta and Turing
+ *
+ *   NVLIPTLnkErrStatus0
+ *     Returns the NVLIPT_LNK Error Mask 0
+ *     Used in Ampere and later
+ *
+ *   NVLIPTLnkErrLogEn0
+ *     Returns the NVLIPT_LNK Log En Mask 0
+ *     Used in Ampere and later
+ *
+ *   NVLIPTLnkCtrlLinkStateRequest
+ *     Returns the NVLIPT_LNK Control Link State Request value
+ *     Used in Ampere and later
+ *
+ *   DLSpeedStatusTx
+ *     Returns the NVLINK DL speed status for sublink Tx
+ *
+ *   DLSpeedStatusRx
+ *     Returns the NVLINK DL speed status for sublink Rx
+ *
+ *   NVLDLRxSlsmErrCntl
+ *     Returns the NVLDL_RXSLSM_ERR_CNTL value
+ *     Used in Hopper and later
+ *
+ *   NVLDLTopLinkState
+ *     Returns the NVLDL_TOP_LINK_STATE value
+ *     Used in Hopper and later
+ *
+ *   NVLDLTopIntr
+ *     Returns the NVLDL_TOP_INTR value
+ *     Used in Hopper and later
+ *
+ *   DLStatMN00
+ *     Returns the DLSTAT MN00 Code and subcode
+ *     Used in Hopper and later
+ *
+ *   DLStatUC01
+ *     Returns the DLSTAT UC01 value
+ *     Used in Hopper and later
+ *
+ *   MinionNvlinkLinkIntr
+ *     Returns the MINION_NVLINK_LINK_INTR code and subcode
+ *     Used in Hopper and later
+ *
+ *   bExcessErrorDL
+ *     Returns true for excessive error rate interrupt from DL
+ */
+typedef struct NV2080_CTRL_NVLINK_ERR_INFO {
+    NvU32  TLErrlog;
+    NvU32  TLIntrEn;
+    NvU32  TLCTxErrStatus0;
+    NvU32  TLCTxErrStatus1;
+    NvU32  TLCTxSysErrStatus0;
+    NvU32  TLCRxErrStatus0;
+    NvU32  TLCRxErrStatus1;
+    NvU32  TLCRxSysErrStatus0;
+    NvU32  TLCTxErrLogEn0;
+    NvU32  TLCTxErrLogEn1;
+    NvU32  TLCTxSysErrLogEn0;
+    NvU32  TLCRxErrLogEn0;
+    NvU32  TLCRxErrLogEn1;
+    NvU32  TLCRxSysErrLogEn0;
+    NvU32  MIFTxErrStatus0;
+    NvU32  MIFRxErrStatus0;
+    NvU32  NVLIPTLnkErrStatus0;
+    NvU32  NVLIPTLnkErrLogEn0;
+    NvU32  NVLIPTLnkCtrlLinkStateRequest;
+    NvU32  DLSpeedStatusTx;
+    NvU32  DLSpeedStatusRx;
+    NvU32  NVLDLRxSlsmErrCntl;
+    NvU32  NVLDLTopLinkState;
+    NvU32  NVLDLTopIntr;
+    NvU32  DLStatMN00;
+    NvU32  DLStatUC01;
+    NvU32  MinionNvlinkLinkIntr;
+    NvBool bExcessErrorDL;
+} NV2080_CTRL_NVLINK_ERR_INFO;
+
+/*
+ * NV2080_CTRL_NVLINK_COMMON_ERR_INFO
+ *   Error information per IOCTRL
+ *
+ *   NVLIPTErrStatus0
+ *     Returns the NVLIPT_COMMON Error Mask 0
+ *     Used in Ampere and later
+ *
+ *   NVLIPTErrLogEn0
+ *     Returns the NVLIPT_COMMON Log En Mask 0
+ *     Used in Ampere and later
+ */
+typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO {
+    NvU32 NVLIPTErrStatus0;
+    NvU32 NVLIPTErrLogEn0;
+} NV2080_CTRL_NVLINK_COMMON_ERR_INFO;
+
+/* Extract the error status bit for a given TL error index i */
+#define NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i)       (((1U << i) & (intr)) >> i)
+
+/* Extract the intr enable bit for a given TL error index i */
+#define NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT(intr, i)        NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i)
+
+/* Error status values for a given NVLINK TL error */
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE                               (0x00000001U)
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE                              (0x00000000U)
+
+/* Intr enable/disable for a given NVLINK TL error */
+#define NV2080_CTRL_NVLINK_TL_INTEN_TRUE                                (0x00000001U)
+#define NV2080_CTRL_NVLINK_TL_INTEN_FALSE                               (0x00000000U)
+
+/* NVLINK TL interrupt enable fields for errors */
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN                0U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN                1U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN                    2U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN                    3U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN               4U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN                5U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN                        6U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN                      7U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN               8U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN                9U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN                  10U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN                   12U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN                      13U
+#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX                             14U
+
+/* NVLINK TL error fields */
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR              0U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR              1U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR                  2U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR                  3U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR             4U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR              5U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR                      6U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR                    7U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR             8U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR              9U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR                10U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR                 12U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR                    13U
+#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX                            14U
+
+/* NVLINK DL speed status for sublink Tx*/
+#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS          (0x00000000U)
+#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE (0x00000004U)
+#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN       (0x00000005U)
+#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE        (0x00000006U)
+#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF         (0x00000007U)
+
+/* NVLINK DL speed status for sublink Rx*/
+#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS          (0x00000000U)
+#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE (0x00000004U)
+#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN       (0x00000005U)
+#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE        (0x00000006U)
+#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF         (0x00000007U)
+
+/* Flags to query different debug registers */
+#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT                       (0x0U)
+#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS                   (0x1U)
+#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS                    (0x2U)
+
+#define NV2080_CTRL_NVLINK_MAX_IOCTRLS                                  3U
+/*
+ *   NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS
+ *
+ *   linkMask (This field will be deprecated in the future, please use links)
+ *     Returns the mask of links enabled
+ *
+ *   links
+ *     Returns the mask of links enabled
+ *
+ *   linkErrInfo
+ *     Returns the error information for all the links
+ *
+ *   ioctrlMask
+ *     Returns the mask of ioctrls
+ *
+ *   commonErrInfo
+ *     Returns the error information common to each IOCTRL
+ *
+ *   ErrInfoFlags
+ *     Input for determining which values to query. Possible values:
+ *     NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS
+ *     NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS
+ *
+ */
+#define NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS {
+    NvU32                              linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV2080_CTRL_NVLINK_ERR_INFO        linkErrInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
+    NvU32                              ioctrlMask;
+    NV2080_CTRL_NVLINK_COMMON_ERR_INFO commonErrInfo[NV2080_CTRL_NVLINK_MAX_IOCTRLS];
+    NvU8                               ErrInfoFlags;
+} NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO
+ *     This command is used to query the NVLINK error information
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO                 (0x20803003U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * APIs for getting NVLink counters
+ */
+
+// These are the bitmask definitions for different counter types
+
+#define NV2080_CTRL_NVLINK_COUNTER_INVALID                  0x00000000U
+
+#define NV2080_CTRL_NVLINK_COUNTER_TL_TX0                   0x00000001U
+#define NV2080_CTRL_NVLINK_COUNTER_TL_TX1                   0x00000002U
+#define NV2080_CTRL_NVLINK_COUNTER_TL_RX0                   0x00000004U
+#define NV2080_CTRL_NVLINK_COUNTER_TL_RX1                   0x00000008U
+
+#define NV2080_CTRL_NVLINK_LP_COUNTERS_DL                   0x00000010U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L(i)      (1 << (i + 8))
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE 4U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0    0x00000100U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1    0x00000200U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2    0x00000400U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3    0x00000800U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT       0x00010000U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i)      (1 << (i + 17))
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE 8U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0    0x00020000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1    0x00040000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2    0x00080000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3    0x00100000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4    0x00200000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5    0x00400000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6    0x00800000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7    0x01000000U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY         0x02000000U
+#define NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY       0x04000000U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY         0x08000000U
+
+#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED     0x10000000U
+
+/*
+ * Note that COUNTER_MAX_TYPES will need to be updated each time
+ * a new counter type gets added to the list above.
+ *
+ */
+#define NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES                32U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_COUNTERS
+ *  This command gets the counts for different counter types.
+ *
+ * [in] counterMask
+ *     Mask of counter types to be queried
+ *     One of NV2080_CTRL_NVLINK_COUNTERS_TYPE_* macros
+ *
+ * [in] linkMask (This field will be deprecated in the future, please use links)
+ *     Mask of links to be queried
+ *
+ * [in] links
+ *     Mask of links to be queried
+ *
+ * [out] counters
+ *     Counter value returned
+ *
+ * [out] bTx0TlCounterOverflow
+ *  This boolean is set to NV_TRUE if TX Counter 0 has rolled over.
+ *
+ * [out] bTx1TlCounterOverflow
+ *  This boolean is set to NV_TRUE if TX Counter 1 has rolled over.
+ *
+ * [out] bRx0TlCounterOverflow
+ *  This boolean is set to NV_TRUE if RX Counter 0 has rolled over.
+ *
+ * [out] bRx1TlCounterOverflow
+ *  This boolean is set to NV_TRUE if RX Counter 1 has rolled over.
+ *
+ * [out] value
+ *  This array contains the error counts for each error type as requested from
+ *  the counterMask. The array indexes correspond to the mask bits one-to-one.
+ */
+typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES {
+    NvBool bTx0TlCounterOverflow;
+    NvBool bTx1TlCounterOverflow;
+    NvBool bRx0TlCounterOverflow;
+    NvBool bRx1TlCounterOverflow;
+    NV_DECLARE_ALIGNED(NvU64 value[NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES], 8);
+} NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES;
+
+#define NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS {
+    NvU32 counterMask;
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
+} NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS   (0x20803004U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID" */
+
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS
+ *  This command clears/resets the counters for the specified types.
+ *
+ * [in] linkMask (This field will be deprecated in the future, please use links)
+ *  This parameter specifies for which links we want to clear the
+ *  counters.
+ *
+ * [in] links
+ *  This parameter specifies for which links we want to clear the
+ *  counters.
+ *
+ * [in] counterMask
+ *  This parameter specifies the input mask for desired counters to be
+ *  cleared. Note that all counters cannot be cleared.
+ *
+ *  NOTE: Bug# 2098529: On Turing all DL errors and LP counters are cleared
+ *        together. They cannot be cleared individually per error type. RM
+ *        would possibly move to a new API on Ampere and beyond
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS (0x20803005U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
+    NvU32 counterMask;
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS;
+
+
+#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0                                  0U
+#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1                                  1U
+#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0                                  2U
+#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1                                  3U
+
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE                4U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0                  4U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1                  5U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2                  6U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3                  7U
+
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE                8U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0                  8U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1                  9U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2                  10U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3                  11U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4                  12U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5                  13U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6                  14U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7                  15U
+
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY                     16U
+
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY                       17U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY                       18U
+
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED                   19U
+#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT                     20U
+
+#define NV2080_CTRL_NVLINK_COUNTER_LP_DL                                      21U
+
+#define NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER NV2080_CTRL_NVLINK_COUNTER_LP_DL
+
+/* Transmit Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS                               22U
+#define NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES                                 23U
+/* Received Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS                                24U
+#define NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES                                  25U
+/* Link Events */
+#define NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER                26U
+#define NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER                        27U
+#define NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER           28U
+/* Link Receive Errors */
+#define NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS                                 29U
+#define NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS                          30U
+#define NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS                         31U
+/* Link Receive Errors Detail */
+#define NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR                    32U
+#define NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR                   33U
+#define NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR                      34U
+/* Link Other Errors Detail */
+#define NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS                      35U
+#define NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS                      36U
+/* Link Transmit Errors */
+#define NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME                             37U
+#define NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS                                38U
+/* FEC Block Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS                        39U
+#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS                           40U
+#define NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS                         41U
+/* FEC Symbol Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0                   42U
+#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1                   43U
+#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL                    44U
+/* FEC Raw Error Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0                          45U
+#define NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1                          46U
+#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS                             47U
+/* FEC Raw BER */
+#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0                             48U
+#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1                             49U
+#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL                              50U
+/* FEC Effective BER */
+#define NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS                            51U
+#define NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS                           52U
+#define NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER                              53U
+/* Phy Symbol Errors Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS                              54U
+#define NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER                                 55U
+#define NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS                              56U
+/* Phy Other Errors Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS                         57U
+#define NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR                      58U
+/* PLR Receive Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS                             59U
+#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS   60U
+#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS                 61U
+/* PLR Transmit Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS                            62U
+#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS                      63U
+#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS                      64U
+/* PLR BW Loss Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS                                65U
+/* NVLE Rx counters */
+#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD                               66U
+#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR                              67U
+#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH                               68U
+/* NVLE Tx Counters */
+#define NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD                               69U
+#define NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR                              70U
+/* FEC Histogram */
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_0                                  71U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_1                                  72U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_2                                  73U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_3                                  74U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_4                                  75U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_5                                  76U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_6                                  77U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_7                                  78U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_8                                  79U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_9                                  80U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_10                                 81U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_11                                 82U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_12                                 83U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_13                                 84U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_14                                 85U
+#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_15                                 86U
+
+/* Throughput counters */
+#define NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA                                 87U
+#define NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA                                 88U
+#define NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW                                  89U
+#define NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW                                  90U
+
+/* Low power counters */
+#define NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY                                   91U
+#define NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE                             92U
+#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT                                    93U
+#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL                              94U
+#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE                             95U
+#define NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME                    96U
+#define NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME            97U
+#define NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME                        98U
+#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME                        99U
+#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME                         100U
+#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME                101U
+#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME                 102U
+#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME                       103U
+#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME                        104U
+#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME               105U
+#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME                106U
+
+#define NV2080_CTRL_NVLINK_COUNTER_PLR_LAST_RAW_BER                           107U
+#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS_WITHIN_T_SEC_MAX_LOW 108U
+#define NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ENTRY                           109U
+#define NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ENTRY_DUE_TO_L1                 110U
+#define NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_REQ_NOT_YET_ACTIVE              111U
+#define NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ACTIVE_DUE_TO_L1_REQ            112U
+#define NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ACTIVE                          113U
+
+#define NV2080_CTRL_NVLINK_COUNTERS_MAX                                       114U
+
+#define NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS                                 2U
+#define NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ               28
+#define NV2080_CTRL_NVLINK_COUNTER_V2_GROUP(i)  ((i) / 64)
+#define NV2080_CTRL_NVLINK_COUNTER_V2_COUNTER_MASK(i) ((NvU64)1 << ((i) % 64))
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2
+ *  This command gets the counts for different counter types.
+ *
+ * [in] linkMask (This field will be deprecated in the future, please use links)
+ *     Mask of links to be queried
+ *
+ * [in] links
+ *     Mask of links to be queried
+ *
+ * [in] counterMask
+ *     Mask of counter types to be queried
+ *     One of NV2080_CTRL_NVLINK_COUNTERS_TYPE_* macros
+ *
+ * [out] counter
+ *     This array contains the error counts for each error type as requested from
+ *     the counterMask. The array indexes correspond to the mask bits one-to-one.
+ */
+
+typedef struct NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES {
+    NvBool overFlow;
+    NV_DECLARE_ALIGNED(NvU64 value, 8);
+} NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES;
+
+#define NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID (0x50U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES counter[NV2080_CTRL_NVLINK_MAX_ARR_SIZE][NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ], 8);
+} NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 (0x20803050U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID)" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2
+ *  This command clears/resets the counters for the specified types.
+ *
+ * [in] linkMask (This field will be deprecated in the future, please use links)
+ *  This parameter specifies for which links we want to clear the
+ *  counters.
+ *
+ * [in] links
+ *  This parameter specifies for which links we want to clear the
+ *  counters.
+ *
+ * [in] counterMask
+ *  This parameter specifies the input mask for desired counters to be
+ *  cleared. Note that all counters cannot be cleared.
+*/
+
+#define NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID (0x51U)
+
+typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
+} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 (0x20803051U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID)" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_INJECT_ERROR
+ *  This command causes all the same actions to occur as if the related
+ *  error were to occur, either fatal or recoverable.
+ *
+ * [in] linkMask (This field will be deprecated in the future, please use links)
+ *  Controls which links to apply error injection to.
+ *
+ * [in] links
+ *  Controls which links to apply error injection to.
+ *
+ * [in] bFatal
+ *  This parameter specifies that the error should be fatal.
+ *
+ */
+#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR      (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS {
+    NvU32  linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NvBool bFatalError;
+} NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS;
+
+/* NVLINK unit list - to be used with error notifiers */
+#define NV2080_CTRL_NVLINK_UNIT_DL       0x01U
+#define NV2080_CTRL_NVLINK_UNIT_TL       0x02U
+#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 0x03U
+#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 0x04U
+#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 0x05U
+#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 0x06U
+#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 0x07U
+#define NV2080_CTRL_NVLINK_UNIT_MINION   0x08U
+
+/*
+ * NV2080_CTRL_NVLINK_ERROR_INJECT_CFG
+ *
+ * [in] errType
+ *  This parameter specifies the type of error injection settings
+ * [in] errSettings
+ *  This parameter specifies the settings for the error type in NVL5
+ */
+
+typedef enum NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE {
+    NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR = 1,
+    NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR = 2,
+    NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR = 3,
+    NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR = 4,
+    NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX = 5,
+} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE;
+
+typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG {
+    NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE errType;
+    NV_DECLARE_ALIGNED(NvU64 errSettings, 8);
+} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG;
+
+/*
+ * Tx error type settings
+ */
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE                                  31:28
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR                   0x00000000U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER                    0x00000001U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER              0x00000002U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_ERR_INJECT_DURATION                   27:12 // Error Injection Duration, in 10ms units.
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_MANTISSA                           11:8
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_EXPONENT                            7:0
+
+/*
+ * Packet error type settings
+ */
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_INJECT_COUNT                          15:0
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP                                16:16
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS                      0x00000000U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN                       0x00000001U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON                               17:17
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS                     0x00000000U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN                      0x00000001U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_CLEAR_COUNTERS                       18:18
+
+/*
+ * Authentication error type settings
+ */
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_PIPE_INDEX                        3:0
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR                          4:4
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS              0x00000000U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN               0x00000001U
+
+/*
+ * Link Error type settings
+ */
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN                       0:0
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS           0x00000000U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN            0x00000001U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT
+ *  This command causes all the same actions to occur as if the related
+ *  error were to occur, either fatal or recoverable.
+ *
+ * [in] linkMask        size: 64 bits (This field will be deprecated in the future, please use links)
+ *  Mask of the links to be configured.
+ *
+ * [in] links
+ *  Mask of the links to be configured.
+ *
+ * [in] errCfg
+ *  This parameter specifies that the error configurations.
+ */
+
+#define NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID (0x81U)
+
+typedef struct NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG errCfg[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
+} NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT (0x20803081U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE                             1:0
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP                  0x00000000U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST     0x00000001U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR      0x00000002U
+
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS                               0:0
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT         0x00000000U
+#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT 0x00000001U
+
+/*
+ * NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO
+ *
+ * [out] txErrInfo
+ *  This info specifies the settings for Tx errs in NVL5
+ * [out] packetErrSettings
+ *  This info specifies the settings for Pkt errs in NVL5
+ * [out] authErrSettings
+ *  This info specifies the settings for NVLE errs in NVL5
+ * [out] linkStatus
+ *  This specifies the status of the link in NVL5
+ * [out] errInjectStatus
+ *  This specifies the status of error injection
+ */
+
+typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO {
+    NvU32 txErrInfo;
+    NvU32 packetErrInfo;
+    NvU32 authErrInfo;
+    NvU32 linkStatus;
+    NvU32 errInjectStatus;
+} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT
+ *  This command get all the current nvlink error config
+ *
+ * [in] linkMask        size: 64 bits (This field will be deprecated in the future, please use links)
+ *  Mask of the links to be configured.
+ *
+ * [in] links
+ *  Mask of the links to be configured.
+ *
+ * [in] errCfg
+ *  This parameter specifies that the error configurations.
+ */
+
+#define NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID (0x82U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO errInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
+} NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT  (0x20803082U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES
+ *  This command gets the number of successful error recoveries
+ *
+ * [in]  linkMask        size: 32 bits (This field will be deprecated in the future, please use links)
+ *    This parameter controls which links to get recoveries for.
+ *
+ * [in]  links
+ *    This parameter controls which links to get recoveries for.
+ *
+ * [out] numRecoveries
+ *    This parameter specifies the number of successful per link error recoveries
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES (0x20803007U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS {
+    NvU32 linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NvU32 numRecoveries[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
+} NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE
+ *
+ * This command queries the remote endpoint type of the link recorded at the
+ * time the last error occurred on the link.
+ *
+ *   [in] linkId
+ *     This parameter specifies the link to get the last remote endpoint type
+ *     recorded for.
+ *
+ *   [out] remoteType
+ *     This parameter returns the remote endpoint type of the link recorded at
+ *     the time the last error occurred on the link. Possible values are:
+ *       NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE
+ *         The link is not connected to an active remote endpoint.
+ *       NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU
+ *         The remote endpoint of the link is a peer GPU.
+ *       NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU
+ *         The remote endpoint of the link is the host system (e.g., an NPU
+ *         on IBM POWER platforms).
+ *       NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA
+ *         The remote endpoint of the link a tegra device
+ *
+ * Possible return status values are:
+ *   NV_OK
+ *     If the remoteType parameter value is valid upon return.
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the linkId parameter does not specify a valid link.
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on this GPU or the remote endpoint type is
+ *     not recorded in non-volatile storage.
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE (0x20803008U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS {
+    NvU32 linkId;
+    NvU32 remoteType;
+} NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS
+ *
+ * This command queries the number of each type of fatal errors that have
+ * occurred on the given link.
+ *
+ *   [in] linkId
+ *     This parameter specifies the link to get the fatal error information
+ *     for.
+ *
+ *   [out] supportedCounts
+ *     This parameter identifies which counts in the fatalErrorCounts array
+ *     are valid for the given link. A bit set in this field means that the
+ *     corresponding index is valid in the fatalErrorCounts array.
+ *
+ *   [out] fatalErrorCounts
+ *     This parameter returns an array of 8-bit counts, one for each type of
+ *     fatal error that can occur on the link. The valid indices of this array
+ *     are:
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_DL_DATA_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_DL_CTRL_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_RAM_DATA_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_RAM_HDR_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_TX_RAM_DATA_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_TX_RAM_HDR_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CTRL_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY
+ *       NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY
+ *
+ * Possible return status values are:
+ *   NV_OK
+ *     If the values in the fatalErrorCounts array are valid upon return.
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the linkId parameter does not specify a valid link.
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on this GPU or aggregate NVLINK fatal error
+ *     counts are not recorded in non-volatile storage.
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS                           (0x20803009U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NVLink 1 Fatal Error Types
+ */
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY                     0U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY                     1U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL                           2U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW                           3U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY                    4U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY                     5U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP                               6U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON                             7U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY                    8U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY                     9U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT                             10U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY                   11U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY                         12U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG                      13U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM                          14U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE                    15U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE               16U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE               17U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL                  18U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT                           19U
+
+/*
+ * NVLink 2 Fatal Error Types
+ */
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY                    0U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY                    1U
+// No direct equivalent to:                 TL_RX_PROTOCOL                            2
+// No direct equivalent to:                 TL_RX_OVERFLOW                            3
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY                   4U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY                    5U
+// No direct equivalent to:                 TL_RX_RESP                                6
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD            7U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY                   8U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY                    9U
+// No direct equivalent to:                 TL_TX_CREDIT                             10
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY            11U
+// No direct equivalent to:                 TL_DL_HDR_PARITY                         12
+// Identical to NVLink 1:                   DL_TX_RECOVERY_LONG                      13
+// Identical to NVLink 1:                   DL_TX_FAULT_RAM                          14
+// Identical to NVLink 1:                   DL_TX_FAULT_INTERFACE                    15
+// Identical to NVLink 1:                   DL_TX_FAULT_SUBLINK_CHANGE               16
+// Identical to NVLink 1:                   DL_RX_FAULT_SUBLINK_CHANGE               17
+// Identical to NVLink 1:                   DL_RX_FAULT_DL_PROTOCOL                  18
+// Identical to NVLink 1:                   DL_LTSSM_FAULT                           19
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY                     20U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD              21U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD              22U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN                23U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN                           24U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC                      25U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC                  26U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE                    27U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS                   28U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS                   29U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ  30U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP 31U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE    32U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE       33U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE      34U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR         35U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP           36U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET                37U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST   38U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW                      39U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW                     40U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD                  41U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL              42U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW           43U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE 44U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE 45U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW               46U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW              47U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW         48U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW           49U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT                  50U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT            51U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET                52U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST   53U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY                   54U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY                    55U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY                   56U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY                    57U
+
+/*
+ * NVLink 3 Fatal Error Types
+ */
+// Identical to NVLink 2:                   TLC_RX_DL_DATA_PARITY                     0
+// Identical to NVLink 2:                   TLC_RX_DL_CTRL_PARITY                     1
+// No direct equivalent to:                 TL_RX_PROTOCOL                            2
+// No direct equivalent to:                 TL_RX_OVERFLOW                            3
+// No direct equivalent to:                 TLC_RX_RAM_DATA_PARITY                    4
+// No direct equivalent to:                 RX_RAM_HDR_PARITY                         5
+// No direct equivalent to:                 TL_RX_RESP                                6
+// No direct equivalent to:                 TLC_RX_DATA_POISONED_PKT_RCVD             7
+// No direct equivalent to:                 TLC_TX_RAM_DATA_PARITY                    8
+// No direct equivalent to:                 TLC_TX_RAM_HDR_PARITY                     9
+// No direct equivalent to:                 TL_TX_CREDIT                             10
+// Identical to NVLink 2:                   TLC_TX_DL_FLOW_CONTROL_PARITY            11
+// No direct equivalent to:                 TL_DL_HDR_PARITY                         12
+// No direct equivalent to:                 DL_TX_RECOVERY_LONG                      13
+// Identical to NVLink 1:                   DL_TX_FAULT_RAM                          14
+// Identical to NVLink 1:                   DL_TX_FAULT_INTERFACE                    15
+// Identical to NVLink 1:                   DL_TX_FAULT_SUBLINK_CHANGE               16
+// Identical to NVLink 1:                   DL_RX_FAULT_SUBLINK_CHANGE               17
+// Identical to NVLink 1:                   DL_RX_FAULT_DL_PROTOCOL                  18
+// No direct equivalent to:                 DL_LTSSM_FAULT                           19
+// Identical to NVLink 2:                   TLC_RX_DL_HDR_PARITY                     20
+// Identical to NVLink 2:                   TLC_RX_INVALID_AE_FLIT_RCVD              21
+// Identical to NVLink 2:                   TLC_RX_INVALID_BE_FLIT_RCVD              22
+// Identical to NVLink 2:                   TLC_RX_INVALID_ADDR_ALIGN                23
+// Identical to NVLink 2:                   TLC_RX_PKT_LEN                           24
+// Identical to NVLink 2:                   TLC_RX_RSVD_CMD_ENC                      25
+// Identical to NVLink 2:                   TLC_RX_RSVD_DAT_LEN_ENC                  26
+// No direct equivalent to:                 TLC_RX_RSVD_ADDR_TYPE                    27
+// No direct equivalent to:                 TLC_RX_RSVD_RSP_STATUS                   28
+// Identical to NVLink 2:                   TLC_RX_RSVD_PKT_STATUS                   29
+// Identical to NVLink 2:                   TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ  30
+// Identical to NVLink 2:                   TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP 31
+// No direct equivalent to:                 TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE    32
+// Identical to NVLink 2:                   TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE       33
+// Identical to NVLink 2:                   TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE      34
+// Identical to NVLink 2:                   TLC_RX_INVALID_PO_FOR_CACHE_ATTR         35
+// Identical to NVLink 2:                   TLC_RX_INVALID_COMPRESSED_RESP           36
+// No direct equivalent to:                 TLC_RX_RESP_STATUS_TARGET                37
+// No direct equivalent to:                 TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST   38
+// Identical to NVLink 2:                   TLC_RX_HDR_OVERFLOW                      39
+// Identical to NVLink 2:                   TLC_RX_DATA_OVERFLOW                     40
+// Identical to NVLink 2:                   TLC_RX_STOMPED_PKT_RCVD                  41
+// No direct equivalent to:                 TLC_RX_CORRECTABLE_INTERNAL              42
+// No direct equivalent to:                 TLC_RX_UNSUPPORTED_VC_OVERFLOW           43
+// No direct equivalent to:                 TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE 44
+// No direct equivalent to:                 TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE 45
+// No direct equivalent to:                 TLC_TX_HDR_CREDIT_OVERFLOW               46
+// No direct equivalent to:                 TLC_TX_DATA_CREDIT_OVERFLOW              47
+// No direct equivalent to:                 TLC_TX_DL_REPLAY_CREDIT_OVERFLOW         48
+// No direct equivalent to:                 TLC_TX_UNSUPPORTED_VC_OVERFLOW           49
+// No direct equivalent to:                 TLC_TX_STOMPED_PKT_SENT                  50
+// No direct equivalent to:                 TLC_TX_DATA_POISONED_PKT_SENT            51
+// No direct equivalent to:                 TLC_TX_RESP_STATUS_TARGET                52
+// No direct equivalent to:                 TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST   53
+// No direct equivalent to:                 MIF_RX_RAM_DATA_PARITY                   54
+// No direct equivalent to:                 MIF_RX_RAM_HDR_PARITY                    55
+// No direct equivalent to:                 MIF_TX_RAM_DATA_PARITY                   56
+// No direct equivalent to:                 MIF_TX_RAM_HDR_PARITY                    57
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE        58U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE                59U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY                     60U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP                        61U
+#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN                      62U
+
+#define NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES                                     63U
+
+#define NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID(count, supportedCounts)    \
+    (!!((supportedCounts) & NVBIT64(count)))
+
+#define NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS {
+    NvU32 linkId;
+    NV_DECLARE_ALIGNED(NvU64 supportedCounts, 8);
+    NvU8  fatalErrorCounts[NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES];
+} NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES
+ *
+ * This command queries recent non-fatal error rates for the given link.
+ *
+ * The error rates specify the maximum number of errors per minute recorded
+ * for the given link within a 24-hour period for daily maximums or a 30-day
+ * period for monthly maximums.
+ *
+ *   [in] linkId
+ *     This parameter specifies the link to get the nonfatal error information
+ *     for.
+ *
+ *   [out] numDailyMaxNonfatalErrorRates
+ *     This parameter returns the number of valid nonfatal error rate entries
+ *     in the dailyMaxNonfatalErrorRates parameter.
+ *
+ *   [out] dailyMaxNonfatalErrorRates
+ *     This parameter returns maximum nonfatal error rate entries recorded
+ *     over the last few 24-hour periods. For example, index 0 contains the
+ *     maximum nonfatal error rate recorded in the current day, index 1
+ *     contains the maximum nonfatal error rate recorded yesterday ago, etc.
+ *
+ *   [out] numMonthlyMaxNonfatalErrorRates
+ *     This parameter returns the number of valid nonfatal error rate entries
+ *     in the monthlyMaxNonfatalErrorRates parameter.
+ *
+ *   [out] monthlyMaxNonfatalErrorRates
+ *     THis parameter returns maximum nonfatal error rate entries recorded
+ *     over the last few 30-day periods. For example, index 0 contains the
+ *     maximum nonfatal error rate recorded in the current month, index 1
+ *     contains the maximum nonfatal error recorded last month, etc.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If any nonfatal error rates are valid upon return.
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the linkId parameter does not specify a valid link.
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on this GPU or NVLINK nonfatal error rates
+ *     are not recorded in non-volatile storage.
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES (0x2080300aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE {
+    NvU32 errorsPerMinute;
+    NvU32 timestamp;
+} NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE;
+
+#define NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES 5U
+
+#define NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS {
+    NvU32                                  linkId;
+    NvU32                                  numDailyMaxNonfatalErrorRates;
+    NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE dailyMaxNonfatalErrorRates[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES];
+    NvU32                                  numMonthlyMaxNonfatalErrorRates;
+    NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE monthlyMaxNonfatalErrorRates[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES];
+} NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE
+ *
+ * This command sets the injection mode so that error handling and error
+ * logging software can be aware that errors cropping up on links are
+ * intentional and not due to HW failures.
+ *
+ *   [in] bEnabled
+ *     This parameter specifies whether injection mode should be enabled or
+ *     disabled.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If injection mode is enabled or disabled according to the parameters.
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on this GPU.
+ */
+#define NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE (0x2080300bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS {
+    NvBool bEnabled;
+} NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SETUP_EOM
+ *
+ * This command passes a packed 32bit params value to NV_PMINION_MISC_0_SCRATCH_SWRW_0
+ * and then issues an EOM DLCMD to minion for the desired link. Only one DLCMD
+ * at a time can be issued to any given link.
+ *
+ * Params Packing is specified in Minion IAS
+ */
+#define NV2080_CTRL_CMD_NVLINK_SETUP_EOM (0x2080300cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS {
+    NvU8  linkId;
+    NvU32 params;
+} NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE
+ *
+ * This command sets the mask of links associated with the GPU
+ * to a target power state
+ *
+ * [in] linkMask (This field will be deprecated in the future, please use links)
+ *     Mask of links that will be put to desired power state
+ *     Note: In Turing RM supports only tansitions into/out of L2
+ *
+ * [in] links
+ *     Mask of links that will be put to desired power state
+ *     Note: In Turing RM supports only tansitions into/out of L2
+ *
+ * [in] powerState
+ *     Target power state to which the links will transition
+ *     This can be any one of NV2080_CTRL_NVLINK_POWER_STATE_* states
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If all links transitioned successfully to the target state
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip or if the power state
+ *     is not enabled on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the any of the links in the mask is not enabled
+ *   NV_ERR_INVALID_REQUEST
+ *     If the power state transition is not supported
+ *   NV_WARN_MORE_PROCESSING_REQUIRED
+ *      Link has received the request for the power transition
+ *      The transition will happen when the remote end also agrees
+ *
+ *  Note: Currently only L0->L2 and L2->L0 is supported
+ */
+#define NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE (0x2080300dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS {
+    NvU32 linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NvU32 powerState;
+} NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS;
+
+// NVLink Power States
+#define NV2080_CTRL_NVLINK_POWER_STATE_L0      (0x00U)
+#define NV2080_CTRL_NVLINK_POWER_STATE_L1      (0x01U)
+#define NV2080_CTRL_NVLINK_POWER_STATE_L2      (0x02U)
+#define NV2080_CTRL_NVLINK_POWER_STATE_L3      (0x03U)
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE
+ *
+ * This command gets the power state of a link associated
+ * with the GPU
+ *
+ * [in] linkId
+ *     Link whose power state is being requested
+ * [out] powerState
+ *     Current power state of the link
+ *     Is any one the NV2080_CTRL_NVLINK_POWER_STATE_* states
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the power state is retrieved successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the link is not enabled on the GPU
+ *   NV_ERR_INVALID_STATE
+ *     If the link is in an invalid state
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE (0x2080300eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS {
+    NvU32 linkId;
+    NvU32 powerState;
+} NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR
+ *
+ * This command injects TLC_*_REPORT_INJECT error. An RM interrupt
+ * will be triggered after injection. Currently the injection call
+ * only deals with HW_ERR, UR_ERR, PRIV_ERR in TX_SYS and RX_LNK devices
+ *
+ * [in] linkId
+ *     Link whose power state is being requested.
+ * [in] errorType
+ *     error type that needs to be injected.
+ * [in] device
+ *     The device this injection is intended for.
+ * [in] bBroadcast
+ *     Whether the link report error should be fired in multiple links.
+
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the injection succeeds.
+ *   NV_ERR_NOT_SUPPORTED
+ *     If the error type of NVLINK is not supported on the chip
+ */
+#define NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR (0x2080300fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE {
+    TLC_RX_LNK = 0,
+    TLC_TX_SYS = 1,
+} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE;
+
+typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE {
+    TX_SYS_TX_RSP_STATUS_HW_ERR = 0,
+    TX_SYS_TX_RSP_STATUS_UR_ERR = 1,
+    TX_SYS_TX_RSP_STATUS_PRIV_ERR = 2,
+} NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE;
+
+typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE {
+    RX_LNK_RX_RSP_STATUS_HW_ERR = 0,
+    RX_LNK_RX_RSP_STATUS_UR_ERR = 1,
+    RX_LNK_RX_RSP_STATUS_PRIV_ERR = 2,
+} NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE;
+
+typedef union NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE {
+    NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE txSysErrorType;
+    NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE rxLnkErrorType;
+} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE;
+
+
+#define NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS {
+    NvU32                                      linkId;
+    NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE device;
+    NvBool                                     bBroadcast;
+    NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE   errorType;
+} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES
+ *
+ * This command returns the per-lane Figure Of Merit (FOM) Values from a link
+ *
+ * [in]  linkId
+ *     The NVLink link ID to report FOM values for
+ * [out] numLanes
+ *     This field specifies the no. of lanes per link
+ * [out] figureOfMeritValues
+ *     This field contains the FOM values per lane
+ *
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES (0x20803011U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_MAX_LANES               4U
+
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID (0x11U)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS {
+    NvU32 linkId;
+    NvU8  numLanes;
+    NvU16 figureOfMeritValues[NV2080_CTRL_NVLINK_MAX_LANES];
+} NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS;
+
+/*
+ * NV2080_CTRL_NVLINK_SET_NVLINK_PEER
+ *
+ * This command sets/unsets the USE_NVLINK_PEER bit for a given
+ *     mask of peers
+ *
+ * [in] peerMask
+ *     Mask of Peer IDs for which USE_NVLINK_PEER needs to be updated
+ * [in] bEnable
+ *     Whether the bit needs to be set or unset
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the USE_NVLINK_PEER bit was updated successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip, or
+ *     If unsetting USE_NVLINK_PEER bit is not supported
+ *
+ * NOTE: This is only supported on Windows
+ *
+ */
+#define NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER (0x20803012U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID (0x12U)
+
+typedef struct NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS {
+    NvU32  peerMask;
+    NvBool bEnable;
+} NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG
+ *
+ * This command packs the lane and addr values into NV_PMINION_MISC_0_SCRATCH_SWRW_0
+ * and then issues a READPADLANEREG DLCMD to minion for the desired link. Only one DLCMD
+ * at a time can be issued to any given link.
+ *
+ * After this command completes it is necessary to read the appropriate
+ * NV_PNVL_BR0_PAD_CTL_7_CFG_RDATA register to retrieve the results of the read
+ * Only GV100 should read NV_PNVL_BR0_PAD_CTL_7_CFG_RDATA.
+ * From TU102+ the ctrl the required data would be updated in phyConfigData.
+ *
+ * [in] linkId
+ *     Link whose pad lane register is being read
+ * [in] lane
+ *     Lane whose pad lane register is being read
+ * [in] addr
+ *     Address of the pad lane register to read
+ * [out] phyConfigData
+ *     Provides phyconfigaddr and landid
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the minion command completed successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the link is not enabled on the GPU or the lane is invalid
+ *   NV_ERR_TIMEOUT
+ *     If a timeout occurred waiting for minion response
+ */
+#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG (0x20803013U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS {
+    NvU8  linkId;
+    NvU8  lane;
+    NvU16 addr;
+    NvU32 phyConfigData;
+} NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS;
+
+/*
+ * Structure to store the ECC error data.
+ * valid
+ *     Is the lane valid or not
+ * eccErrorValue
+ *     Value of the Error.
+ * overflowed
+ *     If the error overflowed or not
+ */
+typedef struct NV2080_CTRL_NVLINK_LANE_ERROR {
+    NvBool bValid;
+    NvU32  eccErrorValue;
+    NvBool overflowed;
+} NV2080_CTRL_NVLINK_LANE_ERROR;
+
+/*
+ * Structure to store ECC error data for Links
+ * errorLane array index corresponds to the lane number.
+ *
+ * errorLane[]
+ *    Stores the ECC error data per lane.
+ */
+typedef struct NV2080_CTRL_NVLINK_LINK_ECC_ERROR {
+    NV2080_CTRL_NVLINK_LANE_ERROR errorLane[NV2080_CTRL_NVLINK_MAX_LANES];
+    NvU32                         eccDecFailed;
+    NvBool                        eccDecFailedOverflowed;
+} NV2080_CTRL_NVLINK_LINK_ECC_ERROR;
+
+/*
+ * NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS
+ *
+ * Control to get the values of ECC ERRORS
+ *
+ * Parameters:
+ *    linkMask [IN] (This field will be deprecated in the future, please use links)
+ *      Links on which the ECC error data requested
+ *      A valid link/port mask returned by the port masks returned by
+ *      NVSWITCH_GET_INFO
+ *    links [IN]
+ *      Links on which the ECC error data requested
+ *      A valid link/port mask returned by the port masks returned by
+ *      NVSWITCH_GET_INFO
+ *    errorLink[] [OUT]
+ *      Stores the ECC error related information for each link.
+ *      errorLink array index corresponds to the link Number.
+ */
+
+#define NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID (0x14U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS {
+    NvU32                             linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV2080_CTRL_NVLINK_LINK_ECC_ERROR errorLink[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
+} NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS;
+
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS     (0x20803014U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID" */
+
+// Nvlink throughput counters reading data flits in TX
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX 0U
+
+// Nvlink throughput counters reading data flits in RX
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX 1U
+
+// Nvlink throughput counters reading all flits in TX
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX  2U
+
+// Nvlink throughput counters reading all flits in RX
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX  3U
+
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX     4U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS
+ *
+ * Reads reserved monotonically increasing NVLINK throughput counters for given linkIds
+ *
+ * [in] counterMask
+ *     Mask of counter types to be queried
+ *     One of NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_* macros
+ * [in] linkMask (This field will be deprecated in the future, please use links)
+ *     Mask of links to be queried
+ * [in] links
+ *     Mask of links to be queried
+ * [out] value
+ *     Throughput counter value returned
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If command completed successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If numLinks is out-of-range or requested link is inactive
+ *
+ * Note:
+ * The following commands will be deprecated in favor of NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS:
+ *     NV90CC_CTRL_CMD_NVLINK_GET_COUNTERS
+ *     NV2080_CTRL_CMD_NVLINK_GET_COUNTERS
+ * Other commands that will be deprecated due to the change in design:
+ *     NV90CC_CTRL_CMD_NVLINK_RESERVE_COUNTERS
+ *     NV90CC_CTRL_CMD_NVLINK_RELEASE_COUNTERS
+ *     NV90CC_CTRL_CMD_NVLINK_SET_COUNTERS_FROZEN
+ *     NV90CC_CTRL_CMD_NVLINK_GET_TL_COUNTER_CFG
+ *     NV90CC_CTRL_CMD_NVLINK_SET_TL_COUNTER_CFG
+ *     NV90CC_CTRL_CMD_NVLINK_CLEAR_COUNTERS
+ *
+ * Also, note that there is no counter overflow handling for these calls.
+ * These counters would be counting in flits and assuming 25GB/s bandwidth per link,
+ * with traffic flowing continuously, it would take 174 years for overflow to happen.
+ * It is reasonable to assume an overflow will not occur within the GPU operation,
+ * given that the counters get reset at system reboot or GPU reset. Counters are 63-bit.
+ */
+
+typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES {
+    NV_DECLARE_ALIGNED(NvU64 value[NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX], 8);
+} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES;
+
+#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID (0x15U)
+
+typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS {
+    NvU16 counterMask;
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
+} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS      (0x20803015U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE
+ *
+ * This command locks the link power state so that RM doesn't modify the state
+ * of the link during pstate switch.
+ *
+ *   [in] linkMask        Links for which power mode needs to be locked.
+ */
+#define NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE (0x20803016U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID (0x16U)
+
+typedef struct NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS {
+    NvBool bLockPowerMode;
+} NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS;
+
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS             0U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH           1U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER            2U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER           3U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT            4U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP            5U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME                   6U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME   7U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME       8U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME        9U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME  10U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME  11U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME      12U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME       13U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME 14U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME          15U
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS              16U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS
+ *
+ * Reads NVLINK low power counters for given linkId
+ *
+ * [in] linkId
+ *     ID of the link to be queried
+ * [in,out] counterValidMask
+ *     Mask of valid counters
+ * [out] counterValues
+ *     Low power counter values returned
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If command completed successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If linkId is out-of-range or requested link is inactive
+ */
+
+#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID (0x18U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
+    NvU32 linkId;
+    NvU32 counterValidMask;
+    NvU32 counterValues[NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS];
+} NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS   (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
+
+
+//
+// Set the near end loopback mode using the following
+// Currently, three modes - NEA, NEDR, NEW
+//
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT              (0x00000000)
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA                  (0x00000001)
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR                 (0x00000002)
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW                 (0x00000003)
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE           (0x00000004)
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL            (0x00000005)
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL            (0x00000006)
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE
+ *
+ * Generic NvLink callback for MODS
+ *
+ * [In] linkdId
+ *     ID of the link to be used
+ * [In] loopbackMode
+ *     This value will decide which loopback mode need to
+ *     set on the specified link.
+ *     Modes are NEA / NEDR / NEDW
+ */
+#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID (0x23U)
+
+typedef struct NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS {
+    NvU32 linkId;
+    NvU8  loopbackMode;
+} NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE (0x20803023U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID" */
+
+//
+// Read Refresh counter - the pass/fail occurrences
+//
+
+typedef struct NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO {
+    // requested links or not
+    NvBool bValid;
+
+    // counters
+    NvU16  passCount;
+    NvU16  failCount;
+} NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO;
+
+#define NV2080_CTRL_NVLINK_MAX_LINK_COUNT 32
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS
+ *
+ *
+ * [In] linkMask (This field will be deprecated in the future, please use links)
+ *     Specifies for which links we want to read the counters
+ * [In] links
+ *     Specifies for which links we want to read the counters
+ * [Out] refreshCountPass
+ *     Count of number of times PHY refresh pass
+ * [Out] refreshCountFail
+ *     Count of number of times PHY refresh fail
+ */
+#define NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x28U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS {
+    NvU32                                      linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO refreshCount[NV2080_CTRL_NVLINK_MAX_LINK_COUNT];
+} NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS (0x20803028U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */
+
+//
+// Clear Refresh counter - the pass/fail occurrences
+//
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS
+ *
+ *
+ * [In] linkMask (This field will be deprecated in the future, please use links)
+ *     Specifies for which links we want to clear the counters
+ * [In] links
+ *     Specifies for which links we want to clear the counters
+ */
+#define NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x29U)
+
+typedef struct NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS {
+    NvU32 linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+} NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS (0x20803029U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR
+ *
+ * Get/Set NVSwitch FLA address
+ *
+ * [In] bGet
+ *     Whether to get or set the NVSwitch FLA address
+ * [In/Out] addr
+ *     Address that is to be set or retrieved.
+ */
+#define NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID (0x38U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS {
+    NvBool bGet;
+    NV_DECLARE_ALIGNED(NvU64 addr, 8);
+} NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR (0x20803038) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO
+ *
+ * Syncs the different link masks and vbios defined values between CPU-RM and GSP-RM
+ *
+ * [in]  discoveredLinks (This field will be deprecated in the future, please use discoveredLinkMask)
+ *     Mask of links discovered from IOCTRLs
+ *
+ * [in]  discoveredLinkMask
+ *     Mask of links discovered from IOCTRLs
+ *
+ * [in]  connectedLinksMask (This field will be deprecated in the future, please use connectedLinks)
+ *     Mask of links which are connected (remote present)
+ *
+ * [in]  connectedLinks
+ *     Mask of links which are connected (remote present)
+ *
+ * [in]  bridgeSensableLinks (This field will be deprecated in the future, please use bridgeSensableLinkMask)
+ *     Mask of links whose remote endpoint presence can be sensed
+ *
+ * [in]  bridgeSensableLinkMask
+ *     Mask of links whose remote endpoint presence can be sensed
+ *
+ * [in]  bridgedLinks (This field will be deprecated in the future, please use bridgedLinkMask)
+ *    Mask of links which are connected (remote present)
+ *    Same as connectedLinksMask, but also tracks the case where link
+ *    is connected but marginal and could not initialize
+ *
+ * [in]  bridgedLinkMask
+ *    Mask of links which are connected (remote present)
+ *    Same as connectedLinks, but also tracks the case where link
+ *    is connected but marginal and could not initialize
+ *
+ * [out] initDisabledLinksMask (This field will be deprecated in the future, please use initDisabledLinks)
+ *      Mask of links for which initialization is disabled
+ *
+ * [out] initDisabledLinks
+ *      Mask of links for which initialization is disabled
+ *
+ * [out] vbiosDisabledLinkMask (This field will be deprecated in the future, please use vbiosDisabledLinks)
+ *      Mask of links disabled in the VBIOS
+ *
+ * [out] vbiosDisabledLinks
+ *      Mask of links disabled in the VBIOS
+ *
+ * [out] initializedLinks (This field will be deprecated in the future, please use initializedLinkMask)
+ *      Mask of initialized links
+ *
+ * [out] initializedLinkMask
+ *      Mask of initialized links
+ *
+ * [out] bEnableTrainingAtLoad
+ *      Whether the links should be trained to active during driver load
+ *
+ * [out] bEnableSafeModeAtLoad
+ *      Whether the links should be initialized to swcfg during driver load
+ */
+
+#define NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID (0x39U)
+
+typedef struct NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK discoveredLinkMasks, 8);
+    NvU32  connectedLinksMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK connectedLinks, 8);
+    NV_DECLARE_ALIGNED(NvU64 bridgeSensableLinks, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK bridgeSensableLinkMasks, 8);
+    NvU32  bridgedLinks;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK bridgedLinkMasks, 8);
+    NvU32  initDisabledLinksMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK initDisabledLinks, 8);
+    NV_DECLARE_ALIGNED(NvU64 vbiosDisabledLinkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK vbiosDisabledLinks, 8);
+    NvU32  initializedLinks;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK initializedLinkMasks, 8);
+    NvBool bEnableTrainingAtLoad;
+    NvBool bEnableSafeModeAtLoad;
+} NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO (0x20803039U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS
+ *
+ * Enable pre-topology setup on the mask of enabled links
+ * This command accepts no parameters.
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS                   (0x2080303aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x3a" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS
+ *
+ * Process the init disabled NVLinks and filter those out
+ *
+ * [in/out]  initDisabledLinksMask (This field will be deprecated in the future, please use initDisabledLinks)
+ *     Mask of links initdisabled on a given GPU
+ *
+ * [in/out]  initDisabledLinks
+ *     Mask of links initdisabled on a given GPU
+ *
+ * [in] bSkipHwNvlinkDisable
+ *     Whether to consider skipping the HW initdisable links
+ */
+
+#define NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID (0x3bU)
+
+typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS {
+    NvU32  initDisabledLinksMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK initDisabledLinks, 8);
+    NvBool bSkipHwNvlinkDisable;
+} NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS (0x2080303bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_EOM_CONTROL
+ *
+ * cmd [IN] enum identifying the EOM related command for the driver to process
+ * link [IN] linkId
+ * params [IN] NvU32 word that is written into NV_PMINION_SCRATCH_SWRW_0 before calling CONFIGEOM dlcmd
+ * measurements [OUT] output of EOM
+ *
+ * Params Packing is specified in Minion IAS
+ */
+
+typedef enum NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND {
+    NVLINK_EOM_CONTROL_START_EOM = 0,
+    NVLINK_EOM_CONTROL_END_EOM = 1,
+    NVLINK_EOM_CONTROL_CONFIG_EOM = 2,
+    NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3,
+} NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND;
+
+typedef struct NV2080_CTRL_NVLINK_EOM_MEASUREMENT {
+    NvU8 upper;
+    NvU8 middle;
+    NvU8 lower;
+    NvU8 composite;
+} NV2080_CTRL_NVLINK_EOM_MEASUREMENT;
+
+#define NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID (0x3cU)
+
+typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS {
+    NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND cmd;
+    NvU32                                             linkId;
+    NvU32                                             params;
+    NV2080_CTRL_NVLINK_EOM_MEASUREMENT                measurements[NV2080_CTRL_NVLINK_MAX_LANES];
+} NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL      (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Inband Received Data
+ */
+#define NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE 5120
+#define NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID (0x3dU)
+
+typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS {
+    NvU8  data[NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE];
+    NvU32 dataSize;
+} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS;
+
+#define NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE (0x2080303d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT (0xFFFFFFFF)
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD
+ *
+ * This command is used to set the L1 threshold value.
+ * A value of NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT
+ * will reset the L1 Threshold to the default values.
+ *
+ * [in] l1Threshold
+ *     Used to set the L1 threshold value
+ *
+ * [in] l1ExitThreshold
+ *     Used to set the L1 Exit threshold value
+ */
+#define NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3eU)
+
+typedef struct NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS {
+    NvU32 l1Threshold;
+    NvU32 l1ExitThreshold;
+} NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD (0x2080303eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD
+ *
+ * This command is used to get the L1 threshold value
+ *
+ * [out] l1Threshold
+ *     Used to get the L1 threshold value
+ *
+ * [out] l1ExitThreshold
+ *     Used to get the L1 Exit Thrshold value
+ */
+#define NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3fU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS {
+    NvU32  l1Threshold;
+    NvU32  l1ExitThreshold;
+    NvBool bL1Enabled;
+    NvBool bL1ThermThrottlingEnabled;
+} NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD (0x2080303fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA
+ *
+ * RPC  for sending Inband data
+ *
+ * [In] data[]
+ *     data to be sent over inband
+ * [In] dataSize
+ *     Size of valid data in data array
+ */
+#define NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID (0x40U)
+
+typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS {
+    NvU8  buffer[NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE];
+    NvU32 dataSize;
+} NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA (0x20803040U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED
+ *
+ * RPC for Getting GPU degraded status upon link error
+ *
+ * [In] linkId
+ *     Id of the link on which error occured
+ * [Out] bIsGpuDegraded
+ *     Boolean to track corresponding GPU is degraded or not
+ */
+#define NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID (0x41U)
+
+typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS {
+    NvU32  linkId;
+    NvBool bIsGpuDegraded;
+} NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED (0x20803041U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK
+ *
+ * This command is used to check for missing
+ * bridge/nvlink for direct connect GPU
+ *
+ * [out] bIsEnoughNvLink
+ *     Check if number of active nvlink meet the minimum requirements.
+ * [out] numBridge
+ *     Number of NVLink bridge
+ * [out] bridgePresenceMask
+ *     Bit mask of NVLink bridges's presence
+ */
+#define NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID (0x42U)
+
+typedef struct NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS {
+    NvBool bIsEnoughNvLink;
+    NvU32  numBridge;
+    NvU32  bridgePresenceMask;
+} NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK (0x20803042U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP
+ *
+ * This command is to trigger the next sequence after the 10 sec delay
+ *
+ * [out] linkId
+ *     Link number which the sequence should be triggered
+ */
+#define NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID (0x43U)
+
+typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS {
+    NvU32 linkId;
+} NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP     (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE 64U
+
+/*
+* Structure to store port event information
+*
+*   portEventType
+*       Type of port even that occurred: NVLINK_PORT_EVENT_TYPE*
+*
+*   gpuId
+*       Gpu that port event occurred on
+*
+*   linkId
+*       Link id that port event occurred on
+*
+*   time
+*       Platform time (nsec) when event occurred
+*/
+typedef struct NV2080_CTRL_NVLINK_PORT_EVENT {
+    NvU32 portEventType;
+    NvU32 gpuId;
+    NvU32 linkId;
+    NV_DECLARE_ALIGNED(NvU64 time, 8);
+} NV2080_CTRL_NVLINK_PORT_EVENT;
+
+/*
+* NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS
+*
+* This command returns the port up and port down events that have occurred
+*
+* Parameters:
+*
+*   portEventIndex [IN/OUT]
+*      On input: The index of the first port event at which to start reading out of the driver.
+*
+*      On output: The index of the first port event that wasn't reported through the 'port event' array
+*                 in this call to NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS.
+*
+*   nextPortEventIndex[OUT]
+*      The index that will be assigned to the next port event that occurs.
+*      Users of the GET_PORT_EVENTS control call may set 'portEventIndex' to this field on initialization
+*      to bypass port events that have already occurred without making multiple control calls.
+*
+*   portEventCount [OUT]
+*      Number of port events returned by the call. Currently, portEventCount is limited
+*      by NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE. In order to query all the port events, a
+*      client needs to keep calling the control till portEventCount is zero.
+*
+*   bOverflow [OUT]
+*       True when the port event log is overflowed and no longer contains all the port
+*       events that have occurred, false otherwise.
+*
+*   portEvent [OUT]
+*      The port event entires.
+*/
+#define NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID (0x44U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 portEventIndex, 8);
+    NV_DECLARE_ALIGNED(NvU64 nextPortEventIndex, 8);
+    NvU32  portEventCount;
+    NvBool bOverflow;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_PORT_EVENT portEvent[NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE], 8);
+} NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID" */
+
+/*
+* NV2080_CTRL_CMD_NVLINK_CYCLE_LINK
+*
+* This command cycles a link by faulting it and then retraining the link
+*
+* Parameters:
+*
+*   linkId [IN]
+*      The link id of the link to be cycled
+*/
+#define NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID (0x45U)
+
+typedef struct NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS {
+    NvU32 linkId;
+} NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_CYCLE_LINK (0x20803045U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG
+ *
+ * This command is to check if a GPU has a reduced nvlink configuration
+ *
+ * [out] bReducedNvlinkConfig
+ *     Link number which the sequence should be triggered
+ */
+#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x46U)
+
+typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
+    NvBool bReducedNvlinkConfig;
+} NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
+
+
+#define NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH 496U
+
+typedef struct NV2080_CTRL_NVLINK_PRM_DATA {
+    NvU8 data[NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH];
+} NV2080_CTRL_NVLINK_PRM_DATA;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS (0x20803074U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID (0x74U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
+} NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS;
+/*
+ * NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS
+ *
+ * This command returns platform-specific information related to the GPU's NVLink setup.
+ *
+ *   ibGuid
+ *     Infiniband GUID reported by platform (for Blackwell, ibGuid is 8 bytes so indices 8-15 are zero)
+ *   rackGuid
+ *     GUID of the rack containing this GPU (for Blackwell rackGuid is 13 bytes so indices 13-15 are zero)
+ *   chassisPhysicalSlotNumber
+ *     The slot number in the rack containing this GPU (includes switches)
+ *   computeSlotIndex
+ *     The index within the compute slots in the rack containing this GPU (does not include switches)
+ *   nodeIndex
+ *     Index of the node within the slot containing this GPU
+ *   peerType
+ *     Platform indicated NVLink-peer type (e.g. switch present or not)
+ *   moduleId
+ *     ID of this GPU within the node
+ *   nvlinkSignalingProtocol  // Deprecated
+ *     signaling protocol used for this platform
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO (0x20803083U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID (0x83U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS {
+    NvU8 ibGuid[16];
+    NvU8 rackGuid[16];
+    NvU8 chassisPhysicalSlotNumber;
+    NvU8 computeSlotIndex;
+    NvU8 nodeIndex;
+    NvU8 peerType;
+    NvU8 moduleId;
+    NvU8 nvlinkSignalingProtocol;
+    NvU8 linksPerSpigot;
+} NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS;
+
+/*
+ * Structure to store UPHY cmd data.
+ * laneId
+ *     Lane ID for specified link
+ * address
+ *     Desired address for read
+ */
+typedef struct NV2080_CTRL_NVLINK_UPHY_CLN_CMD {
+    NvU8  pllIndex;
+    NvU16 address;
+} NV2080_CTRL_NVLINK_UPHY_CLN_CMD;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN
+ *
+ *
+ *  This command retrieves the land id cln select, lane id, and pll index.
+ *
+ * [in] linkMask (This field will be deprecated in the future, please use links)
+ *     Mask of links whose uphy should be read
+ * [in] links
+ *     Mask of links whose uphy should be read
+ * [in] uphyCmd
+ *     Array of input data (pll index and address) for each link,
+ *      where index 0 represents link 0's pll index
+ *      and index 16 represents link 16's pll index.
+ * [out] data
+ *     Data from uphy cln for each link where index 0 represents link 0's pll index
+ *      and index 16 represents link 16's pll index.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the minion command completed successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the link is not enabled on the GPU or the lane is invalid
+ *   NV_ERR_TIMEOUT
+ *     If a timeout occurred waiting for minion response
+ */
+#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN (0x20803084U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID (0x84U)
+
+typedef struct NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS {
+    NvU32                           linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV2080_CTRL_NVLINK_UPHY_CLN_CMD uphyCmd[NV2080_CTRL_NVLINK_MAX_LINKS];
+    NvU32                           data[NV2080_CTRL_NVLINK_MAX_LINKS];
+} NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS;
+
+#define NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT 23U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE
+ *
+ * This command gets the supported RBMs of the GPU
+ *
+ * [out] rbmModesList
+ *     List of supported RBM modes
+ * [out] rbmTotalModes
+ *     Total RBM modes supported
+ * Possible status values returned are: TODO: Update this
+ *   NV_OK
+ *     If the BW mode is retrieved successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the link is not enabled on the GPU
+ *   NV_ERR_INVALID_STATE
+ *     If the link is in an invalid state
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE   (0x20803085U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID (0x85U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS {
+    NvU16 rbmModesList[NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT];
+    NvU8  rbmTotalModes;
+} NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_SET_BW_MODE_POLL_TIMEOUT_MS_INVALID 0
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SET_BW_MODE
+ *
+ * This command sets the requested RBM of the GPU
+ * GB100  -- Control call is synchronous and will try to set the RBM mode within the control handling
+ *
+ * [in] rbmMode
+ *      Possible Legacy values that can be set in bits 2:0:
+ *        NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL
+ *        NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF
+ *        NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN
+ *        NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF
+ *        NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER
+ *      Blackwell bits 3:7 can be used to specify link count
+ *                 bits 8:15 are reserved
+ * [in] bForceSync
+ *     Force synchronous behavior
+ * [out] rbmSetPollTimeoutMs
+ *     timeout value for client to poll for RBM  to complete.
+ *     This will be set to NV2080_CTRL_CMD_NVLINK_SET_BW_MODE_POLL_TIMEOUT_MS_INVALID if
+ *     synchronous behavior is applied
+ *
+ * Possible status values returned are: TODO: Update this
+ *   NV_OK
+ *     If the BW mode is set successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the link is not enabled on the GPU
+ *   NV_ERR_INVALID_STATE
+ *     If the link is in an invalid state
+ */
+#define NV2080_CTRL_CMD_NVLINK_SET_BW_MODE                         (0x20803086U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID (0x86U)
+
+typedef struct NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS {
+    NvU16  rbmMode;
+    NvBool bForceSync;
+    NvU32  rbmSetPollTimeoutMs;
+} NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_BW_MODE
+ *
+ * This command gets the set RBM of the GPU
+ *
+ * [out] rbmMode
+ *     RBM mode currently set
+ *
+ * Possible status values returned are: TODO: Update this
+ *   NV_OK
+ *     If the BW mode is set successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the link is not enabled on the GPU
+ *   NV_ERR_INVALID_STATE
+ *     If the link is in an invalid state
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_BW_MODE (0x20803087U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID (0x87U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS {
+    NvU16 rbmMode;
+} NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO
+ *
+ *   localDeviceInfo
+ *      NVLINK-relevant information about the device
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO (0x20803088U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x88U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO localDeviceInfo, 8);
+} NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR
+ *
+ * This command is used to inject NVL5 ERROR_INJECT_V2 commands
+ *
+ * [in] links
+ *          link mask of which links to inject the error on
+ * [out]
+ *     Error Types to be injected
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *     If the Error is injected successfully
+ *   NV_ERR_NOT_SUPPORTED
+ *     If NVLINK is not supported on the chip
+ *   NV_ERR_INVALID_ARGUMENT
+ *     If the link is not enabled on the GPU
+ *   NV_ERR_INVALID_STATE
+ *     If the link is in an invalid state
+ */
+#define NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR (0x20803089U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID" */
+typedef enum NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY {
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL = 0,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL = 1,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL = 2,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION = 3,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT = 4,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL = 5,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE = 6,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL = 7,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL = 8,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR = 9,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL = 10,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL = 11,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL = 12,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL = 13,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL = 14,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL = 15,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL = 16,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL = 17,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = 18,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = 19,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = 20,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_FATAL = 21,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 22,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_MVB_NON_FATAL = 23,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_MVB_FATAL = 24,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_MVB_NON_FATAL = 25,
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_MVB_FATAL = 26,
+} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY;
+
+#define NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID (0x89U)
+
+typedef struct NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS {
+    NvU32                                       linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY severity;
+} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS;
+
+/*
+ * NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY
+ *
+ *  This command is used to update the NVLE topology in GSP RM
+ *
+ *  [in] localGpuAlid
+ *      ALID of local GPU in P2P object
+ *  [in] localGpuClid
+ *      CLID of local GPU in P2P object
+ *  [in] remoteGpuAlid
+ *      ALID of remote GPU in P2P object
+ *  [in] remoteGpuClid
+ *      CLID of remote GPU in P2P object
+ *  [in] bNvleQualMode
+ *      Implies NVLE Qual mode, which would be using hardcoded keys
+ *  [in] localGpuPlatformInfo
+ *      Platform information for the local GPU
+ *  [in] remoteGpuPlatformInfo
+ *      Platform information for the remote GPU
+ */
+#define NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY (0x2080308cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID (0x8cU)
+
+typedef struct NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS {
+    NvU32                                       localGpuAlid;
+    NvU32                                       localGpuClid;
+    NvU32                                       remoteGpuAlid;
+    NvU32                                       remoteGpuClid;
+    NvBool                                      bNvleQualMode;
+    NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS localGpuPlatformInfo;
+    NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS remoteGpuPlatformInfo;
+} NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS;
+
+/*
+ * Structure to store the NVLE ALID and the corresponding mapped CLID
+ *
+ *  [in] alid
+ *      Represents the ALID
+ *  [in] clid
+ *      Represents the corresponding CLID
+ */
+typedef struct NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP {
+    NvU32 alid;
+    NvU32 clid;
+} NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP;
+
+#define NV2080_CTRL_NVLINK_MAX_REMAP_TABLE_ENTRIES     32U
+
+#define NV2080_CTRL_NVLINK_MAX_REMAP_TABLE_ENTRIES_V2  4096U
+#define NV2080_CTRL_NVLINK_REMAP_TABLE_ENTRIES_CHUNK   128U
+#define NV2080_CTRL_NVLINK_MAX_ALID_CLID_TABLE_ENTRIES 128U
+
+/*
+ * Structure to store the NVLE ALID-CLID maps
+ *
+ *  [in] alidClidMap
+ *      Array of NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP
+ *  [in] numEntries
+ *      Represents the number of entries in the ALID-CLID table
+ */
+typedef struct NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE {
+    NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP alidClidMap[NV2080_CTRL_NVLINK_MAX_REMAP_TABLE_ENTRIES];
+    NvU32                                 numEntries;
+} NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE;
+
+/*
+ * Structure to store the NVLE ALID-CLID maps - version 2 to handle more ALID-CLID mappings
+ *
+ *  [in] alidClidMap
+ *      Array of NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP
+ *  [in] numEntries
+ *      Represents the number of entries in the ALID-CLID table
+ */
+typedef struct NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2 {
+    NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP alidClidMap[NV2080_CTRL_NVLINK_MAX_ALID_CLID_TABLE_ENTRIES];
+    NvU32                                 numEntries;
+} NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2;
+
+/*
+ * NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS
+ *
+ *  This command is used for the following operations.
+ *    If getting the LID information, the command gets the ALID and CLID of the GPU.
+ *    If setting the LID information, the command passes the complete ALID-CLID map.
+ *    The also command returns the status of whether the CLIDs are updated in the remap tables.
+ *
+ *  [in] bGet
+ *      Whether to get the ALIDs or set the CLIDs in the remap table or update the LIDs in the remap tables
+ *  [out] alid
+ *      ALID of the given GPU
+ *  [out] clid
+ *      CLID of the given GPU
+ *  [in] alidClidTable
+ *      Table with the ALIDs and corresponding mapped CLIDs
+ *  [out] bClidUpdated
+ *      Whether CLIDs have been updated in the FLA and GPA remap tables
+ */
+#define NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS (0x2080308dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS_MESSAGE_ID (0x8dU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS {
+    NvBool                                  bGet;
+    NvU32                                   alid;
+    NvU32                                   clid;
+    NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE alidClidTable;
+    NvBool                                  bClidUpdated;
+} NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY
+ *
+ * Signal to GSP that lazy error recovery can proceed.
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY (0x2080308aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x8A" */
+
+/*
+ * NV2080_CTRL_CMD_SET_NVLINK_CONFIGURE_L1_TOGGLE
+ *
+ * This command configures the nvlink L1 toggle pattern
+ *
+ * Commands returns SUCCESS only when it successfully sets value of all
+ * parameter in the list.
+ *
+ * Possible status return values are:
+ *  NV_OK
+ *
+ * Reference:
+ *
+ */
+#define NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE      (0x2080308eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE {
+    NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED = 0,
+    NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE = 1,
+    NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED = 2,
+    NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED = 3,
+    NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE = 4,
+} NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE;
+
+typedef struct NV2080_CTRL_NVLINK_L1_FORCE_CONFIG {
+    NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE mode;
+    NvU8                                        toggleActiveTime;
+    NvU8                                        toggleInactiveTime;
+    NvBool                                      bTrigger;
+} NV2080_CTRL_NVLINK_L1_FORCE_CONFIG;
+
+#define NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID (0x8EU)
+
+typedef struct NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS {
+    NvU32                              linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config;
+} NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE (0x2080308fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID (0x8FU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS {
+    NvU32                              linkMask;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
+    NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config[NV2080_CTRL_NVLINK_MAX_LINKS];
+} NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO
+ *
+ *  This command is used to get the ENCRYPT_EN register info
+ *
+ *  [out] bMmuNvlinkEncryptEn
+ *      Boolean that shows if ENCRYPTION_ENABLED bit in MMU is enabled or not.
+ *  [out] bNvlinkTlwEncryptEn
+ *      Boolean that shows if ENCRYPT_EN bit in NVLPLW TLW is enabled or not.
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO (0x2080308bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID (0x8bU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS {
+    NvBool bMmuNvlinkEncryptEn;
+    NvBool bNvlinkTlwEncryptEn;
+} NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO
+ *
+ *  This command is used to get the firmware version info
+ *
+ *  [out] firmwareVersion
+ *      Array of firmware versions specifying their ucode type, and major/minor/subminor version
+ *  [out] chipTypeArch
+ *      Chip type arch
+ *  [out] numValidEntries
+ *      Number of valid entries in firmwareVersion array
+ */
+
+#define NV2080_CTRL_NVLINK_FIRMWARE_VERSION_LENGTH                (0x10U)
+#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_MSE        (0x01U)
+#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR      (0x02U)
+#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_UPHY (0x03U)
+#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_CLN  (0x04U)
+#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_DLN  (0x05U)
+
+typedef struct NV2080_CTRL_NVLINK_SEMANTIC_VERSION {
+    NvU8  ucodeType;
+    NvU32 major;
+    NvU32 minor;
+    NvU32 subMinor;
+} NV2080_CTRL_NVLINK_SEMANTIC_VERSION;
+
+#define NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO (0x20803091U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS_MESSAGE_ID (0x91U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS {
+    NV2080_CTRL_NVLINK_SEMANTIC_VERSION firmwareVersion[NV2080_CTRL_NVLINK_FIRMWARE_VERSION_LENGTH];
+    NvU8                                chipTypeArch;
+    NvU32                               numValidEntries;
+} NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SET_NVLE_ENABLED_STATE
+ *
+ * This command is used to set the NVLE enablement status in GSP-RM
+ *
+ * [Out] bIsNvleEnabled
+ *     Boolean to determine if Nvlink Encryption is enabled or not
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_SET_NVLE_ENABLED_STATE (0x20803092U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS_MESSAGE_ID (0x92U)
+
+typedef struct NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS {
+    NvBool bIsNvleEnabled;
+} NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS (0x20803095U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID (0x95U)
+
+typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS {
+    NV2080_CTRL_NVLINK_PRM_DATA prm;
+} NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS;
+
+#define NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM_MAX_SIZE 32U
+
+typedef struct NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM {
+    NvUFXP0_8 data[NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM_MAX_SIZE];
+    NvU32     size;
+} NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM;
+
+typedef struct NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY {
+    NvU16 lastPlrTxBwLossLf;
+    NvU16 meanPlrTxBwLossLf;
+    NvU16 maxPlrTxBwLossLf;
+    NvU16 consBelowPlrTxBwLossLfThreshold;
+    NvU16 numOfPlrTxBwLossLfWarnings;
+    NvU16 numOfPlrTxBwLossLfAlarms;
+} NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY;
+
+typedef struct NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY {
+    NvU16 lastRecoveryBwLossLf;
+    NvU16 meanRecoveryBwLossLf;
+    NvU16 maxRecoveryBwLossLf;
+    NvU16 consBelowRecoveryBwLossLfThreshold;
+    NvU16 numOfRecoveryBwLossLfWarnings;
+    NvU16 numOfRecoveryBwLossLfAlarms;
+} NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY;
+
+typedef struct NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY {
+    NvU16 consBelowEffBerLfThreshold;
+    NvU16 numOfEffBerLfWarnings;
+    NvU16 numOfEffBerLfAlarms;
+    NvU8  meanEffBerLfMagnitude;
+    NvU8  lastEffBerLfMagnitude;
+    NvU8  maxEffBerLfMagnitude;
+    NvU8  maxEffBerLfCoef;
+} NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY;
+
+/*
+ * NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA
+ *
+ *  This command is used to retrieve persistent per-link metrics from beginning of life.
+ *    This command is supported for NVL IP version 5.0
+ *
+ *  [in]  linkId
+ *      link ID to query
+ *  [out] globalMaxRawBERExp // Blackwell Only
+ *      Largest lifetime RAW BER (exponent only)
+ *  [out] globalMaxEffBERExp // Blackwell Only
+ *      Largest lifetime EFF BER (exponent only)
+ *  [out] linkDownCount
+ *      Lifetime count of link down events (saturates)
+ *  [out] downReasonHistogram
+ *      Fixed-point histogram of unintentional link down reason codes with
+ *      recency bias
+ *  [out] linkXidHistogram
+  *      Fixed-point histogram of link xid codes with
+ *       recency bias
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA (0x20803097U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS_MESSAGE_ID (0x97U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS {
+    NvU32                                    linkId;
+    NvU8                                     globalMaxRawBERExp;
+    NvU8                                     globalMaxEffBERExp;
+    NvU32                                    linkDownCount;
+    NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM downReasonHistogram;
+    NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM linkXidHistogram;
+} NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS;
+
+/*
+ * NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA
+ *
+ *  This command is used to retrieve most recent persistent per-link metrics.
+ *    This command is supported for NVL IP version 5.0
+ *
+ *  [in]  linkId
+ *      link ID to query
+ *  [out] initialRawBERExp
+ *      Raw BER from most recent linkup (exponent only)
+ *  [out] initialEffBERExp
+ *      Eff BER from most recent linkup (exponent only)
+ *  [out] lastDownReason
+ *      Port down reason code from most recent linkdown
+ *  [out] uptime
+ *      Total time port has been up since most recent linkup (floating point msec)
+ *  [out] localMaxRawBERExp // Blackwell Only
+ *      Largest Raw BER reading since most recent linkup (exponent only)
+ *  [out] localMaxEffBERExp // Blackwell Only
+ *      Largest Eff BER reading since most recent linkup (exponent only)
+ *  [out] currEffBERMonitor
+ *      Current Eff BER monitor from most recent linkup
+ *  [out] plrXmitRetryWithinTSecMaxLo // Deprecated
+ *      PLR retransmissions in time window
+ *  [out] totalSuccessfulRecoveryEvents
+ *      Total number of times the Port Training state machine has
+ *        successfully completed the link error recovery process
+ * [out] plrTxBwLossLf
+ *       Link health statistics - PLR Tx BW loss low frequency
+ * [out] recoveryBwLossLf
+ *       Link health statistics - Recovery BW loss low frequency
+ * [out] effBerLf
+ *       Link health statistics - effective BER low frequency
+ * [out] lastDownAdvancedReason
+ *        More detailed reason code for the link going down
+ */
+#define NV2080_CTRL_CMD_NVLINK_GET_LINK_RECORD_METRIC_DATA (0x20803098U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS_MESSAGE_ID (0x98U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS {
+    NvU32                                             linkId;
+    NvU8                                              initialRawBERExp;
+    NvU8                                              initialEffBERExp;
+    NvU8                                              lastDownReason;
+    NvU32                                             uptime;
+    NvU8                                              localMaxRawBERExp;
+    NvU8                                              localMaxEffBERExp;
+    NvU16                                             currEffBERMonitor;
+    NvU32                                             plrXmitRetryWithinTSecMaxLo;
+    NvU32                                             totalSuccessfulRecoveryEvents;
+    NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY   plrTxBwLossLf;
+    NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY recoveryBwLossLf;
+    NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY    effBerLf;
+    NvU16                                             lastDownAdvancedReason;
+} NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS;
+
+/*
+ * NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA
+ *
+ *  This command is used to retrieve most recent persistent per-device metrics.
+ *    This command is supported for NVL IP version 5.0
+ *
+ *  [out] MFDE
+ *      PRM payload of most recent NETIR_MFDE_EVENT error
+ */
+
+#define NV2080_CTRL_CMD_NVLINK_GET_DEVICE_RECORD_METRIC_DATA (0x20803099U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS_MESSAGE_ID (0x99U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS {
+    NV2080_CTRL_NVLINK_PRM_DATA MFDE;
+} NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS;
+
+/*
+ * NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME
+ * NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME
+ *
+ * These commands store/retrieve a 64 char null-terminated ASCII string which is
+ * treated by the NVLINK firmware as the node's hostname for fabric reporting
+ * purposes.
+ */
+typedef struct NV2080_CTRL_NVLINK_NODE_HOSTNAME {
+    NvU8 name[64];
+} NV2080_CTRL_NVLINK_NODE_HOSTNAME;
+
+#define NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID (0x9AU)
+
+typedef struct NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS {
+    NV2080_CTRL_NVLINK_NODE_HOSTNAME hostname;
+} NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_SAVE_NODE_HOSTNAME (0x2080309aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID (0x9BU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS {
+    NV2080_CTRL_NVLINK_NODE_HOSTNAME hostname;
+} NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS;
+#define NV2080_CTRL_CMD_NVLINK_GET_SAVED_NODE_HOSTNAME (0x2080309bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_UPDATE_CLID
+ *
+ * Update the NVLE CLID
+ */
+#define NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS_MESSAGE_ID (0x9CU)
+
+typedef struct NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS {
+    NvU32 clid;
+} NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_UPDATE_CLID (0x2080309cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_LOCK_REMAP_TABLE_AND_MSE
+ *
+ * Request to lock the remap table to prevent MSE from making any further updates to the remap table for the given links
+ *
+ *  linkMask [IN]
+ *      NVLINK mask
+ *
+ *  bRemapTableMseLocked [OUT]
+ *      Whether remap table of the GPU is locked
+ *
+ *  bRemapTableLockDisabled [OUT]
+ *      Whether locking of remap table is disabled
+ */
+#define NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS_MESSAGE_ID (0x9DU)
+
+typedef struct NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+    NvBool bRemapTableMseLocked;
+    NvBool bRemapTableLockDisabled;
+} NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_LOCK_REMAP_TABLE_AND_MSE (0x2080309d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO
+ *
+ * Return the remap table addrs for all the entries in the FLA and SPA/GPA rempa tables
+ *
+ *  [out] flaRemapTabAddr
+ *      FLA remap table addrs for all the remap table entries
+ *  [out] gpaRemapTabAddr
+ *      SPA/GPA remap table addrs for all the remap table entries
+ *  [out] remapTabSize
+ *      Number of entries in the remap tables
+ */
+#define NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS_MESSAGE_ID (0x9EU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS {
+    NvU32 flaRemapTabAddr[NV_MAX_DEVICES];
+    NvU32 gpaRemapTabAddr[NV_MAX_DEVICES];
+    NvU32 remapTabSize;
+} NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO (0x2080309e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS
+ *
+ * This structure stores the NVLE acket counter information for both pipes of Tx and Rx link
+ *
+ * txPipe0Cntr
+ *    64 bit counter for Tx pipe0
+ * txPipe1Cntr
+ *    64 bit counter for Tx pipe1
+ * rxPipe0Cntr
+ *    64 bit counter for Rx pipe0
+ * rxPipe1Cntr
+ *    64 bit counter for Rx pipe1
+ */
+typedef struct NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS {
+    NV_DECLARE_ALIGNED(NvU64 txPipe0Cntr, 8);
+    NV_DECLARE_ALIGNED(NvU64 txPipe1Cntr, 8);
+    NV_DECLARE_ALIGNED(NvU64 rxPipe0Cntr, 8);
+    NV_DECLARE_ALIGNED(NvU64 rxPipe1Cntr, 8);
+} NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS;
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_NVLE_PKT_COUNTERS
+ *
+ * Get the Tx and Rx pipe0/1 NVLE packet counters for the mask of links passed
+ *
+ * [in] linkMask
+ *     Mask of links for which NVLE packet counters are queried
+ * [out] nvleCounters
+ *     The count of Tx and Rx pipe0/1 NVLE packet counters to be retrieved
+ */
+#define NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS_MESSAGE_ID (0x9FU)
+
+typedef struct NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS {
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK linkMask, 8);
+    NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS nvleCounters[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
+} NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_NVLE_PKT_COUNTERS       (0x2080309f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_NVLINK_NVLE_AES_256_GCM_KEY_SIZE_BYTES 32U
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_SETUP_NVLE_ENCRYPTION_KEY
+ *
+ * Sets the NVLE encryption key between GPUs with the given ALIDs
+ *
+ * [in] nvleKey
+ *     Key secret from which keyMgr will derive the key
+ * [in] localGpuAlid
+ *     ALID of the local GPU
+ * [in] remoteGpuAlid
+ *     ALID of the remote GPU
+ * [in] localGpuPlatformInfo
+ *     Platform information for the local GPU
+ * [in] remoteGpuPlatformInfo
+ *     Platform information for the remote GPU
+ */
+#define NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS_MESSAGE_ID (0xA0U)
+
+typedef struct NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS {
+    NvU8                                        nvleKey[NV2080_CTRL_NVLINK_NVLE_AES_256_GCM_KEY_SIZE_BYTES];
+    NvU32                                       localGpuAlid;
+    NvU32                                       remoteGpuAlid;
+    NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS localGpuPlatformInfo;
+    NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS remoteGpuPlatformInfo;
+} NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_SETUP_NVLE_ENCRYPTION_KEY (0x208030a0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO_V2
+ *
+ * Return the remap table addrs for a given set of entries in the FLA and SPA/GPA rempa tables
+ *
+ *  [out] flaRemapTabAddr
+ *      FLA remap table addrs for the given set of remap table entries
+ *  [out] gpaRemapTabAddr
+ *      SPA/GPA remap table addrs for the given set of remap table entries
+ *  [out] remapTabSize
+ *      Number of entries in the remap tables
+ *  [in] remapEntryStart
+ *      Entry to start parsing from
+ *  [in] remapEntryEnd
+ *      Entry to end parsing at
+ */
+#define NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS_MESSAGE_ID (0xA1U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS {
+    NvU32 flaRemapTabAddr[NV2080_CTRL_NVLINK_REMAP_TABLE_ENTRIES_CHUNK];
+    NvU32 gpaRemapTabAddr[NV2080_CTRL_NVLINK_REMAP_TABLE_ENTRIES_CHUNK];
+    NvU32 remapTabSize;
+    NvU32 remapEntryStart;
+    NvU32 remapEntryEnd;
+} NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS;
+
+#define NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO_V2 (0x208030a1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2
+ *
+ *  This command is used for the following operations.
+ *    If getting the LID information, the command gets the ALID and CLID of the GPU.
+ *    If setting the LID information, the command passes the complete ALID-CLID map.
+ *    The also command returns the status of whether the CLIDs are updated in the remap tables.
+ *
+ *  [in] bGet
+ *      Whether to get the ALIDs or set the CLIDs in the remap table or update the LIDs in the remap tables
+ *  [out] alid
+ *      ALID of the given GPU
+ *  [out] clid
+ *      CLID of the given GPU
+ *  [in] alidClidTable
+ *      Table with the ALIDs and corresponding mapped CLIDs - new version supporting more ALID-CLID mappings
+ *  [out] bClidUpdated
+ *      Whether CLIDs have been updated in the FLA and GPA remap tables
+ */
+#define NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS_MESSAGE_ID (0xA2U)
+
+typedef struct NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS {
+    NvBool                                     bGet;
+    NvU32                                      alid;
+    NvU32                                      clid;
+    NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2 alidClidTable;
+    NvBool                                     bClidUpdated;
+} NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS;
+
+#define NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2 (0x208030a2U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS_MESSAGE_ID" */
+
+
+/* _ctrl2080nvlink_h_ */
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink_common.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink_common.h
new file mode 100644
index 0000000..8a851b8
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink_common.h
@@ -0,0 +1,43 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080nvlink_common.finn
+//
+
+
+
+#define NV2080_CTRL_NVLINK_MAX_LINKS     64
+#define NV2080_CTRL_NVLINK_MAX_ARR_SIZE  64
+#define NV2080_CTRL_LINKS_PER_MASK_INDEX 64
+#define NV2080_CTRL_NVLINK_MAX_MASK_SIZE (0x1) /* finn: Evaluated from "((NV2080_CTRL_NVLINK_MAX_LINKS + 63) / NV2080_CTRL_LINKS_PER_MASK_INDEX)" */
+
+typedef struct NV2080_CTRL_NVLINK_LINK_MASK {
+    NvU8 lenMasks;
+    NV_DECLARE_ALIGNED(NvU64 masks[NV2080_CTRL_NVLINK_MAX_MASK_SIZE], 8);
+} NV2080_CTRL_NVLINK_LINK_MASK;
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf.h
new file mode 100644
index 0000000..778736a
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf.h
@@ -0,0 +1,927 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080perf.finn
+//
+
+#include "nvfixedtypes.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+#define NV_SUBPROC_NAME_MAX_LENGTH                    100
+
+#include "nvmisc.h"
+
+#include "ctrl/ctrl2080/ctrl2080clk.h"
+#include "ctrl/ctrl2080/ctrl2080gpumon.h"
+#include "ctrl/ctrl2080/ctrl2080volt.h"
+#include "ctrl/ctrl2080/ctrl2080vfe.h"
+#include "ctrl/ctrl2080/ctrl2080pmumon.h"
+#include "ctrl/ctrl0080/ctrl0080perf.h"
+//
+// XAPICHK/XAPI_TEST chokes on the "static NVINLINE" defines in nvmisc.h.
+// However, we don't need any of those definitions for those tests (XAPICHK is a
+// syntactical check, not a functional test).  So, instead, just #define out the
+// macros referenced below.
+//
+
+/*
+ * NV2080_CTRL_CMD_PERF_BOOST
+ *
+ * This command can be used to boost P-State up one level or to the highest for a limited
+ * duration for the associated subdevice. Boosts from different clients are being tracked
+ * independently. Note that there are other factors that can limit P-States so the resulting
+ * P-State may differ from expectation.
+ *
+ *   flags
+ *     This parameter specifies the actual command. _CLEAR is to clear existing boost.
+ *     _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost
+ *     to the highest P-State.
+ *   duration
+ *     This parameter specifies the duration of the boost in seconds. This has to be less
+ *     than NV2080_CTRL_PERF_BOOST_DURATION_MAX.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD                1:0
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR        (0x00000000)
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL (0x00000001)
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX (0x00000002)
+
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA               4:4
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO          (0x00000000)
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES         (0x00000001)
+
+#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC              5:5
+#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO         (0x00000000)
+#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES        (0x00000001)
+
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY          6:6
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT  (0x00000000)
+#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH     (0x00000001)
+
+#define NV2080_CTRL_PERF_BOOST_DURATION_MAX           3600 //The duration can be specified up to 1 hour
+#define NV2080_CTRL_PERF_BOOST_DURATION_INFINITE      0xffffffff // If set this way, the boost will last until cleared.
+
+#define NV2080_CTRL_CMD_PERF_BOOST                    (0x2080200a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_PERF_BOOST_PARAMS {
+    NvU32 flags;
+    NvU32 duration;
+} NV2080_CTRL_PERF_BOOST_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW
+ *
+ *  This command reserves HW Performance Monitoring capabilities for exclusive
+ *  use by the requester.  If the HW Performance Monitoring capabilities are
+ *  currently in use then NVOS_STATUS_ERROR_STATE_IN_USE is returned.
+ *
+ *   bAcquire
+ *     When set to TRUE this parameter indicates that the client wants to
+ *     acquire the Performance Monitoring capabilities on the subdevice.
+ *     When set to FALSE this parameter releases the Performance Monitoring
+ *     capabilities on the subdevice.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NVOS_STATUS_ERROR_STATE_IN_USE
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW (0x20802093) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID (0x93U)
+
+typedef struct NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS {
+    NvBool bAcquire;
+} NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS;
+
+/*
+ * NV2080_CTRL_PERF_POWERSTATE
+ *
+ * This structure describes power state information.
+ *
+ *    powerState
+ *       This parameter specifies the type of power source.
+ *       Legal values for this parameter include:
+ *          NV2080_CTRL_PERF_POWER_SOURCE_AC
+ *             This values indicates that the power state is AC.
+ *          NV2080_CTRL_PERF_POWER_SOURCE_BATTERY
+ *             This values indicates that the power state is battery.
+ */
+#define NV2080_CTRL_PERF_POWER_SOURCE_AC      (0x00000000)
+#define NV2080_CTRL_PERF_POWER_SOURCE_BATTERY (0x00000001)
+
+typedef struct NV2080_CTRL_PERF_POWERSTATE_PARAMS {
+    NvU32 powerState;
+} NV2080_CTRL_PERF_POWERSTATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_SET_POWERSTATE
+ *
+ * This command can be used to set the perf power state as AC or battery.
+ *
+ *    powerStateInfo
+ *       This parameter specifies the power source type to set.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_PERF_SET_POWERSTATE (0x2080205b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID (0x5BU)
+
+typedef struct NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS {
+    NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo;
+} NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE
+ *
+ * This command allows the forcing of a performance level based on auxiliary
+ * power-states.
+ *
+ *   powerState
+ *     This parameter specifies the target auxiliary Power state. Legal aux
+ *     power-states for this parameter are defined by the
+ *     NV2080_CTRL_PERF_AUX_POWER_STATE_P* definitions that follow.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE (0x20802092) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x92U)
+
+typedef struct NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS {
+    NvU32 powerState;
+} NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS;
+
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_P0    (0x00000000)
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_P1    (0x00000001)
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_P2    (0x00000002)
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_P3    (0x00000003)
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_P4    (0x00000004)
+#define NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT (0x00000005)
+
+/*!
+ * Enumeration of the RATED_TDP arbitration clients which make requests to force
+ * enable/disable VF points above the RATED_TDP point.
+ *
+ * These clients are sorted in descending priority - the RM will arbitrate
+ * between all clients in order of priority, taking as output the first client
+ * whose input action != @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT.
+ */
+typedef enum NV2080_CTRL_PERF_RATED_TDP_CLIENT {
+    /*!
+     * Internal RM client corresponding to the RM's internal state and features.
+     * The RM client will either allow default behavior (@ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT) or will limit to RATED_TDP
+     * (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) when no power
+     * controllers are active.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = 0,
+    /*!
+     * This Client is specifically for Bug 1785342 where we need to limit the TDP
+     * to Min value on boot. And clear the Max TDP limit.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = 1,
+    /*!
+     * Global client request.  This client is expected to be used by a global
+     * switch functionality in an end-user tool, such as EVGA Precision, to
+     * either force enabling boost above RATED_TDP (@ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED) or to force limiting to
+     * RATED_TDP (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) across the
+     * board, regardless of any app-profie settings.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = 2,
+    /*!
+     * Operating system request.  This client is expected to be used by the
+     * operating system to set @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK
+     * for performance profiling.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = 3,
+    /*!
+     * App profile client requests.  This client is expected to be used by the
+     * app-profile settings to either default to whatever was requested by
+     * higher-priority clients (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT)
+     * or to limit to RATED_TDP (@ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) for apps which have shown
+     * bad behavior when boosting.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = 4,
+    /*!
+     * Number of supported clients.
+     *
+     * @Note MUST ALWAYS BE LAST!
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = 5,
+} NV2080_CTRL_PERF_RATED_TDP_CLIENT;
+
+/*!
+ * Enumeration RATED_TDP actions - these are the requested actions clients can
+ * make to change the behavior of the RATED_TDP functionality.
+ */
+typedef enum NV2080_CTRL_PERF_RATED_TDP_ACTION {
+    /*!
+     * The default action - meaning no explicit request from the client other
+     * than to take the default behavior (allowing boosting above RATED_TDP) or
+     * any explicit actions from lower priority clients.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = 0,
+    /*!
+     * Force allow boosting above RATED_TDP - this action explicitly requests
+     * boosting above RATED_TDP, preventing lower priority clients to limit to
+     * RATED_TDP.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = 1,
+    /*!
+     * Force to limit above RATED_TDP - this action explicitly requests to limit
+     * to RATED_TDP.  This is the opposite of the default behavior to allow
+     * boosting above RATED_TDP.  Clients specify this action when they
+     * explicitly need boost to be disabled (e.g. eliminating perf variation,
+     * special apps which exhibit bad behavior, etc.).
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = 2,
+    /*!
+     * Lock to RATED_TDP - this action requests the clocks to be fixed at the
+     * RATED_TDP.  Used for achieving stable clocks required for profiling.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = 3,
+    /*!
+     * Lock to Min TDP - This requests min to be fixed at RATED_TDP but allow
+     * boosting for max
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4,
+} NV2080_CTRL_PERF_RATED_TDP_ACTION;
+
+/*!
+ * Enumeration VPstates - these are possible VPStates that clients can
+ * request
+ */
+typedef enum NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE {
+    /*!
+     * Choise of the RATED TDP VPstate
+     */
+    NV2080_CTRL_PERF_VPSTATE_RATED_TDP = 0,
+    /*!
+     * Choise of the TURBO BOOST VPstate
+     */
+    NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST = 1,
+    /*!
+     * Number of supported vpstates.
+     *
+     * @Note MUST ALWAYS BE LAST!
+     */
+    NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES = 2,
+} NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE;
+
+/*!
+ * Enumeration VPstates - these are possible VPStates that clients can
+ * request
+ */
+typedef struct NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST {
+    /*!
+     * [in] - Specified client for request.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION       action;
+    /*!
+     * [in/out] - Client's requested action.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateType;
+} NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST;
+
+/*!
+ * Structure describing dynamic state of the RATED_TDP feature.
+ */
+#define NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID (0x6DU)
+
+typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS {
+    /*!
+     * Structure of internal RM state - these values are used to determine the
+     * behavior of NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM per the RM's @ref
+     * perfPwrRatedTdpLimitRegisterClientActive() interface.
+     */
+    struct {
+        /*!
+         * [out] - Mask of active client controllers (@ref
+         * PERF_PWR_RATED_TDP_CLIENT) which are currently regulating TDP.  When
+         * this mask is zero, NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request
+         * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
+         */
+        NvU32 clientActiveMask;
+        /*!
+         * [out] - Boolean indicating that user has requested locking to
+         * RATED_TDP vPstate via corresponding regkey
+         * NV_REG_STR_RM_PERF_RATED_TDP_LIMIT.  When the boolean value is true,
+         * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request
+         * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
+         */
+        NvU8  bRegkeyLimitRatedTdp;
+    } rm;
+
+    /*!
+     * [out] - Arbitrated output action of all client requests (@ref inputs).
+     * This is the current state of the RATED_TDP feature.  Will only be @ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED or @ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION       output;
+    /*
+     * [out] - Arbitrated output VPStates of all client requests (@ref inputs).
+     * This is the current VPState of the RATED_TDP feature.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE outputVPstate;
+    /*!
+     * [out] - Array of input client request actions, indexed via @ref
+     * NV2080_CTRL_PERF_RATED_TDP_CLIENT_<xyz>.  RM will arbitrate between these
+     * requests, choosing the highest priority request != @ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION       inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
+    /*!
+     * [out] - Array of input client request VPstates, indexed via @ref
+     * NV2080_CTRL_PERF_RATED_TDP_CLIENT_<xyz>.  RM will arbitrate between these
+     * requests, choosing the highest priority request != @ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref
+     * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateTypes[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
+} NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL
+ *
+ * This command retrieves the current requested RATED_TDP action corresponding
+ * to the specified client.
+ *
+ * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
+ * parameters.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID" */
+
+/*!
+ * Structure containing the requested action for a RATED_TDP client (@ref
+ * NV2080_CTRL_PERF_RATED_TDP_CLIENT).
+ */
+typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS {
+    /*!
+     * [in] - Specified client for request.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_CLIENT       client;
+    /*!
+     * [in/out] - Client's requested action.
+     */
+    NV2080_CTRL_PERF_RATED_TDP_ACTION       input;
+    /*
+     * [in] - Specified VPState of the request
+     */
+    NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateType;
+} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS;
+
+#define NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID (0x6EU)
+
+typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL
+ *
+ * This command sets the requested RATED_TDP action corresponding to the
+ * specified client.  @Note, however, that this command is unable to set @ref
+ * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM.
+ *
+ * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
+ * parameters.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID (0x6FU)
+
+typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS;
+
+/*!
+ * This struct represents the GPU monitoring perfmon sample for an engine.
+ */
+typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE {
+    /*!
+     * Percentage during the sample that the engine remains busy. This
+     * is in units of pct*100.
+     */
+    NvU32 util;
+    /*!
+     * Scaling factor to convert utilization from full GPU to per vGPU.
+     */
+    NvU32 vgpuScale;
+    /*!
+     * Process ID of the process that was active on the engine when the
+     * sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID
+     * will be returned.
+     */
+    NvU32 procId;
+    /*!
+     * Process ID of the process in the vGPU VM that was active on the engine when
+     * the sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID
+     * will be returned.
+     */
+    NvU32 subProcessID;
+     /*!
+     * Process name of the process in the vGPU VM that was active on the engine when
+     * the sample was taken. If no process is active then NULL will be returned.
+     */
+    char  subProcessName[NV_SUBPROC_NAME_MAX_LENGTH];
+    /*!
+     * PID struct pointer of the process that was active on the engine when the
+     * the sample was taken. If no process is active then NULL pointer
+     * will be returned
+     */
+    NV_DECLARE_ALIGNED(NvU64 pOsPidInfo, 8);
+} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE;
+
+/*!
+ * This struct represents the GPU monitoring perfmon sample.
+ */
+typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE {
+    /*!
+     * Base GPU monitoring sample.
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_GPUMON_SAMPLE base, 8);
+    /*!
+     * FB bandwidth utilization sample.
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb, 8);
+    /*!
+     * GR utilization sample.
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr, 8);
+    /*!
+     * NV ENCODER utilization sample.
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc, 8);
+    /*!
+     * NV DECODER utilization sample.
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec, 8);
+    /*!
+     * NV JPEG utilization sample.
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg, 8);
+    /*!
+     * NV OFA utilization sample.
+     */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa, 8);
+} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE;
+
+/*!
+ * This struct represents the GPU monitoring samples of perfmon values that
+ * client wants the access to.
+ */
+#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID (0x83U)
+
+typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM;
+
+/*!
+ * Number of GPU monitoring sample in their respective buffers.
+ */
+#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL       72
+
+#define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE           \
+    sizeof(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) *          \
+    NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL
+
+/*!
+ * NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2
+ *
+ * This command returns perfmon gpu monitoring utilization samples.
+ * This command is not supported with SMC enabled.
+ *
+ * See NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_V2 for documentation
+ * on the parameters.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *
+ * Note this is the same as NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES
+ * but without the embedded pointer.
+ *
+ */
+#define NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 (0x20802096) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID" */
+
+/*!
+ *  This structure represents the GPU monitoring samples of utilization values that
+ *  the client wants access to.
+ */
+#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID (0x96U)
+
+typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS {
+    /*!
+    * Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference.
+    */
+    NvU8  type;
+    /*!
+    * Size of the buffer, this should be
+    * bufSize ==  NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_*
+    *    sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE).
+    */
+    NvU32 bufSize;
+    /*!
+    * Number of samples in ring buffer.
+    */
+    NvU32 count;
+    /*!
+    * tracks the offset of the tail in the circular queue array pSamples.
+    */
+    NvU32 tracker;
+    /*!
+    * A circular queue with size == bufSize.
+    *
+    * @note This circular queue wraps around after 10 seconds of sampling,
+    * and it is clients' responsibility to query within this time frame in
+    * order to avoid losing samples.
+    * @note With one exception, this queue contains last 10 seconds of samples
+    * with tracker poiniting to oldest entry and entry before tracker as the
+    * newest entry. Exception is when queue is not full (i.e. tracker is
+    * pointing to a zeroed out entry), in that case valid entries are between 0
+    * and tracker.
+    * @note Clients can store tracker from previous query in order to provide
+    * samples since last read.
+    */
+    NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL], 8);
+} NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_GPU_IS_IDLE
+ *
+ * This command notifies RM to make p state switching aggressive by setting
+ * required limiting factors to speed up GC6 Entry initiation.
+ *
+ *  prevPstate [out]
+ *      This parameter will contain the pstate before the switch was initiated
+ *
+ * Possible status return values are:
+ *   NV_OK : If P State Switch is successful
+ *   NV_INVALID_STATE : If unable to access P State structure
+ *   NVOS_STATUS_ERROR   : If P State Switch is unsuccessful
+ */
+#define NV2080_CTRL_CMD_PERF_GPU_IS_IDLE (0x20802089) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID (0x89U)
+
+typedef struct NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS {
+    NvU32 prevPstate;
+    NvU32 action;
+} NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS;
+
+#define NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE             (0x00000001)
+#define NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE            (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY
+ *
+ * This command is for the KMD Aggressive P-state feature.
+ *
+ *  bGpuIsIdle [in]
+ *      When true, applies cap to lowest P-state/GPCCLK. When false, releases cap.
+ *  idleTimeUs [in]
+ *      The amount of time (in microseconds) the GPU was idle since previous
+ *      call, part of the GPU utilization data from KMD.
+ *  busyTimeUs [in]
+ *      The amount of time (in microseconds) the GPU was not idle since
+ *      previous call, part of the GPU utilization data from KMD.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+
+
+#define NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY (0x2080208f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID (0x8FU)
+
+typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS {
+    NvBool bGpuIsIdle;
+    NvBool bRestoreToMax;
+    NV_DECLARE_ALIGNED(NvU64 idleTimeUs, 8);
+    NV_DECLARE_ALIGNED(NvU64 busyTimeUs, 8);
+} NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS;
+
+
+typedef struct NV2080_CTRL_PERF_GET_CLK_INFO {
+    NvU32 flags;
+    NvU32 domain;
+    NvU32 currentFreq;
+    NvU32 defaultFreq;
+    NvU32 minFreq;
+    NvU32 maxFreq;
+} NV2080_CTRL_PERF_GET_CLK_INFO;
+
+
+#define NV2080_CTRL_PERF_CLK_MAX_DOMAINS    32U
+
+#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO (0x20802002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS {
+    NvU32 level;
+    NvU32 flags;
+    NV_DECLARE_ALIGNED(NvP64 perfGetClkInfoList, 8);
+    NvU32 perfGetClkInfoListSize;
+} NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 (0x2080200b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS {
+    NvU32                         level;
+    NvU32                         flags;
+    NV2080_CTRL_PERF_GET_CLK_INFO perfGetClkInfoList[NV2080_CTRL_PERF_CLK_MAX_DOMAINS];
+    NvU32                         perfGetClkInfoListSize;
+} NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS;
+
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_LEVEL_STANDARD       0
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_LEVEL_CONSERVATIVE   1
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_LEVEL_AGGRESSIVE     2
+
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE                 0:0
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT   (0x00000000)
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK (0x00000001)
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE                 2:1
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE      (0x00000000)
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP   (0x00000001)
+#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF   (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE
+ *
+ * This command can be used to obtain video decoder utilization of
+ * the associated subdevice.
+ * This command is not supported with SMC enabled.
+ *
+ *   engineType
+ *     This parameter will allow clients to set type of video
+ *     engine in question. It can be NVENC or NVDEC.
+ *   clkPercentBusy
+ *     This parameter contains the percentage during the sample that
+ *     the clock remains busy.
+ *   samplingPeriodUs
+ *     This field returns the sampling period in microseconds.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE      (0x20802087) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID" */
+
+typedef enum NV2080_CTRL_CMD_PERF_VID_ENG {
+    /*!
+     * GPU Video encoder engine.
+     */
+    NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = 1,
+
+    /*!
+     * GPU video decoder engine.
+     */
+    NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = 2,
+
+    /*!
+     * GPU JPEG engine.
+     */
+    NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = 3,
+
+    /*!
+     * GPU OFA engine.
+     */
+    NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = 4,
+} NV2080_CTRL_CMD_PERF_VID_ENG;
+
+#define NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID (0x87U)
+
+typedef struct NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS {
+    NV2080_CTRL_CMD_PERF_VID_ENG engineType;
+    NvU32                        clkPercentBusy;
+    NvU32                        samplingPeriodUs;
+} NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_GET_POWERSTATE
+ *
+ * This command can be used to find out whether the perf power state is AC/battery.
+ *
+ *    powerStateInfo
+ *       This parameter specifies the power source type.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_PERF_GET_POWERSTATE (0x2080205a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID (0x5AU)
+
+typedef struct NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS {
+    NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo;
+} NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT
+ *
+ * This command can be used by video driver to notify RM concerning
+ * performance related events.
+ *
+ *    videoEvent
+ *       This parameter specifies the video event to notify.
+ *       Legal values for this parameter include:
+ *          NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START
+ *          NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP
+ *             These values indicate that a HD video stream (less than 4K)
+ *             has started/stopped.
+ *          NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START
+ *          NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP
+ *             These are now obsolete in new products as we no longer
+ *             need to differentiate between SD and HD.
+ *          NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START
+ *          NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP
+ *             These value indicates that a 4K video stream (3840x2160 pixels
+ *             or higher) has started/stopped.
+ *          NV2080_CTRL_PERF_VIDEOEVENT_OFA_START
+ *          NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP
+ *             These value indicates that Optical Flow Accelerator usage has
+ *             started/stopped.
+ *       The following flags may be or'd into the event value:
+ *          NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE
+ *              The stream operates BSP/VP2 or MSVLD/MSPDEC communication in
+ *              linear mode (default is ring mode).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+#define NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT (0x2080205d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID (0x5DU)
+
+typedef struct NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS {
+    NvU32 videoEvent;
+} NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS;
+
+#define NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK       (0x0000ffff)
+#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START  (0x00000001)
+#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP   (0x00000002)
+#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START     NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START
+#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP      NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP
+#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START  (0x00000003)
+#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP   (0x00000004)
+#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START  (0x00000005)
+#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP   (0x00000006)
+#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_START        (0x00000007)
+#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP         (0x00000008)
+#define NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE (0x00010000)
+
+/*!
+ * @defgroup NV2080_CTRL_PERF_PSTATES
+ *
+ * These are definitions of performance states (P-states) values.
+ * P0 has the maximum performance capability and consumes maximum
+ * power. P1 has a lower perf and power than P0, and so on.
+ * For NVIDIA GPUs, the following definitions are made:
+ * P0    - maximum 3D performance
+ * P1    - original P0 when active clocked
+ * P2-P3 - balanced 3D performance-power
+ * P8    - basic HD video playback
+ * P10   - SD video playback
+ * P12   - minimum idle power
+ * P15   - max possible P-state under current scheme (currently not used)
+ * Not all P-states are available on a given system.
+ *
+ * @note    The @ref NV2080_CTRL_PERF_PSTATES_ID was introduced after the
+ *          original constants were added, so not all places that intend to use
+ *          these values are using the type. They should be updated to do so.
+ * @{
+ */
+typedef NvU32 NV2080_CTRL_PERF_PSTATES_ID;
+#define NV2080_CTRL_PERF_PSTATES_UNDEFINED      (0x00000000U)
+#define NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED   (0x00000000U)
+#define NV2080_CTRL_PERF_PSTATES_MIN            (0x00000001U)
+#define NV2080_CTRL_PERF_PSTATES_P0             (0x00000001U)
+#define NV2080_CTRL_PERF_PSTATES_P1             (0x00000002U)
+#define NV2080_CTRL_PERF_PSTATES_P2             (0x00000004U)
+#define NV2080_CTRL_PERF_PSTATES_P3             (0x00000008U)
+#define NV2080_CTRL_PERF_PSTATES_P4             (0x00000010U)
+#define NV2080_CTRL_PERF_PSTATES_P5             (0x00000020U)
+#define NV2080_CTRL_PERF_PSTATES_P6             (0x00000040U)
+#define NV2080_CTRL_PERF_PSTATES_P7             (0x00000080U)
+#define NV2080_CTRL_PERF_PSTATES_P8             (0x00000100U)
+#define NV2080_CTRL_PERF_PSTATES_P9             (0x00000200U)
+#define NV2080_CTRL_PERF_PSTATES_P10            (0x00000400U)
+#define NV2080_CTRL_PERF_PSTATES_P11            (0x00000800U)
+#define NV2080_CTRL_PERF_PSTATES_P12            (0x00001000U)
+#define NV2080_CTRL_PERF_PSTATES_P13            (0x00002000U)
+#define NV2080_CTRL_PERF_PSTATES_P14            (0x00004000U)
+#define NV2080_CTRL_PERF_PSTATES_P15            (0x00008000U)
+#define NV2080_CTRL_PERF_PSTATES_MAX            NV2080_CTRL_PERF_PSTATES_P15
+#define NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY     (0x10000U) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX << 1)" */
+#define NV2080_CTRL_PERF_PSTATES_ALL            (0xffffU) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX | (NV2080_CTRL_PERF_PSTATES_MAX - 1))" */
+/*!@}*/
+
+/*
+ * NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE
+ *
+ * This command returns the current performance state of the GPU.
+ *
+ *   currPstate
+ *     This parameter returns the current P-state, as defined in
+ *     NV2080_CTRL_PERF_PSTATES values.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE (0x20802068) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID (0x68U)
+
+typedef struct NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS {
+    NvU32 currPstate;
+} NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_PERF_GET_TEGRA_PERFMON_SAMPLE
+ *
+ * Fetch the busyness of the specified clock domain in percentage
+ * for Tegra chips.
+ *
+ *   clkDomain
+ *     Clock domain identifier for Tegra platforms.
+ *
+ *   clkPercentBusy
+ *     Busyness of the specified clock domain in percentage
+ *     unit ranging from 0 to 100.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_PERF_GET_TEGRA_PERFMON_SAMPLE (0x20802069) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS_MESSAGE_ID" */
+
+typedef NvU32 NV2080_CTRL_CLK_DOMAIN_TEGRA;
+
+#define NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS_MESSAGE_ID (0x69U)
+
+typedef struct NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS {
+    NV2080_CTRL_CLK_DOMAIN_TEGRA clkDomain;
+    NvU32                        clkPercentBusy;
+} NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS;
+
+
+/* _ctrl2080perf_h_ */
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf.h
new file mode 100644
index 0000000..137549f
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf.h
@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080perf_cf.finn
+//
+
+
+/* _ctrl2080perf_cf_h_ */
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h
new file mode 100644
index 0000000..a0b1190
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn
+//
+
+
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmgr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmgr.h
new file mode 100644
index 0000000..6fcd9ac
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmgr.h
@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080pmgr.finn
+//
+
+
+
+#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED  0U
+#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED      1U
+#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE 2U
+
+/*!
+ * NV2080_CTRL_PMGR_MODULE_INFO_PARAMS
+ *
+ * This provides information about different module properties
+ *
+ * moduleId[OUT]
+ *     - This is a static HW identifier that is unique for each module on a given baseboard.
+ *       For non-baseboard products this would always be 0.
+ * nvswitchSupport[OUT]
+ *     - NVSwitch present or not. Possible values are
+ *        NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED
+ *        NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED
+ *        NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE
+ */
+#define NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_PMGR_MODULE_INFO_PARAMS {
+    NvU32 moduleId;
+    NvU8  nvswitchSupport;
+} NV2080_CTRL_PMGR_MODULE_INFO_PARAMS;
+
+/*!
+ * NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO
+ *
+ * Control call to query the subdevice module INFO.
+ *
+ */
+#define NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO (0x20802609) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID << 8) | NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID" */
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmu.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmu.h
new file mode 100644
index 0000000..a364a64
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmu.h
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080pmu.finn
+//
+
+
+
+/*!
+ * @file
+ *
+ * @brief   Enumeration of all PMU RMCTRL identifiers.
+ */
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmumon.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmumon.h
new file mode 100644
index 0000000..2cdde1e
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmumon.h
@@ -0,0 +1,100 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080pmumon.finn
+//
+
+
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/*!
+ * Enumeration of retrieval modes that dictate how many 
+ * samples to grab from the PMUMON queue.
+ */
+typedef enum NV2080_CTRL_PMUMON_RETRIEVAL_MODE {
+    NV2080_CTRL_PMUMON_RETRIEVAL_MODE_ALL_SAMPLES = 0,
+    NV2080_CTRL_PMUMON_RETRIEVAL_MODE_LATEST_SAMPLE_ONLY = 1,
+} NV2080_CTRL_PMUMON_RETRIEVAL_MODE;
+
+/*!
+ *  This structure represents base class of PMUMON sample.
+ */
+typedef struct NV2080_CTRL_PMUMON_SAMPLE {
+    /*!
+    * Ptimer timestamp in nano-seconds at the time this sample was taken.
+    */
+    NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
+} NV2080_CTRL_PMUMON_SAMPLE;
+
+/*!
+ * Common meta-data to be used in control call parameters regarding sampling of
+ * FB Circular Queues.
+ */
+typedef struct NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER {
+    /*!
+     * [in/out] Requested starting index for reading into the circular queue.
+     *          This field will be set to (headIndex + 1) % QUEUE_SIZE
+     *          automatically by the control call.
+     */
+    NvU32                             tailIndex;
+
+    /*!
+     * [in/out] Current sequence ID of the underlying PMUMON queue. Not to be
+     *          modified by the caller. Will be modified automatically by the
+     *          control call.
+     */
+    NvU32                             sequenceId;
+
+    /*!
+     * [out] Current head of the queue. The entry at this index in the queue
+     *       is the most recently published.
+     */
+    NvU32                             headIndex;
+
+    /*!
+     * [out] Number of elements copied into samples[] starting from samples[0]
+     *       of parent structure. This is the number of elements between the
+     *       input tailIndex and current headIndex
+     */
+    NvU32                             numSamples;
+
+    /*!
+     * [out] Number of times the PMUMON queue in FB has been reset
+     *       (i.e. pmuStateLoad). When resetCount of the RM and the client
+     *       differ, the RM will correctly resume reading of queue from index 0
+     *       instead of attempting to catch up from last read.
+     */
+    NvU32                             resetCount;
+
+    /*!
+     * [in] @copydoc NV2080_CTRL_PMUMON_RETRIEVAL_MODE
+     */
+    NV2080_CTRL_PMUMON_RETRIEVAL_MODE retrievalMode;
+} NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER;
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080power.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080power.h
new file mode 100644
index 0000000..2f0abcb
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080power.h
@@ -0,0 +1,123 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080power.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+
+
+/*!
+ * @brief GC6 flavor ids
+ */
+typedef enum NV2080_CTRL_GC6_FLAVOR_ID {
+    NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = 0,
+    NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = 1,
+
+
+    NV2080_CTRL_GC6_FLAVOR_ID_MAX = 4,
+} NV2080_CTRL_GC6_FLAVOR_ID;
+
+/*
+ * NV2080_CTRL_CMD_GC6_ENTRY
+ *
+ * This command executes the steps of GC6 entry sequence
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED (non-fatal)
+ *   NV_ERR_INVALID_STATE (non-fatal)
+ *   NV_ERR_INVALID_ARGUMENT (non-fatal)
+ *   NV_ERR_NOT_READY (non-fatal)
+ *   NV_ERR_TIMEOUT
+ *   NV_ERR_GENERIC
+ */
+#define NV2080_CTRL_CMD_GC6_ENTRY (0x2080270d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV2080_CTRL_GC6_ENTRY_PARAMS {
+    NV2080_CTRL_GC6_FLAVOR_ID flavorId;
+    NvU32                     stepMask;
+    struct {
+
+
+        NvBool bIsRTD3Transition;
+        NvBool bIsRTD3CoreRailPowerCut;
+
+
+        NvBool bSkipPstateSanity;
+    } params;
+} NV2080_CTRL_GC6_ENTRY_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_GC6_EXIT
+ *
+ * This command executes the steps of GC6 exit sequence
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_GENERIC
+ */
+#define NV2080_CTRL_CMD_GC6_EXIT (0x2080270e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_GC6_EXIT_PARAMS {
+    NV2080_CTRL_GC6_FLAVOR_ID flavorId;
+    struct {
+        NvBool bIsGpuSelfWake;
+        NvBool bIsRTD3Transition;
+
+
+        NvBool bIsRTD3HotTransition;   //output
+    } params;
+} NV2080_CTRL_GC6_EXIT_PARAMS;
+
+/*!
+ * @brief GC6 step ids
+ */
+typedef enum NV2080_CTRL_GC6_STEP_ID {
+    NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = 0,
+    NV2080_CTRL_GC6_STEP_ID_GPU_OFF = 1,
+    NV2080_CTRL_GC6_STEP_ID_MAX = 2,
+} NV2080_CTRL_GC6_STEP_ID;
+
+typedef struct NV2080_CTRL_GC6_FLAVOR_INFO {
+    NV2080_CTRL_GC6_FLAVOR_ID flavorId;
+    NvU32                     stepMask;
+} NV2080_CTRL_GC6_FLAVOR_INFO;
+
+
+
+/* _ctrl2080power_h_ */
+
+
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080rc.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080rc.h
new file mode 100644
index 0000000..25039c5
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080rc.h
@@ -0,0 +1,414 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080rc.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/*
+ * NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM
+ *
+ * This command returns data read from the specified virtual memory address for
+ * the associated subdevice.
+ *
+ *   hChannel
+ *      This parameter specifies the channel object handle from which the virtual
+ *      memory range applies.
+ *   virtAddress
+ *      This parameter specifies the GPU base virtual memory address from which data should
+ *      be read.  The amount of data read is specified by the bufferSize parameter.
+ *   bufferPtr
+ *      This parameter specifies the buffer address in the caller's address space into which
+ *      the data is to be returned.  The address must be aligned on an 8-byte boundary.
+ *      The buffer must be at least as big as the value specified bufferSize parameter (in bytes).
+ *   bufferSize
+ *      This parameter specifies the size of the buffer referenced by the bufferPtr parameter.
+ *      This parameter also indicates the total number of bytes to be returned.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_XLATE
+ */
+#define NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS {
+    NvHandle hChannel;
+    NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
+    NV_DECLARE_ALIGNED(NvP64 bufferPtr, 8);
+    NvU32    bufferSize;
+} NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS;
+
+#define NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM (0x20802204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_RC_GET_ERROR_COUNT
+ *
+ * This command returns the number of RC errors.
+ *
+ *   errorCount
+ *      Number of RC errors.
+ *
+ * Note: If SMC is enabled, mig/monitor capability must be acquired to query
+ * aggregate information. Otherwise, the control call returns
+ * NV_ERR_INSUFFICIENT_PERMISSIONS.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS.
+ */
+#define NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS {
+    NvU32 errorCount;
+} NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS;
+
+#define NV2080_CTRL_CMD_RC_GET_ERROR_COUNT      (0x20802205) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE (0x2000) /* finn: Evaluated from "(8 * 1024)" */
+
+#define NV2080_CTRL_CMD_RC_GET_ERROR            (0x20802206) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x6" */
+
+/*
+ * NV2080_CTRL_CMD_RC_GET_ERROR_V2
+ *
+ * This command returns an error element in the RC error list.
+ *
+ *   whichBuffer
+ *      Which Error to return (0 is oldest)
+ *   outputRecordSize
+ *      Output Size of Buffer -- Zero if error record doesn't exist
+ *   recordBuffer
+ *      buffer
+ *
+ * Note: If SMC is enabled, mig/monitor capability must be acquired to query
+ * aggregate information. Otherwise, the control call returns
+ * NV_ERR_INSUFFICIENT_PERMISSIONS.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INSUFFICIENT_PERMISSIONS.
+ *
+ */
+
+#define NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_RC_GET_ERROR_V2_PARAMS {
+
+    NvU32 whichBuffer;                   // [IN]   - which error to return (0 is oldest)
+    NvU32 outputRecordSize;              // [OUT]
+    NvU8  recordBuffer[NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE];
+} NV2080_CTRL_RC_GET_ERROR_V2_PARAMS;
+
+#define NV2080_CTRL_CMD_RC_GET_ERROR_V2            (0x20802213) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY
+ *
+ * This command cleans error history.
+ *
+ * This command has no input parameters.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+
+#define NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY (0x20802207) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x7" */
+
+/*
+ * NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO
+ *
+ * This command returns information about the RC watchdog.
+ *
+ *   watchdogStatusFlags
+ *     This output parameter is a combination of one or more of the following:
+ *
+ *       NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE
+ *         This is the value of watchdogStatusFlags if no flags are set.
+ *
+ *       NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED
+ *         This means that the watchdog is disabled.
+ *
+ *       NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING
+ *         This means that the watchdog is running.
+ *
+ *       NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED
+ *         This means that the watchdog has been initialized.
+ *
+ *     A typical result would be either "running and initialized", or
+ *     "disabled".  However, "initialized, but not running, and not disabled"
+ *     is also quite reasonable (if the computer is hibernating, for example).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS {
+    NvU32 watchdogStatusFlags;
+} NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO               (0x20802209) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */
+
+/* valid values for watchdogStatusFlags */
+#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE        (0x00000000)
+#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED    (0x00000001)
+#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING     (0x00000002)
+#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED (0x00000004)
+
+/*
+ * NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG
+ *
+ * This command disables the RC watchdog, if possible.
+ * If, however, another RM client has already explicitly (via NV2080 call) enabled
+ * the RC watchdog, then this method returns NV_ERR_STATE_IN_USE.
+ *
+ * This command, if successful, will prevent other clients from enabling the
+ * watchdog until the calling RM client releases its request with
+ * NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS or frees its NV20_SUBDEVICE.
+ *
+ * See NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG for disabling the watchdog
+ * without preventing other clients from enabling it.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG                (0x2080220a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xA" */
+
+/*
+ * NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG
+ *
+ * This command enables the RC watchdog, if possible.
+ * If, however, another RM client has already explicitly (via NV2080 call) disabled
+ * the RC watchdog, then this method returns NV_ERR_STATE_IN_USE.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG                 (0x2080220b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xB" */
+
+/*
+ * NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS
+ *
+ * This command releases all of the RM client's outstanding requests to enable
+ * or disable the watchdog.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS       (0x2080220c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xC" */
+
+/*
+ * NV2080_CTRL_CMD_SET_RC_RECOVERY/NV2080_CTRL_CMD_GET_RC_RECOVERY
+ *
+ * This command disables/enables RC recovery.
+ *
+ *   rcEnable
+ *       NV2080_CTRL_CMD_SET_RC_RECOVERY_DISABLED
+ *         Disable robust channel recovery.
+ *
+ *       NV2080_CTRL_CMD_SET_RC_RECOVERY_ENABLED
+ *         Enable robust channel recovery with default breakpoint handling.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+typedef struct NV2080_CTRL_CMD_RC_RECOVERY_PARAMS {
+    NvU32 rcEnable;
+} NV2080_CTRL_CMD_RC_RECOVERY_PARAMS;
+
+#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xDU)
+
+typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_SET_RC_RECOVERY_PARAMS;
+
+#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xEU)
+
+typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_GET_RC_RECOVERY_PARAMS;
+
+/* valid values for rcEnable */
+#define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED  (0x00000000)
+#define NV2080_CTRL_CMD_RC_RECOVERY_ENABLED   (0x00000001)
+
+/*
+ * NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE
+ *
+ * This command can be used to set TDR timeout state.
+ *
+ * It can be used to indicate that a timeout has occurred and that a GPU
+ * reset will start. It can also be used to indicate that the reset has
+ * completed along with the corresponding complition status.
+ *
+ *   cmd
+ *    This parameter is used to indicate the stage of the TDR recovery
+ *    process. Legal values for this parameter are:
+ *     NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN
+ *      This value indicates that TDR recovery is about to begin.
+ *     NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END
+ *      This value indicates that TDR recovery has completed.
+ *
+ *   status
+ *     This parameter is valid when the cmd parameter is set to
+ *     NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END. It is used
+ *     to specify the completion status of the TDR recovery. Legal
+ *     values for this parameter include:
+ *       NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL
+ *         This value indicates the recovery failed.
+ *       NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS
+ *         This value indicates the recovery succeeded.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_COMMAND
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE (0x2080220f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS {
+    NvU32 cmd;
+    NvS32 status;
+} NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS;
+
+/* valid cmd values */
+#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN (0x00000000)
+#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END   (0x00000001)
+
+/* valid status values */
+#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS      (0x00000000)
+#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL         (0x00000001)
+
+/*
+ * NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG
+ *
+ * This command disables the RC watchdog, similarly to how
+ * NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG does. However, unlike that command, this
+ * command will not prevent another RM client from explicitly enabling the RC
+ * watchdog with NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG              (0x20802210) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x10" */
+
+/*
+ * NV2080_CTRL_CMD_GET_RC_INFO/NV2080_CTRL_CMD_SET_RC_INFO
+ *
+ * This command can be used to set robust channel parameters.
+ *
+ *   rcMode
+ *       NV2080_CTRL_CMD_SET_RC_INFO_MODE_DISABLE
+ *         Disable robust channel operation.
+ *
+ *       NV2080_CTRL_CMD_SET_RC_INFO_MODE_ENABLE
+ *         Enable robust channel operation.
+ *
+ *   rcBreak
+ *       NV2080_CTRL_CMD_SET_RC_INFO_BREAK_DISABLE
+ *         Disable breakpoint handling during robust channel operation.
+ *
+ *       NV2080_CTRL_CMD_SET_RC_INFO_BREAK_ENABLE
+ *         Enable breakpoint handling during robust channel operation.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+typedef struct NV2080_CTRL_CMD_RC_INFO_PARAMS {
+    NvU32 rcMode;
+    NvU32 rcBreak;
+} NV2080_CTRL_CMD_RC_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID (0x11U)
+
+typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_SET_RC_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID (0x12U)
+
+typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_GET_RC_INFO_PARAMS;
+
+/* valid rcMode values */
+#define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE  (0x00000000)
+#define NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE   (0x00000001)
+
+/* valid rcBreak values */
+#define NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE (0x00000000)
+#define NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE  (0x00000001)
+
+/*
+ * NV2080_CTRL_CMD_GET_RC_WATCHDOG_INFO/NV2080_CTRL_CMD_SET_RC_WATCHDOG_INFO
+ *
+ * This command can be used to set RC watchdog parameters.
+ * This control is supported only on MODS.
+ *
+ * Possible status return values are:
+ *   NV_OK
+ */
+typedef struct NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS {
+    NvU32 channelTestInterval;
+    NvU32 thwapChannelMask;
+    NvU32 stompChannelMask;
+    NvU32 thwapRepeatMask;
+    NvU32 stompRepeatMask;
+    NvU32 allocFailMask;
+} NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_SET_RC_WATCHDOG_INFO (0x20802214) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_SET_RC_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x14U)
+
+typedef NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS NV2080_CTRL_SET_RC_WATCHDOG_INFO_PARAMS;
+
+#define NV2080_CTRL_CMD_GET_RC_WATCHDOG_INFO (0x20802215) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GET_RC_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x15U)
+
+typedef NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS NV2080_CTRL_GET_RC_WATCHDOG_INFO_PARAMS;
+
+/* _ctrl2080rc_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spdm.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spdm.h
new file mode 100644
index 0000000..4c25165
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spdm.h
@@ -0,0 +1,248 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080spdm.finn
+//
+
+
+
+/*************************** SPDM COMMANDS ************************************/
+
+#include "cc_drv.h"
+
+/*!
+ * @brief SPDM Command Types
+ *
+ */
+#define RM_GSP_SPDM_CMD_ID_CC_INIT                        (0x1)
+#define RM_GSP_SPDM_CMD_ID_CC_DEINIT                      (0x2)
+#define RM_GSP_SPDM_CMD_ID_CC_CTRL                        (0x3)
+#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA                (0x4)
+#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL              (0x5)
+#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST                  (0x6)
+
+
+#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND                (0xFF)
+
+#define SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE 0x2400
+
+
+
+#define RSVD7_SIZE                                        16
+
+#define RSVD8_SIZE                                        2
+
+/*!
+ * Guest RM provides INIT context
+ */
+typedef struct RM_GSP_SPDM_CMD_CC_INIT {
+    // Command must be first as this struct is the part of union
+    NvU8 cmdType;
+} RM_GSP_SPDM_CMD_CC_INIT;
+typedef struct RM_GSP_SPDM_CMD_CC_INIT *PRM_GSP_SPDM_CMD_CC_INIT;
+
+/*!
+ * Guest RM provides INIT context
+ */
+typedef struct RM_GSP_SPDM_CMD_CC_DEINIT {
+    // Command must be first as this struct is the part of union
+    NvU8 cmdType;
+} RM_GSP_SPDM_CMD_CC_DEINIT;
+typedef struct RM_GSP_SPDM_CMD_CC_DEINIT *PRM_GSP_SPDM_CMD_CC_DEINIT;
+
+/*!
+ * RM provides the SPDM request info to GSP
+ */
+typedef struct RM_GSP_SPDM_CMD_CC_CTRL {
+    // Command must be first as this struct is the part of union
+    NvU8 cmdType;
+} RM_GSP_SPDM_CMD_CC_CTRL;
+typedef struct RM_GSP_SPDM_CMD_CC_CTRL *PRM_GSP_SPDM_CMD_CC_CTRL;
+
+typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA {
+    // Command must be first as this struct is the part of union
+    NvU8  cmdType;
+
+    NvU32 rsvd0[2];
+
+    NvU32 rsvd1;
+
+    char  rsvd2[9];
+
+    char  rsvd3[5];
+
+    char  rsvd4[5];
+
+    char  rsvd5[5];
+
+    char  rsvd6[2];
+
+    char  rsvd7[RSVD7_SIZE];
+
+    NvU32 rsvd8[RSVD8_SIZE];
+} RM_GSP_SPDM_CMD_CC_INIT_RM_DATA;
+typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA;
+
+typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL {
+    // Command must be first as this struct is the part of union
+    NvU8   cmdType;
+
+    // Whether to enable or disable heartbeats
+    NvBool bEnable;
+} RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
+typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL *PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
+
+
+
+/*! 
+ * HCC FIPS Self-test.
+ */
+#define CE_FIPS_SELF_TEST_DATA_SIZE     16
+#define CE_FIPS_SELF_TEST_AUTH_TAG_SIZE 16
+#define CE_FIPS_SELF_TEST_IV_SIZE       12
+
+typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST {
+    NvU8   cmdType;
+    NvU8   isEnc;
+    CC_KMB kmb;
+    NvU8   text[CE_FIPS_SELF_TEST_DATA_SIZE];
+    NvU8   authTag[CE_FIPS_SELF_TEST_AUTH_TAG_SIZE];
+} RM_GSP_SPDM_CMD_FIPS_SELFTEST;
+typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST *PRM_GSP_SPDM_CMD_FIPS_SELFTEST;
+
+
+
+/*!
+ * NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives 
+ * getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in 
+ * other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior 
+ * when paired with alignment directives on Linux and Windows. 
+ */
+
+/*!
+ * A union of all SPDM Commands.
+ */
+typedef union RM_GSP_SPDM_CMD {
+    NvU8                              cmdType;
+    RM_GSP_SPDM_CMD_CC_INIT           ccInit;
+    RM_GSP_SPDM_CMD_CC_DEINIT         ccDeinit;
+    RM_GSP_SPDM_CMD_CC_CTRL           ccCtrl;
+    RM_GSP_SPDM_CMD_CC_INIT_RM_DATA   rmDataInitCmd;
+    RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL ccHeartbeatCtrl;
+
+
+    RM_GSP_SPDM_CMD_FIPS_SELFTEST     ccFipsTest;
+
+} RM_GSP_SPDM_CMD;
+typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
+
+/***************************** SPDM MESSAGES  *********************************/
+
+/*!
+ * SPDM Message Status
+ */
+
+/*!
+ * Returns the status for program CE keys to RM
+ */
+#define RM_GSP_SPDM_MSG_ID_CC_INIT           (0x1)
+#define RM_GSP_SPDM_MSG_ID_CC_DEINIT         (0x2)
+#define RM_GSP_SPDM_MSG_ID_CC_CTRL           (0x3)
+#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA   (0x4)
+#define RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL (0x5)
+#define RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST     (0x6)
+
+
+
+/*!
+ * Returns the Error Status for Invalid Command
+ */
+#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND   (0xFF)
+
+/*!
+ * NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives 
+ * getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in 
+ * other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior 
+ * when paired with alignment directives on Linux and Windows. 
+ */
+
+/*!
+ * SPDM message structure.
+ */
+typedef struct RM_GSP_SPDM_MSG {
+    NvU8  msgType;
+
+    // status returned from GSP message infrastructure.
+    NvU32 status;
+
+    NvU32 rsvd1;
+
+    NvU32 rsvd2;
+
+    NvU32 rsvd3;
+
+    NvU32 rsvd4;
+
+    NvU32 rsvd5;
+} RM_GSP_SPDM_MSG;
+typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG;
+
+/*
+ * NV2080_CTRL_CMD_INTERNAL_SPDM_PARTITION
+ *
+ * This command does a partition switch to SPDM partition
+ *
+ */
+#define NV2080_CTRL_INTERNAL_SPDM_PARTITION (0x20800ad9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID (0xD9U)
+
+typedef struct NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS {
+    NvU8            index;
+    RM_GSP_SPDM_CMD cmd;
+    RM_GSP_SPDM_MSG msg;
+} NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS;
+
+/*
+ * NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT
+ *
+ * This command retrieves the transcript of SPDM session establishment messages.
+ *
+ */
+#define NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID (0xDAU)
+
+typedef struct NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS {
+    NvU8  transcript[SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE];
+    NvU32 transcriptSize;
+} NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS;
+
+
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spi.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spi.h
new file mode 100644
index 0000000..0b378d2
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spi.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080spi.finn
+//
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080thermal.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080thermal.h
new file mode 100644
index 0000000..25d6c42
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080thermal.h
@@ -0,0 +1,417 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080thermal.finn
+//
+
+
+
+/*
+ * Thermal System rmcontrol api versioning
+ */
+#define THERMAL_SYSTEM_API_VER                                       1U
+#define THERMAL_SYSTEM_API_REV                                       0U
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM constants
+ *
+ */
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_TARGET
+ *
+ *  Targets (ie the things the thermal system can observe). Target mask
+ *  have to be in sync with corresponding element of NVAPI_THERMAL_TARGET
+ *  enum, until there is a translation layer between these two.
+ *
+ *   NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE
+ *       There is no target.
+ *
+ *   NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU
+ *       The GPU is the target.
+ *
+ *   NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY
+ *       The memory is the target.
+ *
+ *   NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY
+ *       The power supply is the target.
+ *
+ *   NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD
+ *       The board (PCB) is the target.
+ */
+
+
+ /*   NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN
+ *       The target is unknown.
+ */
+#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE                       (0x00000000U)
+#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU                        (0x00000001U)
+#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY                     (0x00000002U)
+#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY               (0x00000004U)
+#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD                      (0x00000008U)
+
+
+#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN                    (0xFFFFFFFFU)
+
+/*
+ * executeFlags values
+ */
+#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT             (0x00000000U)
+#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL         (0x00000001U)
+
+
+/*
+ * NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2
+ *
+ * This command will execute a list of thermal system instructions:
+ *
+ *   clientAPIVersion
+ *       This field must be set by the client to THERMAL_SYSTEM_API_VER,
+ *       which allows the driver to determine api compatibility.
+ *
+ *   clientAPIRevision
+ *       This field must be set by the client to THERMAL_SYSTEM_API_REV,
+ *       which allows the driver to determine api compatibility.
+ *
+ *   clientInstructionSizeOf
+ *       This field must be set by the client to
+ *       sizeof(NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION), which allows the
+ *       driver to determine api compatibility.
+ *
+ *   executeFlags
+ *       This field is set by the client to control instruction execution.
+ *        NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT
+ *         Execute instructions normally. The first instruction
+ *         failure will cause execution to stop.
+ *        NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL
+ *         Execute all instructions, ignoring individual instruction failures.
+ *
+ *   successfulInstructions
+ *       This field is set by the driver and is the number of instructions
+ *       that returned NV_OK on execution.  If this field
+ *       matches instructionListSize, all instructions executed successfully.
+ *
+ *   instructionListSize
+ *       This field is set by the client to the number of instructions in
+ *       instruction list.
+ *
+ *   instructionList
+ *       This field is set an array of thermal system instructions
+ *       (NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION) to execute, filled in by the
+ *       client.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ */
+
+#define NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2                    (0x20800513U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_THERMAL_INTERFACE_ID << 8) | NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2_PHYSICAL           (0x20808513U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_THERMAL_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID" */
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO instructions...
+ *
+ */
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE instruction
+ *
+ * Get the number of available targets.
+ *
+ *   availableTargets
+ *       Returns the number of available targets.  Targets are
+ *       identified by an index, starting with 0.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPCODE (0x00000100U)
+typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS {
+    NvU32 availableTargets;
+} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS;
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE instruction
+ *
+ * Get a target's type.
+ *
+ *   targetIndex
+ *       Set by the client to the desired target index.
+ *
+ *   type
+ *       Returns a target's type.
+ *       Possible values returned are:
+ *          NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE
+ *          NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU
+ *          NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY
+ *          NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY
+ *          NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD
+ *          NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE (0x00000101U)
+typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS {
+    NvU32 targetIndex;
+    NvU32 type;
+} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS;
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE instruction
+ *
+ * Get a providers's type.
+ *
+ *   providerIndex
+ *       Set by the client to the desired provider index.
+ *
+ *   type
+ *       Returns a provider's type.
+ */
+
+
+ /*
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE (0x00000301U)
+typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS {
+    NvU32 providerIndex;
+    NvU32 type;
+} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS;
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE instruction
+ *
+ * Get the number of available sensors.
+ *
+ *   availableSensors
+ *       Returns the number of available sensors.  Sensors are
+ *       identified by an index, starting with 0.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE (0x00000500U)
+typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS {
+    NvU32 availableSensors;
+} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS;
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER instruction
+ *
+ * Get a sensor's provider index.
+ *
+ *   sensorIndex
+ *       Set by the client to the desired sensor index.
+ *
+ *   providerIndex
+ *       Returns a sensor's provider index.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE (0x00000510U)
+typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS {
+    NvU32 sensorIndex;
+    NvU32 providerIndex;
+} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS;
+
+/*!
+ * Union of mode-specific arguments.
+ */
+
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING instruction
+ *
+ * Get a sensor's current reading.
+ *
+ *   sensorIndex
+ *       Set by the client to the desired sensor index.
+ *
+ *   value
+ *       Returns a sensor's current reading.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE (0x00001500U)
+typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS {
+    NvU32 sensorIndex;
+    NvS32 value;
+} NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS;
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET instruction
+ *
+ * Get a sensor's target index.
+ *
+ *   sensorIndex
+ *       Set by the client to the desired sensor index.
+ *
+ *   targetIndex
+ *       Returns a sensor's target index.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE (0x00000520U)
+typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS {
+    NvU32 sensorIndex;
+    NvU32 targetIndex;
+} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS;
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE instruction
+ *
+ * Get a sensor's readings range (ie min, max).
+ *
+ *   sensorIndex
+ *       Set by the client to the desired sensor index.
+ *
+ *   minimum
+ *       Returns a sensor's range minimum.
+ *
+ *   maximum
+ *       Returns a sensor's range maximum.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE (0x00000540U)
+typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS {
+    NvU32 sensorIndex;
+    NvS32 minimum;
+    NvS32 maximum;
+} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS;
+
+/*
+ * Thermal System instruction operand
+ */
+typedef union NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS {
+
+    NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS          getInfoTargetsAvailable;
+
+    NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS                getInfoTargetType;
+
+    NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS              getInfoProviderType;
+
+    NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS          getInfoSensorsAvailable;
+
+    NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS            getInfoSensorProvider;
+
+    NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS              getInfoSensorTarget;
+
+    NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS       getInfoSensorReadingRange;
+
+    NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS           getStatusSensorReading;
+
+
+    NvU32                                                                   space[8];
+} NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS;
+
+/*
+ * NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION
+ *
+ * All thermal system instructions have the following layout:
+ *
+ *   result
+ *       This field is set by the driver, and is the result of the
+ *       instruction's execution. This value is only valid if the
+ *       executed field is not 0 upon return.
+ *       Possible status values returned are:
+ *        NV_OK
+ *        NV_ERR_INVALID_ARGUMENT
+ *        NV_ERR_INVALID_PARAM_STRUCT
+ *
+ *   executed
+ *       This field is set by the driver, and
+ *       indicates if the instruction was executed.
+ *       Possible status values returned are:
+ *        0: Not executed
+ *        1: Executed
+ *
+ *   opcode
+ *       This field is set by the client to the desired instruction opcode.
+ *       Possible values are:
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE
+ */
+
+
+ /*
+ *   operands
+ *       This field is actually a union of all of the available operands.
+ *       The interpretation of this field is opcode context dependent.
+ *       Possible values are:
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS
+ *        NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS
+ */
+
+
+typedef struct NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION {
+    NvU32                                           result;
+    NvU32                                           executed;
+    NvU32                                           opcode;
+    NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS operands;
+} NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION;
+
+#define NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT 0x20U
+#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID (0x13U)
+
+typedef struct NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS {
+    NvU32                                  clientAPIVersion;
+    NvU32                                  clientAPIRevision;
+    NvU32                                  clientInstructionSizeOf;
+    NvU32                                  executeFlags;
+    NvU32                                  successfulInstructions;
+    NvU32                                  instructionListSize;
+    NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION instructionList[NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT];
+} NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS;
+
+/* _ctrl2080thermal_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080tmr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080tmr.h
new file mode 100644
index 0000000..4d51f63
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080tmr.h
@@ -0,0 +1,260 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2008-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080tmr.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_TIMER related control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_TIMER_SCHEDULE
+ *
+ * This command schedules a GPU timer event to fire at the specified time interval.
+ * Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and
+ * NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags
+ *
+ *   time_nsec
+ *     This parameter specifies the time in nanoseconds at which the GPU timer
+ *     event is to fire.
+ *   flags
+ *     This parameter determines the interpretation of the value specified by
+ *     the time_nsec parameter:
+ *       NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS
+ *         This flag indicates that time_nsec is in absolute time.
+ *       NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL
+ *         This flag indicates that time_nsec is in relative time.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_PARAM_STRUCT
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_TIMER_SCHEDULE (0x20800401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 time_nsec, 8);
+    NvU32 flags;
+} NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS;
+
+/* valid flag values */
+#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME               0:0
+#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS (0x00000000)
+#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL (0x00000001)
+
+/*
+ * NV2080_CTRL_CMD_TIMER_CANCEL
+ *
+ * This command cancels any pending timer events initiated with the
+ * NV2080_CTRL_CMD_TIMER_SCHEDULE command.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_TIMER_CANCEL              (0x20800402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | 0x2" */
+
+/* 
+ * NV2080_CTRL_CMD_TIMER_GET_TIME 
+ * 
+ * This command returns the current GPU timer value.  The current time is 
+ * expressed in elapsed nanoseconds since 00:00 GMT, January 1, 1970 
+ * (zero hour) with a resolution of 32 nanoseconds. 
+ *
+ * Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and
+ * NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags
+ * 
+ * Possible status values returned are: 
+ *   NV_OK 
+ *   NV_ERR_INVALID_ARGUMENT 
+ */
+#define NV2080_CTRL_CMD_TIMER_GET_TIME            (0x20800403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_TIMER_GET_TIME_PARAMS {
+    NV_DECLARE_ALIGNED(NvU64 time_nsec, 8);
+} NV2080_CTRL_TIMER_GET_TIME_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET
+ *
+ * The command returns the offset of the timer registers, so that clients may
+ * map them directly. 
+ *
+ * Possible status values returned are: 
+ *   NV_OK 
+ */
+
+#define NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET (0x20800404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS {
+    NvU32 tmr_offset;
+} NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS;
+
+/*
+ * NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE
+ *
+ * This structure describes the information obtained with
+ * NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO command.
+ *
+ *   gpuTime
+ *     GPU time is the value of GPU global timer (PTIMER) with a resolution
+ *     of 32 nano seconds.
+ *   cpuTime
+ *     CPU time. Resolution of the cpu time depends on its source. Refer to
+ *     NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_*  for more information.
+
+ */
+typedef struct NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE {
+    NV_DECLARE_ALIGNED(NvU64 cpuTime, 8);
+    NV_DECLARE_ALIGNED(NvU64 gpuTime, 8);
+} NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE;
+
+
+/*
+ * NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO
+ *
+ * This command returns correlation information between GPU time and CPU time
+ * for a given CPU clock type.
+ *
+ *   cpuClkId
+ *     This parameter specifies the source of the CPU clock. This parameter is
+ *     composed of two fields:
+ *     NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE
+ *       This field specifies source ID of the CPU clock in question. Legal
+ *       values for this parameter include:
+ *         NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME
+ *           This clock id will provide real time in microseconds since
+ *           00:00:00 UTC on January 1, 1970, as reported by the host OS.
+ *         NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API
+ *           This clock id will provide time stamp that is constant-rate, high
+ *           precision using platform API that is also available in the user
+ *           mode.
+ *         NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC
+ *           This clock id will provide time stamp using CPU's time stamp
+ *           counter.
+ *     NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR
+ *       This field specifies the processor whose clock should be used for the
+ *       source. The control call and cpuClkId parameter remain named for the
+ *       CPU specifically for legacy reasons. Not all processors will support
+ *       all clock sources. Legal values for this parameter include:
+ *         NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU
+ *           The clock information will be fulfilled by the CPU. This value
+ *           is defined to be 0 so that it is the default for backwards
+ *           compatibility.
+ *         NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP
+ *           The clock information will be fulfilled by the GSP.
+ *
+ *   sampleCount
+ *     This field specifies the number of clock samples to be taken.
+ *     This value cannot exceed NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES.
+ *
+ *   samples
+ *     This field returns an array of requested samples. Refer to
+ *     NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE to get details about each entry
+ *     in the array.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO (0x20800406) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES              16
+
+#define NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS {
+    NvU8 cpuClkId;
+    NvU8 sampleCount;
+    NV_DECLARE_ALIGNED(NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE samples[NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES], 8);
+} NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS;
+
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE    3:0
+
+/* Legal NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE values */
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME        (0x00000001)
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC           (0x00000002)
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API  (0x00000003)
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS        (0x00000004)
+
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR 7:4
+
+/* Legal NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR values */
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU (0x00000000)
+#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP (0x00000001)
+
+
+/*!
+ * NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ
+ *
+ * This command changes the frequency at which Graphics Engine time stamp is
+ * updated. Frequency can either be set to max or restored to default.
+ * Clients can independently use this call to increase the timer frequency 
+ * as a global reference count is maintained for requests to Max frequency.
+ * Client is assured that the system stays in this state till the requested
+ * client releases the state or is killed. Timer frequency will automatically
+ * be restored to default when there is no pending request to increase.
+ *
+ * Note that recursive requests for the same state from the same client
+ * are considered invalid.
+ *
+ * bSetMaxFreq
+ *      Set to NV_TRUE if GR tick frequency needs to be set to Max.
+ *
+ * See @ref NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS for
+ * documentation of parameters.
+ *
+ * Possible status values returned are
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ *   NV_ERR_STATE_IN_USE
+ *   NV_ERR_INVALID_OPERATION
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ             (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */
+
+/*!
+ * This struct contains bSetMaxFreq flag.
+ */
+#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS {
+    NvBool bSetMaxFreq;
+} NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS;
+
+/* _ctrl2080tmr_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h
new file mode 100644
index 0000000..56463fb
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080ucodefuzzer.finn
+//
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080unix.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080unix.h
new file mode 100644
index 0000000..b058211
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080unix.h
@@ -0,0 +1,190 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080unix.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+
+/* NV20_SUBDEVICE_XX OS control commands and parameters */
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT
+ *
+ * This command increases or decreases the value of the per-GPU GC6 blocker
+ * refCount used by Linux kernel clients to prevent the GPU from entering GC6.
+ *
+ * When the refCount is non-zero, the GPU cannot enter GC6. When the refCount
+ * transitions from zero to non-zero as a result of this command, the GPU will
+ * automatically come out of GC6.
+ *
+ * action   Whether to increment or decrement the value of the refCount.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT (0x20803d01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS {
+    NvU32 action;
+} NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS;
+
+// Possible values for action
+#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC   (0x00000001)
+#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC   (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF
+ *
+ * RM by default allows GCOFF but when the X driver disallows to enter in GCOFF
+ * then this rmcontrol sets flag as NV_FALSE and if it allows to enter in GCOFF
+ * then the flag is set as NV_TRUE.
+ *
+ * action   Whether to allow or disallow the user mode clients to enter in GCOFF.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ *   NV_ERR_INVALID_OBJECT_HANDLE
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_NOT_SUPPORTED
+ */
+
+#define NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF (0x20803d02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS {
+    NvU32 action;
+} NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS;
+
+// Possible values for action
+#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW    (0x00000001)
+#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW (0x00000002)
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER
+ *
+ * GPU can have integrated HDA (High Definition Audio) controller which
+ * can be in active or suspended state during dynamic power management.
+ * This command will perform HDA controller wakeup (if bEnter is false) or
+ * suspend (if bEnter is true).
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER       (0x20803d03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS {
+    NvBool bEnter;
+} NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS
+ *
+ * Initialize cyclestats HWPM support in the kernel. This will set up a callback
+ * event for the channel indicated by hNotifierResource. This callback will execute
+ * perf register read / write commands enqueued in the shared buffer indicated by
+ * hNotifyDataMemory. Only one client may use HWPM functionality at a time.
+ *
+ * Additionally, if perfmonIdCount is greater than zero, mode-e HWPM streaming into
+ * the buffer indicated by hSnapshotMemory will be initialized (but not turned on).
+ * Data will be copied into the provided buffer every 10ms, or whenever a
+ * NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER command is issued.
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS (0x20803d04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS {
+    NvHandle hNotifierResource;
+    NvU32    notifyDataSize;
+    NvHandle hNotifyDataMemory;
+    NvU32    perfmonIdCount;
+    NvU32    snapshotBufferSize;
+    NvHandle hSnapshotMemory;
+} NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER
+ *
+ * Immediately copies any pending mode-e HWPM data into the previously
+ * installed snapshot buffer instead of waiting for the timer.
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER     (0x20803d05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x5" */
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER
+ *
+ * Stop the timer responsible for copying mode-e HWPM data to the snapshot buffer.
+ * The snapshot buffer must not be freed by the client before this command is issued.
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER             (0x20803d06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x6" */
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS
+ *
+ * This command will be used by clients to check if the GPU video memory will
+ * be persistent during system suspend/resume cycle.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS (0x20803d07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS {
+    NvBool bVidmemPersistent;
+} NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS
+ *
+ * This command will be used by clients to set restore TGP flag which will
+ * help to restore TGP limits when clients are destroyed.
+ *
+ * Possible status values returned are:
+ * NV_OK
+ */
+#define NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS (0x20803d08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS {
+    NvBool bUpdateTGP;
+} NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS;
+/* _ctrl2080unix_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vfe.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vfe.h
new file mode 100644
index 0000000..5742c5e
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vfe.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080vfe.finn
+//
+
+
+
+/* _ctrl2080vfe_h_ */
+#include "nvfixedtypes.h"
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080boardobj.h"
+#include "ctrl/ctrl2080/ctrl2080bios.h"
+
+/* --------------------------- Forward Defines ----------------------------- */
+/* --------------------------- VFE Variable -------------------------------- */
+/* --------------------------- VFE Equation -------------------------------- */
+
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
new file mode 100644
index 0000000..4b63733
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
@@ -0,0 +1,522 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <nvtypes.h>
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn
+//
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrla081.h"
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK
+ *
+ * This command is used to bootload GSP VGPU plugin task.
+ * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature.
+ *
+ * dbdf                        - domain (31:16), bus (15:8), device (7:3), function (2:0)
+ * gfid                        - Gfid
+ * vgpuType                    - The Type ID for VGPU profile
+ * vmPid                       - Plugin process ID of vGPU guest instance
+ * swizzId                     - SwizzId
+ * numChannels                 - Number of channels
+ * numPluginChannels           - Number of plugin channels
+ * bDisableSmcPartitionRestore - If set to true, SMC default execution partition
+ *                               save/restore will not be done in host-RM
+ * guestFbPhysAddrList         - list of VMMU segment aligned physical address of guest FB memory
+ * guestFbLengthList           - list of guest FB memory length in bytes
+ * pluginHeapMemoryPhysAddr    - plugin heap memory offset
+ * pluginHeapMemoryLength      - plugin heap memory length in bytes
+ * migRmHeapMemoryPhysAddr     - Mig rm heap memory region's physical offset.
+ * migRmHeapMemoryLength       - Mig rm heap memory length in bytes
+ * bDeviceProfilingEnabled     - If set to true, profiling is allowed
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK (0x20804001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_MAX_VMMU_SEGMENTS                                   384
+
+/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
+#define NV2080_GPU_MAX_ENGINES                                          0x54
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS {
+    NvU32  dbdf;
+    NvU32  gfid;
+    NvU32  vgpuType;
+    NvU32  vmPid;
+    NvU32  swizzId;
+    NvU32  numChannels;
+    NvU32  numPluginChannels;
+    NvU32  chidOffset[NV2080_GPU_MAX_ENGINES];
+    NvBool bDisableDefaultSmcExecPartRestore;
+    NvU32  numGuestFbSegments;
+    NV_DECLARE_ALIGNED(NvU64 guestFbPhysAddrList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8);
+    NV_DECLARE_ALIGNED(NvU64 guestFbLengthList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8);
+    NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryPhysAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryLength, 8);
+    NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 kernelLogBuffOffset, 8);
+    NV_DECLARE_ALIGNED(NvU64 kernelLogBuffSize, 8);
+    NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryPhysAddr, 8);
+    NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryLength, 8);
+    NvBool bDeviceProfilingEnabled;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK
+ *
+ * This command is used to shutdown GSP VGPU plugin task.
+ * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature.
+ *
+ * gfid                        - Gfid
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK (0x20804002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x2U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS {
+    NvU32 gfid;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE
+ *
+ * This command is used to add a new vGPU config to the pGPU in physical RM.
+ * Unlike NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO, it does no validation
+ * and is only to be used internally.
+ *
+ * discardVgpuTypes [IN]
+ *  This parameter specifies if existing vGPU configuration should be
+ *  discarded for given pGPU
+ *
+ * vgpuInfoCount [IN]
+ *   This parameter specifies the number of entries of virtual GPU type
+*    information
+ *
+ * vgpuInfo [IN]
+ *   This parameter specifies virtual GPU type information
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE (0x20804003) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID (0x3U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS {
+    NvBool discardVgpuTypes;
+    NvU32  vgpuInfoCount;
+    NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo[NVA081_MAX_VGPU_TYPES_PER_PGPU], 8);
+} NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS;
+
+/*
+ * NV2080_GUEST_VM_INFO
+ *
+ * This structure represents vGPU guest's (VM's) information
+ *
+ * vmPid [OUT]
+ *  This param specifies the vGPU plugin process ID
+ * guestOs [OUT]
+ *  This param specifies the vGPU guest OS type
+ * migrationProhibited [OUT]
+ *  This flag indicates whether migration is prohibited for VM or not
+ * guestNegotiatedVgpuVersion [OUT]
+ *  This param specifies the vGPU version of guest driver after negotiation
+ * frameRateLimit [OUT]
+ *  This param specifies the current value of FRL set for guest
+ * licensed [OUT]
+ *  This param specifies whether the VM is Unlicensed/Licensed
+ * licenseState [OUT]
+ *  This param specifies the current state of the GRID license state machine
+ * licenseExpiryTimestamp [OUT]
+ *  License expiry time in seconds since UNIX epoch
+ * licenseExpiryStatus [OUT]
+ *  License expiry status
+ * guestDriverVersion [OUT]
+ *  This param specifies the driver version of the driver installed on the VM
+ * guestDriverBranch [OUT]
+ *  This param specifies the driver branch of the driver installed on the VM
+ * guestVmInfoState [OUT]
+ *  This param stores the current state of guest dependent fields
+ *
+ */
+typedef struct NV2080_GUEST_VM_INFO {
+    NvU32               vmPid;
+    NvU32               guestOs;
+    NvU32               migrationProhibited;
+    NvU32               guestNegotiatedVgpuVersion;
+    NvU32               frameRateLimit;
+    NvBool              licensed;
+    NvU32               licenseState;
+    NvU32               licenseExpiryTimestamp;
+    NvU8                licenseExpiryStatus;
+    NvU8                guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE];
+    NvU8                guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE];
+    GUEST_VM_INFO_STATE guestVmInfoState;
+} NV2080_GUEST_VM_INFO;
+
+/*
+ * NV2080_GUEST_VGPU_DEVICE
+ *
+ * This structure represents host vgpu device's (assigned to VM) information
+ *
+ * gfid [OUT]
+ *  This parameter specifies the gfid of vGPU assigned to VM.
+ * vgpuPciId [OUT]
+ *  This parameter specifies vGPU PCI ID
+ * vgpuDeviceInstanceId [OUT]
+ *  This paramter specifies the vGPU device instance per VM to be used for supporting
+ *  multiple vGPUs per VM.
+ * fbUsed [OUT]
+ *  This parameter specifies FB usage in bytes
+ * eccState [OUT]
+ *  This parameter specifies the ECC state of the virtual GPU.
+ *  One of NVA081_CTRL_ECC_STATE_xxx values.
+ * bDriverLoaded [OUT]
+ *  This parameter specifies whether driver is loaded on this particular vGPU.
+ *
+ */
+typedef struct NV2080_HOST_VGPU_DEVICE {
+    NvU32  gfid;
+    NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8);
+    NvU32  vgpuDeviceInstanceId;
+    NvU32  accountingPid;
+    NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
+    NvU32  encoderCapacity;
+    NvU32  eccState;
+    NvBool bDriverLoaded;
+} NV2080_HOST_VGPU_DEVICE;
+
+/*
+ * NV2080_VGPU_GUEST
+ *
+ * This structure represents a vGPU guest
+ *
+ */
+typedef struct NV2080_VGPU_GUEST {
+    NV2080_GUEST_VM_INFO guestVmInfo;
+    NV_DECLARE_ALIGNED(NV2080_HOST_VGPU_DEVICE vgpuDevice, 8);
+} NV2080_VGPU_GUEST;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU
+ *
+ * This command enumerates list of vGPU guest instances per pGpu
+ *
+ * numVgpu [OUT]
+ *  This parameter specifies the number of virtual GPUs created on this physical GPU
+ *
+ * vgpuGuest [OUT]
+ *  This parameter specifies an array containing guest vgpu's information for
+ *  all vGPUs created on this physical GPU
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU (0x20804004) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x4U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS {
+    NvU32 numVgpu;
+    NV_DECLARE_ALIGNED(NV2080_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8);
+} NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO
+ *
+ * This command is used clear guest vm info. It should be used when
+ * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE
+ * is called with NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED state.
+ *
+ * gfid [IN]
+ *  This parameter specifies the gfid of vGPU assigned to VM.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO (0x20804005) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID (0x5U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS {
+    NvU32 gfid;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE
+ *
+ * This command is used to get the FB usage of all vGPU instances running on a GPU.
+ *
+ * vgpuCount [OUT]
+ *  This field specifies the number of vGPU devices for which FB usage is returned.
+ * vgpuFbUsage [OUT]
+ *  This is an array of type NV2080_VGPU_FB_USAGE, which contains a list of vGPU gfid
+ *  and their corresponding FB usage in bytes.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE (0x20804006) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */
+
+typedef struct NV2080_VGPU_FB_USAGE {
+    NvU32 gfid;
+    NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
+} NV2080_VGPU_FB_USAGE;
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS {
+    NvU32 vgpuCount;
+    NV_DECLARE_ALIGNED(NV2080_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8);
+} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY
+ *
+ * This command is used to set vGPU instance's (represented by gfid) encoder Capacity.
+ *
+ * gfid [IN]
+ *  This parameter specifies the gfid of vGPU assigned to VM.
+ * encoderCapacity [IN]
+ *  Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance
+ *  may be minimal for this GPU and software should fall back to CPU-based encode.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY (0x20804007) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x7U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS {
+    NvU32 gfid;
+    NvU32 encoderCapacity;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP
+ *
+ * This command is used to cleanup all the GSP VGPU plugin task allocated resources after its shutdown.
+ * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature.
+ *
+ * gfid [IN]
+ *  This parameter specifies the gfid of vGPU assigned to VM.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_NOT_SUPPORTED
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP (0x20804008) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID (0x8U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS {
+    NvU32 gfid;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS;
+
+#define NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN             8
+#define NV2080_CTRL_MAX_GPC_COUNT                              32
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING
+ *
+ * Reroutes kvgpumgrGetPgpuFSEncoding to vgpuMgrGetPgpuFSEncoding.
+ *
+ * pgpuString [OUT]
+ *  Resulting PGPU string
+ * pgpuStringSize
+ *  PGPU string size
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING (0x20804009) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID (0x9U)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS {
+    NvU8  pgpuString[NVA081_PGPU_METADATA_STRING_SIZE];
+    NvU32 pgpuStringSize;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT
+ *
+ * Reroutes kvgpumgrCheckPgpuMigrationSupport to vgpuMgrCheckPgpuMigrationSupport.
+ *
+ * bIsMigrationSupported [OUT]
+ *  Resulting status of the migration support
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT (0x2080400a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID (0xAU)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS {
+    NvBool bIsMigrationSupported;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG
+ *
+ * Sets vgpu manager parameters. This control is used after GSP initialization.
+ *
+ * bSupportHeterogeneousTimeSlicedVgpuTypes [IN]
+ *  Enable/disable heterogeneous time-sliced vgpu types
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG (0x2080400b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID (0xBU)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS {
+    NvBool bSupportHeterogeneousTimeSlicedVgpuTypes;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT
+ *
+ * Reroutes NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES to GSP RM to enable
+ * kernel clients to utilize NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES.
+ *
+ * gfid [IN]
+ *   This parameter specifies the gfid of vGPU assigned to VM.
+ * flags [IN]
+ *   Specifies what component of HostVgpuDevice to free.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES (0x2080400c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID (0xCU)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS {
+    NvU32 gfid;
+    NvU32 flags;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS
+ *
+ * Returns information whether frame rate limiter is disabled.
+ *
+ * bFlrDisabled [OUT]
+ *   True, if frame rate limiter is disabled.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ *   NV_ERR_INVALID_STATE
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS (0x2080400d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID (0xDU)
+
+typedef struct NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS {
+    NvBool bFlrDisabled;
+} NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE
+ *
+ *  This command will set heterogenous mode in GSP RM
+ *
+ *  bHeterogeneousMode
+ *      Mode of heterogeneous
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_OBJECT_NOT_FOUND
+ *    NV_ERR_INVALID_STATE
+ *    NV_ERR_INVALID_ARGUMENT
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE (0x2080400e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0xEU)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
+    NvBool bHeterogeneousMode;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS;
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE
+ *
+ *  This command will set MIG timeslice mode in GSP RM
+ *
+ *  bMigTimeslicingModeEnabled
+ *      Mode of MIG timeslice
+ *
+ * Possible status values returned are:
+ *    NV_OK
+ *    NV_ERR_OBJECT_NOT_FOUND
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE (0x2080400f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID (0xFU)
+
+typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS {
+    NvBool bMigTimeslicingModeEnabled;
+} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS;
+
+
+
+/*
+ * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE
+ *
+ * This command is used to share the Power State from KMD side to GSP-RM.
+ *
+ * state
+ *     This parameter contains Power State Information.
+ *
+ * Possible status values returned are:
+ *   NV_OK
+ */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE (0x20804010) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS_MESSAGE_ID (0x10U)
+
+typedef struct NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS {
+    NvU32 state;
+} NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS;
+
+/* _ctrl2080vgpumgrinternal_h_ */
diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080volt.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080volt.h
new file mode 100644
index 0000000..a136214
--- /dev/null
+++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080volt.h
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      ctrl/ctrl2080/ctrl2080volt.finn
+//
+
+
+
+/* _ctrl2080volt_h_ */
+
+#include "ctrl/ctrl2080/ctrl2080base.h"
+#include "ctrl/ctrl2080/ctrl2080boardobj.h"
+#include "ctrl/ctrl2080/ctrl2080pmumon.h"
+