kernel: serve CE caps + CE->PCE masks (unblocks UVM channel manager)archive/pre-squash

kceGetDeviceCaps (kernel_ce.c) copies the caps the client hands to UVM from
NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07), which reaches GSP-RM and
was answered with zeros. With capsTbl = {0,0} no CE had the SYSMEM bit, so
UVM's channel manager found no usable CE and UVM_REGISTER_GPU failed with
NV_ERR_NOT_SUPPORTED ("Failed to initialize the channel manager",
uvm_gpu.c:1574 - visible with uvm_debug_prints=1).

New handlers:
- CE_GET_PHYSICAL_CAPS (0x20802a07): {ceEngineType, capsTbl[2]} with
  SYSMEM_READ|SYSMEM_WRITE|SYSMEM|P2P|BL_GT_64K (0xEC) for COPY0..COPY4,
  NOT_SUPPORTED otherwise (matches subdeviceCtrlCmdCeGetCaps_IMPL).
- CE_GET_ALL_CAPS (0x20802a0a) / CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b):
  capsTbl[64][2] + present bitmap with the five CEs.
- CE_GET_CE_PCE_MASK (0x20802a02): pceMask = BIT(ceIdx) (one PCE per LCE).

Verified in-guest progress: UVM now gets past the channel manager and
creates channels; the register path's new blocker is the first channel
push (channel_init, uvm_channel.c:2535) whose semaphore release the
emulated GPU must complete ("Tracker entry ... stuck waiting for 90s",
sema VA 0x121000000 on channel 1:3 CE 0).

1 files changed, 33 insertions, 1 deletions

diff --git a/tools/guest-diag/guest_engines.c b/tools/guest-diag/guest_engines.c
index 066eec6..10209e2 100644
--- a/tools/guest-diag/guest_engines.c
+++ b/tools/guest-diag/guest_engines.c
@@ -11,6 +11,7 @@
 #include <sys/ioctl.h>
 #include <fcntl.h>
 #include <unistd.h>
+#include <stdlib.h>
 
 typedef uint32_t NvU32;
 typedef uint32_t NvHandle;
@@ -20,6 +21,7 @@ typedef uint64_t NvP64;
 #define NV_ESC_RM_ALLOC     0x2B
 #define NV_ESC_RM_CONTROL   0x2A
 #define NV01_ROOT           0x0
+#define NV01_ROOT_CLIENT    0x41
 #define NV01_DEVICE_0       0x80
 #define NV20_SUBDEVICE_0    0x2080
 
@@ -97,7 +99,7 @@ int main(void)
 	fd = open("/dev/nvidiactl", O_RDWR | O_CLOEXEC);
 	if (fd < 0) { perror("open nvidiactl"); return 1; }
 
-	st = rm_alloc(0, 0, NV01_ROOT, &hClient);
+	st = rm_alloc(0, 0, getenv("RC") ? NV01_ROOT_CLIENT : NV01_ROOT, &hClient);
 	printf("alloc client: st=0x%x hClient=0x%x\n", st, hClient);
 
 	st = rm_alloc64(hClient, hClient, NV01_DEVICE_0, &hDevice);
@@ -156,5 +158,35 @@ int main(void)
 			printf("  CE_GET_CAPS_V2(type=0x%x): st=0x%x caps=%02x %02x\n", t, st, cc.caps[0], cc.caps[1]);
 		}
 	}
+	if (hSubdevice) {
+		struct {
+			NvU32 engineData[16];
+			NvU32 pbdmaIds[2];
+			NvU32 pbdmaFaultIds[2];
+			NvU32 numPbdmas;
+			char  engineName[16];
+		} e[32];
+		struct {
+			NvU32 baseIndex, numEntries, bMore;
+			typeof(e) entries;
+		} t;
+		int i, j;
+		NvU32 base = 0;
+		memset(&t, 0, sizeof(t));
+		do {
+			t.baseIndex = base;
+			st = rm_control(hClient, hSubdevice, 0x20801112, &t, sizeof(t));
+			if (st) { printf("FIFO_GET_DEVICE_INFO_TABLE: st=0x%x\n", st); break; }
+			for (i = 0; i < (int)t.numEntries; i++) {
+				printf("  [%2u] %-8s numPbdmas=%u pbdmaIds=[%u,%u] engineData=[",
+				       base + i, t.entries[i].engineName, t.entries[i].numPbdmas,
+				       t.entries[i].pbdmaIds[0], t.entries[i].pbdmaIds[1]);
+				for (j = 0; j < 16; j++)
+					printf("%s%u", j ? "," : "", t.entries[i].engineData[j]);
+				printf("]\n");
+			}
+			base += t.numEntries;
+		} while (t.bMore);
+	}
 	return 0;
 }