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authorArthur Hanson Rasmusson <arthur@vgpu.io>2026-09-23 01:26:25 -0400
committerArthur Hanson Rasmusson <arthur@vgpu.io>2026-09-23 01:26:25 -0400
commit5367ffa2108fd9204d98f1cb23bb718a9143a25d (patch)
tree53ad60ad65302ea0f307da9c40a9bae12cf77f83 /tools/ghidra/gsp-fwimage-570.144/scripts/ExtractFunctions.java
parent841da7540f4397b0cac5f47537d2a39aca9ec3cf (diff)
downloadopen-iov-archive/pre-squash.tar.gz
open-iov-archive/pre-squash.zip
kernel: serve CE caps + CE->PCE masks (unblocks UVM channel manager)archive/pre-squash
kceGetDeviceCaps (kernel_ce.c) copies the caps the client hands to UVM from NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07), which reaches GSP-RM and was answered with zeros. With capsTbl = {0,0} no CE had the SYSMEM bit, so UVM's channel manager found no usable CE and UVM_REGISTER_GPU failed with NV_ERR_NOT_SUPPORTED ("Failed to initialize the channel manager", uvm_gpu.c:1574 - visible with uvm_debug_prints=1). New handlers: - CE_GET_PHYSICAL_CAPS (0x20802a07): {ceEngineType, capsTbl[2]} with SYSMEM_READ|SYSMEM_WRITE|SYSMEM|P2P|BL_GT_64K (0xEC) for COPY0..COPY4, NOT_SUPPORTED otherwise (matches subdeviceCtrlCmdCeGetCaps_IMPL). - CE_GET_ALL_CAPS (0x20802a0a) / CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b): capsTbl[64][2] + present bitmap with the five CEs. - CE_GET_CE_PCE_MASK (0x20802a02): pceMask = BIT(ceIdx) (one PCE per LCE). Verified in-guest progress: UVM now gets past the channel manager and creates channels; the register path's new blocker is the first channel push (channel_init, uvm_channel.c:2535) whose semaphore release the emulated GPU must complete ("Tracker entry ... stuck waiting for 90s", sema VA 0x121000000 on channel 1:3 CE 0).
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