kernel: Fix mdev PCI config space to match TU104 hardware layout

- Fix vendor/device/subsys ID byte order from vGPU type info
- BAR0: 16MB 32-bit non-prefetchable (matches physical TU104)
- BAR1: 256MB 64-bit prefetchable VRAM (consumes BAR2 upper half)
- BAR3: 32MB 64-bit prefetchable (consumes BAR4 upper half)
- Subsystem vendor/device IDs at correct offsets 0x2C/0x2E
- MSI-X: 32 vectors (table size 31), chain to PCIe cap at 0x80
- Capabilities pointer at 0x34 -> PM at 0x40
- Interrupt pin INTA at 0x3D

1 files changed, 39 insertions, 25 deletions

diff --git a/kernel/main.c b/kernel/main.c
index d35dad5..8ba7083 100644
--- a/kernel/main.c
+++ b/kernel/main.c
@@ -1369,10 +1369,10 @@ static int nv_vgpu_config_space_init(struct nv_vgpu_device *vgpu, struct pci_dev
 	if (vgpu->mdev && vgpu->mdev->type && vgpu->mdev->type->sysfs_name) {
 		for (i = 0; i < g_num_vgpu_types; i++) {
 			if (strcmp(vgpu->mdev->type->sysfs_name, g_vgpu_type_infos[i].name) == 0) {
-				vendor_id = (u16)(g_vgpu_type_infos[i].vdev_id & 0xFFFF);
-				device_id = (u16)((g_vgpu_type_infos[i].vdev_id >> 16) & 0xFFFF);
-				subsys_vendor = (u16)(g_vgpu_type_infos[i].pdev_id & 0xFFFF);
-				subsys_device = (u16)((g_vgpu_type_infos[i].pdev_id >> 16) & 0xFFFF);
+				vendor_id = (u16)((g_vgpu_type_infos[i].vdev_id >> 16) & 0xFFFF);
+				device_id = (u16)(g_vgpu_type_infos[i].vdev_id & 0xFFFF);
+				subsys_vendor = (u16)((g_vgpu_type_infos[i].pdev_id >> 16) & 0xFFFF);
+				subsys_device = (u16)(g_vgpu_type_infos[i].pdev_id & 0xFFFF);
 				nv_vgpu_info(vgpu, "Using vGPU type: name='%s', vendor=0x%04x, device=0x%04x, subsys_vendor=0x%04x, subsys_device=0x%04x",
 					g_vgpu_type_infos[i].name, vendor_id, device_id, subsys_vendor, subsys_device);
 				break;
@@ -1414,63 +1414,77 @@ static int nv_vgpu_config_space_init(struct nv_vgpu_device *vgpu, struct pci_dev
 	/* BIST (0x0F) */
 	cfg[0x0f] = bist;
 
-	/* BAR0 - 16MB Memory space (prefetchable) */
-	cfg[0x10] = 0x04;  /* 64-bit, prefetchable */
+	/* BAR0 - 16MB Memory space (32-bit, non-prefetchable) - matches TU104 */
+	cfg[0x10] = 0x00;  /* 32-bit, non-prefetchable */
 	cfg[0x11] = 0x00;
 	cfg[0x12] = 0x00;
 	cfg[0x13] = 0x00;
-	cfg[0x14] = 0x00;
+
+	/* BAR1 - 256MB Memory space (64-bit, prefetchable) - VRAM */
+	cfg[0x14] = 0x0c;  /* 64-bit, prefetchable */
 	cfg[0x15] = 0x00;
 	cfg[0x16] = 0x00;
 	cfg[0x17] = 0x00;
-
-	/* BAR1 - 256MB Memory space (prefetchable) */
-	cfg[0x18] = 0x04;
+	cfg[0x18] = 0x00;  /* Upper 32 bits */
 	cfg[0x19] = 0x00;
 	cfg[0x1a] = 0x00;
 	cfg[0x1b] = 0x00;
+
+	/* BAR2 - Not present (consumed by BAR1 upper half) */
 	cfg[0x1c] = 0x00;
 	cfg[0x1d] = 0x00;
 	cfg[0x1e] = 0x00;
 	cfg[0x1f] = 0x00;
 
-	/* BAR2 - 32MB Memory space */
-	cfg[0x20] = 0x04;
+	/* BAR3 - 32MB Memory space (64-bit, prefetchable) */
+	cfg[0x20] = 0x0c;  /* 64-bit, prefetchable */
 	cfg[0x21] = 0x00;
 	cfg[0x22] = 0x00;
 	cfg[0x23] = 0x00;
-	cfg[0x24] = 0x00;
+	cfg[0x24] = 0x00;  /* Upper 32 bits */
 	cfg[0x25] = 0x00;
 	cfg[0x26] = 0x00;
 	cfg[0x27] = 0x00;
 
-	/* BAR3 - 32MB Memory space */
-	cfg[0x28] = 0x04;
+	/* BAR4 - Not present (consumed by BAR3 upper half) */
+	cfg[0x28] = 0x00;
 	cfg[0x29] = 0x00;
 	cfg[0x2a] = 0x00;
 	cfg[0x2b] = 0x00;
+
+	/* CardBus CIS Pointer (0x2C) - Not used */
 	cfg[0x2c] = 0x00;
 	cfg[0x2d] = 0x00;
 	cfg[0x2e] = 0x00;
 	cfg[0x2f] = 0x00;
 
-	/* BAR4 - Not used */
+	/* Subsystem Vendor ID (0x2E) and Subsystem ID (0x2F) - wait, correct offsets: */
+	/* Subsystem Vendor ID at 0x2C, Subsystem ID at 0x2E */
+	cfg[0x2c] = subsys_vendor & 0xff;
+	cfg[0x2d] = (subsys_vendor >> 8) & 0xff;
+	cfg[0x2e] = subsys_device & 0xff;
+	cfg[0x2f] = (subsys_device >> 8) & 0xff;
+
+	/* Expansion ROM Base Address (0x30-0x33) - Not used */
 	cfg[0x30] = 0x00;
 	cfg[0x31] = 0x00;
 	cfg[0x32] = 0x00;
 	cfg[0x33] = 0x00;
 
-	/* BAR5 - Not used */
-	cfg[0x34] = 0x00;
+	/* Capabilities Pointer (0x34) - Point to Power Management at 0x40 */
+	cfg[0x34] = 0x40;
 	cfg[0x35] = 0x00;
 	cfg[0x36] = 0x00;
 	cfg[0x37] = 0x00;
 
-	/* CardBus CIS Pointer (0x38-0x3B) - Not used */
-	cfg[0x38] = 0x00;
-	cfg[0x39] = 0x00;
-	cfg[0x3a] = 0x00;
-	cfg[0x3b] = 0x00;
+	/* Interrupt Line (0x3C) - Will be set by guest */
+	cfg[0x3c] = 0x00;
+	/* Interrupt Pin (0x3D) - INTA */
+	cfg[0x3d] = 0x01;
+	/* Min_Gnt (0x3E) */
+	cfg[0x3e] = 0x00;
+	/* Max_Lat (0x3F) */
+	cfg[0x3f] = 0x00;
 
 	/* Subsystem Vendor ID (0x3C) */
 	cfg[0x3c] = subsys_vendor & 0xff;
@@ -1525,8 +1539,8 @@ static int nv_vgpu_config_space_init(struct nv_vgpu_device *vgpu, struct pci_dev
 
 	/* MSI-X Capability (0x70) */
 	cfg[0x70] = 0x11;  /* Capability ID: MSI-X */
-	cfg[0x71] = 0x00;  /* Next capability: None */
-	cfg[0x72] = 0x00;  /* Table size = 0 (1 vector), 64-bit */
+	cfg[0x71] = 0x80;  /* Next capability: PCI Express at 0x80 */
+	cfg[0x72] = 0x1f;  /* Table size = 31 (32 vectors), 64-bit */
 	cfg[0x73] = 0x00;
 	/* Table Offset/BIR (0x74) - Table at BAR0 offset 0x2000 */
 	cfg[0x74] = 0x00;