Open-IOV: initial public release

Open-IOV virtualizes NVIDIA GPUs so that unmodified guest drivers run with
real GPU functionality - CUDA first, 3D and video to follow - on unmodified
hosts, without a proprietary vGPU license and without patching any driver,
firmware or hypervisor.

Core principle: emulate the interface, pass through the work.

  kernel/     open-iov-vfio.ko - host VFIO mdev driver: virtual GPU device
              (PCI config space, BAR shadows, MSI-X), GSP boot emulation,
              GSP-RM message-queue/RPC emulation, memory model (GPU-VA to
              guest-PA discovery) and the semaphore-completion service that
              advances guest UVM progress.
  userspace/  libiov.so management API and examples.
  tools/      guest diagnostics, firmware analysis wrappers, RM probes.
  scripts/    stack manager, VM harness, build/load/test automation.
  config/     hardware/version profiles (the portability surface).
  docs/       documentation tree - start at docs/README.md.
  wiki/       long-form firmware and protocol deep dives.

Status: initialization works end to end for a stock 570.144 Linux guest on
Turing (TU104): driver probe, nvidia-smi, the full GSP-RM control battery,
object creation and the early CUDA/UVM start-up path. GPU work forwarding -
the step that makes CUDA kernels execute on real hardware - is the active
work item; see docs/04-implementation/01-known-knowns-and-unknowns.md.

License: BSD-3-Clause for the project; GPL-2.0 for kernel modules that link
GPL-only kernel interfaces. See LICENSE and docs/09-reference/legal-and-licensing.md.

1 files changed, 45 insertions, 0 deletions

diff --git a/kernel/include/irq.h b/kernel/include/irq.h
new file mode 100644
index 0000000..d06ac5b
--- /dev/null
+++ b/kernel/include/irq.h
@@ -0,0 +1,45 @@
+#ifndef _NV_VGPU_IRQ_H_
+#define _NV_VGPU_IRQ_H_
+
+#include "nvidia-vgpu-vfio.h"
+
+#define NV_VGPU_MAX_MSI_VECTORS 32
+
+struct nv_vgpu_msi_irq {
+	int virq;
+	u32 vector;
+	bool enabled;
+	struct eventfd_ctx *trigger;
+	struct irq_domain *domain;
+	struct msi_msg msg;
+};
+
+struct nv_vgpu_irq_ctx {
+	struct nv_vgpu_device *vgpu;
+	struct mutex lock;
+	struct nv_vgpu_msi_irq msis[NV_VGPU_MAX_MSI_VECTORS];
+	int msi_count;
+	bool msi_enabled;
+	bool msix_enabled;
+};
+
+int nv_vgpu_irq_init(struct nv_vgpu_device *vgpu);
+void nv_vgpu_irq_cleanup(struct nv_vgpu_device *vgpu);
+
+int nv_vgpu_irq_enable(struct nv_vgpu_device *vgpu, int irq_idx);
+int nv_vgpu_irq_disable(struct nv_vgpu_device *vgpu, int irq_idx);
+
+int nv_vgpu_irq_setup_msi(struct nv_vgpu_device *vgpu, int num_vectors);
+int nv_vgpu_irq_setup_msix(struct nv_vgpu_device *vgpu, int num_vectors);
+void nv_vgpu_irq_teardown_msi(struct nv_vgpu_device *vgpu);
+void nv_vgpu_irq_teardown_msix(struct nv_vgpu_device *vgpu);
+
+int nv_vgpu_irq_set_trigger(struct nv_vgpu_device *vgpu, int irq_idx, int fd);
+int nv_vgpu_irq_get_virq(struct nv_vgpu_device *vgpu, int irq_idx);
+
+static inline struct nv_vgpu_irq_ctx *vgpu_to_irq_ctx(struct nv_vgpu_device *vgpu)
+{
+	return (struct nv_vgpu_irq_ctx *)vgpu->irq_ctx;
+}
+
+#endif
\ No newline at end of file