Phase 2: PCI Config Space & BAR Enhancements

- Enhanced PCI config space write handlers in main.c:
  - Added MSI-X Message Control (0x72-0x73) write support
  - Added MSI-X Table Offset/BIR (0x74-0x77) write support
  - Added MSI-X PBA Offset/BIR (0x78-0x7B) write support

- Enhanced BAR emulation in bar_emulation.c:
  - Added MSI-X Table emulation (32 entries at BAR0+0x2000)
  - Added MSI-X PBA emulation (64-bit at BAR0+0x3000)
  - Added nv_vgpu_msix_set_pending/clear_pending for interrupt injection
  - Integrated with GSP emulation constants from gsp_emulation.h

- Updated bar_emulation.h with MSI-X struct definitions and function declarations
- Added GSP emulation constants to gsp_emulation.h (MSIX offsets, polling params)

1 files changed, 22 insertions, 0 deletions

diff --git a/kernel/include/bar_emulation.h b/kernel/include/bar_emulation.h
index 759fa25..326e70e 100644
--- a/kernel/include/bar_emulation.h
+++ b/kernel/include/bar_emulation.h
@@ -3,12 +3,30 @@
 
 #include "nvidia-vgpu-vfio.h"
 
+/* MSI-X Table entry size (16 bytes: addr_lo, addr_hi, data, vector_control) */
+#define NV_VGPU_MSIX_ENTRY_SIZE 16
+#define NV_VGPU_MSIX_TABLE_ENTRIES 32
+#define NV_VGPU_MSIX_TABLE_SIZE (NV_VGPU_MSIX_ENTRY_SIZE * NV_VGPU_MSIX_TABLE_ENTRIES)
+#define NV_VGPU_MSIX_PBA_SIZE 8  /* 64 bits for 32 vectors */
+
+struct nv_vgpu_msix_entry {
+	u64 addr;
+	u32 data;
+	u32 vector_control;
+};
+
 struct nv_vgpu_bar_emul_ctx {
 	struct nv_vgpu_device *vgpu;
 	void *bar0_shadow;
 	size_t bar0_shadow_size;
 	spinlock_t shadow_lock;
 	
+	/* MSI-X emulation */
+	struct nv_vgpu_msix_entry msix_table[NV_VGPU_MSIX_TABLE_ENTRIES];
+	u64 msix_pba;  /* Pending Bit Array */
+	spinlock_t msix_lock;
+	bool msix_enabled;
+	
 	struct {
 		u32 offset;
 		u32 value;
@@ -34,6 +52,10 @@ int nv_vgpu_bar_emul_write(struct nv_vgpu_device *vgpu, int bar_idx,
 int nv_vgpu_bar_emul_handle_fault(struct nv_vgpu_device *vgpu,
 				   unsigned long addr, bool write);
 
+/* MSI-X emulation */
+void nv_vgpu_msix_set_pending(struct nv_vgpu_device *vgpu, int vector);
+void nv_vgpu_msix_clear_pending(struct nv_vgpu_device *vgpu, int vector);
+
 static inline u32 nv_vgpu_read_reg(void __iomem *base, u32 offset)
 {
 	return readl(base + offset);