Open-IOV: initial public release

Open-IOV virtualizes NVIDIA GPUs so that unmodified guest drivers run with
real GPU functionality - CUDA first, 3D and video to follow - on unmodified
hosts, without a proprietary vGPU license and without patching any driver,
firmware or hypervisor.

Core principle: emulate the interface, pass through the work.

  kernel/     open-iov-vfio.ko - host VFIO mdev driver: virtual GPU device
              (PCI config space, BAR shadows, MSI-X), GSP boot emulation,
              GSP-RM message-queue/RPC emulation, memory model (GPU-VA to
              guest-PA discovery) and the semaphore-completion service that
              advances guest UVM progress.
  userspace/  libiov.so management API and examples.
  tools/      guest diagnostics, firmware analysis wrappers, RM probes.
  scripts/    stack manager, VM harness, build/load/test automation.
  config/     hardware/version profiles (the portability surface).
  docs/       documentation tree - start at docs/README.md.
  wiki/       long-form firmware and protocol deep dives.

Status: initialization works end to end for a stock 570.144 Linux guest on
Turing (TU104): driver probe, nvidia-smi, the full GSP-RM control battery,
object creation and the early CUDA/UVM start-up path. GPU work forwarding -
the step that makes CUDA kernels execute on real hardware - is the active
work item; see docs/04-implementation/01-known-knowns-and-unknowns.md.

License: BSD-3-Clause for the project; GPL-2.0 for kernel modules that link
GPL-only kernel interfaces. See LICENSE and docs/09-reference/legal-and-licensing.md.

1 files changed, 79 insertions, 0 deletions

diff --git a/kernel/include/bar_emulation.h b/kernel/include/bar_emulation.h
new file mode 100644
index 0000000..326e70e
--- /dev/null
+++ b/kernel/include/bar_emulation.h
@@ -0,0 +1,79 @@
+#ifndef _NV_VGPU_BAR_EMULATION_H_
+#define _NV_VGPU_BAR_EMULATION_H_
+
+#include "nvidia-vgpu-vfio.h"
+
+/* MSI-X Table entry size (16 bytes: addr_lo, addr_hi, data, vector_control) */
+#define NV_VGPU_MSIX_ENTRY_SIZE 16
+#define NV_VGPU_MSIX_TABLE_ENTRIES 32
+#define NV_VGPU_MSIX_TABLE_SIZE (NV_VGPU_MSIX_ENTRY_SIZE * NV_VGPU_MSIX_TABLE_ENTRIES)
+#define NV_VGPU_MSIX_PBA_SIZE 8  /* 64 bits for 32 vectors */
+
+struct nv_vgpu_msix_entry {
+	u64 addr;
+	u32 data;
+	u32 vector_control;
+};
+
+struct nv_vgpu_bar_emul_ctx {
+	struct nv_vgpu_device *vgpu;
+	void *bar0_shadow;
+	size_t bar0_shadow_size;
+	spinlock_t shadow_lock;
+	
+	/* MSI-X emulation */
+	struct nv_vgpu_msix_entry msix_table[NV_VGPU_MSIX_TABLE_ENTRIES];
+	u64 msix_pba;  /* Pending Bit Array */
+	spinlock_t msix_lock;
+	bool msix_enabled;
+	
+	struct {
+		u32 offset;
+		u32 value;
+		bool is_write;
+		bool trapped;
+	} trap_regs[256];
+	int trap_count;
+};
+
+int nv_vgpu_bar_emul_init(struct nv_vgpu_device *vgpu);
+void nv_vgpu_bar_emul_cleanup(struct nv_vgpu_device *vgpu);
+
+int nv_vgpu_bar_trap_register(struct nv_vgpu_device *vgpu, int bar_idx,
+			       u32 offset, u32 size);
+int nv_vgpu_bar_untrap_register(struct nv_vgpu_device *vgpu, int bar_idx,
+				 u32 offset);
+
+int nv_vgpu_bar_emul_read(struct nv_vgpu_device *vgpu, int bar_idx,
+			   u64 offset, void *val, size_t size);
+int nv_vgpu_bar_emul_write(struct nv_vgpu_device *vgpu, int bar_idx,
+			    u64 offset, void *val, size_t size);
+
+int nv_vgpu_bar_emul_handle_fault(struct nv_vgpu_device *vgpu,
+				   unsigned long addr, bool write);
+
+/* MSI-X emulation */
+void nv_vgpu_msix_set_pending(struct nv_vgpu_device *vgpu, int vector);
+void nv_vgpu_msix_clear_pending(struct nv_vgpu_device *vgpu, int vector);
+
+static inline u32 nv_vgpu_read_reg(void __iomem *base, u32 offset)
+{
+	return readl(base + offset);
+}
+
+static inline void nv_vgpu_write_reg(void __iomem *base, u32 offset, u32 val)
+{
+	writel(val, base + offset);
+}
+
+static inline u64 nv_vgpu_read_reg64(void __iomem *base, u32 offset)
+{
+	return readq(base + offset);
+}
+
+static inline void nv_vgpu_write_reg64(void __iomem *base, u32 offset, u64 val)
+{
+	writeq(val, base + offset);
+}
+
+#endif
\ No newline at end of file