vgsp: host CUDA bridge + sema release recovery; greeneye simulator wave

- kernel: gsp_cuda_bridge (QMD launch capture, debugfs job/out/done, param+output resolution cached from inline writes), sema drain fixes (never hold/starve a channel), GR ring autopin + counter autoreg, per-page push reads, counter-derive gate; module builds clean
- tools/cuda-bridge: CUDA driver-API daemon executing mail/vadd kernels on the physical GPU, CUBB2/CBD2 v2 protocol, layout check + self-tests
- tools/guest-diag + tools/cuda-ab: scanner/pin fixes, victory push-only mode
- debug/risc-v-gsp-rm-vm: Phase S simulator wave (GSP device model, boot ladder, triage/re-demo harnesses, docs 30-41), GPGPU-sim scaffolding
- STATE-CURRENT/docs updates

1 files changed, 10 insertions, 0 deletions

diff --git a/kernel/gsp_sema_service.h b/kernel/gsp_sema_service.h
index d5a62e9..530663e 100644
--- a/kernel/gsp_sema_service.h
+++ b/kernel/gsp_sema_service.h
@@ -155,6 +155,16 @@ void gsp_sema_service_fwd_fault_stats(u64 *matched, u64 *unmatched,
 extern bool gsp_sema_gr_rings;
 
 /*
+ * In-kernel GR completion-counter slot derivation (svc_counter_derive): on an
+ * injected-pin miss, resolve a counter slot from the structural translations
+ * (the driver-published page directories, the self-discovered directory and
+ * the targeted rm_mem record) and author the release there instead of waiting
+ * for the external pin watcher. Default on; set 0 to restore the
+ * injected-pin-only behaviour for an A/B without a rebuild.
+ */
+extern bool gsp_sema_counter_derive;
+
+/*
  * Acknowledge tracking-semaphore releases from CE pushes the pump could not
  * read: write the expected payload into the channel's pool semaphore so the
  * driver's wait clears immediately instead of after the content sweep.