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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-25 02:53:50 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-25 02:53:50 -0400 |
| commit | b968c287865b8860e7938f56db3fa358c5bef66e (patch) | |
| tree | 44ea9f681ff2b4bfe948a547045056d8a88a3501 /kernel/gsp_rm_tu104.h | |
| parent | 6fdbe6219f540f23070949648d09c9fd86029d79 (diff) | |
| download | open-iov-b968c287865b8860e7938f56db3fa358c5bef66e.tar.gz open-iov-b968c287865b8860e7938f56db3fa358c5bef66e.zip | |
gsp_rm: implement missing RM_CONTROL handlers for 570.144 guest driver
- Added TU104_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT (0x20800a6c)
- Added TU104_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE (0x20800a38)
- Added TU104_CTRL_SYSTEM_MAP_SHARED_DATA (0x730151)
- Fixed async RPCs (72 GSP_SET_SYSTEM_INFO, 73 SET_REGISTRY, 71 CONTINUATION_RECORD)
to send SUCCESS replies instead of silent consume
- Added explicit handlers for RPC 47 (UNLOADING_GUEST_DRIVER) and 70 (UPDATE_BAR_PDE)
with proper reply semantics
Guest driver was failing at GSP-RM level with unknown RPCs 47, 70, 72, 73.
Channels registered then immediately unregistered.
Now they should stay registered and complete initialization.
Diffstat (limited to 'kernel/gsp_rm_tu104.h')
| -rw-r--r-- | kernel/gsp_rm_tu104.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/kernel/gsp_rm_tu104.h b/kernel/gsp_rm_tu104.h index 3ac01b7..593dfb3 100644 --- a/kernel/gsp_rm_tu104.h +++ b/kernel/gsp_rm_tu104.h @@ -971,6 +971,13 @@ struct tu104_gr_static_info { * Driver computes numGpcs from floorsweepingMasks.gpcMask - zero kills * krcWatchdogInit ("numGpcs > 0" assert -> RmInitAdapter bails). */ #define TU104_CTRL_STATIC_KGR_GET_FLOORSWEEPING_MASKS 0x20800a26 + +/* Missing RM_CONTROL commands observed in guest driver (570.144) */ +#define TU104_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT 0x20800a6c +#define TU104_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE 0x20800a38 + +/* NV0073 (SYSTEM) interface */ +#define TU104_CTRL_SYSTEM_MAP_SHARED_DATA 0x730151 #define TU104_GR_MAX_GPC 12 #define TU104_GR_MAX_TPC_PER_GPC_COUNT 10 |