kernel: guest probe completes - nvidia-smi enumerates the emulated TU104

Root cause of the golden-image NV_ERR_NO_MEMORY: STATIC_KGR_GET_CONTEXT_
BUFFERS_INFO (0x20800a32) fell through to the generic zeroed reply, so
kgraphicsInitializeDeferredStaticData() stored a 0-byte main ctx buffer
size and kgrctxAllocMainCtxBuffer() did a 0-page allocation
(mem_desc.c:1353). Serve the TU104 per-engine ctx buffer table (26 engine
IDs x 8 GR engines; NV_U32_MAX = unsupported, which the client skips).

Second blocker after that: L2 cache-op and TLB-invalidate completion
registers. Turing reaches them through the virtual-register window
(GPU_VREG_* = BAR0 + sriovState.virtualRegPhysOffset + offset, 0xB80000
for a non-SRIOV virtual GPU): NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE
(0xB830B0, TRIGGER bit31) and the L2 invalidate/dirty-flush set
(0x70000-0x70014 and 0xB80F00/0xB80F04). The driver soft-locked spinning
in osDevReadReg032 on 0xB830B4 (kgmmuCheckPendingInvalidates_TU102) and
timed out in kmemsysDoCacheOp_GM107; auto-clear all of them (both the
plain and windowed aliases).

Third: re-probe failed with GspStatusQueueInit msgqRxLink timeout because
gsp_rm_emu_reset() was not called before a fresh boot, leaving rm->parsed
set so the new libos args were never parsed. Reset GSP-RM state on the
fresh FWSEC kick.

Verified: guest nvidia-smi and nvidia-smi -L both exit 0 (full
unload/reload cycle), GPU enumerated as "NVIDIA GeForce RTX 2080 SUPER"
with 256MB, no NO_MEMORY / timeouts / soft lockups in the guest.

Also add tools/rmq/grctx_oracle.c documenting that the host RM does not
expose the ctx-buffer table to userspace (the real values are probed from
the ctxsw ucode by GSP-RM), so the emulation serves synthesized sizes.

1 files changed, 78 insertions, 0 deletions

diff --git a/kernel/gsp_rm_tu104.h b/kernel/gsp_rm_tu104.h
index ff2a4a7..f40c77d 100644
--- a/kernel/gsp_rm_tu104.h
+++ b/kernel/gsp_rm_tu104.h
@@ -702,6 +702,84 @@ static const struct tu104_internal_device_info tu104_internal_device_table[] = {
 #define TU104_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE	0x20802a08
 #define TU104_CTRL_STATIC_KGR_GET_GLOBAL_SM_ORDER	0x20800a22
 #define TU104_CTRL_STATIC_KGR_GET_INFO		0x20800a2a
+#define TU104_CTRL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO	0x20800a32
+
+/* NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO (engine context buffer info)
+ * NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO: engine[ENGINE_ID_COUNT]
+ * NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS:
+ *     engineContextBuffersInfo[GR_MAX_ENGINES]
+ *
+ * The driver's kgraphicsInitializeDeferredStaticData() asks the physical RM
+ * (GSP-RM) for this table; kgrctxAllocMainCtxBuffer() then sizes the golden
+ * image ctx buffer from engine[GRAPHICS].size. A zeroed reply produces a
+ * 0-byte (0-page) allocation -> NV_ERR_NO_MEMORY (mem_desc.c:1353).
+ *
+ * The physical RM probes these sizes from the ctxsw ucode at GR init
+ * (grSetupInitialCtxState -> grDiscoverCtxBufferSize) and reports
+ * NV_U32_MAX for engine IDs the chip does not support. The values below are
+ * the emulated TU104 layout (own buffers, no real GR engine behind them):
+ * sizes are page-aligned scratch regions, NV_U32_MAX = "not supported". */
+#define TU104_CTX_ENGINE_ID_COUNT	26	/* _ENGINE_ID_COUNT (0x1a) */
+#define TU104_CTX_GPU_MAX_ENGINES	8	/* INTERNAL_GR_MAX_ENGINES */
+
+/* NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_* */
+#define TU104_CTX_ENG_GRAPHICS			0x00
+#define TU104_CTX_ENG_VLD			0x01
+#define TU104_CTX_ENG_VIDEO			0x02
+#define TU104_CTX_ENG_MPEG			0x03
+#define TU104_CTX_ENG_CAPTURE			0x04
+#define TU104_CTX_ENG_DISPLAY			0x05
+#define TU104_CTX_ENG_ENCRYPTION		0x06
+#define TU104_CTX_ENG_POSTPROCESS		0x07
+#define TU104_CTX_ENG_GRAPHICS_ZCULL		0x08
+#define TU104_CTX_ENG_GRAPHICS_PM		0x09
+#define TU104_CTX_ENG_COMPUTE_PREEMPT		0x0a
+#define TU104_CTX_ENG_GRAPHICS_PREEMPT		0x0b
+#define TU104_CTX_ENG_GRAPHICS_SPILL		0x0c
+#define TU104_CTX_ENG_GRAPHICS_PAGEPOOL		0x0d
+#define TU104_CTX_ENG_GRAPHICS_BETACB		0x0e
+#define TU104_CTX_ENG_GRAPHICS_RTV		0x0f
+#define TU104_CTX_ENG_GRAPHICS_PATCH		0x10
+#define TU104_CTX_ENG_GRAPHICS_BUNDLE_CB	0x11
+#define TU104_CTX_ENG_GRAPHICS_PAGEPOOL_GLOBAL	0x12
+#define TU104_CTX_ENG_GRAPHICS_ATTRIBUTE_CB	0x13
+#define TU104_CTX_ENG_GRAPHICS_RTV_CB_GLOBAL	0x14
+#define TU104_CTX_ENG_GRAPHICS_GFXP_POOL	0x15
+#define TU104_CTX_ENG_GRAPHICS_GFXP_CTRL_BLK	0x16
+#define TU104_CTX_ENG_GRAPHICS_FECS_EVENT	0x17
+#define TU104_CTX_ENG_GRAPHICS_PRIV_ACCESS_MAP	0x18
+#define TU104_CTX_ENG_GRAPHICS_SETUP		0x19
+
+/* grabbag: emulated ctx buffer sizes (bytes) */
+#define TU104_CTX_SIZE_MAIN			0x200000
+#define TU104_CTX_SIZE_ZCULL			0x100000
+#define TU104_CTX_SIZE_PM			0x8000
+#define TU104_CTX_SIZE_PREEMPT			0x1000
+#define TU104_CTX_SIZE_SPILL			0x1000
+#define TU104_CTX_SIZE_PAGEPOOL			0x10000
+#define TU104_CTX_SIZE_BETACB			0x1000
+#define TU104_CTX_SIZE_RTV			0x1000
+#define TU104_CTX_SIZE_PATCH			0x2000
+#define TU104_CTX_SIZE_BUNDLE_CB		0x1000
+#define TU104_CTX_SIZE_ATTRIBUTE_CB		0x1000
+#define TU104_CTX_SIZE_RTV_CB_GLOBAL		0x1000
+#define TU104_CTX_SIZE_FECS_EVENT		0x1000
+#define TU104_CTX_SIZE_PRIV_ACCESS_MAP		0x1000
+
+struct tu104_ctx_buffer_info {
+	u32 size;
+	u32 alignment;
+};
+
+struct tu104_gr_context_buffers_info {
+	struct tu104_ctx_buffer_info engine[TU104_CTX_ENGINE_ID_COUNT];
+};
+
+struct tu104_gr_get_context_buffers_info_params {
+	struct tu104_gr_context_buffers_info
+		engineContextBuffersInfo[TU104_CTX_GPU_MAX_ENGINES];
+};
+
 
 /* NV0080_CTRL_GR_INFO entry + infoList indices (ctrl0080gr.h) */
 struct tu104_gr_info_entry {