kernel: GSP-RM msgq emulation + TU104 hardware tables (GET_GSP_STATIC_INFO, GSP_RM_CONTROL)

Implements the GSP-RM reply content layer for the msgq RPC channel:

- kernel/gsp_rm_emulation.c/h: GSP-RM msgq emulation engine
  - Queue chain discovery (libos args → RMARGS → GSP_ARGUMENTS_CACHED)
  - Status queue link + GSP_INIT_DONE emission
  - Command queue polling + RPC dispatch
  - SET_GUEST_SYSTEM_INFO version negotiation (VGX 41.12)
  - GET_GSP_STATIC_INFO(65) with 1656-byte GspStaticConfigInfo
  - GSP_RM_CONTROL(76) sub-command dispatch:
    - FIFO_GET_DEVICE_INFO_TABLE (0x20801112)
    - INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c)
    - GPU_GET_CONSTRUCTED_FALCON_INFO (0x208001b0)
    - INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40)

- kernel/gsp_rm_tu104.h: TU104 hardware tables
  - 12-entry FIFO engine table (GR0, CE0-4, NVDEC0-1, NVENC0, SEC2, NVJPG, SW)
  - 8-entry interrupt table (from intr_phys_tu102.c)
  - 1-entry constructed falcon table (FBFLCN)
  - 11-entry internal device info table
  - GspStaticConfigInfo layout (1656 bytes, ABI-verified offsets)
  - Data from NVIDIA driver material (ext-tree) + hwref/turing/tu104

- tools/rmq/: Userspace RM API client (oracle for ground-truth tables)

KNOWN ISSUE: gsp_rm_send crashes (fortify_panic) on multi-element messages
when reply data exceeds one 4096-byte queue element. Affects cmd 0x20800a41
(paramsSize=8204). Multi-element splitting is the next fix.

1 files changed, 694 insertions, 0 deletions

diff --git a/kernel/gsp_rm_tu104.h b/kernel/gsp_rm_tu104.h
new file mode 100644
index 0000000..dc08b1d
--- /dev/null
+++ b/kernel/gsp_rm_tu104.h
@@ -0,0 +1,694 @@
+/*
+ * TU104 Hardware Tables for GSP-RM Emulation
+ *
+ * Static device/engine/interrupt tables for the emulated TU104 GPU.
+ * Data extracted from NVIDIA driver material (ext-tree) and hardware
+ * reference headers (hwref/turing/tu104).
+ *
+ * These tables replace what the real GSP-RM firmware would read from
+ * PTOP hardware registers during boot.
+ */
+
+#ifndef _GSP_RM_TU104_H_
+#define _GSP_RM_TU104_H_
+
+#include <linux/types.h>
+
+/* ============================================================
+ * Wire structures (from 570.144 reference, ABI-checked)
+ * ============================================================ */
+
+/* NV2080_CTRL_FIFO_DEVICE_ENTRY (ctrl2080fifo.h) - 100 bytes */
+struct tu104_fifo_device_entry {
+	u32 engineData[16];	/* ENGINE_INFO_TYPE_* indexed */
+	u32 pbdmaIds[2];
+	u32 pbdmaFaultIds[2];
+	u32 numPbdmas;
+	char engineName[16];
+};
+
+/* NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS - 3212 bytes max */
+#define TU104_FIFO_TABLE_MAX_ENTRIES	32
+#define TU104_FIFO_TABLE_MAX_DEVICES	256
+
+struct tu104_fifo_get_device_info_params {
+	u32 baseIndex;
+	u32 numEntries;
+	u8  bMore;
+	u8  _pad[3];
+	struct tu104_fifo_device_entry entries[TU104_FIFO_TABLE_MAX_ENTRIES];
+};
+
+/* NV2080_CTRL_INTERNAL_DEVICE_INFO (ctrl2080internal.h) - 48 bytes */
+struct tu104_internal_device_info {
+	u32 faultId;
+	u32 instanceId;
+	u32 typeEnum;
+	u32 resetId;
+	u32 devicePriBase;
+	u32 isEngine;
+	u32 rlEngId;
+	u32 runlistPriBase;
+	u32 groupId;
+	u32 ginTargetId;
+	u32 deviceBroadcastPriBase;
+	u32 groupLocalInstanceId;
+};
+
+/* NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS - up to 512 entries */
+#define TU104_INTERNAL_TABLE_MAX_ENTRIES	512
+
+struct tu104_internal_get_device_info_params {
+	u32 numEntries;
+	struct tu104_internal_device_info deviceInfoTable[TU104_INTERNAL_TABLE_MAX_ENTRIES];
+};
+
+/* NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS */
+#define TU104_INTR_TABLE_MAX_SIZE	128
+
+struct tu104_intr_table_entry {
+	u16 engineIdx;
+	u16 _pad0;
+	u32 pmcIntrMask;
+	u32 vectorStall;
+	u32 vectorNonStall;
+};
+
+struct tu104_intr_get_kernel_table_params {
+	u32 tableLen;
+	struct tu104_intr_table_entry table[TU104_INTR_TABLE_MAX_SIZE];
+	u32 subtreeMap[7];	/* NV2080_INTR_CATEGORY_* count */
+};
+
+/* NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO (ctrl2080gpu.h) - 20 bytes */
+struct tu104_constructed_falcon_info {
+	u32 engDesc;
+	u32 ctxAttr;
+	u32 ctxBufferSize;
+	u32 addrSpaceList;
+	u32 registerBase;
+};
+
+#define TU104_MAX_CONSTRUCTED_FALCONS	0x40
+
+struct tu104_get_constructed_falcon_info_params {
+	u32 numConstructedFalcons;
+	struct tu104_constructed_falcon_info constructedFalconsTable[TU104_MAX_CONSTRUCTED_FALCONS];
+};
+
+/* ============================================================
+ * ENGINE_INFO_TYPE indices (engine_info.h) - frozen vGPU ABI
+ * ============================================================ */
+#define EI_ENG_DESC			0
+#define EI_FIFO_TAG			1
+#define EI_RM_ENGINE_TYPE		2
+#define EI_RUNLIST			3
+#define EI_MMU_FAULT_ID			4
+#define EI_RC_MASK			5
+#define EI_RESET			6
+#define EI_INTR				7
+#define EI_MC				8
+#define EI_DEV_TYPE_ENUM		9
+#define EI_INSTANCE_ID			10
+#define EI_RUNLIST_PRI_BASE		11
+#define EI_IS_HOST_DRIVEN_ENGINE	12
+#define EI_RUNLIST_ENGINE_ID		13
+#define EI_CHRAM_PRI_BASE		14
+#define EI_KERNEL_RM_MAX		15
+
+/* ============================================================
+ * ENG_DESC values (MKENGDESC = classId << 8 | instance)
+ * ============================================================ */
+#define TU104_ENG_GR0		0xd334df00	/* classId(Graphics)=0xd334df, inst 0 */
+#define TU104_ENG_CE0		0x793ceb00	/* classId(OBJCE)=0x793ceb, inst 0 */
+#define TU104_ENG_CE1		0x793ceb01
+#define TU104_ENG_CE2		0x793ceb02
+#define TU104_ENG_CE3		0x793ceb03
+#define TU104_ENG_CE4		0x793ceb04
+#define TU104_ENG_NVDEC0	0x8f99e100	/* classId(OBJBSP)=0x8f99e1, inst 0 */
+#define TU104_ENG_NVDEC1	0x8f99e101
+#define TU104_ENG_NVENC0	0xe97b6c00	/* classId(OBJMSENC)=0xe97b6c, inst 0 */
+#define TU104_ENG_SEC2		0x28c40800	/* classId(OBJSEC2)=0x28c408, inst 0 */
+#define TU104_ENG_NVJPG		0x2b3a5400	/* classId(OBJNVJPG)=0x2b3a54, inst 0 */
+#define TU104_ENG_SW		0x95a6f500	/* classId(OBJSWENG)=0x95a6f5, inst 0 */
+#define TU104_ENG_FBFLCN	0x8a20bf00	/* classId(OBJFBFLCN)=0x8a20bf, inst 0 */
+
+/* ============================================================
+ * RM_ENGINE_TYPE values (gpu_engine_type.h)
+ * ============================================================ */
+#define TU104_RM_ENGINE_GR0		0x01
+#define TU104_RM_ENGINE_CE0		0x09
+#define TU104_RM_ENGINE_CE1		0x0a
+#define TU104_RM_ENGINE_CE2		0x0b
+#define TU104_RM_ENGINE_CE3		0x0c
+#define TU104_RM_ENGINE_CE4		0x0d
+#define TU104_RM_ENGINE_NVDEC0		0x1d
+#define TU104_RM_ENGINE_NVDEC1		0x1e
+#define TU104_RM_ENGINE_NVENC0		0x25
+#define TU104_RM_ENGINE_SW		0x2d
+#define TU104_RM_ENGINE_SEC2		0x31
+#define TU104_RM_ENGINE_HOST		0x32
+#define TU104_RM_ENGINE_PMU		0x34
+#define TU104_RM_ENGINE_FBFLCN		0x35
+#define TU104_RM_ENGINE_NVJPG0		0x36
+
+/* ============================================================
+ * MC_ENGINE_IDX values (engine_idx.h)
+ * ============================================================ */
+#define TU104_MC_ENGINE_GR		84
+#define TU104_MC_ENGINE_CE0		15
+#define TU104_MC_ENGINE_CE1		16
+#define TU104_MC_ENGINE_CE2		17
+#define TU104_MC_ENGINE_CE3		18
+#define TU104_MC_ENGINE_CE4		19
+#define TU104_MC_ENGINE_NVDEC0		65
+#define TU104_MC_ENGINE_NVDEC1		66
+#define TU104_MC_ENGINE_NVENC0		38
+#define TU104_MC_ENGINE_SEC2		47
+#define TU104_MC_ENGINE_NVJPG		51
+
+/* ============================================================
+ * NV_PFAULT_MMU_ENG_ID values (tu104/dev_fault.h)
+ * ============================================================ */
+#define TU104_FAULT_ID_GR		64
+#define TU104_FAULT_ID_CE0		15
+#define TU104_FAULT_ID_CE1		16
+#define TU104_FAULT_ID_CE2		17
+#define TU104_FAULT_ID_CE3		18
+#define TU104_FAULT_ID_CE4		19
+#define TU104_FAULT_ID_NVDEC0		10
+#define TU104_FAULT_ID_NVDEC1		25
+#define TU104_FAULT_ID_NVENC0		11
+#define TU104_FAULT_ID_SEC2		14
+#define TU104_FAULT_ID_NVJPG0		24
+#define TU104_FAULT_ID_GSP		2
+#define TU104_FAULT_ID_PMU		6
+
+/* PBDMA fault ID base (NV_PFIFO_CFG0_PBDMA_FAULT_ID_INIT = 32) */
+#define TU104_PBDMA_FAULT_ID_BASE	32
+#define TU104_NUM_PBDMAS		12
+
+/* ============================================================
+ * ROBUST_CHANNEL values (rc.h)
+ * ============================================================ */
+#define TU104_RC_GRAPHICS		40
+#define TU104_RC_CE0			22
+#define TU104_RC_CE1			23
+#define TU104_RC_CE2			24
+#define TU104_RC_CE3			25
+#define TU104_RC_CE4			26
+#define TU104_RC_NVDEC0			14
+#define TU104_RC_NVDEC1			15
+#define TU104_RC_NVENC0			11
+#define TU104_RC_SEC2			2
+#define TU104_RC_NVJPG0			32
+
+/* ============================================================
+ * NV_PTOP_DEVICE_INFO_TYPE_ENUM (tu104/dev_top.h)
+ * ============================================================ */
+#define TU104_PTOP_TYPE_GRAPHICS	0
+#define TU104_PTOP_TYPE_LCE		19
+#define TU104_PTOP_TYPE_NVDEC		16
+#define TU104_PTOP_TYPE_NVENC		14
+#define TU104_PTOP_TYPE_NVJPG		21
+#define TU104_PTOP_TYPE_SEC		13
+#define TU104_PTOP_TYPE_GSP		20
+#define TU104_PTOP_TYPE_IOCTRL		18
+
+/* ============================================================
+ * FIFO_TAG values (hardware engine enum, 4 bits)
+ * ============================================================ */
+#define TU104_TAG_GR			0
+#define TU104_TAG_CE0			1
+#define TU104_TAG_CE1			2
+#define TU104_TAG_CE2			3
+#define TU104_TAG_CE3			4
+#define TU104_TAG_CE4			5
+#define TU104_TAG_NVDEC0		10
+#define TU104_TAG_NVDEC1		11
+#define TU104_TAG_NVENC0		13
+#define TU104_TAG_NVJPG			14
+#define TU104_TAG_SEC2			15
+
+/* ============================================================
+ * TU104 FIFO Engine Table (11 hardware engines + 1 SW)
+ *
+ * Runlist assignment: each engine gets its own runlist.
+ * Runlist 0=GR, 1-5=CE0-CE4, 6-7=NVDEC0-1, 8=NVENC0, 9=SEC2, 10=NVJPG
+ * PBDMA assignment: 1:1 with runlists (PBDMA N services runlist N).
+ * SW engine shares NVJPG's runlist/PBDMA (per fifoConstructSwEngine).
+ * ============================================================ */
+
+static const struct tu104_fifo_device_entry tu104_engine_table[] = {
+	/* [0] GR0 - Graphics */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_GR0,
+			[EI_FIFO_TAG]       = TU104_TAG_GR,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_GR0,
+			[EI_RUNLIST]        = 0,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_GR,
+			[EI_RC_MASK]        = TU104_RC_GRAPHICS,
+			[EI_RESET]          = 12,	/* NV_PMC_ENABLE_PGRAPH bit */
+			[EI_INTR]           = 0,
+			[EI_MC]             = TU104_MC_ENGINE_GR,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_GRAPHICS,
+			[EI_INSTANCE_ID]    = 0,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {0, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 0, 0},
+		.numPbdmas     = 1,
+		.engineName    = "GRAPHICS",
+	},
+	/* [1] CE0 */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_CE0,
+			[EI_FIFO_TAG]       = TU104_TAG_CE0,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CE0,
+			[EI_RUNLIST]        = 1,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_CE0,
+			[EI_RC_MASK]        = TU104_RC_CE0,
+			[EI_RESET]          = 1,
+			[EI_INTR]           = 1,
+			[EI_MC]             = TU104_MC_ENGINE_CE0,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_LCE,
+			[EI_INSTANCE_ID]    = 0,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {1, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 1, 0},
+		.numPbdmas     = 1,
+		.engineName    = "CE0",
+	},
+	/* [2] CE1 */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_CE1,
+			[EI_FIFO_TAG]       = TU104_TAG_CE1,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CE1,
+			[EI_RUNLIST]        = 2,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_CE1,
+			[EI_RC_MASK]        = TU104_RC_CE1,
+			[EI_RESET]          = 2,
+			[EI_INTR]           = 2,
+			[EI_MC]             = TU104_MC_ENGINE_CE1,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_LCE,
+			[EI_INSTANCE_ID]    = 1,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {2, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 2, 0},
+		.numPbdmas     = 1,
+		.engineName    = "CE1",
+	},
+	/* [3] CE2 */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_CE2,
+			[EI_FIFO_TAG]       = TU104_TAG_CE2,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CE2,
+			[EI_RUNLIST]        = 3,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_CE2,
+			[EI_RC_MASK]        = TU104_RC_CE2,
+			[EI_RESET]          = 3,
+			[EI_INTR]           = 3,
+			[EI_MC]             = TU104_MC_ENGINE_CE2,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_LCE,
+			[EI_INSTANCE_ID]    = 2,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {3, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 3, 0},
+		.numPbdmas     = 1,
+		.engineName    = "CE2",
+	},
+	/* [4] CE3 */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_CE3,
+			[EI_FIFO_TAG]       = TU104_TAG_CE3,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CE3,
+			[EI_RUNLIST]        = 4,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_CE3,
+			[EI_RC_MASK]        = TU104_RC_CE3,
+			[EI_RESET]          = 4,
+			[EI_INTR]           = 4,
+			[EI_MC]             = TU104_MC_ENGINE_CE3,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_LCE,
+			[EI_INSTANCE_ID]    = 3,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {4, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 4, 0},
+		.numPbdmas     = 1,
+		.engineName    = "CE3",
+	},
+	/* [5] CE4 */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_CE4,
+			[EI_FIFO_TAG]       = TU104_TAG_CE4,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CE4,
+			[EI_RUNLIST]        = 5,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_CE4,
+			[EI_RC_MASK]        = TU104_RC_CE4,
+			[EI_RESET]          = 5,
+			[EI_INTR]           = 5,
+			[EI_MC]             = TU104_MC_ENGINE_CE4,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_LCE,
+			[EI_INSTANCE_ID]    = 4,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {5, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 5, 0},
+		.numPbdmas     = 1,
+		.engineName    = "CE4",
+	},
+	/* [6] NVDEC0 */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_NVDEC0,
+			[EI_FIFO_TAG]       = TU104_TAG_NVDEC0,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_NVDEC0,
+			[EI_RUNLIST]        = 6,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_NVDEC0,
+			[EI_RC_MASK]        = TU104_RC_NVDEC0,
+			[EI_RESET]          = 14,
+			[EI_INTR]           = 6,
+			[EI_MC]             = TU104_MC_ENGINE_NVDEC0,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_NVDEC,
+			[EI_INSTANCE_ID]    = 0,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {6, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 6, 0},
+		.numPbdmas     = 1,
+		.engineName    = "NVDEC0",
+	},
+	/* [7] NVDEC1 */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_NVDEC1,
+			[EI_FIFO_TAG]       = TU104_TAG_NVDEC1,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_NVDEC1,
+			[EI_RUNLIST]        = 7,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_NVDEC1,
+			[EI_RC_MASK]        = TU104_RC_NVDEC1,
+			[EI_RESET]          = 15,
+			[EI_INTR]           = 7,
+			[EI_MC]             = TU104_MC_ENGINE_NVDEC1,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_NVDEC,
+			[EI_INSTANCE_ID]    = 1,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {7, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 7, 0},
+		.numPbdmas     = 1,
+		.engineName    = "NVDEC1",
+	},
+	/* [8] NVENC0 */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_NVENC0,
+			[EI_FIFO_TAG]       = TU104_TAG_NVENC0,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_NVENC0,
+			[EI_RUNLIST]        = 8,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_NVENC0,
+			[EI_RC_MASK]        = TU104_RC_NVENC0,
+			[EI_RESET]          = 17,
+			[EI_INTR]           = 8,
+			[EI_MC]             = TU104_MC_ENGINE_NVENC0,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_NVENC,
+			[EI_INSTANCE_ID]    = 0,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {8, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 8, 0},
+		.numPbdmas     = 1,
+		.engineName    = "NVENC0",
+	},
+	/* [9] SEC2 */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_SEC2,
+			[EI_FIFO_TAG]       = TU104_TAG_SEC2,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_SEC2,
+			[EI_RUNLIST]        = 9,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_SEC2,
+			[EI_RC_MASK]        = TU104_RC_SEC2,
+			[EI_RESET]          = 19,
+			[EI_INTR]           = 9,
+			[EI_MC]             = TU104_MC_ENGINE_SEC2,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_SEC,
+			[EI_INSTANCE_ID]    = 0,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {9, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 9, 0},
+		.numPbdmas     = 1,
+		.engineName    = "SEC2",
+	},
+	/* [10] NVJPG */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_NVJPG,
+			[EI_FIFO_TAG]       = TU104_TAG_NVJPG,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_NVJPG0,
+			[EI_RUNLIST]        = 10,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_NVJPG0,
+			[EI_RC_MASK]        = TU104_RC_NVJPG0,
+			[EI_RESET]          = 20,
+			[EI_INTR]           = 10,
+			[EI_MC]             = TU104_MC_ENGINE_NVJPG,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_NVJPG,
+			[EI_INSTANCE_ID]    = 0,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {10, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 10, 0},
+		.numPbdmas     = 1,
+		.engineName    = "NVJPG",
+	},
+	/* [11] SW (software engine - shares NVJPG's runlist per fifoConstructSwEngine) */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_SW,
+			[EI_FIFO_TAG]       = 0xffffffff,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_SW,
+			[EI_RUNLIST]        = 10,	/* NVJPG's runlist */
+			[EI_MMU_FAULT_ID]   = 0xffffffff,
+			[EI_RC_MASK]        = 0,
+			[EI_RESET]          = 0,
+			[EI_INTR]           = 0,
+			[EI_MC]             = 0,
+			[EI_DEV_TYPE_ENUM]  = 0,
+			[EI_INSTANCE_ID]    = 0,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 0,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {10, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 10, 0},
+		.numPbdmas     = 1,
+		.engineName    = "SOFTWARE",
+	},
+};
+
+#define TU104_ENGINE_TABLE_SIZE	12
+
+/* ============================================================
+ * TU104 Interrupt Table (from intr_phys_tu102.c, kernel table)
+ *
+ * These are the CPU-RM (guest) visible interrupts.
+ * NV_PMC_INTR_INVALID_MASK = 0 (no PMC mask for these).
+ * NV_INTR_VECTOR_INVALID = 0xFFFFFFFF.
+ * ============================================================ */
+
+#define TU104_NV_INTR_VECTOR_INVALID	0xFFFFFFFF
+
+static const struct tu104_intr_table_entry tu104_intr_kernel_table[] = {
+	/* MC_ENGINE_IDX_REPLAYABLE_FAULT = 59 */
+	{ .engineIdx = 59, .pmcIntrMask = 0,
+	  .vectorStall = 64,    /* NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_REPLAYABLE */
+	  .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID },
+	/* MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR = 62 */
+	{ .engineIdx = 62, .pmcIntrMask = 0,
+	  .vectorStall = 131,   /* NV_PFB_PRI_MMU_INT_VECTOR_FAULT_ERROR_REPLAYABLE */
+	  .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID },
+	/* MC_ENGINE_IDX_ACCESS_CNTR = 60 */
+	{ .engineIdx = 60, .pmcIntrMask = 0,
+	  .vectorStall = 72,    /* HUB_ACCESS_CNTR_INTR_VECTOR */
+	  .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID },
+	/* MC_ENGINE_IDX_CPU_DOORBELL = 73 */
+	{ .engineIdx = 73, .pmcIntrMask = 0,
+	  .vectorStall = 129,   /* NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT */
+	  .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID },
+	/* MC_ENGINE_IDX_PRIV_DOORBELL = 74 */
+	{ .engineIdx = 74, .pmcIntrMask = 0,
+	  .vectorStall = 130,   /* NV_CTRL_VIRTUAL_INTR_VECTORID_VALUE_CONSTANT */
+	  .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID },
+	/* MC_ENGINE_IDX_GR_FECS_LOG = 156 */
+	{ .engineIdx = 156, .pmcIntrMask = 0,
+	  .vectorStall = TU104_NV_INTR_VECTOR_INVALID,
+	  .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID },
+	/* MC_ENGINE_IDX_GSP = 50 */
+	{ .engineIdx = 50, .pmcIntrMask = 0,
+	  .vectorStall = 155,   /* GSP_INTR_0_VECTOR */
+	  .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID },
+	/* MC_ENGINE_IDX_DISP = 2 */
+	{ .engineIdx = 2, .pmcIntrMask = 0,
+	  .vectorStall = 154,   /* PDISP_VECTOR */
+	  .vectorNonStall = TU104_NV_INTR_VECTOR_INVALID },
+};
+
+#define TU104_INTR_KERNEL_TABLE_SIZE	8
+
+/* ============================================================
+ * TU104 Constructed Falcon Table
+ *
+ * Only FBFLCN (framebuffer falcon) is a "constructed falcon" on Turing
+ * (SEC2, GSP, PMU are skipped as they have their own kernel objects).
+ * ============================================================ */
+
+static const struct tu104_constructed_falcon_info tu104_falcon_table[] = {
+	{
+		.engDesc       = TU104_ENG_FBFLCN,
+		.ctxAttr       = 0,
+		.ctxBufferSize = 0x400,		/* 1KB context buffer */
+		.addrSpaceList = 0,
+		.registerBase  = 0x009a4000,	/* NV_PFBFALCON base */
+	},
+};
+
+#define TU104_FALCON_TABLE_SIZE	1
+
+/* ============================================================
+ * TU104 Internal Device Info Table
+ *
+ * Engines + key non-engine devices. The guest driver queries this
+ * by typeEnum to find device register bases and fault IDs.
+ * ============================================================ */
+
+static const struct tu104_internal_device_info tu104_internal_device_table[] = {
+	/* Engines (isEngine=1) */
+	{ .faultId = TU104_FAULT_ID_GR,    .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_GRAPHICS, .resetId = 12, .devicePriBase = 0x00400000, .isEngine = 1, .rlEngId = 0,  .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 },
+	{ .faultId = TU104_FAULT_ID_CE0,   .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_LCE,      .resetId = 1,  .devicePriBase = 0x00040000, .isEngine = 1, .rlEngId = 1,  .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 },
+	{ .faultId = TU104_FAULT_ID_CE1,   .instanceId = 1, .typeEnum = TU104_PTOP_TYPE_LCE,      .resetId = 2,  .devicePriBase = 0x00041000, .isEngine = 1, .rlEngId = 2,  .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 1 },
+	{ .faultId = TU104_FAULT_ID_CE2,   .instanceId = 2, .typeEnum = TU104_PTOP_TYPE_LCE,      .resetId = 3,  .devicePriBase = 0x00042000, .isEngine = 1, .rlEngId = 3,  .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 2 },
+	{ .faultId = TU104_FAULT_ID_CE3,   .instanceId = 3, .typeEnum = TU104_PTOP_TYPE_LCE,      .resetId = 4,  .devicePriBase = 0x00043000, .isEngine = 1, .rlEngId = 4,  .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 3 },
+	{ .faultId = TU104_FAULT_ID_CE4,   .instanceId = 4, .typeEnum = TU104_PTOP_TYPE_LCE,      .resetId = 5,  .devicePriBase = 0x00044000, .isEngine = 1, .rlEngId = 5,  .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 4 },
+	{ .faultId = TU104_FAULT_ID_NVDEC0, .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_NVDEC,   .resetId = 14, .devicePriBase = 0x00060000, .isEngine = 1, .rlEngId = 6,  .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 },
+	{ .faultId = TU104_FAULT_ID_NVDEC1, .instanceId = 1, .typeEnum = TU104_PTOP_TYPE_NVDEC,   .resetId = 15, .devicePriBase = 0x00061000, .isEngine = 1, .rlEngId = 7,  .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 1 },
+	{ .faultId = TU104_FAULT_ID_NVENC0, .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_NVENC,   .resetId = 17, .devicePriBase = 0x00070000, .isEngine = 1, .rlEngId = 8,  .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 },
+	{ .faultId = TU104_FAULT_ID_SEC2,  .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_SEC,      .resetId = 19, .devicePriBase = 0x00840000, .isEngine = 1, .rlEngId = 9,  .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 },
+	{ .faultId = TU104_FAULT_ID_NVJPG0, .instanceId = 0, .typeEnum = TU104_PTOP_TYPE_NVJPG,   .resetId = 20, .devicePriBase = 0x00080000, .isEngine = 1, .rlEngId = 10, .runlistPriBase = 0, .groupId = 0, .ginTargetId = 0, .deviceBroadcastPriBase = 0, .groupLocalInstanceId = 0 },
+};
+
+#define TU104_INTERNAL_DEVICE_TABLE_SIZE	11
+
+/* ============================================================
+ * GspStaticConfigInfo field offsets (ABI-verified, 1656 bytes total)
+ * ============================================================ */
+#define TU104_GSCI_OFF_grCapsBits		0	/* 23 bytes */
+#define TU104_GSCI_OFF_gidInfo			24	/* 268 bytes */
+#define TU104_GSCI_OFF_SKUInfo			292	/* 48 bytes */
+#define TU104_GSCI_OFF_fbRegionInfoParams	344	/* 776 bytes */
+#define TU104_GSCI_OFF_sriovCaps		1120	/* 80 bytes */
+#define TU104_GSCI_OFF_sriovMaxGfid		1200	/* 4 bytes */
+#define TU104_GSCI_OFF_engineCaps		1204	/* 12 bytes */
+#define TU104_GSCI_OFF_poisonFuseEnabled	1216	/* 1 byte */
+#define TU104_GSCI_OFF_fb_length		1224	/* 8 bytes */
+#define TU104_GSCI_OFF_fbio_mask		1232	/* 8 bytes */
+#define TU104_GSCI_OFF_fb_bus_width		1240	/* 4 bytes */
+#define TU104_GSCI_OFF_fb_ram_type		1244	/* 4 bytes */
+#define TU104_GSCI_OFF_fbp_mask			1248	/* 8 bytes */
+#define TU104_GSCI_OFF_l2_cache_size		1256	/* 4 bytes */
+#define TU104_GSCI_OFF_gpuNameString		1260	/* 64 bytes */
+#define TU104_GSCI_OFF_gpuShortNameString	1324	/* 64 bytes */
+#define TU104_GSCI_OFF_gpuNameString_Unicode	1388	/* 128 bytes */
+#define TU104_GSCI_OFF_bIsMobile		1524	/* 1 byte */
+#define TU104_GSCI_OFF_bar1PdeBase		1536	/* 8 bytes */
+#define TU104_GSCI_OFF_bar2PdeBase		1544	/* 8 bytes */
+#define TU104_GSCI_OFF_bVbiosValid		1552	/* 1 byte */
+#define TU104_GSCI_OFF_vbiosSubVendor		1556	/* 4 bytes */
+#define TU104_GSCI_OFF_vbiosSubDevice		1560	/* 4 bytes */
+#define TU104_GSCI_OFF_hInternalClient		1600	/* 4 bytes */
+#define TU104_GSCI_OFF_hInternalDevice		1604	/* 4 bytes */
+#define TU104_GSCI_OFF_hInternalSubdevice	1608	/* 4 bytes */
+#define TU104_GSCI_OFF_ecidInfo			1616	/* 24 bytes */
+#define TU104_GSCI_OFF_fwWprLayoutOffset	1640	/* 16 bytes */
+#define TU104_GSCI_SIZE				1656
+
+/* Internal handle values (g_gpu_nvoc.h, g_resserv_nvoc.h) */
+#define TU104_H_INTERNAL_CLIENT			0xC1E00000
+#define TU104_H_INTERNAL_DEVICE			0xABCD0080
+#define TU104_H_INTERNAL_SUBDEVICE		0xABCD2080
+
+/* GSP_RM_CONTROL sub-commands */
+#define TU104_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE	0x20800a40
+#define TU104_CTRL_FIFO_GET_DEVICE_INFO_TABLE	0x20801112
+#define TU104_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE	0x20800a5c
+#define TU104_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO	0x208001b0
+
+/* FB region info params: numFBRegions(4) + 16 × 48B entries = 772 → aligned 776 */
+struct tu104_fb_region {
+	u64 base;
+	u64 limit;
+	u64 reserved;
+	u32 performance;
+	u8  supportCompressed;
+	u8  supportISO;
+	u8  bProtected;
+	u8  blackList[17];
+	u8  _pad[6];
+};
+
+#endif /* _GSP_RM_TU104_H_ */