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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-21 23:18:53 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-21 23:18:53 -0400 |
| commit | 38425e0891760d86d8a34cc84e8b8f8b39479a8d (patch) | |
| tree | e8ed197a6af7ec7ab427f95dbdf6d9e5cfc2c17b /kernel/gsp_rm_tu104.h | |
| parent | 3f9ea98c15a63c1d65d8157fa54a7c29690f9ddc (diff) | |
| download | open-iov-38425e0891760d86d8a34cc84e8b8f8b39479a8d.tar.gz open-iov-38425e0891760d86d8a34cc84e8b8f8b39479a8d.zip | |
kernel: STATIC_KGR_GET_INFO handler - TU104 litter topology + maxSubcontext=64
Driver caches the GR infoList as pGrInfo and reads MAX_SUBCONTEXT_COUNT
(0x2c) - zero made channel-group numMax==0, asserting channel allocation
(numMax == numFree && numMax != 0 -> NV_ERR_INVALID_STATE, blocking the
per-device open -> NVML 'No devices'). Fill litter topology (6 GPC x
4 TPC x 2 SM = 48 SMs) and subcontext counts = 64
(NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT_INIT).
Diffstat (limited to 'kernel/gsp_rm_tu104.h')
| -rw-r--r-- | kernel/gsp_rm_tu104.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/kernel/gsp_rm_tu104.h b/kernel/gsp_rm_tu104.h index 5a5fecd..db05f68 100644 --- a/kernel/gsp_rm_tu104.h +++ b/kernel/gsp_rm_tu104.h @@ -701,6 +701,32 @@ static const struct tu104_internal_device_info tu104_internal_device_table[] = { #define TU104_CTRL_I2C_TRANSACTION 0x402c0105 #define TU104_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE 0x20802a08 #define TU104_CTRL_STATIC_KGR_GET_GLOBAL_SM_ORDER 0x20800a22 +#define TU104_CTRL_STATIC_KGR_GET_INFO 0x20800a2a + +/* NV0080_CTRL_GR_INFO entry + infoList indices (ctrl0080gr.h) */ +struct tu104_gr_info_entry { + u32 index; + u32 data; +}; +#define TU104_GR_INFO_MAX_SIZE 58 /* NV0080_CTRL_GR_INFO_MAX_SIZE (0x3a) */ +#define TU104_GR_INFO_MAX_ENGINES 8 + +struct tu104_gr_static_info { + struct tu104_gr_info_entry infoList[TU104_GR_INFO_MAX_SIZE]; +}; + +/* infoList indices we populate (ctrl0080gr.h) */ +#define TU104_GR_INFO_IDX_LITTER_NUM_GPCS 0x14 +#define TU104_GR_INFO_IDX_LITTER_NUM_TPC_PER_GPC 0x17 +#define TU104_GR_INFO_IDX_GPU_CORE_COUNT 0x1d +#define TU104_GR_INFO_IDX_LITTER_NUM_SM_PER_TPC 0x20 +#define TU104_GR_INFO_IDX_FAMILY_MAX_TPC_PER_GPC 0x2a +#define TU104_GR_INFO_IDX_MAX_SUBCONTEXT_COUNT 0x2c +#define TU104_GR_INFO_IDX_MAX_LEGACY_SUBCONTEXT_COUNT 0x2d +#define TU104_GR_INFO_IDX_MAX_PER_ENGINE_SUBCONTEXT_COUNT 0x2e + +/* TU104 max subcontexts (NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT_INIT) */ +#define TU104_MAX_SUBCONTEXT_COUNT 64 /* TU104 SM topology: 6 GPCs x 4 TPCs x 2 SMs = 48 SMs, 24 TPCs (RTX 2080 SUPER) */ #define TU104_NUM_GPC 6 |