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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-30 04:04:22 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-30 04:04:22 -0400 |
| commit | 4649ee9c83584b2a59b2c72ce67a1f08d3240810 (patch) | |
| tree | 89771f293d99f33eefb87126ea4d3c113ec53f2e /kernel/gsp_rm_emulation.c | |
| parent | ffa76c353e28437535e10388d64734ac06f93b9f (diff) | |
| download | open-iov-4649ee9c83584b2a59b2c72ce67a1f08d3240810.tar.gz open-iov-4649ee9c83584b2a59b2c72ce67a1f08d3240810.zip | |
gsp-rm: fill GR info indices 7/9/0x17/0x22 (libcuda clock-table path; e94 TPC count)
Diffstat (limited to 'kernel/gsp_rm_emulation.c')
| -rw-r--r-- | kernel/gsp_rm_emulation.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/kernel/gsp_rm_emulation.c b/kernel/gsp_rm_emulation.c index 777c63c..a9b63b1 100644 --- a/kernel/gsp_rm_emulation.c +++ b/kernel/gsp_rm_emulation.c @@ -1775,11 +1775,25 @@ static void gsp_rm_handle_kgr_get_info(struct gsp_emu_context *ctx, /* TU104 litter topology: 6 GPC x 4 TPC x 2 SM = 48 SMs */ info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_GPCS].data = TU104_NUM_GPC; - info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_TPC_PER_GPC].data = TU104_TPC_PER_GPC; + info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_TPC_PER_GPC].data = + TU104_GR_INFO_LITTER_NUM_TPC_PER_GPC; info->infoList[TU104_GR_INFO_IDX_GPU_CORE_COUNT].data = TU104_NUM_SM; info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_SM_PER_TPC].data = TU104_SM_PER_TPC; info->infoList[TU104_GR_INFO_IDX_FAMILY_MAX_TPC_PER_GPC].data = TU104_TPC_PER_GPC; + /* Indices libcuda fetches via NV2080_CTRL_CMD_GR_GET_INFO when it + * builds the ucode-image clock table (GR_GET_INFO copies + * pGrInfo->infoList[index].data). Observed on real TU104: index 9 + * -> 24 (devstate+0xe94 TPC count; 0 makes FUN_003e35f0 return + * NV_ERR_INVALID_ARGUMENT and cuCtxCreate fail 999), index 7 -> 6, + * index 0x17 -> 6 (devstate+0xb0/+0xb4 SM/TPC), index 0x22 -> 48. */ + info->infoList[TU104_GR_INFO_IDX_SHADER_PIPE_COUNT].data = + TU104_GR_INFO_SHADER_PIPE_COUNT; + info->infoList[TU104_GR_INFO_IDX_SHADER_PIPE_SUB_COUNT].data = + TU104_GR_INFO_SHADER_PIPE_SUB_COUNT; + info->infoList[TU104_GR_INFO_IDX_RT_CORE_COUNT].data = + TU104_GR_INFO_RT_CORE_COUNT; + /* subcontext (VEID) counts: 64 per hw */ info->infoList[TU104_GR_INFO_IDX_MAX_SUBCONTEXT_COUNT].data = TU104_MAX_SUBCONTEXT_COUNT; info->infoList[TU104_GR_INFO_IDX_MAX_LEGACY_SUBCONTEXT_COUNT].data = TU104_MAX_SUBCONTEXT_COUNT; |