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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-01 07:22:09 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-01 07:22:09 -0400 |
| commit | aeb9e292925d8942a53f258416dea5de4218ec43 (patch) | |
| tree | f98fc9a66b99d522ccd93b59cd671708691caab6 /kernel/gsp_phys_gpu.c | |
| parent | 64d13b26509e77e9384284586deb20d8903cfafc (diff) | |
| download | open-iov-aeb9e292925d8942a53f258416dea5de4218ec43.tar.gz open-iov-aeb9e292925d8942a53f258416dea5de4218ec43.zip | |
gsp-phys: read-only FWSEC dry-run mode; match the 6-byte BIT token decode
Diffstat (limited to 'kernel/gsp_phys_gpu.c')
| -rw-r--r-- | kernel/gsp_phys_gpu.c | 30 |
1 files changed, 26 insertions, 4 deletions
diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c index a7c8e57..9726b84 100644 --- a/kernel/gsp_phys_gpu.c +++ b/kernel/gsp_phys_gpu.c @@ -703,15 +703,37 @@ int gsp_phys_gpu_claim(void) phys.bar1_len)) { pr_warn("gsp-phys: boot layout/allocation failed; " "backend stays at rung 2\n"); - } else if (gsp_phys_fwsec_enabled()) { - if (gsp_phys_fwsec_run(&phys.boot, phys.pdev, - phys.bar0)) + } else if (gsp_phys_fwsec_enabled() || + gsp_phys_fwsec_dryrun_enabled()) { + if (gsp_phys_fwsec_enabled() && + gsp_phys_fwsec_dryrun_enabled()) { + pr_err("gsp-phys: gsp_phys_fwsec=1 and " + "gsp_phys_fwsec_dryrun=1 are " + "mutually exclusive; refusing " + "both (no writes, nothing run)\n"); + } else if (gsp_phys_fwsec_dryrun_enabled()) { + if (gsp_phys_fwsec_dryrun_run( + &phys.boot, phys.pdev, + phys.bar0)) + pr_warn("gsp-phys: stage 3c " + "dry-run failed " + "(read-only; see log " + "above)\n"); + else + pr_info("gsp-phys: stage 3c " + "dry-run complete " + "(read-only; nothing " + "written)\n"); + } else if (gsp_phys_fwsec_run(&phys.boot, + phys.pdev, + phys.bar0)) { pr_warn("gsp-phys: stage 3c FWSEC failed " "(see recovery log above)\n"); - else + } else { pr_info("gsp-phys: stage 3c FWSEC complete " "(WPR2 up; release will tear it " "down)\n"); + } } } } |