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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-06 13:47:57 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-06 13:47:57 -0400 |
| commit | 20e0fbcfb258dfc067265694ddae9c5250f353ce (patch) | |
| tree | 8871dc6af7590eadcbd145e421276ae07526dc89 /kernel/gsp_phys_gpu.c | |
| parent | 14e5418b24b4dff131c311213cfa17a4aadd813d (diff) | |
| download | open-iov-20e0fbcfb258dfc067265694ddae9c5250f353ce.tar.gz open-iov-20e0fbcfb258dfc067265694ddae9c5250f353ce.zip | |
vgsp: install the Tier-2 scratch-pool window spine via PDE_UPDATE + IQ2M sentinel diagnostic
- The Tier-2 shadow VAs (0x200000 + page<<21 + line<<16) had no PTE chain
in the engine's table view on the shared-management VAS: pdb_build's
client PD0 spine for the guest scratch PT pool is discarded by the
server's root migration, so every param/program/release/alias leg the
launch rewrites to a shadow VA was unreachable by the engine. Install
each scratch pool window lazily through DMA_UPDATE_PDE_2 (same control
shape as the Tier-1 installer, pool chunk as the leaf PT) the first
time a shadow line in it is consumed; shared VAS only, idempotent via
rmcall_guest_pt_win_mask. m17 confirmed the install is accepted
(pdeIndex=1 VA 0x200000 status 0x0).
- IQ2M sentinel: write 0xdeadbeef to the inline-QMD destination word 0
after the prewrite and report iq2m=ran/not-run in the post-mortem so
'engine stalled before the inline window' is distinguishable from 'QMD
deposited but not executed' without a server capture.
Diffstat (limited to 'kernel/gsp_phys_gpu.c')
0 files changed, 0 insertions, 0 deletions