kernel: GR context-promote bisection modes 4-17 and server-managed-ctxbuf registry variant; complete vgsp rename; docs/tooling refresh

- gsp_phys_booter: GR promote bisection modes 4-17 (two-phase zero-field VA,
  batched entries, hVirtMemory, bare VA, KMD SKIP_CTXBUFFER_ALLOC channel,
  old-interface GPU_INITIALIZE_CTX, FBMEM context buffer, UVM-faithful PA-only,
  PATCH/PM auxiliary promotes, server-managed no-promote path); PATCH/PM
  geometry queries and buffers; pre-boot SET_REGISTRY profile selection
- gsp_phys_gpu: gsp_phys_rmcall_gr_promote clamp 0..17 and gsp_phys_srv_ctxbuf
  parameter; registry image variant with RMSetClientRMAllocatedCtxBuffer=0
- vgsp rename across kernel, scripts, tools and docs (module vgsp.ko,
  /sys/kernel/debug/vgsp/, vgsp-<subsystem>: log prefixes)
- risc-v-gsp-rm-debugger user-facing rename and docs/CI refresh; guest-diag
  tool updates; README/SBOM/install/Makefile sync

Live status: CE ladder and P6 guest-copy forwarding green; GR engine context
commit still open (all promote shapes accepted or cleanly refused; the channel
stays CTXNOTVALID) - see Handoff-vGPU-IO.md Addendum 21 (local).

1 files changed, 117 insertions, 117 deletions

diff --git a/kernel/gsp_phys_fwsec.c b/kernel/gsp_phys_fwsec.c
index c20758b..c20543c 100644
--- a/kernel/gsp_phys_fwsec.c
+++ b/kernel/gsp_phys_fwsec.c
@@ -306,7 +306,7 @@ bool gsp_phys_fwsec_board_debug(void __iomem *bar0)
 	u32 fuse = readl(bar0 + GSP_PHYS_FUSE_SECURE_GSP_DEBUG_DIS);
 	bool debug = !(fuse & GSP_PHYS_FUSE_SECURE_GSP_DEBUG_DIS_FIELD);
 
-	pr_info("gsp-phys-fwsec: fuse SECURE_GSP_DEBUG_DIS=0x%08x -> %s board mode\n",
+	pr_info("vgsp-fwsec: fuse SECURE_GSP_DEBUG_DIS=0x%08x -> %s board mode\n",
 		fuse, debug ? "debug" : "production");
 	return debug;
 }
@@ -348,7 +348,7 @@ static bool gsp_phys_fwsec_scratch14_all_done(void __iomem *bar0)
 
 static void gsp_phys_fwsec_dump_state(void __iomem *bar0, const char *what)
 {
-	pr_info("gsp-phys-fwsec: %s: GSP_CPUCTL=0x%08x SEC2_CPUCTL=0x%08x GSP_BOOTVEC=0x%08x WPR2_LO=0x%08x WPR2_HI=0x%08x scratch0E=0x%08x scratch15=0x%08x GFW_BOOT=0x%08x SEC2_M0=0x%08x SEC2_M1=0x%08x\n",
+	pr_info("vgsp-fwsec: %s: GSP_CPUCTL=0x%08x SEC2_CPUCTL=0x%08x GSP_BOOTVEC=0x%08x WPR2_LO=0x%08x WPR2_HI=0x%08x scratch0E=0x%08x scratch15=0x%08x GFW_BOOT=0x%08x SEC2_M0=0x%08x SEC2_M1=0x%08x\n",
 		what,
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_CPUCTL),
 		readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_CPUCTL),
@@ -392,7 +392,7 @@ int gsp_phys_falcon_reset(void __iomem *bar0, u32 base)
 			       GSP_PHYS_DMACTL_IMEM_SCRUBBING)))
 			break;
 		if (time_after_eq(jiffies, deadline)) {
-			pr_err("gsp-phys-fwsec: falcon@0x%x reset scrub not done (DMACTL=0x%08x)\n",
+			pr_err("vgsp-fwsec: falcon@0x%x reset scrub not done (DMACTL=0x%08x)\n",
 			       base, value);
 			ret = -ETIMEDOUT;
 			break;
@@ -405,7 +405,7 @@ int gsp_phys_falcon_reset(void __iomem *bar0, u32 base)
 
 	writel(readl(bar0 + GSP_PHYS_PMC_BOOT_0),
 	       bar0 + base + GSP_PHYS_FALCON_RM);
-	pr_info("gsp-phys-fwsec: falcon@0x%x reset: DMACTL=0x%08x FALCON_RM=0x%08x (PMC_BOOT_0) ENGINE=0x%08x\n",
+	pr_info("vgsp-fwsec: falcon@0x%x reset: DMACTL=0x%08x FALCON_RM=0x%08x (PMC_BOOT_0) ENGINE=0x%08x\n",
 		base, readl(bar0 + base + GSP_PHYS_FALCON_DMACTL),
 		readl(bar0 + base + GSP_PHYS_FALCON_RM),
 		readl(bar0 + base + GSP_PHYS_FALCON_ENGINE));
@@ -426,7 +426,7 @@ void gsp_phys_falcon_disable_ctx_req(void __iomem *bar0, u32 base,
 	       bar0 + fbif + GSP_PHYS_FBIF_CTL);
 	writel(0, bar0 + base + GSP_PHYS_FALCON_DMACTL);
 
-	pr_info("gsp-phys-fwsec: falcon@0x%x FBIF_CTL=0x%08x (ALLOW_PHYS_NO_CTX) DMACTL=0x%08x\n",
+	pr_info("vgsp-fwsec: falcon@0x%x FBIF_CTL=0x%08x (ALLOW_PHYS_NO_CTX) DMACTL=0x%08x\n",
 		base, readl(bar0 + fbif + GSP_PHYS_FBIF_CTL),
 		readl(bar0 + base + GSP_PHYS_FALCON_DMACTL));
 }
@@ -505,7 +505,7 @@ void gsp_phys_falcon_start_cpu(void __iomem *bar0, u32 base)
 	u32 cpuctl = readl(bar0 + base + GSP_PHYS_FALCON_CPUCTL);
 
 	if (cpuctl & GSP_PHYS_CPUCTL_ALIAS_EN) {
-		pr_info("gsp-phys-fwsec: falcon@0x%x ALIAS_EN set, starting via CPUCTL_ALIAS\n",
+		pr_info("vgsp-fwsec: falcon@0x%x ALIAS_EN set, starting via CPUCTL_ALIAS\n",
 			base);
 		writel(GSP_PHYS_CPUCTL_STARTCPU,
 		       bar0 + base + GSP_PHYS_FALCON_CPUCTL_ALIAS);
@@ -526,7 +526,7 @@ int gsp_phys_falcon_wait_halt(void __iomem *bar0, u32 base,
 		if (cpuctl & GSP_PHYS_CPUCTL_HALTED)
 			return 0;
 		if (time_after_eq(jiffies, deadline)) {
-			pr_err("gsp-phys-fwsec: falcon@0x%x did not halt (CPUCTL=0x%08x, timeout %ums)\n",
+			pr_err("vgsp-fwsec: falcon@0x%x did not halt (CPUCTL=0x%08x, timeout %ums)\n",
 			       base, cpuctl, timeout_ms);
 			return -ETIMEDOUT;
 		}
@@ -555,7 +555,7 @@ static int gsp_phys_fwsec_wait_gfw_boot(void __iomem *bar0)
 		if ((cpuctl & GSP_PHYS_CPUCTL_HALTED) &&
 		    (plm & GSP_PHYS_GFW_PLM_LEVEL0) &&
 		    progress == GSP_PHYS_GFW_BOOT_COMPLETED) {
-			pr_info("gsp-phys-fwsec: GFW boot complete: CPUCTL=0x%08x (halted) PLM=0x%08x progress=0xff\n",
+			pr_info("vgsp-fwsec: GFW boot complete: CPUCTL=0x%08x (halted) PLM=0x%08x progress=0xff\n",
 				cpuctl, plm);
 			return 0;
 		}
@@ -564,7 +564,7 @@ static int gsp_phys_fwsec_wait_gfw_boot(void __iomem *bar0)
 		msleep(1);
 	}
 
-	pr_err("gsp-phys-fwsec: GFW boot not complete (CPUCTL=0x%08x PLM=0x%08x progress=0x%x, timeout %ums); not resetting or kicking the falcon\n",
+	pr_err("vgsp-fwsec: GFW boot not complete (CPUCTL=0x%08x PLM=0x%08x progress=0x%x, timeout %ums); not resetting or kicking the falcon\n",
 	       cpuctl, plm, progress, GSP_PHYS_GFW_BOOT_TIMEOUT_MS);
 	return -ETIMEDOUT;
 }
@@ -597,14 +597,14 @@ static int gsp_phys_fwsec_patch_interface(struct gsp_phys_fwsec_ucode *u,
 
 	if (interface_offset > mapped_size ||
 	    sizeof(*hdr) > mapped_size - interface_offset) {
-		pr_err("gsp-phys-fwsec: interface offset 0x%x outside DMEM image 0x%x\n",
+		pr_err("vgsp-fwsec: interface offset 0x%x outside DMEM image 0x%x\n",
 		       interface_offset, mapped_size);
 		return -EINVAL;
 	}
 
 	hdr = (struct gsp_phys_fwsec_intf_header *)(data + interface_offset);
 	if (hdr->entry_count < 2) {
-		pr_err("gsp-phys-fwsec: interface at 0x%x has only %u entries\n",
+		pr_err("vgsp-fwsec: interface at 0x%x has only %u entries\n",
 		       interface_offset, hdr->entry_count);
 		return -EINVAL;
 	}
@@ -628,18 +628,18 @@ static int gsp_phys_fwsec_patch_interface(struct gsp_phys_fwsec_ucode *u,
 	}
 
 	if (!mapper) {
-		pr_err("gsp-phys-fwsec: no DMEM mapper entry for cmd 0x%x\n",
+		pr_err("vgsp-fwsec: no DMEM mapper entry for cmd 0x%x\n",
 		       cmd);
 		return -EINVAL;
 	}
 
 	mapper->init_cmd = cmd;
 	if (mapper->cmd_in_buffer_size < cmd_size)
-		pr_warn("gsp-phys-fwsec: interface input buffer 0x%x smaller than cmd 0x%x (0x%x bytes)\n",
+		pr_warn("vgsp-fwsec: interface input buffer 0x%x smaller than cmd 0x%x (0x%x bytes)\n",
 			mapper->cmd_in_buffer_size, cmd, cmd_size);
 	if (mapper->cmd_in_buffer_offset > mapped_size ||
 	    cmd_size > mapped_size - mapper->cmd_in_buffer_offset) {
-		pr_err("gsp-phys-fwsec: cmd buffer 0x%x+0x%x outside DMEM image 0x%x\n",
+		pr_err("vgsp-fwsec: cmd buffer 0x%x+0x%x outside DMEM image 0x%x\n",
 		       mapper->cmd_in_buffer_offset, cmd_size, mapped_size);
 		return -EINVAL;
 	}
@@ -647,7 +647,7 @@ static int gsp_phys_fwsec_patch_interface(struct gsp_phys_fwsec_ucode *u,
 	memcpy(data + mapper->cmd_in_buffer_offset, cmd_buf, cmd_size);
 	if (cmd_offset)
 		*cmd_offset = mapper->cmd_in_buffer_offset;
-	pr_info("gsp-phys-fwsec: interface patched: mapper@0x%x init_cmd=0x%x cmd@0x%x (0x%x bytes), out buffer 0x%x/0x%x\n",
+	pr_info("vgsp-fwsec: interface patched: mapper@0x%x init_cmd=0x%x cmd@0x%x (0x%x bytes), out buffer 0x%x/0x%x\n",
 		(u32)((u8 *)mapper - data), cmd,
 		mapper->cmd_in_buffer_offset, cmd_size,
 		mapper->cmd_out_buffer_offset, mapper->cmd_out_buffer_size);
@@ -669,7 +669,7 @@ static int gsp_phys_fwsec_bl_desc_fill(const struct gsp_phys_fwsec_ucode *u,
 	secure_off64 = (s64)d->imem_sec_base - d->imem_virt_base +
 		       d->imem_phys_base;
 	if (secure_off64 < 0) {
-		pr_err("gsp-phys-fwsec: secure IMEM offset underflows (base=0x%x virt=0x%x phys=0x%x)\n",
+		pr_err("vgsp-fwsec: secure IMEM offset underflows (base=0x%x virt=0x%x phys=0x%x)\n",
 		       d->imem_sec_base, d->imem_virt_base,
 		       d->imem_phys_base);
 		return -EINVAL;
@@ -679,7 +679,7 @@ static int gsp_phys_fwsec_bl_desc_fill(const struct gsp_phys_fwsec_ucode *u,
 
 	if (secure_off + secure_size > u->code_size ||
 	    d->imem_phys_base + d->imem_load_size > u->code_size) {
-		pr_err("gsp-phys-fwsec: code placement invalid (phys=0x%x load=0x%x secOff=0x%x secSize=0x%x alloc=0x%zx)\n",
+		pr_err("vgsp-fwsec: code placement invalid (phys=0x%x load=0x%x secOff=0x%x secSize=0x%x alloc=0x%zx)\n",
 		       d->imem_phys_base, d->imem_load_size, secure_off,
 		       secure_size, u->code_size);
 		return -EINVAL;
@@ -726,24 +726,24 @@ static void gsp_phys_fwsec_dump_kick_state(void __iomem *bar0,
 
 	if (fwsec.pdev)
 		pci_read_config_word(fwsec.pdev, PCI_COMMAND, &pci_cmd);
-	pr_info("gsp-phys-fwsec: FAILDUMP PCI_COMMAND=0x%04x [bus_master=%s mem=%s io=%s]\n",
+	pr_info("vgsp-fwsec: FAILDUMP PCI_COMMAND=0x%04x [bus_master=%s mem=%s io=%s]\n",
 		pci_cmd, pci_cmd & PCI_COMMAND_MASTER ? "on" : "OFF",
 		pci_cmd & PCI_COMMAND_MEMORY ? "on" : "off",
 		pci_cmd & PCI_COMMAND_IO ? "on" : "off");
 
-	pr_info("gsp-phys-fwsec: FAILDUMP GSP CPUCTL=0x%08x HWCFG=0x%08x HWCFG2=0x%08x ENGINE=0x%08x DMACTL=0x%08x BOOTVEC=0x%08x\n",
+	pr_info("vgsp-fwsec: FAILDUMP GSP CPUCTL=0x%08x HWCFG=0x%08x HWCFG2=0x%08x ENGINE=0x%08x DMACTL=0x%08x BOOTVEC=0x%08x\n",
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_CPUCTL),
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_HWCFG),
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_HWCFG2),
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_ENGINE),
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_DMACTL),
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_BOOTVEC));
-	pr_info("gsp-phys-fwsec: FAILDUMP GSP MBOX0=0x%08x MBOX1=0x%08x FALCON_OS=0x%08x FALCON_RM=0x%08x\n",
+	pr_info("vgsp-fwsec: FAILDUMP GSP MBOX0=0x%08x MBOX1=0x%08x FALCON_OS=0x%08x FALCON_RM=0x%08x\n",
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_MAILBOX0),
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_MAILBOX1),
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_OS),
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_RM));
-	pr_info("gsp-phys-fwsec: FAILDUMP SEC2 CPUCTL=0x%08x HWCFG=0x%08x ENGINE=0x%08x MBOX0=0x%08x MBOX1=0x%08x FALCON_OS=0x%08x\n",
+	pr_info("vgsp-fwsec: FAILDUMP SEC2 CPUCTL=0x%08x HWCFG=0x%08x ENGINE=0x%08x MBOX0=0x%08x MBOX1=0x%08x FALCON_OS=0x%08x\n",
 		readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_CPUCTL),
 		readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_HWCFG),
 		readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_ENGINE),
@@ -751,7 +751,7 @@ static void gsp_phys_fwsec_dump_kick_state(void __iomem *bar0,
 		readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_MAILBOX1),
 		readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_OS));
 
-	pr_info("gsp-phys-fwsec: FAILDUMP state WPR2_LO raw=0x%08x VAL=0x%x WPR2_HI raw=0x%08x VAL=0x%x PLM=0x%08x GFW_BOOT=0x%08x SCRATCH_0E=0x%08x FRTS_ERR=0x%x SCRATCH_15=0x%08x SB_ERR=0x%x RISCV_STATUS=0x%08x\n",
+	pr_info("vgsp-fwsec: FAILDUMP state WPR2_LO raw=0x%08x VAL=0x%x WPR2_HI raw=0x%08x VAL=0x%x PLM=0x%08x GFW_BOOT=0x%08x SCRATCH_0E=0x%08x FRTS_ERR=0x%x SCRATCH_15=0x%08x SB_ERR=0x%x RISCV_STATUS=0x%08x\n",
 		readl(bar0 + GSP_PHYS_WPR2_ADDR_LO),
 		gsp_phys_fwsec_wpr2_lo_val(bar0),
 		readl(bar0 + GSP_PHYS_WPR2_ADDR_HI),
@@ -766,14 +766,14 @@ static void gsp_phys_fwsec_dump_kick_state(void __iomem *bar0,
 
 	for (i = 0; i < GSP_PHYS_VBIOS_SCRATCH_WORDS; i++)
 		words[i] = readl(bar0 + GSP_PHYS_VBIOS_SCRATCH_BASE + i * 4);
-	pr_info("gsp-phys-fwsec: FAILDUMP scratch 0x1400..0x143f: %*ph\n",
+	pr_info("vgsp-fwsec: FAILDUMP scratch 0x1400..0x143f: %*ph\n",
 		64, (const u8 *)words);
-	pr_info("gsp-phys-fwsec: FAILDUMP scratch 0x1440..0x147f: %*ph\n",
+	pr_info("vgsp-fwsec: FAILDUMP scratch 0x1440..0x147f: %*ph\n",
 		64, (const u8 *)words + 64);
 
 	gsp_phys_falcon_dmem_read(bar0, GSP_PHYS_GSP_BASE, 0, words,
 				  sizeof(*bl) / 4);
-	pr_info("gsp-phys-fwsec: FAILDUMP DMEM0 (84 B): %*ph\n",
+	pr_info("vgsp-fwsec: FAILDUMP DMEM0 (84 B): %*ph\n",
 		(int)sizeof(*bl), (const u8 *)words);
 	desc_intact = memcmp(words, bl, sizeof(*bl)) == 0;
 	data_image = u->data_va &&
@@ -784,7 +784,7 @@ static void gsp_phys_fwsec_dump_kick_state(void __iomem *bar0,
 
 	gsp_phys_falcon_imem_read(bar0, GSP_PHYS_GSP_BASE, bl_dst, words, 4);
 	bl_intact = words[0] == expected_bl0;
-	pr_info("gsp-phys-fwsec: FAILDUMP IMEM BL @0x%x: %08x %08x %08x %08x (word0 want 0x%08x -> %s)\n",
+	pr_info("vgsp-fwsec: FAILDUMP IMEM BL @0x%x: %08x %08x %08x %08x (word0 want 0x%08x -> %s)\n",
 		bl_dst, words[0], words[1], words[2], words[3], expected_bl0,
 		bl_intact ? "intact" : "CHANGED");
 
@@ -796,7 +796,7 @@ static void gsp_phys_fwsec_dump_kick_state(void __iomem *bar0,
 	gsp_phys_falcon_imem_read(bar0, GSP_PHYS_GSP_BASE,
 				  u->desc.imem_phys_base, words, 4);
 	code_loaded = have_expected_code && words[0] == expected_code0;
-	pr_info("gsp-phys-fwsec: FAILDUMP IMEM ns code @0x%x: %08x %08x %08x %08x (word0 want 0x%08x -> %s)\n",
+	pr_info("vgsp-fwsec: FAILDUMP IMEM ns code @0x%x: %08x %08x %08x %08x (word0 want 0x%08x -> %s)\n",
 		u->desc.imem_phys_base, words[0], words[1], words[2], words[3],
 		expected_code0, code_loaded ? "loaded" : "NOT loaded");
 
@@ -804,7 +804,7 @@ static void gsp_phys_fwsec_dump_kick_state(void __iomem *bar0,
 	    u->data_size >= (size_t)fwsec.cmd_offset + 48) {
 		gsp_phys_falcon_dmem_read(bar0, GSP_PHYS_GSP_BASE,
 					  fwsec.cmd_offset, words, 12);
-		pr_info("gsp-phys-fwsec: FAILDUMP interface patch @DMEM 0x%x (48 B): %*ph\n",
+		pr_info("vgsp-fwsec: FAILDUMP interface patch @DMEM 0x%x (48 B): %*ph\n",
 			fwsec.cmd_offset, 48, (const u8 *)words);
 	}
 
@@ -816,7 +816,7 @@ static void gsp_phys_fwsec_dump_kick_state(void __iomem *bar0,
 		verdict = "BL descriptor intact, code not loaded -> stalled at the code DMA (or the BL never entered; check bus_master and TRANSCFG)";
 	else
 		verdict = "DMEM0 matches neither the BL descriptor nor the FWSEC data image";
-	pr_info("gsp-phys-fwsec: FAILDUMP verdict: %s\n", verdict);
+	pr_info("vgsp-fwsec: FAILDUMP verdict: %s\n", verdict);
 }
 
 /*
@@ -847,14 +847,14 @@ static int gsp_phys_fwsec_exec_with_loader(void __iomem *bar0,
 		    GSP_PHYS_FBIF_TRANSCFG_MEM_TYPE;
 	writel(transcfg, bar0 + GSP_PHYS_GSP_FBIF_BASE +
 	       GSP_PHYS_FBIF_TRANSCFG(4));
-	pr_info("gsp-phys-fwsec: TRANSCFG[4]@0x%x = 0x%08x (coherent sysmem, physical)\n",
+	pr_info("vgsp-fwsec: TRANSCFG[4]@0x%x = 0x%08x (coherent sysmem, physical)\n",
 		GSP_PHYS_GSP_FBIF_BASE + GSP_PHYS_FBIF_TRANSCFG(4),
 		readl(bar0 + GSP_PHYS_GSP_FBIF_BASE +
 		      GSP_PHYS_FBIF_TRANSCFG(4)));
 
 	gsp_phys_falcon_dmem_copy(bar0, GSP_PHYS_GSP_BASE, 0, (const u8 *)&bl,
 				  sizeof(bl));
-	pr_info("gsp-phys-fwsec: BL descriptor at DMEM0: ctxDma=%u codeDma=0x%llx nsOff/Size=0x%x/0x%x secOff/Size=0x%x/0x%x dataDma=0x%llx dataSize=0x%x\n",
+	pr_info("vgsp-fwsec: BL descriptor at DMEM0: ctxDma=%u codeDma=0x%llx nsOff/Size=0x%x/0x%x secOff/Size=0x%x/0x%x dataDma=0x%llx dataSize=0x%x\n",
 		bl.ctx_dma, (u64)u->code_dma, bl.non_secure_code_off,
 		bl.non_secure_code_size, bl.secure_code_off,
 		bl.secure_code_size, (u64)u->data_dma, bl.data_size);
@@ -862,7 +862,7 @@ static int gsp_phys_fwsec_exec_with_loader(void __iomem *bar0,
 	block_count = readl(bar0 + GSP_PHYS_GSP_BASE +
 			    GSP_PHYS_FALCON_HWCFG) & GSP_PHYS_HWCFG_IMEM_SIZE;
 	if (block_count * 256 < GSP_PHYS_SEC2_BL_CODE_SIZE) {
-		pr_err("gsp-phys-fwsec: GSP IMEM too small for the boot-loader (%u blocks)\n",
+		pr_err("vgsp-fwsec: GSP IMEM too small for the boot-loader (%u blocks)\n",
 		       block_count);
 		return -EINVAL;
 	}
@@ -871,7 +871,7 @@ static int gsp_phys_fwsec_exec_with_loader(void __iomem *bar0,
 				  gsp_phys_sec2_bl_image,
 				  GSP_PHYS_SEC2_BL_CODE_SIZE, false,
 				  GSP_PHYS_SEC2_BL_START_TAG << 8);
-	pr_info("gsp-phys-fwsec: generic SEC2 BL code 0x%x bytes at IMEM 0x%x (IMEM_SIZE=%u blocks, 256-byte blocks, tag 0x%x)\n",
+	pr_info("vgsp-fwsec: generic SEC2 BL code 0x%x bytes at IMEM 0x%x (IMEM_SIZE=%u blocks, 256-byte blocks, tag 0x%x)\n",
 		GSP_PHYS_SEC2_BL_CODE_SIZE, bl_dst, block_count,
 		GSP_PHYS_SEC2_BL_START_TAG);
 
@@ -890,7 +890,7 @@ static int gsp_phys_fwsec_exec_with_loader(void __iomem *bar0,
 					  imem_rd, 4);
 		if (memcmp(dmem_rd, &bl, sizeof(dmem_rd)) ||
 		    memcmp(imem_rd, gsp_phys_sec2_bl_image, sizeof(imem_rd))) {
-			pr_err("gsp-phys-fwsec: staging not visible before kick (DMEM0 %08x/%08x/%08x/%08x IMEM %08x/%08x/%08x/%08x); the falcon is not accepting DMA - aborting before STARTCPU\n",
+			pr_err("vgsp-fwsec: staging not visible before kick (DMEM0 %08x/%08x/%08x/%08x IMEM %08x/%08x/%08x/%08x); the falcon is not accepting DMA - aborting before STARTCPU\n",
 			       dmem_rd[0], dmem_rd[1], dmem_rd[2], dmem_rd[3],
 			       imem_rd[0], imem_rd[1], imem_rd[2], imem_rd[3]);
 			return -EIO;
@@ -900,14 +900,14 @@ static int gsp_phys_fwsec_exec_with_loader(void __iomem *bar0,
 	writel(GSP_PHYS_SEC2_BL_START_TAG << 8,
 	       bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_BOOTVEC);
 	cpuctl = readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_CPUCTL);
-	pr_info("gsp-phys-fwsec: BOOTVEC=0x%08x CPUCTL before start=0x%08x\n",
+	pr_info("vgsp-fwsec: BOOTVEC=0x%08x CPUCTL before start=0x%08x\n",
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_BOOTVEC),
 		cpuctl);
 
 	gsp_phys_falcon_start_cpu(bar0, GSP_PHYS_GSP_BASE);
 	ret = gsp_phys_falcon_wait_halt(bar0, GSP_PHYS_GSP_BASE,
 					GSP_PHYS_FWSEC_HALT_TIMEOUT_MS);
-	pr_info("gsp-phys-fwsec: GSP CPUCTL after FWSEC kick=0x%08x\n",
+	pr_info("vgsp-fwsec: GSP CPUCTL after FWSEC kick=0x%08x\n",
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_CPUCTL));
 	if (ret || gsp_phys_fwsec_verbose_param)
 		gsp_phys_fwsec_dump_kick_state(bar0, &bl, u, bl_dst);
@@ -962,25 +962,25 @@ static int gsp_phys_fwsec_ucode_stage(struct pci_dev *pdev,
 	    desc->imem_load_size > code_alloc - desc->imem_phys_base ||
 	    secure_off >= code_alloc ||
 	    secure_size > code_alloc - secure_off) {
-		pr_err("gsp-phys-fwsec: FWSEC IMEM does not fit the code allocation (phys=0x%x load=0x%x secOff=0x%x secSize=0x%x alloc=0x%x)\n",
+		pr_err("vgsp-fwsec: FWSEC IMEM does not fit the code allocation (phys=0x%x load=0x%x secOff=0x%x secSize=0x%x alloc=0x%x)\n",
 		       desc->imem_phys_base, desc->imem_load_size, secure_off,
 		       secure_size, code_alloc);
 		return -EINVAL;
 	}
 	if (desc->dmem_phys_base >= data_alloc ||
 	    desc->dmem_load_size > data_alloc - desc->dmem_phys_base) {
-		pr_err("gsp-phys-fwsec: FWSEC DMEM does not fit the data allocation (phys=0x%x load=0x%x alloc=0x%x)\n",
+		pr_err("vgsp-fwsec: FWSEC DMEM does not fit the data allocation (phys=0x%x load=0x%x alloc=0x%x)\n",
 		       desc->dmem_phys_base, desc->dmem_load_size, data_alloc);
 		return -EINVAL;
 	}
 	if (desc->dmem_phys_base != 0)
-		pr_warn("gsp-phys-fwsec: FWSEC DMEM physical base is 0x%x (not 0); interface patching uses the image-buffer offsets as the distribution driver does\n",
+		pr_warn("vgsp-fwsec: FWSEC DMEM physical base is 0x%x (not 0); interface patching uses the image-buffer offsets as the distribution driver does\n",
 			desc->dmem_phys_base);
 
 	if (image_start + desc->imem_load_size > vbios->size ||
 	    image_start + desc->dmem_offset + desc->dmem_load_size >
 	    vbios->size) {
-		pr_err("gsp-phys-fwsec: FWSEC images outside the VBIOS copy\n");
+		pr_err("vgsp-fwsec: FWSEC images outside the VBIOS copy\n");
 		return -EINVAL;
 	}
 
@@ -990,14 +990,14 @@ static int gsp_phys_fwsec_ucode_stage(struct pci_dev *pdev,
 	u->code_va = dma_alloc_coherent(&pdev->dev, code_alloc, &u->code_dma,
 					GFP_KERNEL);
 	if (!u->code_va) {
-		pr_err("gsp-phys-fwsec: FWSEC code allocation (0x%x) failed\n",
+		pr_err("vgsp-fwsec: FWSEC code allocation (0x%x) failed\n",
 		       code_alloc);
 		return -ENOMEM;
 	}
 	u->data_va = dma_alloc_coherent(&pdev->dev, data_alloc, &u->data_dma,
 					GFP_KERNEL);
 	if (!u->data_va) {
-		pr_err("gsp-phys-fwsec: FWSEC data allocation (0x%x) failed\n",
+		pr_err("vgsp-fwsec: FWSEC data allocation (0x%x) failed\n",
 		       data_alloc);
 		gsp_phys_fwsec_ucode_free(pdev, u);
 		return -ENOMEM;
@@ -1011,7 +1011,7 @@ static int gsp_phys_fwsec_ucode_stage(struct pci_dev *pdev,
 	       vbios->data + image_start + desc->dmem_offset,
 	       desc->dmem_load_size);
 
-	pr_info("gsp-phys-fwsec: staged FWSEC: code alloc 0x%x dma=0x%llx (imemLoad=0x%x secOff/Size=0x%x/0x%x), data alloc 0x%x dma=0x%llx (dmemLoad=0x%x)\n",
+	pr_info("vgsp-fwsec: staged FWSEC: code alloc 0x%x dma=0x%llx (imemLoad=0x%x secOff/Size=0x%x/0x%x), data alloc 0x%x dma=0x%llx (dmemLoad=0x%x)\n",
 		code_alloc, (u64)u->code_dma, desc->imem_load_size,
 		secure_off, secure_size, data_alloc, (u64)u->data_dma,
 		desc->dmem_load_size);
@@ -1090,7 +1090,7 @@ static bool gsp_phys_booter_seed_sequence_state(void __iomem *bar0)
 		 (after & (GSP_PHYS_SCRATCH14_BOOTER_VERSION_MASK |
 			   GSP_PHYS_SCRATCH14_HANDOFF_MASK));
 
-	pr_info("gsp-phys-fwsec: booter sequence seed: PLM@0x%x 0x%08x (host-open=%s, restored 0x%08x), scratch14 0x%08x -> 0x%08x (booterVersion=%u want %u, handoffs 0x%x) -> %s\n",
+	pr_info("vgsp-fwsec: booter sequence seed: PLM@0x%x 0x%08x (host-open=%s, restored 0x%08x), scratch14 0x%08x -> 0x%08x (booterVersion=%u want %u, handoffs 0x%x) -> %s\n",
 		plm_addr, plm_orig, opened ? "yes" : "no",
 		readl(bar0 + plm_addr), before, readback,
 		(readback & GSP_PHYS_SCRATCH14_BOOTER_VERSION_MASK) >>
@@ -1101,7 +1101,7 @@ static bool gsp_phys_booter_seed_sequence_state(void __iomem *bar0)
 		seeded ? "SEEDED" : "NOT SEEDED (host write blocked)");
 
 	if (!seeded)
-		pr_warn("gsp-phys-fwsec: scratch14 write protection is not host-open; the booter unload handoff gate cannot be satisfied in a FWSEC-only carve\n");
+		pr_warn("vgsp-fwsec: scratch14 write protection is not host-open; the booter unload handoff gate cannot be satisfied in a FWSEC-only carve\n");
 	return seeded;
 }
 
@@ -1125,7 +1125,7 @@ static int gsp_phys_booter_unload(void __iomem *bar0)
 	u32 m0, m1, scratch;
 	int ret;
 
-	pr_info("gsp-phys-fwsec: booter unload: resetting SEC2 falcon\n");
+	pr_info("vgsp-fwsec: booter unload: resetting SEC2 falcon\n");
 	ret = gsp_phys_falcon_reset(bar0, GSP_PHYS_SEC2_BASE);
 	if (ret)
 		return ret;
@@ -1152,7 +1152,7 @@ static int gsp_phys_booter_unload(void __iomem *bar0)
 	writel(GSP_PHYS_BOOTER_UNLOAD_MBOX,
 	       bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_MAILBOX1);
 
-	pr_info("gsp-phys-fwsec: booter unload: image 0x%zx bytes (ns 0x%x, sec 0x%x, data 0x%x), MAILBOX0/1=0xff, BOOTVEC=0\n",
+	pr_info("vgsp-fwsec: booter unload: image 0x%zx bytes (ns 0x%x, sec 0x%x, data 0x%x), MAILBOX0/1=0xff, BOOTVEC=0\n",
 		sizeof(gsp_phys_booter_unload_image),
 		GSP_PHYS_BOOTER_UNLOAD_NS_CODE_SIZE,
 		GSP_PHYS_BOOTER_UNLOAD_SEC_CODE_SIZE,
@@ -1167,17 +1167,17 @@ static int gsp_phys_booter_unload(void __iomem *bar0)
 	scratch = readl(bar0 + GSP_PHYS_BSI_VPR_SECURE_SCRATCH_14);
 	m0 = readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_MAILBOX0);
 	m1 = readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_MAILBOX1);
-	pr_info("gsp-phys-fwsec: booter unload done: SEC2 M0=0x%08x M1=0x%08x WPR2_LO=0x%08x WPR2_HI=0x%08x scratch14=0x%08x\n",
+	pr_info("vgsp-fwsec: booter unload done: SEC2 M0=0x%08x M1=0x%08x WPR2_LO=0x%08x WPR2_HI=0x%08x scratch14=0x%08x\n",
 		m0, m1, readl(bar0 + GSP_PHYS_WPR2_ADDR_LO),
 		readl(bar0 + GSP_PHYS_WPR2_ADDR_HI), scratch);
-	pr_info("gsp-phys-fwsec: booter unload scratch14: booterVersion=%u handoffs=0x%x (unload clears both)\n",
+	pr_info("vgsp-fwsec: booter unload scratch14: booterVersion=%u handoffs=0x%x (unload clears both)\n",
 		(scratch & GSP_PHYS_SCRATCH14_BOOTER_VERSION_MASK) >>
 			GSP_PHYS_SCRATCH14_BOOTER_VERSION_SHIFT,
 		(scratch & GSP_PHYS_SCRATCH14_HANDOFF_MASK) >>
 			GSP_PHYS_SCRATCH14_HANDOFF_SHIFT);
 
 	if (m0 != 0) {
-		pr_err("gsp-phys-fwsec: booter unload reported error 0x%x\n",
+		pr_err("vgsp-fwsec: booter unload reported error 0x%x\n",
 		       m0);
 		return -EIO;
 	}
@@ -1204,12 +1204,12 @@ static void gsp_phys_host_wpr2_unlock(void __iomem *bar0)
 
 	fuse = readl(bar0 + GSP_PHYS_FUSE_SECURE_MMU_PLM_WR_SECURE);
 	opened = gsp_phys_plm_open(bar0, plm_addr, &plm_orig);
-	pr_info("gsp-phys-fwsec: host WPR2 unlock: MMU PLM@0x%x 0x%08x -> 0x%08x (host-open=%s), fuse SECURE_MMU_PLM_WR_SECURE=0x%08x\n",
+	pr_info("vgsp-fwsec: host WPR2 unlock: MMU PLM@0x%x 0x%08x -> 0x%08x (host-open=%s), fuse SECURE_MMU_PLM_WR_SECURE=0x%08x\n",
 		plm_addr, plm_orig, readl(bar0 + plm_addr),
 		opened ? "yes" : "no", fuse);
 	if (!opened) {
 		writel(plm_orig, bar0 + plm_addr);
-		pr_warn("gsp-phys-fwsec: MMU PLM write protection is fuse-locked (restored 0x%08x); not touching WPR2 (fail-safe stays in force, reboot with approval may be required)\n",
+		pr_warn("vgsp-fwsec: MMU PLM write protection is fuse-locked (restored 0x%08x); not touching WPR2 (fail-safe stays in force, reboot with approval may be required)\n",
 			readl(bar0 + plm_addr));
 		return;
 	}
@@ -1242,7 +1242,7 @@ static void gsp_phys_host_wpr2_unlock(void __iomem *bar0)
 	writel(reg & ~GSP_PHYS_PFB_MMU_WPR2_ALLOW_MASK,
 	       bar0 + GSP_PHYS_PFB_MMU_WPR_ALLOW_WRITE);
 
-	pr_info("gsp-phys-fwsec: host WPR2 unlock applied: WPR2_LO=0x%08x WPR2_HI=0x%08x ALLOW_READ=0x%08x ALLOW_WRITE=0x%08x\n",
+	pr_info("vgsp-fwsec: host WPR2 unlock applied: WPR2_LO=0x%08x WPR2_HI=0x%08x ALLOW_READ=0x%08x ALLOW_WRITE=0x%08x\n",
 		readl(bar0 + GSP_PHYS_WPR2_ADDR_LO),
 		readl(bar0 + GSP_PHYS_WPR2_ADDR_HI),
 		readl(bar0 + GSP_PHYS_PFB_MMU_WPR_ALLOW_READ),
@@ -1250,7 +1250,7 @@ static void gsp_phys_host_wpr2_unlock(void __iomem *bar0)
 
 	/* Restore the board's original privilege mask (best effort). */
 	writel(plm_orig, bar0 + plm_addr);
-	pr_info("gsp-phys-fwsec: host WPR2 unlock: MMU PLM restored to 0x%08x\n",
+	pr_info("vgsp-fwsec: host WPR2 unlock: MMU PLM restored to 0x%08x\n",
 		readl(bar0 + plm_addr));
 }
 
@@ -1266,21 +1266,21 @@ static int gsp_phys_fwsec_teardown(void __iomem *bar0)
 	int ret;
 
 	if (!gsp_phys_fwsec_wpr2_up(bar0)) {
-		pr_info("gsp-phys-fwsec: teardown: WPR2 already down; resetting the GSP falcon only\n");
+		pr_info("vgsp-fwsec: teardown: WPR2 already down; resetting the GSP falcon only\n");
 		gsp_phys_falcon_reset(bar0, GSP_PHYS_GSP_BASE);
 		return 0;
 	}
 
 	if (fwsec.ucode.code_va) {
 		gsp_phys_read_vbios_desc_init(&sb_cmd);
-		pr_info("gsp-phys-fwsec: FWSEC-SB cmd 0x%x (readVbiosDesc version=%u size=%u flags=%u)\n",
+		pr_info("vgsp-fwsec: FWSEC-SB cmd 0x%x (readVbiosDesc version=%u size=%u flags=%u)\n",
 			GSP_PHYS_FWSEC_CMD_SB, sb_cmd.version, sb_cmd.size,
 			sb_cmd.flags);
 		ret = gsp_phys_fwsec_exec_cmd(bar0, &fwsec.ucode,
 					      GSP_PHYS_FWSEC_CMD_SB, &sb_cmd,
 					      sizeof(sb_cmd));
 		if (ret) {
-			pr_err("gsp-phys-fwsec: FWSEC-SB execution failed: %d; continuing to booter unload\n",
+			pr_err("vgsp-fwsec: FWSEC-SB execution failed: %d; continuing to booter unload\n",
 			       ret);
 		} else {
 			plm = readl(bar0 + GSP_PHYS_GFW_PLM);
@@ -1288,33 +1288,33 @@ static int gsp_phys_fwsec_teardown(void __iomem *bar0)
 				   GSP_PHYS_GFW_BOOT_PROGRESS_MASK;
 			scratch = readl(bar0 + GSP_PHYS_VBIOS_SCRATCH_15);
 			sb_err = scratch & 0xffff;
-			pr_info("gsp-phys-fwsec: FWSEC-SB done: SB_ERR=0x%x PLM_LEVEL0=%u GFW_progress=0x%x\n",
+			pr_info("vgsp-fwsec: FWSEC-SB done: SB_ERR=0x%x PLM_LEVEL0=%u GFW_progress=0x%x\n",
 				sb_err, !!(plm & GSP_PHYS_GFW_PLM_LEVEL0),
 				progress);
 			if (sb_err != 0)
-				pr_warn("gsp-phys-fwsec: FWSEC-SB reported error 0x%x\n",
+				pr_warn("vgsp-fwsec: FWSEC-SB reported error 0x%x\n",
 					sb_err);
 		}
 	} else {
-		pr_warn("gsp-phys-fwsec: no staged FWSEC ucode for FWSEC-SB; running booter unload only\n");
+		pr_warn("vgsp-fwsec: no staged FWSEC ucode for FWSEC-SB; running booter unload only\n");
 	}
 
 	ret = gsp_phys_booter_unload(bar0);
 	if (ret)
-		pr_err("gsp-phys-fwsec: booter unload failed: %d\n", ret);
+		pr_err("vgsp-fwsec: booter unload failed: %d\n", ret);
 
 	if (gsp_phys_fwsec_wpr2_up(bar0)) {
-		pr_warn("gsp-phys-fwsec: booter unload left WPR2 up (its handoff gate is unsatisfiable after a FWSEC-only carve); trying the host-side WPR2 unlock\n");
+		pr_warn("vgsp-fwsec: booter unload left WPR2 up (its handoff gate is unsatisfiable after a FWSEC-only carve); trying the host-side WPR2 unlock\n");
 		gsp_phys_host_wpr2_unlock(bar0);
 	}
 
 	if (gsp_phys_fwsec_wpr2_up(bar0)) {
-		pr_err("gsp-phys-fwsec: teardown did not clear WPR2 (HI=0x%08x)\n",
+		pr_err("vgsp-fwsec: teardown did not clear WPR2 (HI=0x%08x)\n",
 		       readl(bar0 + GSP_PHYS_WPR2_ADDR_HI));
 		return -EIO;
 	}
 
-	pr_info("gsp-phys-fwsec: teardown complete: WPR2 down\n");
+	pr_info("vgsp-fwsec: teardown complete: WPR2 down\n");
 	return 0;
 }
 
@@ -1331,28 +1331,28 @@ int gsp_phys_fwsec_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 	if (!boot || !pdev || !bar0)
 		return -EINVAL;
 	if (!boot->initialized) {
-		pr_err("gsp-phys-fwsec: boot layout not initialised; refusing stage 3c\n");
+		pr_err("vgsp-fwsec: boot layout not initialised; refusing stage 3c\n");
 		return -EINVAL;
 	}
 
 	if (boot->frts_size != ((u64)GSP_PHYS_FRTS_REGION_SIZE_4K << 12)) {
-		pr_err("gsp-phys-fwsec: FRTS region size mismatch: boot layout 0x%llx, FWSEC constant 0x%llx; refusing stage 3c\n",
+		pr_err("vgsp-fwsec: FRTS region size mismatch: boot layout 0x%llx, FWSEC constant 0x%llx; refusing stage 3c\n",
 		       boot->frts_size,
 		       (u64)GSP_PHYS_FRTS_REGION_SIZE_4K << 12);
 		return -EINVAL;
 	}
 
-	pr_info("gsp-phys-fwsec: stage 3c FWSEC/FRTS on %s: frtsOffset=0x%llx frtsSize=0x%llx\n",
+	pr_info("vgsp-fwsec: stage 3c FWSEC/FRTS on %s: frtsOffset=0x%llx frtsSize=0x%llx\n",
 		pci_name(pdev), boot->frts_offset, boot->frts_size);
 
 	/* Precondition 1: WPR2 must be down. */
 	wpr2_hi = gsp_phys_fwsec_wpr2_hi_val(bar0);
 	wpr2_lo = gsp_phys_fwsec_wpr2_lo_val(bar0);
-	pr_info("gsp-phys-fwsec: precondition WPR2: LO=0x%08x (VAL=0x%x) HI=0x%08x (VAL=0x%x), must be down\n",
+	pr_info("vgsp-fwsec: precondition WPR2: LO=0x%08x (VAL=0x%x) HI=0x%08x (VAL=0x%x), must be down\n",
 		readl(bar0 + GSP_PHYS_WPR2_ADDR_LO), wpr2_lo,
 		readl(bar0 + GSP_PHYS_WPR2_ADDR_HI), wpr2_hi);
 	if (wpr2_hi != 0) {
-		pr_err("gsp-phys-fwsec: unexpected WPR2 already up; the GPU is in a bad state, refusing FWSEC\n");
+		pr_err("vgsp-fwsec: unexpected WPR2 already up; the GPU is in a bad state, refusing FWSEC\n");
 		return -EBUSY;
 	}
 
@@ -1364,11 +1364,11 @@ int gsp_phys_fwsec_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 	/* Precondition 3: the RISC-V core exists (HWCFG2.RISCV). */
 	hwcfg2 = readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_HWCFG2);
 	if (!(hwcfg2 & BIT(10))) {
-		pr_err("gsp-phys-fwsec: RISC-V core not enabled (HWCFG2=0x%08x); refusing FWSEC\n",
+		pr_err("vgsp-fwsec: RISC-V core not enabled (HWCFG2=0x%08x); refusing FWSEC\n",
 		       hwcfg2);
 		return -ENODEV;
 	}
-	pr_info("gsp-phys-fwsec: precondition RISC-V enabled (HWCFG2=0x%08x)\n",
+	pr_info("vgsp-fwsec: precondition RISC-V enabled (HWCFG2=0x%08x)\n",
 		hwcfg2);
 
 	/* Read and parse the VBIOS for the FWSEC image. */
@@ -1378,14 +1378,14 @@ int gsp_phys_fwsec_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 
 	fuse = readl(bar0 + GSP_PHYS_FUSE_SECURE_GSP_DEBUG_DIS);
 	use_debug_app = !(fuse & GSP_PHYS_FUSE_SECURE_GSP_DEBUG_DIS_FIELD);
-	pr_info("gsp-phys-fwsec: fuse SECURE_GSP_DEBUG_DIS=0x%08x -> %s FWSEC image (appId 0x%x)\n",
+	pr_info("vgsp-fwsec: fuse SECURE_GSP_DEBUG_DIS=0x%08x -> %s FWSEC image (appId 0x%x)\n",
 		fuse, use_debug_app ? "debug" : "production",
 		use_debug_app ? GSP_PHYS_FWSEC_APPID_DEBUG :
 		GSP_PHYS_FWSEC_APPID_PROD);
 
 	ret = gsp_phys_vbios_parse_fwsec(&vbios, use_debug_app, &desc);
 	if (ret) {
-		pr_err("gsp-phys-fwsec: FWSEC parse from VBIOS failed: %d\n", ret);
+		pr_err("vgsp-fwsec: FWSEC parse from VBIOS failed: %d\n", ret);
 		gsp_phys_vbios_free(&vbios);
 		return ret;
 	}
@@ -1407,7 +1407,7 @@ int gsp_phys_fwsec_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 	frts.frts_region_desc.frts_region_size = GSP_PHYS_FRTS_REGION_SIZE_4K;
 	frts.frts_region_desc.frts_region_media_type =
 		GSP_PHYS_FRTS_REGION_MEDIA_FB;
-	pr_info("gsp-phys-fwsec: FRTS cmd: readVbiosDesc{version=%u size=%u flags=%u}, region{offset4K=0x%x size=0x%x(4K) media=FB}\n",
+	pr_info("vgsp-fwsec: FRTS cmd: readVbiosDesc{version=%u size=%u flags=%u}, region{offset4K=0x%x size=0x%x(4K) media=FB}\n",
 		frts.read_vbios_desc.version, frts.read_vbios_desc.size,
 		frts.read_vbios_desc.flags,
 		frts.frts_region_desc.frts_region_offset4k,
@@ -1417,7 +1417,7 @@ int gsp_phys_fwsec_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 				      GSP_PHYS_FWSEC_CMD_FRTS, &frts,
 				      sizeof(frts));
 	if (ret) {
-		pr_err("gsp-phys-fwsec: FWSEC/FRTS execution failed: %d\n", ret);
+		pr_err("vgsp-fwsec: FWSEC/FRTS execution failed: %d\n", ret);
 		goto recover;
 	}
 
@@ -1427,27 +1427,27 @@ int gsp_phys_fwsec_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 	wpr2_hi = gsp_phys_fwsec_wpr2_hi_val(bar0);
 	wpr2_lo = gsp_phys_fwsec_wpr2_lo_val(bar0);
 	gsp_phys_fwsec_dump_state(bar0, "after FWSEC/FRTS");
-	pr_info("gsp-phys-fwsec: checks: FRTS_ERR_CODE=0x%x (want 0), WPR2_HI VAL=0x%x (want nonzero), WPR2_LO VAL=0x%x (want 0x%x)\n",
+	pr_info("vgsp-fwsec: checks: FRTS_ERR_CODE=0x%x (want 0), WPR2_HI VAL=0x%x (want nonzero), WPR2_LO VAL=0x%x (want 0x%x)\n",
 		frts_err, wpr2_hi, wpr2_lo, (u32)(boot->frts_offset >> 12));
 
 	if (frts_err != 0 || wpr2_hi == 0 ||
 	    wpr2_lo != (u32)(boot->frts_offset >> 12)) {
-		pr_err("gsp-phys-fwsec: stage 3c FWSEC/FRTS checks FAILED\n");
+		pr_err("vgsp-fwsec: stage 3c FWSEC/FRTS checks FAILED\n");
 		ret = -EIO;
 		goto recover;
 	}
 
-	pr_info("gsp-phys-fwsec: stage 3c complete: WPR2 up at frtsOffset=0x%llx; device stays WPR2-owned until release tears it down\n",
+	pr_info("vgsp-fwsec: stage 3c complete: WPR2 up at frtsOffset=0x%llx; device stays WPR2-owned until release tears it down\n",
 		boot->frts_offset);
 	return 0;
 
 recover:
-	pr_err("gsp-phys-fwsec: running WPR2 teardown (FWSEC-SB + booter unload)\n");
+	pr_err("vgsp-fwsec: running WPR2 teardown (FWSEC-SB + booter unload)\n");
 	recover_ret = gsp_phys_fwsec_teardown(bar0);
 	if (recover_ret) {
-		pr_err("gsp-phys-fwsec: teardown FAILED: WPR2 is still up; release will refuse the hand-back (reboot may be required; do not retry in this boot)\n");
+		pr_err("vgsp-fwsec: teardown FAILED: WPR2 is still up; release will refuse the hand-back (reboot may be required; do not retry in this boot)\n");
 	} else {
-		pr_info("gsp-phys-fwsec: teardown complete after failure: WPR2 down; the GPU can be handed back at release\n");
+		pr_info("vgsp-fwsec: teardown complete after failure: WPR2 down; the GPU can be handed back at release\n");
 	}
 	gsp_phys_fwsec_dump_state(bar0, "after teardown");
 	return ret;
@@ -1482,48 +1482,48 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 		return -EINVAL;
 
 	if (gsp_phys_fwsec_param) {
-		pr_err("gsp-phys-fwsec-dryrun: gsp_phys_fwsec=1 is also set; the device-writing FWSEC run and this read-only dry-run are mutually exclusive - refusing both\n");
+		pr_err("vgsp-fwsec-dryrun: gsp_phys_fwsec=1 is also set; the device-writing FWSEC run and this read-only dry-run are mutually exclusive - refusing both\n");
 		return -EINVAL;
 	}
 	if (!boot->initialized) {
-		pr_err("gsp-phys-fwsec-dryrun: boot layout not initialised; refusing dry-run\n");
+		pr_err("vgsp-fwsec-dryrun: boot layout not initialised; refusing dry-run\n");
 		return -EINVAL;
 	}
 	if (boot->frts_size != ((u64)GSP_PHYS_FRTS_REGION_SIZE_4K << 12)) {
-		pr_err("gsp-phys-fwsec-dryrun: FRTS region size mismatch: boot layout 0x%llx, FWSEC constant 0x%llx; refusing dry-run\n",
+		pr_err("vgsp-fwsec-dryrun: FRTS region size mismatch: boot layout 0x%llx, FWSEC constant 0x%llx; refusing dry-run\n",
 		       boot->frts_size,
 		       (u64)GSP_PHYS_FRTS_REGION_SIZE_4K << 12);
 		return -EINVAL;
 	}
 
-	pr_info("gsp-phys-fwsec-dryrun: READ-ONLY stage 3c validation on %s: frtsOffset=0x%llx frtsSize=0x%llx (no BAR0 writes, no falcon reset, no DMA kick)\n",
+	pr_info("vgsp-fwsec-dryrun: READ-ONLY stage 3c validation on %s: frtsOffset=0x%llx frtsSize=0x%llx (no BAR0 writes, no falcon reset, no DMA kick)\n",
 		pci_name(pdev), boot->frts_offset, boot->frts_size);
 
 	/* Read-only preconditions, each pass/fail. */
 	wpr2_lo = gsp_phys_fwsec_wpr2_lo_val(bar0);
 	wpr2_hi = gsp_phys_fwsec_wpr2_hi_val(bar0);
-	pr_info("gsp-phys-fwsec-dryrun: precondition WPR2 down: LO raw=0x%08x VAL=0x%x HI raw=0x%08x VAL=0x%x -> %s\n",
+	pr_info("vgsp-fwsec-dryrun: precondition WPR2 down: LO raw=0x%08x VAL=0x%x HI raw=0x%08x VAL=0x%x -> %s\n",
 		readl(bar0 + GSP_PHYS_WPR2_ADDR_LO), wpr2_lo,
 		readl(bar0 + GSP_PHYS_WPR2_ADDR_HI), wpr2_hi,
 		wpr2_hi == 0 ? "PASS" : "FAIL");
 	if (wpr2_hi != 0) {
-		pr_err("gsp-phys-fwsec-dryrun: WPR2 already up; a real stage 3c would refuse, dry-run stops here\n");
+		pr_err("vgsp-fwsec-dryrun: WPR2 already up; a real stage 3c would refuse, dry-run stops here\n");
 		return -EBUSY;
 	}
 
 	ret = gsp_phys_fwsec_wait_gfw_boot(bar0);
-	pr_info("gsp-phys-fwsec-dryrun: precondition GFW boot complete (halted + PLM level0 + progress 0xff) -> %s\n",
+	pr_info("vgsp-fwsec-dryrun: precondition GFW boot complete (halted + PLM level0 + progress 0xff) -> %s\n",
 		ret ? "FAIL" : "PASS");
 	if (ret)
 		return ret;
 
 	hwcfg2 = readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_HWCFG2);
-	pr_info("gsp-phys-fwsec-dryrun: precondition RISC-V core enabled (HWCFG2[10]): HWCFG2=0x%08x -> %s\n",
+	pr_info("vgsp-fwsec-dryrun: precondition RISC-V core enabled (HWCFG2[10]): HWCFG2=0x%08x -> %s\n",
 		hwcfg2, (hwcfg2 & BIT(10)) ? "PASS" : "FAIL");
 	if (!(hwcfg2 & BIT(10)))
 		return -ENODEV;
 
-	pr_info("gsp-phys-fwsec-dryrun: precondition falcon state (read-only): GSP_CPUCTL=0x%08x SEC2_CPUCTL=0x%08x\n",
+	pr_info("vgsp-fwsec-dryrun: precondition falcon state (read-only): GSP_CPUCTL=0x%08x SEC2_CPUCTL=0x%08x\n",
 		readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_CPUCTL),
 		readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_CPUCTL));
 
@@ -1537,7 +1537,7 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 
 	ret = gsp_phys_vbios_parse_fwsec(&vbios, use_debug_app, &desc);
 	if (ret) {
-		pr_err("gsp-phys-fwsec-dryrun: FWSEC parse from VBIOS failed: %d\n",
+		pr_err("vgsp-fwsec-dryrun: FWSEC parse from VBIOS failed: %d\n",
 		       ret);
 		gsp_phys_vbios_free(&vbios);
 		return ret;
@@ -1547,17 +1547,17 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 	image_start = desc.desc_offset + desc.desc_size;
 	data_start = image_start + desc.dmem_offset;
 
-	pr_info("gsp-phys-fwsec-dryrun: VBIOS summary: ROM size=0x%zx pciOffset=0x%x expansionRomOffset=0x%x IFRversion=%u VBIOSversion=0x%llx\n",
+	pr_info("vgsp-fwsec-dryrun: VBIOS summary: ROM size=0x%zx pciOffset=0x%x expansionRomOffset=0x%x IFRversion=%u VBIOSversion=0x%llx\n",
 		vbios.size, vbios.pci_offset, vbios.expansion_rom_offset,
 		vbios.ifr_version, vbios.version);
-	pr_info("gsp-phys-fwsec-dryrun: BIT summary: header@0x%x tokenType=%u-byte (%s) tokens=%u; selected entry appId=0x%x targetId=%u (%s, fuse SECURE_GSP_DEBUG_DIS=0x%08x)\n",
+	pr_info("vgsp-fwsec-dryrun: BIT summary: header@0x%x tokenType=%u-byte (%s) tokens=%u; selected entry appId=0x%x targetId=%u (%s, fuse SECURE_GSP_DEBUG_DIS=0x%08x)\n",
 		vbios.bit_addr, vbios.bit_token_size,
 		vbios.bit_token_size >= GSP_PHYS_BIT_TOKEN_SIZE_8 ?
 			"2b1w1d u32 DataPtr" : "2b2w u16 DataPtr",
 		vbios.bit_token_entries, desc.app_id, desc.target_id,
 		is_fallback ? "fallback FIRMWARE_SEC_LIC 0x05" :
 		(use_debug_app ? "debug 0x45" : "production 0x85"), fuse);
-	pr_info("gsp-phys-fwsec-dryrun: FWSEC descriptor type=V%u size=%u at 0x%x; ucode code at 0x%x size=0x%x, data at 0x%x size=0x%x, interfaceOff=0x%x entry=0x%x\n",
+	pr_info("vgsp-fwsec-dryrun: FWSEC descriptor type=V%u size=%u at 0x%x; ucode code at 0x%x size=0x%x, data at 0x%x size=0x%x, interfaceOff=0x%x entry=0x%x\n",
 		desc.desc_version, desc.desc_size, desc.desc_offset,
 		image_start, desc.imem_load_size, data_start,
 		desc.dmem_load_size, desc.interface_offset,
@@ -1569,7 +1569,7 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 	    desc.imem_load_size < 16 ||
 	    data_start > vbios.size ||
 	    desc.dmem_load_size > vbios.size - data_start) {
-		pr_err("gsp-phys-fwsec-dryrun: FWSEC image outside the ROM copy (image=0x%x imem=0x%x data=0x%x dmem=0x%x rom=0x%zx); refusing\n",
+		pr_err("vgsp-fwsec-dryrun: FWSEC image outside the ROM copy (image=0x%x imem=0x%x data=0x%x dmem=0x%x rom=0x%zx); refusing\n",
 		       image_start, desc.imem_load_size, data_start,
 		       desc.dmem_load_size, vbios.size);
 		gsp_phys_vbios_free(&vbios);
@@ -1579,15 +1579,15 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 	code = vbios.data + image_start;
 	code_crc = crc32_le(0, code, desc.imem_load_size);
 	data_crc = crc32_le(0, vbios.data + data_start, desc.dmem_load_size);
-	pr_info("gsp-phys-fwsec-dryrun: ucode first 4 words: %08x %08x %08x %08x\n",
+	pr_info("vgsp-fwsec-dryrun: ucode first 4 words: %08x %08x %08x %08x\n",
 		get_unaligned_le32(code), get_unaligned_le32(code + 4),
 		get_unaligned_le32(code + 8), get_unaligned_le32(code + 12));
-	pr_info("gsp-phys-fwsec-dryrun: ucode last 4 words:  %08x %08x %08x %08x\n",
+	pr_info("vgsp-fwsec-dryrun: ucode last 4 words:  %08x %08x %08x %08x\n",
 		get_unaligned_le32(code + desc.imem_load_size - 16),
 		get_unaligned_le32(code + desc.imem_load_size - 12),
 		get_unaligned_le32(code + desc.imem_load_size - 8),
 		get_unaligned_le32(code + desc.imem_load_size - 4));
-	pr_info("gsp-phys-fwsec-dryrun: CRC32 code(0x%x bytes)=0x%08x data(0x%x bytes)=0x%08x\n",
+	pr_info("vgsp-fwsec-dryrun: CRC32 code(0x%x bytes)=0x%08x data(0x%x bytes)=0x%08x\n",
 		desc.imem_load_size, code_crc, desc.dmem_load_size, data_crc);
 
 	/* Capacity registers the staging/placement math depends on. */
@@ -1595,13 +1595,13 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 	imem_blocks = gsp_hwcfg & GSP_PHYS_HWCFG_IMEM_SIZE;
 	bl_blocks = imem_blocks >= GSP_PHYS_SEC2_BL_CODE_SIZE / 256 ?
 		    imem_blocks - GSP_PHYS_SEC2_BL_CODE_SIZE / 256 : 0;
-	pr_info("gsp-phys-fwsec-dryrun: GSP falcon HWCFG=0x%08x IMEM_SIZE=%u blocks (256 B) -> generic BL at block %u (IMEM addr 0x%x), tag 0x%x, fits=%s\n",
+	pr_info("vgsp-fwsec-dryrun: GSP falcon HWCFG=0x%08x IMEM_SIZE=%u blocks (256 B) -> generic BL at block %u (IMEM addr 0x%x), tag 0x%x, fits=%s\n",
 		gsp_hwcfg, imem_blocks, bl_blocks, bl_blocks << 8,
 		GSP_PHYS_SEC2_BL_START_TAG,
 		imem_blocks * 256 >= GSP_PHYS_SEC2_BL_CODE_SIZE ? "yes" :
 		"no");
 	if (imem_blocks * 256 < GSP_PHYS_SEC2_BL_CODE_SIZE) {
-		pr_err("gsp-phys-fwsec-dryrun: GSP IMEM too small for the generic boot-loader (%u blocks); refusing\n",
+		pr_err("vgsp-fwsec-dryrun: GSP IMEM too small for the generic boot-loader (%u blocks); refusing\n",
 		       imem_blocks);
 		gsp_phys_vbios_free(&vbios);
 		return -EINVAL;
@@ -1610,19 +1610,19 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 	sec2_hwcfg = readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_HWCFG);
 	dmem_blocks = (sec2_hwcfg & GSP_PHYS_HWCFG_DMEM_SIZE) >>
 		      GSP_PHYS_HWCFG_DMEM_SIZE_SHIFT;
-	pr_info("gsp-phys-fwsec-dryrun: SEC2 falcon HWCFG=0x%08x IMEM_SIZE=%u blocks DMEM_SIZE=%u blocks (0x%x bytes) vs booter-unload DMEM data 0x%x -> %s\n",
+	pr_info("vgsp-fwsec-dryrun: SEC2 falcon HWCFG=0x%08x IMEM_SIZE=%u blocks DMEM_SIZE=%u blocks (0x%x bytes) vs booter-unload DMEM data 0x%x -> %s\n",
 		sec2_hwcfg, sec2_hwcfg & GSP_PHYS_HWCFG_IMEM_SIZE,
 		dmem_blocks, dmem_blocks * 256,
 		GSP_PHYS_BOOTER_UNLOAD_DATA_SIZE,
 		dmem_blocks * 256 >= GSP_PHYS_BOOTER_UNLOAD_DATA_SIZE ?
 		"PASS" : "FAIL");
 	if (dmem_blocks == 0) {
-		pr_err("gsp-phys-fwsec-dryrun: SEC2 HWCFG DMEM_SIZE (bits 17:9) decodes to zero - the capacity is not readable/reporting on this part; refusing\n");
+		pr_err("vgsp-fwsec-dryrun: SEC2 HWCFG DMEM_SIZE (bits 17:9) decodes to zero - the capacity is not readable/reporting on this part; refusing\n");
 		gsp_phys_vbios_free(&vbios);
 		return -ENODEV;
 	}
 	if (dmem_blocks * 256 < GSP_PHYS_BOOTER_UNLOAD_DATA_SIZE) {
-		pr_err("gsp-phys-fwsec-dryrun: Booter-Unload DMEM data 0x%x does not fit SEC2 DMEM 0x%x; the unload split would not load; refusing\n",
+		pr_err("vgsp-fwsec-dryrun: Booter-Unload DMEM data 0x%x does not fit SEC2 DMEM 0x%x; the unload split would not load; refusing\n",
 		       GSP_PHYS_BOOTER_UNLOAD_DATA_SIZE, dmem_blocks * 256);
 		gsp_phys_vbios_free(&vbios);
 		return -ENOSPC;
@@ -1652,11 +1652,11 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 	if (ret)
 		goto out_free;
 
-	pr_info("gsp-phys-fwsec-dryrun: staging plan (host DMA only): code alloc=0x%zx dma=0x%llx (imemLoad=0x%x secOff/Size=0x%x/0x%x), data alloc=0x%zx dma=0x%llx (dmemLoad=0x%x)\n",
+	pr_info("vgsp-fwsec-dryrun: staging plan (host DMA only): code alloc=0x%zx dma=0x%llx (imemLoad=0x%x secOff/Size=0x%x/0x%x), data alloc=0x%zx dma=0x%llx (dmemLoad=0x%x)\n",
 		u.code_size, (u64)u.code_dma, u.desc.imem_load_size,
 		bl.secure_code_off, bl.secure_code_size, u.data_size,
 		(u64)u.data_dma, u.desc.dmem_load_size);
-	pr_info("gsp-phys-fwsec-dryrun: 84-byte BL descriptor: reserved[4]=0 signature[4]=0 ctxDma=%u codeDma=0x%llx nsOff/Size=0x%x/0x%x secOff/Size=0x%x/0x%x entry=0x%x dataDma=0x%llx dataSize=0x%x argc=%u argv=%u\n",
+	pr_info("vgsp-fwsec-dryrun: 84-byte BL descriptor: reserved[4]=0 signature[4]=0 ctxDma=%u codeDma=0x%llx nsOff/Size=0x%x/0x%x secOff/Size=0x%x/0x%x entry=0x%x dataDma=0x%llx dataSize=0x%x argc=%u argv=%u\n",
 		bl.ctx_dma,
 		((u64)bl.code_dma_hi << 32) | bl.code_dma_lo,
 		bl.non_secure_code_off, bl.non_secure_code_size,
@@ -1664,24 +1664,24 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 		bl.code_entry_point,
 		((u64)bl.data_dma_hi << 32) | bl.data_dma_lo,
 		bl.data_size, bl.argc, bl.argv);
-	pr_info("gsp-phys-fwsec-dryrun: generic-BL placement from real HWCFG: block %u IMEM addr 0x%x BOOTVEC=0x%x code 0x%x bytes tag 0x%x\n",
+	pr_info("vgsp-fwsec-dryrun: generic-BL placement from real HWCFG: block %u IMEM addr 0x%x BOOTVEC=0x%x code 0x%x bytes tag 0x%x\n",
 		bl_blocks, bl_blocks << 8, GSP_PHYS_SEC2_BL_START_TAG << 8,
 		GSP_PHYS_SEC2_BL_CODE_SIZE, GSP_PHYS_SEC2_BL_START_TAG);
-	pr_info("gsp-phys-fwsec-dryrun: FRTS region: frtsOffset>>12=0x%x size4K=0x%x media=FB(%u); readVbiosDesc{version=%u size=%u flags=%u}\n",
+	pr_info("vgsp-fwsec-dryrun: FRTS region: frtsOffset>>12=0x%x size4K=0x%x media=FB(%u); readVbiosDesc{version=%u size=%u flags=%u}\n",
 		frts.frts_region_desc.frts_region_offset4k,
 		frts.frts_region_desc.frts_region_size,
 		frts.frts_region_desc.frts_region_media_type,
 		frts.read_vbios_desc.version, frts.read_vbios_desc.size,
 		frts.read_vbios_desc.flags);
-	pr_info("gsp-phys-fwsec-dryrun: interface-patch block at DMEM 0x%x (0x%zx bytes): %*ph\n",
+	pr_info("vgsp-fwsec-dryrun: interface-patch block at DMEM 0x%x (0x%zx bytes): %*ph\n",
 		cmd_off, sizeof(frts), (int)sizeof(frts),
 		(const u8 *)u.data_va + cmd_off);
-	pr_info("gsp-phys-fwsec-dryrun: expected WPR2 after a real run: HI VAL nonzero; LO VAL=0x%x raw encoding=0x%08x\n",
+	pr_info("vgsp-fwsec-dryrun: expected WPR2 after a real run: HI VAL nonzero; LO VAL=0x%x raw encoding=0x%08x\n",
 		(u32)(boot->frts_offset >> 12),
 		(u32)((boot->frts_offset >> 12) << 4));
 
 	/* Bindata header/size/tag verification (compile-time vs image). */
-	pr_info("gsp-phys-fwsec-dryrun: generic SEC2 BL bindata: image=0x%zx code=0x%x at 0 data=0x100 at 0x200 blStartTag=0x%x blDmemDescLoadOff=0 -> %s\n",
+	pr_info("vgsp-fwsec-dryrun: generic SEC2 BL bindata: image=0x%zx code=0x%x at 0 data=0x100 at 0x200 blStartTag=0x%x blDmemDescLoadOff=0 -> %s\n",
 		sizeof(gsp_phys_sec2_bl_image), GSP_PHYS_SEC2_BL_CODE_SIZE,
 		GSP_PHYS_SEC2_BL_START_TAG,
 		sizeof(gsp_phys_sec2_bl_image) == 0x300 &&
@@ -1700,7 +1700,7 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 		   GSP_PHYS_BOOTER_UNLOAD_DATA_OFF +
 			GSP_PHYS_BOOTER_UNLOAD_DATA_SIZE ==
 			GSP_PHYS_BOOTER_UNLOAD_IMAGE_SIZE;
-	pr_info("gsp-phys-fwsec-dryrun: Booter-Unload bindata: image=0x%zx nsCode=0x%x@0x%x secCode=0x%x@0x%x codeEnd=0x%x data=0x%x@0x%x dataEnd=0x%x mailboxTag=0x%x/0x%x sig@0x4e00=%08x -> %s\n",
+	pr_info("vgsp-fwsec-dryrun: Booter-Unload bindata: image=0x%zx nsCode=0x%x@0x%x secCode=0x%x@0x%x codeEnd=0x%x data=0x%x@0x%x dataEnd=0x%x mailboxTag=0x%x/0x%x sig@0x4e00=%08x -> %s\n",
 		sizeof(gsp_phys_booter_unload_image),
 		GSP_PHYS_BOOTER_UNLOAD_NS_CODE_SIZE,
 		GSP_PHYS_BOOTER_UNLOAD_NS_CODE_OFF,
@@ -1717,7 +1717,7 @@ int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 		uload_ok ? "PASS" : "FAIL");
 
 	gsp_phys_fwsec_ucode_free(pdev, &u);
-	pr_info("gsp-phys-fwsec-dryrun: stage 3c dry-run complete: VBIOS/BIT/FWSEC parse, capacity registers, staging and placement plan validated; no device writes (WPR2 stays down, no falcon reset, no DMA kick)\n");
+	pr_info("vgsp-fwsec-dryrun: stage 3c dry-run complete: VBIOS/BIT/FWSEC parse, capacity registers, staging and placement plan validated; no device writes (WPR2 stays down, no falcon reset, no DMA kick)\n");
 	return 0;
 
 out_free:
@@ -1736,25 +1736,25 @@ int gsp_phys_fwsec_release(struct gsp_phys_boot *boot, struct pci_dev *pdev,
 		return 0;
 
 	if (!gsp_phys_fwsec_wpr2_up(bar0)) {
-		pr_info("gsp-phys-fwsec: release: WPR2 already down; freeing FWSEC staging and handing back\n");
+		pr_info("vgsp-fwsec: release: WPR2 already down; freeing FWSEC staging and handing back\n");
 		gsp_phys_fwsec_ucode_free(pdev, &fwsec.ucode);
 		fwsec.touched = false;
 		return 0;
 	}
 
-	pr_info("gsp-phys-fwsec: release: WPR2 is up; tearing down before hand-back\n");
-	pr_info("gsp-phys-fwsec: release: booter-unload gate input: scratch14 handoff bits all four DONE=%u\n",
+	pr_info("vgsp-fwsec: release: WPR2 is up; tearing down before hand-back\n");
+	pr_info("vgsp-fwsec: release: booter-unload gate input: scratch14 handoff bits all four DONE=%u\n",
 		gsp_phys_fwsec_scratch14_all_done(bar0));
 	ret = gsp_phys_fwsec_teardown(bar0);
 	gsp_phys_fwsec_ucode_free(pdev, &fwsec.ucode);
 
 	if (ret || gsp_phys_fwsec_wpr2_up(bar0)) {
-		pr_err("gsp-phys-fwsec: release: WPR2 still up after teardown (HI=0x%08x); refusing the hand-back to the distribution driver\n",
+		pr_err("vgsp-fwsec: release: WPR2 still up after teardown (HI=0x%08x); refusing the hand-back to the distribution driver\n",
 		       readl(bar0 + GSP_PHYS_WPR2_ADDR_HI));
 		return -EIO;
 	}
 
-	pr_info("gsp-phys-fwsec: release: WPR2 down after teardown; hand-back is safe\n");
+	pr_info("vgsp-fwsec: release: WPR2 down after teardown; hand-back is safe\n");
 	fwsec.touched = false;
 	return 0;
 }