Initial commit: Open-IOV vGPU-IO complete stack

- Firmware decompilation: GSP 570.144W (28.5MB ELF, RV64IMAC), 132 decompiled C files
- Kernel modules: nvidia.ko (34MB, OpenRM), open-iov-vfio.ko (2.8MB, VFIO mdev), gsp-vgpu.ko (1.8MB, guest driver)
- Userspace: libiov.so/libvgpu.so (76KB), example_vgpu (28KB), rpc_emulator.c
- PCI config space emulation (256B with PM, MSI, MSI-X, PCIe caps)
- 12 RPC types fully mapped from firmware decompilation
- BAR trap, WPR, scheduling, notification, migration emulation
- Helper scripts: load_vgpu_stack, create_mdev, launch_qemu_vgpu, test_vgpu_stack, setup_guest_driver, unload_vgpu_stack
- Architecture documentation
- Wiki: 10 technical documents
- Git LFS for large binaries (.ko, .bin, .iso, .img, .o, ghidra repos)
- nvidia-open-gpu-kernel-modules as submodule

1 files changed, 146 insertions, 0 deletions

diff --git a/kernel/bar_init.c b/kernel/bar_init.c
new file mode 100644
index 0000000..bf993ab
--- /dev/null
+++ b/kernel/bar_init.c
@@ -0,0 +1,146 @@
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/iommu.h>
+#include <linux/vmalloc.h>
+
+#include "nvidia-vgpu-vfio.h"
+#include "bar_emulation.h"
+#include "irq.h"
+
+int nv_vgpu_bar_init(struct nv_vgpu_device *vgpu)
+{
+	struct pci_dev *pdev = vgpu->pdev;
+	struct nv_vgpu_bar *bar;
+	u64 bar_addr;
+	u64 bar_size;
+	int i, ret;
+
+	if (vgpu->dry_run) {
+		nv_vgpu_info(vgpu, "DRY-RUN: BAR init validation");
+		for (i = 0; i < 4; i++) {
+			bar_addr = pci_resource_start(pdev, i);
+			bar_size = pci_resource_len(pdev, i);
+			if (bar_addr && bar_size) {
+				nv_vgpu_info(vgpu, "  BAR%d: gpa=0x%llx, size=0x%llx (%s)", 
+					     i, bar_addr, bar_size,
+					     i == 0 ? "config" : (i == 1 ? "FB" : (i == 2 ? "I/O" : "other")));
+			}
+		}
+		nv_vgpu_info(vgpu, "DRY-RUN: BAR validation passed");
+		return 0;
+	}
+
+	for (i = 0; i < NV_VGPU_MAX_REGIONS; i++) {
+		bar = &vgpu->bars[i];
+		mutex_init(&bar->lock);
+		bar->mapped = false;
+		bar->trapped = false;
+	}
+
+	bar_addr = pci_resource_start(pdev, 0);
+	bar_size = pci_resource_len(pdev, 0);
+	if (bar_addr && bar_size) {
+		vgpu->bars[0].gpa = bar_addr;
+		vgpu->bars[0].size = bar_size;
+		vgpu->bars[0].vaddr = ioremap_wc(bar_addr, bar_size);
+		if (!vgpu->bars[0].vaddr) {
+			nv_vgpu_err(vgpu, "Failed to map BAR0");
+			return -ENOMEM;
+		}
+		vgpu->bar0_config_base = bar_addr;
+		nv_vgpu_info(vgpu, "BAR0: gpa=0x%llx, size=0x%llx, vaddr=%p", bar_addr, bar_size, vgpu->bars[0].vaddr);
+	}
+
+	bar_addr = pci_resource_start(pdev, 1);
+	bar_size = pci_resource_len(pdev, 1);
+	if (bar_addr && bar_size) {
+		vgpu->bars[1].gpa = bar_addr;
+		vgpu->bars[1].size = bar_size;
+		/* BAR1 (FB) is already mapped by nvidia.ko - don't remap */
+		vgpu->bars[1].vaddr = NULL;
+		nv_vgpu_info(vgpu, "BAR1: gpa=0x%llx, size=0x%llx (managed by nvidia.ko)", bar_addr, bar_size);
+	}
+
+	bar_addr = pci_resource_start(pdev, 2);
+	bar_size = pci_resource_len(pdev, 2);
+	if (bar_addr && bar_size) {
+		vgpu->bars[2].gpa = bar_addr;
+		vgpu->bars[2].size = bar_size;
+		vgpu->bars[2].vaddr = ioremap_wc(bar_addr, bar_size);
+		if (!vgpu->bars[2].vaddr) {
+			nv_vgpu_err(vgpu, "Failed to map BAR2");
+			return -ENOMEM;
+		}
+		nv_vgpu_info(vgpu, "BAR2: gpa=0x%llx, size=0x%llx, vaddr=%p", bar_addr, bar_size, vgpu->bars[2].vaddr);
+	}
+
+	bar_addr = pci_resource_start(pdev, 3);
+	bar_size = pci_resource_len(pdev, 3);
+	if (bar_addr && bar_size) {
+		vgpu->bars[3].gpa = bar_addr;
+		vgpu->bars[3].size = bar_size;
+		vgpu->bars[3].vaddr = ioremap_wc(bar_addr, bar_size);
+		if (!vgpu->bars[3].vaddr) {
+			nv_vgpu_err(vgpu, "Failed to map BAR3");
+			return -ENOMEM;
+		}
+		nv_vgpu_info(vgpu, "BAR3: gpa=0x%llx, size=0x%llx, vaddr=%p", bar_addr, bar_size, vgpu->bars[3].vaddr);
+	}
+
+	ret = nv_vgpu_bar_emul_init(vgpu);
+	if (ret) {
+		nv_vgpu_err(vgpu, "BAR emulation init failed: %d", ret);
+		return ret;
+	}
+
+	/* MSI/MSI-X is managed by nvidia.ko - don't try to set up our own */
+	nv_vgpu_info(vgpu, "MSI/MSI-X managed by nvidia.ko");
+
+	vgpu->fb_base = pci_resource_start(pdev, 1);
+	vgpu->fb_size = pci_resource_len(pdev, 1);
+
+	return 0;
+}
+
+void nv_vgpu_bar_cleanup(struct nv_vgpu_device *vgpu)
+{
+	int i;
+
+	if (vgpu->dry_run) {
+		nv_vgpu_info(vgpu, "DRY-RUN: BAR cleanup (no hardware resources to release)");
+		return;
+	}
+
+	nv_vgpu_irq_teardown_msix(vgpu);
+	nv_vgpu_irq_teardown_msi(vgpu);
+	nv_vgpu_bar_emul_cleanup(vgpu);
+
+	for (i = 0; i < NV_VGPU_MAX_REGIONS; i++) {
+		if (vgpu->bars[i].vaddr) {
+			iounmap(vgpu->bars[i].vaddr);
+			vgpu->bars[i].vaddr = NULL;
+		}
+		vgpu->bars[i].mapped = false;
+		vgpu->bars[i].trapped = false;
+		vgpu->bars[i].iova = 0;
+	}
+}
+
+int nv_vgpu_bar_trap(struct nv_vgpu_device *vgpu, int bar_idx)
+{
+	if (bar_idx < 0 || bar_idx >= NV_VGPU_MAX_REGIONS)
+		return -EINVAL;
+
+	if (!vgpu->bars[bar_idx].vaddr)
+		return -ENODEV;
+
+	return nv_vgpu_bar_trap_register(vgpu, bar_idx, 0, vgpu->bars[bar_idx].size);
+}
+
+void nv_vgpu_bar_untrap(struct nv_vgpu_device *vgpu, int bar_idx)
+{
+	if (bar_idx < 0 || bar_idx >= NV_VGPU_MAX_REGIONS)
+		return;
+
+	nv_vgpu_bar_untrap_register(vgpu, bar_idx, 0);
+}