gsp-phys: populate the chipset/CL block of the pre-boot system info

Fill the GspSystemInfo chipset fields the production client syncs before
the GSP boot instead of leaving them zero:

- clPdbProperties (bitmask in the client's clSyncWithGsp order): bit 0
  (config space accessible, from the OS MCFG/ECAM availability), bit 7
  and bit 21 (Intel Skylake-family upstream-port setup: ASPM POR list,
  root-port nosnoop WAR), bit 13 (upstream port ASPM L1 capable), bit 27
  (LTR supported+enabled up to the root port) and bit 32 (IO coherent).
  PDB_PROP_CL_UNSUPPORTED_CHIPSET is never assigned by the client, so the
  faithful unmatched-chipset value is 0.
- Chipset = 0 (CS_UNKNOWN) for a host bridge with no chipsetInfo[] entry,
  the reference's no-match fallback.
- FHBBusInfo/chipsetIDInfo: 10-byte BUSINFO blobs of the first host
  bridge of the GPU's domain (device, vendor, subdevice, subvendor,
  revision), with the subsystem-capability fallback on chipsetIDInfo.

acpiMethodData is intentionally sent all-zero (bValid=0): no ACPI/AML
calls are made and every consumer tolerates the no-data encoding. All
device lookups use refcounted pci_get_device()/pci_dev_put().

1 files changed, 8 insertions, 1 deletions

diff --git a/docs/03-architecture/08-physical-gpu-integration.md b/docs/03-architecture/08-physical-gpu-integration.md
index 9949227..2ea44a1 100644
--- a/docs/03-architecture/08-physical-gpu-integration.md
+++ b/docs/03-architecture/08-physical-gpu-integration.md
@@ -201,7 +201,14 @@ Booter Load kick the module also queues the two pre-boot asynchronous init
 RPCs the production client sends in the same spot: `GSP_SET_SYSTEM_INFO` (72,
 the host/GPU address and PCI environment description GSP-RM consumes before it
 creates its GPU object) and `SET_REGISTRY` (73; a header-only empty table,
-which the server explicitly accepts). The server
+which the server explicitly accepts). The system-info payload also carries the
+chipset description the production client syncs into the firmware before boot:
+the core-logic property bitmask, the `Chipset` value and two host-bridge
+BUSINFO blobs (device/vendor/subsystem ids and revision of the first host
+bridge of the GPU's domain), built from the live PCI topology
+(root-port/chipset class match, upstream link and LTR capabilities). The ACPI
+method-data block is sent invalid/zero: the boot path deliberately makes no
+ACPI/AML calls and every consumer tolerates the no-data encoding. The server
 waits for the host to execute the sequencer command buffer carried in that
 event before it raises `GSP_INIT_DONE` (0x1001). **A plain release is not yet
 possible:** the Booter Unload gate requires all four secure scratch14 handoff