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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-06 15:31:39 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-06 15:31:39 -0400 |
| commit | 6317a17fdf1ddb3752f59128537dc5fc7168d2ff (patch) | |
| tree | e93e4351d927d453938721ecab77309d6d952f21 | |
| parent | 3105ada03531dfe6b2b5fa28c94db4f4c518e799 (diff) | |
| download | open-iov-6317a17fdf1ddb3752f59128537dc5fc7168d2ff.tar.gz open-iov-6317a17fdf1ddb3752f59128537dc5fc7168d2ff.zip | |
vgsp: default the QMD-virt 0x29c pair off (m26 falsified it; non-vendor without BASE)
| -rw-r--r-- | kernel/gsp_phys_gpu.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c index b299d68..4848f4b 100644 --- a/kernel/gsp_phys_gpu.c +++ b/kernel/gsp_phys_gpu.c @@ -598,16 +598,19 @@ int gsp_phys_rmcall_gr_prelude_value(void) EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_prelude_value); /* - * QMD virtualization control gate (default 1). When set, the GR launch block - * emits NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL (0x29c) = IQ2M_ADDR_ENABLE - * (bit 16) | SEND_PCAS_ENABLE (bit 24) after the compute init and before the - * inline-QMD window; 0 omits the method pair. Read at each launch. + * QMD virtualization control gate (default 0 after m26 falsified the + * hypothesis: on Turing the context init value is 0, native CUDA never + * writes 0x29c, and the nonzero enable alone does not schedule). When set, + * the GR launch block emits NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL (0x29c) = + * IQ2M_ADDR_ENABLE (bit 16) | SEND_PCAS_ENABLE (bit 24) after the compute + * init and before the inline-QMD window; 0 omits the method pair. Read at + * each launch (controlled A/B knob only). */ -static int gsp_phys_rmcall_gr_qmdvirt_param = 1; +static int gsp_phys_rmcall_gr_qmdvirt_param; module_param_named(gsp_phys_rmcall_gr_qmdvirt, gsp_phys_rmcall_gr_qmdvirt_param, int, 0644); MODULE_PARM_DESC(gsp_phys_rmcall_gr_qmdvirt, - "Emit NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL (0x29c = IQ2M_ADDR_ENABLE|SEND_PCAS_ENABLE) in the GR launch block (default 1; 0 omits the method pair)"); + "Emit NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL (0x29c = IQ2M_ADDR_ENABLE|SEND_PCAS_ENABLE) in the GR launch block (default 0; 1 enables the A/B method pair)"); int gsp_phys_rmcall_gr_qmdvirt_value(void) { |