<feed xmlns='http://www.w3.org/2005/Atom'>
<title>open-iov.git/tools/test/cuda_drv_test2.c, branch gr-forwarding</title>
<subtitle>Open-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers
</subtitle>
<id>https://git.vgpu.io/open-iov.git/atom?h=gr-forwarding</id>
<link rel='self' href='https://git.vgpu.io/open-iov.git/atom?h=gr-forwarding'/>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/'/>
<updated>2026-09-30T12:40:17+00:00</updated>
<entry>
<title>guest-diag: cdt2 mapping scan is opt-in (CDT_SCAN=1); it can wedge the client</title>
<updated>2026-09-30T12:40:17+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-09-30T12:40:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=126bf47b524d9de254fb6e4c62f5ac14dd687159'/>
<id>urn:sha1:126bf47b524d9de254fb6e4c62f5ac14dd687159</id>
<content type='text'>
</content>
</entry>
<entry>
<title>guest-diag: cdt2 payload scan limited to anon mappings (device-mapping reads can block)</title>
<updated>2026-09-30T12:25:49+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-09-30T12:25:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=9d7bb10c06b882f5164ab47a74caa6bee97de0b5'/>
<id>urn:sha1:9d7bb10c06b882f5164ab47a74caa6bee97de0b5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>guest-diag: cdt2 payload scan only touches anon/device mappings (avoid SIGBUS on truncated file maps)</title>
<updated>2026-09-30T12:08:32+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-09-30T12:08:32+00:00</published>
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<id>urn:sha1:662912d8961ec73e1cbc2b4f0903627c242cf9d6</id>
<content type='text'>
</content>
</entry>
<entry>
<title>guest-diag: cdt2 scans its own mappings for the payload after HtoD (DtoH mechanism probe)</title>
<updated>2026-09-30T11:25:45+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-09-30T11:25:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=0ffc3bf8effd69af2910ad38294cb99894c6b44b'/>
<id>urn:sha1:0ffc3bf8effd69af2910ad38294cb99894c6b44b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>sema-svc: decode GRCE inline-data DMA (small HtoD path)</title>
<updated>2026-09-30T10:13:26+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-09-30T10:13:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=4c1eff4b6af581187b847bd61a9f846bafca2713'/>
<id>urn:sha1:4c1eff4b6af581187b847bd61a9f846bafca2713</id>
<content type='text'>
The 256-byte cuMemcpyHtoD payload never appears in any CE push: CUDA
submits it on the compute channel as a compute-class DMA whose source is
the push's own inline data (LINE_LENGTH_IN=256, OFFSET_OUT=&lt;device VA&gt;,
LAUNCH_DMA=0x41, LOAD_INLINE_DATA 64 dwords, then the channel's
SET_REPORT_SEMAPHORE release). The CE-shaped decoder skipped the data run
(opcode 3) and no GR work ran at all.

- Decode NVC5C0 GRCE methods on subchannel 1 (LINE_LENGTH_IN, LINE_COUNT,
  OFFSET_OUT/UPPER, LAUNCH_DMA) and the opcode-3 LOAD_INLINE_DATA run.
- svc_grce_inline_write resolves the destination VA through trusted
  sources (pins, map, published page directories, targeted rm_mem
  resolve), pins the page and writes into vidmem or guest RAM; budgeted
  sema-grce logs name the target or report UNRESOLVED.
- cdt2 test binary gains CDT_CP_PAUSE / CDT_HP_PAUSE for live inspection
  of the copy path; pushed by push_guest_tools.sh.
</content>
</entry>
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