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<title>open-iov.git/tools/guest-diag/bridge_sems.sh, branch master</title>
<subtitle>Open-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers
</subtitle>
<id>https://git.vgpu.io/open-iov.git/atom?h=master</id>
<link rel='self' href='https://git.vgpu.io/open-iov.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/'/>
<updated>2026-10-08T15:53:20+00:00</updated>
<entry>
<title>spdx: add BSD-3-Clause identifiers to userspace/tools/scripts sources</title>
<updated>2026-10-08T15:53:20+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-08T15:53:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=3485a440c69a042ae043ad8089329601272155e8'/>
<id>urn:sha1:3485a440c69a042ae043ad8089329601272155e8</id>
<content type='text'>
Sweep of the 155 tracked C/Python/shell files under userspace/ (excluding
the MIT-licensed vendored userspace/extern/), tools/ and scripts/ that had
no per-file license identifier. Each gains the minimal two-line header in
the area's existing form: 'SPDX-License-Identifier: BSD-3-Clause' plus
'Copyright (c) 2026 Open-IOV contributors'; shebang and coding lines stay
first. No other content touched. kernel/** is deliberately out of scope
(recorded as a follow-up in CODESTD-REPORT-2026-10-08.md): its SPDX
coverage and MODULE_LICENSE normalization need their own GPL-2.0 pass.
</content>
</entry>
<entry>
<title>kernel: GR context-promote bisection modes 4-17 and server-managed-ctxbuf registry variant; complete vgsp rename; docs/tooling refresh</title>
<updated>2026-10-02T19:13:06+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-02T19:13:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=4bb8550a72597ec098c6d62a75006a0aba61972e'/>
<id>urn:sha1:4bb8550a72597ec098c6d62a75006a0aba61972e</id>
<content type='text'>
- gsp_phys_booter: GR promote bisection modes 4-17 (two-phase zero-field VA,
  batched entries, hVirtMemory, bare VA, KMD SKIP_CTXBUFFER_ALLOC channel,
  old-interface GPU_INITIALIZE_CTX, FBMEM context buffer, UVM-faithful PA-only,
  PATCH/PM auxiliary promotes, server-managed no-promote path); PATCH/PM
  geometry queries and buffers; pre-boot SET_REGISTRY profile selection
- gsp_phys_gpu: gsp_phys_rmcall_gr_promote clamp 0..17 and gsp_phys_srv_ctxbuf
  parameter; registry image variant with RMSetClientRMAllocatedCtxBuffer=0
- vgsp rename across kernel, scripts, tools and docs (module vgsp.ko,
  /sys/kernel/debug/vgsp/, vgsp-&lt;subsystem&gt;: log prefixes)
- risc-v-gsp-rm-debugger user-facing rename and docs/CI refresh; guest-diag
  tool updates; README/SBOM/install/Makefile sync

Live status: CE ladder and P6 guest-copy forwarding green; GR engine context
commit still open (all promote shapes accepted or cleanly refused; the channel
stays CTXNOTVALID) - see Handoff-vGPU-IO.md Addendum 21 (local).
</content>
</entry>
<entry>
<title>tools/guest-diag: keep bridge_sems replies under the guest-agent size limit</title>
<updated>2026-09-26T05:38:46+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-09-26T05:38:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=b4870a19e83c5601a867214ddfb7e883d61f9d60'/>
<id>urn:sha1:b4870a19e83c5601a867214ddfb7e883d61f9d60</id>
<content type='text'>
</content>
</entry>
<entry>
<title>kernel: enlarge the pin table and its probe window; tools: bridge client mappings into the service</title>
<updated>2026-09-24T14:48:08+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-09-24T14:48:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=13c07f7585c71bb75870d2a25475b4c9401a57fc'/>
<id>urn:sha1:13c07f7585c71bb75870d2a25475b4c9401a57fc</id>
<content type='text'>
The pin table became the primary VA-&gt;PA store once push-buffer regions and
bridged client mappings started adding thousands of pages per boot; at
8192 slots with an 8-probe window, inserts were silently dropped and
lookups missed at half load. 32768 slots and a 32-probe window keep the
mapped set intact.

tools/guest-diag/{guest_pmap_all.py,bridge_sems.sh} translate the CUDA
client's /dev/nvidia* mappings through the guest's own pagemap and inject
each present page into the service as a sysmem pin. With the client's
semaphore pages pinned the service applies their releases into the page
the client polls (verified: applied 67 -&gt; 109, misses stop growing for
those VAs), where before every write went to the vidmem shadow.
</content>
</entry>
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